generated from hulk/gd32e23x_template_cmake_vscode
sync: 合并内网 LDC1612_last_version 代码变更
- 覆盖 Src/Inc/SDK/LD/doc 等源码文件 - 保留 cmake 构建配置和 Git 历史不变 - 来源: 内网 LDC1612_last_version
This commit is contained in:
+12
-12
@@ -1,13 +1,13 @@
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project(CMSIS LANGUAGES C CXX ASM)
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add_library(CMSIS INTERFACE)
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target_include_directories(CMSIS INTERFACE
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${CMAKE_SOURCE_DIR}/SDK/CMSIS
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${CMAKE_SOURCE_DIR}/SDK/CMSIS/GD/GD32E23x/Include
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# Added directory of "gd32e23x_libopt.h".
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${CMAKE_SOURCE_DIR}/Inc
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# 如有其它需要的头文件目录，可继续添加
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project(CMSIS LANGUAGES C CXX ASM)
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add_library(CMSIS INTERFACE)
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target_include_directories(CMSIS INTERFACE
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${CMAKE_SOURCE_DIR}/SDK/CMSIS
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||||
${CMAKE_SOURCE_DIR}/SDK/CMSIS/GD/GD32E23x/Include
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# Added directory of "gd32e23x_libopt.h".
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${CMAKE_SOURCE_DIR}/Inc
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# 如有其它需要的头文件目录，可继续添加
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)
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@@ -1,213 +1,213 @@
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/*!
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\file gd32e23x.h
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\brief general definitions for GD32E23x
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\version 2025-02-10, V2.3.0, firmware for GD32E23x
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||||
*/
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||||
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||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
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||||
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||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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||||
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||||
#ifndef GD32E23X_H
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#define GD32E23X_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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||||
/* define GD32E23x */
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#if !defined (GD32E23x)
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#define GD32E23x
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#endif /* define GD32E23x */
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#if !defined (GD32E23x)
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#error "Please select the target GD32E23x device used in your application (in gd32e23x.h file)"
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||||
#endif /* undefine GD32E23x tip */
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||||
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||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)8000000)
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#endif /* high speed crystal oscillator value */
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||||
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||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
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||||
#endif /* high speed crystal oscillator startup timeout */
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||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
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||||
#if !defined (IRC8M_VALUE)
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||||
#define IRC8M_VALUE ((uint32_t)8000000)
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||||
#endif /* internal 8MHz RC oscillator value */
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||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
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||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
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#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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||||
#endif /* internal 8MHz RC oscillator startup timeout */
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||||
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||||
/* define value of internal RC oscillator for ADC in Hz */
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||||
#if !defined (IRC28M_VALUE)
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||||
#define IRC28M_VALUE ((uint32_t)28000000)
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||||
#endif /* IRC28M_VALUE */
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||||
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||||
#if !defined (IRC48M_VALUE)
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||||
#define IRC48M_VALUE ((uint32_t)48000000)
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||||
#endif /* IRC48M_VALUE */
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||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
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||||
#if !defined (IRC40K_VALUE)
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||||
#define IRC40K_VALUE ((uint32_t)40000)
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||||
#endif /* internal 40KHz RC oscillator value */
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||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
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||||
#if !defined (LXTAL_VALUE)
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||||
#define LXTAL_VALUE ((uint32_t)32768)
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||||
#endif /* low speed crystal oscillator value */
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||||
|
||||
/* GD32E23x firmware library version number V1.0 */
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||||
#define __GD32E23x_STDPERIPH_VERSION_MAIN (0x02) /*!< [31:24] main version */
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||||
#define __GD32E23x_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
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||||
#define __GD32E23x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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||||
#define __GD32E23x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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||||
#define __GD32E23x_STDPERIPH_VERSION ((__GD32E23x_STDPERIPH_VERSION_MAIN << 24)\
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||||
|(__GD32E23x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M23 processor and core peripherals */
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||||
#define __CM23_REV 0x0100U /*!< Core revision r1p0 */
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||||
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
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||||
#define __MPU_PRESENT 0U /*!< MPU is present */
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||||
#define __VTOR_PRESENT 1U /*!< VTOR is present */
|
||||
#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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||||
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M23 processor exceptions numbers */
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||||
NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
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||||
HardFault_IRQn = -13, /*!< hardfault interrupt */
|
||||
|
||||
SVCall_IRQn = -5, /*!< sv call interrupt */
|
||||
|
||||
PendSV_IRQn = -2, /*!< pend sv interrupt */
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||||
SysTick_IRQn = -1, /*!< system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 3, /*!< FMC interrupt */
|
||||
RCU_IRQn = 4, /*!< RCU interrupt */
|
||||
EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
|
||||
EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
|
||||
EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
|
||||
DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
|
||||
DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
|
||||
DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
|
||||
ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */
|
||||
TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
|
||||
TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
|
||||
TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
|
||||
TIMER5_IRQn = 17, /*!< TIMER5 interrupt */
|
||||
TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
|
||||
TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
|
||||
TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
|
||||
TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
|
||||
I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
|
||||
I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
|
||||
SPI0_IRQn = 25, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 26, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 27, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 28, /*!< USART1 interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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||||
} IRQn_Type;
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||||
|
||||
/* includes */
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||||
#include "core_cm23.h"
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#include "system_gd32e23x.h"
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||||
#include <stdint.h>
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||||
|
||||
/* enum definitions */
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||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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||||
|
||||
/* bit operations */
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||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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||||
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||||
/* main flash and SRAM memory map */
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||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
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/* SRAM and peripheral base bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
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||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
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||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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||||
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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||||
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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||||
/* advanced peripheral bus 2 memory map */
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||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
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||||
#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
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||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
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#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
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||||
/* advanced high performance bus 1 memory map */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
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#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
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#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
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||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
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||||
/* advanced high performance bus 2 memory map */
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||||
#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
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||||
/* option byte and debug memory map */
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||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
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||||
#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */
|
||||
|
||||
#include "gd32e23x_libopt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GD32E23X_H */
|
||||
/*!
|
||||
\file gd32e23x.h
|
||||
\brief general definitions for GD32E23x
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef GD32E23X_H
|
||||
#define GD32E23X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32E23x */
|
||||
#if !defined (GD32E23x)
|
||||
#define GD32E23x
|
||||
#endif /* define GD32E23x */
|
||||
#if !defined (GD32E23x)
|
||||
#error "Please select the target GD32E23x device used in your application (in gd32e23x.h file)"
|
||||
#endif /* undefine GD32E23x tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined (HXTAL_VALUE)
|
||||
#define HXTAL_VALUE ((uint32_t)8000000)
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||
#if !defined (IRC8M_VALUE)
|
||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||
#endif /* internal 8MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal RC oscillator for ADC in Hz */
|
||||
#if !defined (IRC28M_VALUE)
|
||||
#define IRC28M_VALUE ((uint32_t)28000000)
|
||||
#endif /* IRC28M_VALUE */
|
||||
|
||||
#if !defined (IRC48M_VALUE)
|
||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||
#endif /* IRC48M_VALUE */
|
||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||
#if !defined (IRC40K_VALUE)
|
||||
#define IRC40K_VALUE ((uint32_t)40000)
|
||||
#endif /* internal 40KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* GD32E23x firmware library version number V1.0 */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_MAIN (0x02) /*!< [31:24] main version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32E23x_STDPERIPH_VERSION ((__GD32E23x_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M23 processor and core peripherals */
|
||||
#define __CM23_REV 0x0100U /*!< Core revision r1p0 */
|
||||
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
|
||||
#define __MPU_PRESENT 0U /*!< MPU is present */
|
||||
#define __VTOR_PRESENT 1U /*!< VTOR is present */
|
||||
#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M23 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
|
||||
HardFault_IRQn = -13, /*!< hardfault interrupt */
|
||||
|
||||
SVCall_IRQn = -5, /*!< sv call interrupt */
|
||||
|
||||
PendSV_IRQn = -2, /*!< pend sv interrupt */
|
||||
SysTick_IRQn = -1, /*!< system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 3, /*!< FMC interrupt */
|
||||
RCU_IRQn = 4, /*!< RCU interrupt */
|
||||
EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
|
||||
EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
|
||||
EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
|
||||
DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
|
||||
DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
|
||||
DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
|
||||
ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */
|
||||
TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
|
||||
TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
|
||||
TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
|
||||
TIMER5_IRQn = 17, /*!< TIMER5 interrupt */
|
||||
TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
|
||||
TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
|
||||
TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
|
||||
TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
|
||||
I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
|
||||
I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
|
||||
SPI0_IRQn = 25, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 26, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 27, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 28, /*!< USART1 interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm23.h"
|
||||
#include "system_gd32e23x.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
|
||||
/* SRAM and peripheral base bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
|
||||
#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
|
||||
#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */
|
||||
|
||||
#include "gd32e23x_libopt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GD32E23X_H */
|
||||
|
||||
@@ -1,66 +1,66 @@
|
||||
/*!
|
||||
\file system_gd32e23x.h
|
||||
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for
|
||||
GD32E23x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32E23X_H
|
||||
#define SYSTEM_GD32E23X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* firmware version can be acquired by uncommenting the macro */
|
||||
#define __FIRMWARE_VERSION_DEFINE
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/* get firmware version */
|
||||
extern uint32_t gd32e23x_firmware_version_get(void);
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32E23X_H */
|
||||
/*!
|
||||
\file system_gd32e23x.h
|
||||
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for
|
||||
GD32E23x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32E23X_H
|
||||
#define SYSTEM_GD32E23X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* firmware version can be acquired by uncommenting the macro */
|
||||
#define __FIRMWARE_VERSION_DEFINE
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/* get firmware version */
|
||||
extern uint32_t gd32e23x_firmware_version_get(void);
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32E23X_H */
|
||||
|
||||
@@ -1,270 +1,270 @@
|
||||
;/*!
|
||||
; \file startup_gd32e23x.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 19:FMC
|
||||
DCD RCU_IRQHandler ; 20:RCU
|
||||
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER2_IRQHandler ; 32:TIMER2
|
||||
DCD TIMER5_IRQHandler ; 33:TIMER5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; 35:TIMER13
|
||||
DCD TIMER14_IRQHandler ; 36:TIMER14
|
||||
DCD TIMER15_IRQHandler ; 37:TIMER15
|
||||
DCD TIMER16_IRQHandler ; 38:TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
|
||||
DCD SPI0_IRQHandler ; 41:SPI0
|
||||
DCD SPI1_IRQHandler ; 42:SPI1
|
||||
DCD USART0_IRQHandler ; 43:USART0
|
||||
DCD USART1_IRQHandler ; 44:USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x1FFFF7E0
|
||||
LDR R2, [R0]
|
||||
LDR R0, = 0xFFFF0000
|
||||
ANDS R2, R2, R0
|
||||
LSRS R2, R2, #16
|
||||
LSLS R2, R2, #10
|
||||
LDR R1, =0x20000000
|
||||
MOV R0, #0x00
|
||||
SRAM_INIT STM R1!, {R0}
|
||||
SUBS R2, R2, #4
|
||||
CMP R2, #0x00
|
||||
BNE SRAM_INIT
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_15_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel1_2_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel3_4_IRQHandler [WEAK]
|
||||
EXPORT ADC_CMP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER14_IRQHandler [WEAK]
|
||||
EXPORT TIMER15_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_IRQHandler
|
||||
EXTI0_1_IRQHandler
|
||||
EXTI2_3_IRQHandler
|
||||
EXTI4_15_IRQHandler
|
||||
DMA_Channel0_IRQHandler
|
||||
DMA_Channel1_2_IRQHandler
|
||||
DMA_Channel3_4_IRQHandler
|
||||
ADC_CMP_IRQHandler
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER13_IRQHandler
|
||||
TIMER14_IRQHandler
|
||||
TIMER15_IRQHandler
|
||||
TIMER16_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
;/*!
|
||||
; \file startup_gd32e23x.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 19:FMC
|
||||
DCD RCU_IRQHandler ; 20:RCU
|
||||
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER2_IRQHandler ; 32:TIMER2
|
||||
DCD TIMER5_IRQHandler ; 33:TIMER5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; 35:TIMER13
|
||||
DCD TIMER14_IRQHandler ; 36:TIMER14
|
||||
DCD TIMER15_IRQHandler ; 37:TIMER15
|
||||
DCD TIMER16_IRQHandler ; 38:TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
|
||||
DCD SPI0_IRQHandler ; 41:SPI0
|
||||
DCD SPI1_IRQHandler ; 42:SPI1
|
||||
DCD USART0_IRQHandler ; 43:USART0
|
||||
DCD USART1_IRQHandler ; 44:USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
|
||||
LDR R0, =0x1FFFF7E0
|
||||
LDR R2, [R0]
|
||||
LDR R0, = 0xFFFF0000
|
||||
ANDS R2, R2, R0
|
||||
LSRS R2, R2, #16
|
||||
LSLS R2, R2, #10
|
||||
LDR R1, =0x20000000
|
||||
MOV R0, #0x00
|
||||
SRAM_INIT STM R1!, {R0}
|
||||
SUBS R2, R2, #4
|
||||
CMP R2, #0x00
|
||||
BNE SRAM_INIT
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler\
|
||||
PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler\
|
||||
PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_15_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel1_2_IRQHandler [WEAK]
|
||||
EXPORT DMA_Channel3_4_IRQHandler [WEAK]
|
||||
EXPORT ADC_CMP_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_IRQHandler [WEAK]
|
||||
EXPORT TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER14_IRQHandler [WEAK]
|
||||
EXPORT TIMER15_IRQHandler [WEAK]
|
||||
EXPORT TIMER16_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_IRQHandler
|
||||
EXTI0_1_IRQHandler
|
||||
EXTI2_3_IRQHandler
|
||||
EXTI4_15_IRQHandler
|
||||
DMA_Channel0_IRQHandler
|
||||
DMA_Channel1_2_IRQHandler
|
||||
DMA_Channel3_4_IRQHandler
|
||||
ADC_CMP_IRQHandler
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER5_IRQHandler
|
||||
TIMER13_IRQHandler
|
||||
TIMER14_IRQHandler
|
||||
TIMER15_IRQHandler
|
||||
TIMER16_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
@@ -1,296 +1,296 @@
|
||||
;/*!
|
||||
; \file startup_gd32e23x.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 19:FMC
|
||||
DCD RCU_IRQHandler ; 20:RCU
|
||||
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER2_IRQHandler ; 32:TIMER2
|
||||
DCD TIMER5_IRQHandler ; 33:TIMER5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; 35:TIMER13
|
||||
DCD TIMER14_IRQHandler ; 36:TIMER14
|
||||
DCD TIMER15_IRQHandler ; 37:TIMER15
|
||||
DCD TIMER16_IRQHandler ; 38:TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
|
||||
DCD SPI0_IRQHandler ; 41:SPI0
|
||||
DCD SPI1_IRQHandler ; 42:SPI1
|
||||
DCD USART0_IRQHandler ; 43:USART0
|
||||
DCD USART1_IRQHandler ; 44:USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =0x1FFFF7E0
|
||||
LDR R2, [R0]
|
||||
LDR R0, = 0xFFFF0000
|
||||
ANDS R2, R2, R0
|
||||
LSRS R2, R2, #16
|
||||
LSLS R2, R2, #10
|
||||
LDR R1, =0x20000000
|
||||
MOV R0, #0x00
|
||||
SRAM_INIT STM R1!, {R0}
|
||||
SUBS R2, R2, #4
|
||||
CMP R2, #0x00
|
||||
BNE SRAM_INIT
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_1_IRQHandler
|
||||
B EXTI0_1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_3_IRQHandler
|
||||
B EXTI2_3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_15_IRQHandler
|
||||
B EXTI4_15_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel0_IRQHandler
|
||||
B DMA_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel1_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel1_2_IRQHandler
|
||||
B DMA_Channel1_2_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel3_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel3_4_IRQHandler
|
||||
B DMA_Channel3_4_IRQHandler
|
||||
|
||||
PUBWEAK ADC_CMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_CMP_IRQHandler
|
||||
B ADC_CMP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
B TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER13_IRQHandler
|
||||
B TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER14_IRQHandler
|
||||
B TIMER14_IRQHandler
|
||||
|
||||
PUBWEAK TIMER15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER15_IRQHandler
|
||||
B TIMER15_IRQHandler
|
||||
|
||||
PUBWEAK TIMER16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER16_IRQHandler
|
||||
B TIMER16_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
;/*!
|
||||
; \file startup_gd32e23x.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
;*/
|
||||
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
;*/
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
|
||||
DCD FMC_IRQHandler ; 19:FMC
|
||||
DCD RCU_IRQHandler ; 20:RCU
|
||||
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
|
||||
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
|
||||
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
|
||||
DCD 0 ; Reserved
|
||||
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
|
||||
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
|
||||
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
|
||||
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
|
||||
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
|
||||
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER2_IRQHandler ; 32:TIMER2
|
||||
DCD TIMER5_IRQHandler ; 33:TIMER5
|
||||
DCD 0 ; Reserved
|
||||
DCD TIMER13_IRQHandler ; 35:TIMER13
|
||||
DCD TIMER14_IRQHandler ; 36:TIMER14
|
||||
DCD TIMER15_IRQHandler ; 37:TIMER15
|
||||
DCD TIMER16_IRQHandler ; 38:TIMER16
|
||||
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
|
||||
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
|
||||
DCD SPI0_IRQHandler ; 41:SPI0
|
||||
DCD SPI1_IRQHandler ; 42:SPI1
|
||||
DCD USART0_IRQHandler ; 43:USART0
|
||||
DCD USART1_IRQHandler ; 44:USART1
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD 0 ; Reserved
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =0x1FFFF7E0
|
||||
LDR R2, [R0]
|
||||
LDR R0, = 0xFFFF0000
|
||||
ANDS R2, R2, R0
|
||||
LSRS R2, R2, #16
|
||||
LSLS R2, R2, #10
|
||||
LDR R1, =0x20000000
|
||||
MOV R0, #0x00
|
||||
SRAM_INIT STM R1!, {R0}
|
||||
SUBS R2, R2, #4
|
||||
CMP R2, #0x00
|
||||
BNE SRAM_INIT
|
||||
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_IRQHandler
|
||||
B RCU_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_1_IRQHandler
|
||||
B EXTI0_1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_3_IRQHandler
|
||||
B EXTI2_3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_15_IRQHandler
|
||||
B EXTI4_15_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel0_IRQHandler
|
||||
B DMA_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel1_2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel1_2_IRQHandler
|
||||
B DMA_Channel1_2_IRQHandler
|
||||
|
||||
PUBWEAK DMA_Channel3_4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA_Channel3_4_IRQHandler
|
||||
B DMA_Channel3_4_IRQHandler
|
||||
|
||||
PUBWEAK ADC_CMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_CMP_IRQHandler
|
||||
B ADC_CMP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
B TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_IRQHandler
|
||||
B TIMER5_IRQHandler
|
||||
|
||||
PUBWEAK TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER13_IRQHandler
|
||||
B TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER14_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER14_IRQHandler
|
||||
B TIMER14_IRQHandler
|
||||
|
||||
PUBWEAK TIMER15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER15_IRQHandler
|
||||
B TIMER15_IRQHandler
|
||||
|
||||
PUBWEAK TIMER16_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER16_IRQHandler
|
||||
B TIMER16_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
END
|
||||
@@ -1,451 +1,451 @@
|
||||
/*!
|
||||
\file system_gd32e23x.c
|
||||
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for
|
||||
GD32E23x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
|
||||
|
||||
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
|
||||
|
||||
/* select a system clock by uncommenting the following line */
|
||||
//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
|
||||
//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
|
||||
#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
|
||||
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
|
||||
|
||||
/* The following is to prevent Vcore fluctuations caused by frequency switching.
|
||||
It is strongly recommended to include it to avoid issues caused by self-removal.
|
||||
*/
|
||||
#define RCU_MODIFY(__delay) do{ \
|
||||
volatile uint32_t i,reg; \
|
||||
if(0 != __delay){ \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
/* CK_AHB = SYSCLK/2 */ \
|
||||
reg |= RCU_AHB_CKSYS_DIV2; \
|
||||
RCU_CFG0 = reg; \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV4; \
|
||||
/* CK_AHB = SYSCLK/4 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
#define SEL_IRC8M 0x00
|
||||
#define SEL_HXTAL 0x01
|
||||
#define SEL_PLL 0x02
|
||||
|
||||
/* set the system clock frequency and declare the system clock configuration function */
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
|
||||
static void system_clock_8m_hxtal(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
|
||||
static void system_clock_72m_hxtal(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
|
||||
static void system_clock_72m_irc8m(void);
|
||||
|
||||
#else
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
|
||||
static void system_clock_8m_irc8m(void);
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/* software delay to prevent the impact of Vcore fluctuations.
|
||||
It is strongly recommended to include it to avoid issues caused by self-removal. */
|
||||
static void _soft_delay_(uint32_t time)
|
||||
{
|
||||
__IO uint32_t i;
|
||||
for(i=0; i<time*10; i++){
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
}
|
||||
if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLL)){
|
||||
RCU_MODIFY(0x80);
|
||||
}
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
_soft_delay_(100);
|
||||
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
|
||||
/* reset RCU */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
|
||||
RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
|
||||
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
|
||||
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
|
||||
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
|
||||
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
|
||||
RCU_INT = 0x00000000U;
|
||||
|
||||
/* configure system clock */
|
||||
system_clock_config();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
|
||||
#else
|
||||
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
system_clock_8m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
system_clock_72m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
system_clock_72m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
|
||||
system_clock_72m_irc48m();
|
||||
#else
|
||||
system_clock_8m_irc8m();
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
}
|
||||
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
/*!
|
||||
\brief configure the system clock to 8M by HXTAL
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_8m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select HXTAL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_HXTAL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until HXTAL is selected as system clock */
|
||||
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* PLL = HXTAL * 9 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||||
}
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select PLL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_PLL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
/* PLL = (IRC8M/2) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||||
}
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select PLL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_PLL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/*!
|
||||
\brief configure the system clock to 8M by IRC8M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_8m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select IRC8M as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_IRC8M;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until IRC8M is selected as system clock */
|
||||
while(RCU_SCSS_IRC8M != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t sws = 0U;
|
||||
uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
|
||||
/* exponent of AHB clock divider */
|
||||
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||||
switch(sws){
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
case SEL_IRC8M:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
/* PLL is selected as CK_SYS */
|
||||
case SEL_PLL:
|
||||
/* get the value of PLLMF[3:0] */
|
||||
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
||||
pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
|
||||
/* high 16 bits */
|
||||
if(1U == pllmf4){
|
||||
pllmf += 17U;
|
||||
}else if(15U == pllmf){
|
||||
pllmf = 16U;
|
||||
} else {
|
||||
pllmf += 2U;
|
||||
}
|
||||
|
||||
/* PLL clock source selection, HXTAL or IRC8M/2 */
|
||||
pllsel = GET_BITS(RCU_CFG0, 16, 16);
|
||||
if(0U != pllsel){
|
||||
prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
|
||||
SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
|
||||
} else {
|
||||
SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
|
||||
}
|
||||
break;
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
default:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
}
|
||||
/* calculate AHB clock frequency */
|
||||
idx = GET_BITS(RCU_CFG0, 4, 7);
|
||||
clk_exp = ahb_exp[idx];
|
||||
SystemCoreClock >>= clk_exp;
|
||||
}
|
||||
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/*!
|
||||
\brief get firmware version
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval firmware version
|
||||
*/
|
||||
uint32_t gd32e23x_firmware_version_get(void)
|
||||
{
|
||||
return __GD32E23x_STDPERIPH_VERSION;
|
||||
}
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
/*!
|
||||
\file system_gd32e23x.c
|
||||
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for
|
||||
GD32E23x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* system frequency define */
|
||||
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
|
||||
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
|
||||
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
|
||||
|
||||
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
|
||||
|
||||
/* select a system clock by uncommenting the following line */
|
||||
//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
|
||||
//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
|
||||
#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
|
||||
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
|
||||
|
||||
/* The following is to prevent Vcore fluctuations caused by frequency switching.
|
||||
It is strongly recommended to include it to avoid issues caused by self-removal.
|
||||
*/
|
||||
#define RCU_MODIFY(__delay) do{ \
|
||||
volatile uint32_t i,reg; \
|
||||
if(0 != __delay){ \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
/* CK_AHB = SYSCLK/2 */ \
|
||||
reg |= RCU_AHB_CKSYS_DIV2; \
|
||||
RCU_CFG0 = reg; \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
reg = RCU_CFG0; \
|
||||
reg &= ~(RCU_CFG0_AHBPSC); \
|
||||
reg |= RCU_AHB_CKSYS_DIV4; \
|
||||
/* CK_AHB = SYSCLK/4 */ \
|
||||
RCU_CFG0 = reg; \
|
||||
for(i=0; i<__delay; i++){ \
|
||||
} \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
#define SEL_IRC8M 0x00
|
||||
#define SEL_HXTAL 0x01
|
||||
#define SEL_PLL 0x02
|
||||
|
||||
/* set the system clock frequency and declare the system clock configuration function */
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
|
||||
static void system_clock_8m_hxtal(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
|
||||
static void system_clock_72m_hxtal(void);
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
|
||||
static void system_clock_72m_irc8m(void);
|
||||
|
||||
#else
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
|
||||
static void system_clock_8m_irc8m(void);
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
|
||||
/* configure the system clock */
|
||||
static void system_clock_config(void);
|
||||
|
||||
/* software delay to prevent the impact of Vcore fluctuations.
|
||||
It is strongly recommended to include it to avoid issues caused by self-removal. */
|
||||
static void _soft_delay_(uint32_t time)
|
||||
{
|
||||
__IO uint32_t i;
|
||||
for(i=0; i<time*10; i++){
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief setup the microcontroller system, initialize the system
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
}
|
||||
if(((RCU_CFG0 & RCU_CFG0_SCSS) == RCU_SCSS_PLL)){
|
||||
RCU_MODIFY(0x80);
|
||||
}
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
_soft_delay_(100);
|
||||
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
|
||||
/* reset RCU */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
|
||||
RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
|
||||
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
|
||||
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
|
||||
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
|
||||
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
|
||||
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
|
||||
RCU_INT = 0x00000000U;
|
||||
|
||||
/* configure system clock */
|
||||
system_clock_config();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
|
||||
#else
|
||||
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the system clock
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_config(void)
|
||||
{
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
system_clock_8m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
system_clock_72m_hxtal();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
system_clock_72m_irc8m();
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
|
||||
system_clock_72m_irc48m();
|
||||
#else
|
||||
system_clock_8m_irc8m();
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
}
|
||||
|
||||
#ifdef __SYSTEM_CLOCK_8M_HXTAL
|
||||
/*!
|
||||
\brief configure the system clock to 8M by HXTAL
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_8m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select HXTAL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_HXTAL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until HXTAL is selected as system clock */
|
||||
while(RCU_SCSS_HXTAL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_hxtal(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable HXTAL */
|
||||
RCU_CTL0 |= RCU_CTL0_HXTALEN;
|
||||
|
||||
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
|
||||
|
||||
/* HXTAL is stable */
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
/* PLL = HXTAL * 9 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||||
}
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select PLL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_PLL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
|
||||
/*!
|
||||
\brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_72m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
FMC_WS = (FMC_WS & (~FMC_WS_WSCNT)) | WS_WSCNT_2;
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
/* PLL = (IRC8M/2) * 18 = 72 MHz */
|
||||
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
|
||||
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
|
||||
|
||||
/* enable PLL */
|
||||
RCU_CTL0 |= RCU_CTL0_PLLEN;
|
||||
|
||||
/* wait until PLL is stable */
|
||||
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
|
||||
}
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select PLL as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_PLL;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until PLL is selected as system clock */
|
||||
while(RCU_SCSS_PLL != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
/*!
|
||||
\brief configure the system clock to 8M by IRC8M
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
static void system_clock_8m_irc8m(void)
|
||||
{
|
||||
uint32_t timeout = 0U;
|
||||
uint32_t stab_flag = 0U;
|
||||
__IO uint32_t reg_temp;
|
||||
|
||||
/* enable IRC8M */
|
||||
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
|
||||
|
||||
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
|
||||
do{
|
||||
timeout++;
|
||||
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
|
||||
}
|
||||
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
|
||||
|
||||
/* if fail */
|
||||
if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
|
||||
while(1){
|
||||
}
|
||||
}
|
||||
|
||||
/* AHB = SYSCLK */
|
||||
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
|
||||
/* APB2 = AHB */
|
||||
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
|
||||
/* APB1 = AHB */
|
||||
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
|
||||
|
||||
reg_temp = RCU_CFG0;
|
||||
/* select IRC8M as system clock */
|
||||
reg_temp &= ~RCU_CFG0_SCS;
|
||||
reg_temp |= RCU_CKSYSSRC_IRC8M;
|
||||
RCU_CFG0 = reg_temp;
|
||||
|
||||
/* wait until IRC8M is selected as system clock */
|
||||
while(RCU_SCSS_IRC8M != (RCU_CFG0 & RCU_CFG0_SCSS)){
|
||||
}
|
||||
}
|
||||
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
|
||||
|
||||
/*!
|
||||
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t sws = 0U;
|
||||
uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
|
||||
/* exponent of AHB clock divider */
|
||||
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
sws = GET_BITS(RCU_CFG0, 2, 3);
|
||||
switch(sws){
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
case SEL_IRC8M:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
/* HXTAL is selected as CK_SYS */
|
||||
case SEL_HXTAL:
|
||||
SystemCoreClock = HXTAL_VALUE;
|
||||
break;
|
||||
/* PLL is selected as CK_SYS */
|
||||
case SEL_PLL:
|
||||
/* get the value of PLLMF[3:0] */
|
||||
pllmf = GET_BITS(RCU_CFG0, 18, 21);
|
||||
pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
|
||||
/* high 16 bits */
|
||||
if(1U == pllmf4){
|
||||
pllmf += 17U;
|
||||
}else if(15U == pllmf){
|
||||
pllmf = 16U;
|
||||
} else {
|
||||
pllmf += 2U;
|
||||
}
|
||||
|
||||
/* PLL clock source selection, HXTAL or IRC8M/2 */
|
||||
pllsel = GET_BITS(RCU_CFG0, 16, 16);
|
||||
if(0U != pllsel){
|
||||
prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
|
||||
SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
|
||||
} else {
|
||||
SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
|
||||
}
|
||||
break;
|
||||
/* IRC8M is selected as CK_SYS */
|
||||
default:
|
||||
SystemCoreClock = IRC8M_VALUE;
|
||||
break;
|
||||
}
|
||||
/* calculate AHB clock frequency */
|
||||
idx = GET_BITS(RCU_CFG0, 4, 7);
|
||||
clk_exp = ahb_exp[idx];
|
||||
SystemCoreClock >>= clk_exp;
|
||||
}
|
||||
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/*!
|
||||
\brief get firmware version
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval firmware version
|
||||
*/
|
||||
uint32_t gd32e23x_firmware_version_get(void)
|
||||
{
|
||||
return __GD32E23x_STDPERIPH_VERSION;
|
||||
}
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
|
||||
+707
-707
File diff suppressed because it is too large
Load Diff
+708
-708
File diff suppressed because it is too large
Load Diff
+292
-292
@@ -1,292 +1,292 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Compiler Generic Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
/*
|
||||
* TI Arm Clang Compiler (tiarmclang)
|
||||
*/
|
||||
#elif defined (__ti__)
|
||||
#include "cmsis_tiarmclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* LLVM/Clang Compiler
|
||||
*/
|
||||
#elif defined ( __clang__ )
|
||||
#include "cmsis_clang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "a-profile/cmsis_iccarm_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "r-profile/cmsis_iccarm_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_iccarm_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler (armcl)
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Compiler Generic Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
/*
|
||||
* TI Arm Clang Compiler (tiarmclang)
|
||||
*/
|
||||
#elif defined (__ti__)
|
||||
#include "cmsis_tiarmclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* LLVM/Clang Compiler
|
||||
*/
|
||||
#elif defined ( __clang__ )
|
||||
#include "cmsis_clang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "a-profile/cmsis_iccarm_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "r-profile/cmsis_iccarm_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_iccarm_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler (armcl)
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
|
||||
+1006
-1006
File diff suppressed because it is too large
Load Diff
+44
-44
@@ -1,44 +1,44 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Core Version Definitions
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS-Core(M) Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */
|
||||
|
||||
/* CMSIS-Core(A) Version definitions */
|
||||
#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */
|
||||
#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
|
||||
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Core Version Definitions
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS-Core(M) Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */
|
||||
|
||||
/* CMSIS-Core(A) Version definitions */
|
||||
#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */
|
||||
#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
|
||||
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
|
||||
|
||||
#endif
|
||||
|
||||
+2253
-2253
File diff suppressed because it is too large
Load Diff
@@ -1,439 +1,439 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) Level 1 Cache API for Armv7-M and later
|
||||
*/
|
||||
|
||||
#ifndef ARM_ARMV7M_CACHEL1_H
|
||||
#define ARM_ARMV7M_CACHEL1_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
struct {
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
} locals
|
||||
#if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
|
||||
__ALIGNED(__SCB_DCACHE_LINE_SIZE)
|
||||
#endif
|
||||
;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
#if !defined(__OPTIMIZE__)
|
||||
/*
|
||||
* For the endless loop issue with no optimization builds.
|
||||
* More details, see https://github.com/ARM-software/CMSIS_5/issues/620
|
||||
*
|
||||
* The issue only happens when local variables are in stack. If
|
||||
* local variables are saved in general purpose register, then the function
|
||||
* is OK.
|
||||
*
|
||||
* When local variables are in stack, after disabling the cache, flush the
|
||||
* local variables cache line for data consistency.
|
||||
*/
|
||||
/* Clean and invalidate the local variable cache. */
|
||||
#if defined(__ICCARM__)
|
||||
/* As we can't align the stack to the cache line size, invalidate each of the variables */
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.sets;
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.ways;
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
|
||||
#else
|
||||
SCB->DCCIMVAC = (uint32_t)&locals;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
locals.ccsidr = SCB->CCSIDR;
|
||||
/* clean & invalidate D-Cache */
|
||||
locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
|
||||
do {
|
||||
locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (locals.ways-- != 0U);
|
||||
} while(locals.sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_ARMV7M_CACHEL1_H */
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) Level 1 Cache API for Armv7-M and later
|
||||
*/
|
||||
|
||||
#ifndef ARM_ARMV7M_CACHEL1_H
|
||||
#define ARM_ARMV7M_CACHEL1_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
struct {
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
} locals
|
||||
#if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
|
||||
__ALIGNED(__SCB_DCACHE_LINE_SIZE)
|
||||
#endif
|
||||
;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
#if !defined(__OPTIMIZE__)
|
||||
/*
|
||||
* For the endless loop issue with no optimization builds.
|
||||
* More details, see https://github.com/ARM-software/CMSIS_5/issues/620
|
||||
*
|
||||
* The issue only happens when local variables are in stack. If
|
||||
* local variables are saved in general purpose register, then the function
|
||||
* is OK.
|
||||
*
|
||||
* When local variables are in stack, after disabling the cache, flush the
|
||||
* local variables cache line for data consistency.
|
||||
*/
|
||||
/* Clean and invalidate the local variable cache. */
|
||||
#if defined(__ICCARM__)
|
||||
/* As we can't align the stack to the cache line size, invalidate each of the variables */
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.sets;
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.ways;
|
||||
SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
|
||||
#else
|
||||
SCB->DCCIMVAC = (uint32_t)&locals;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
|
||||
locals.ccsidr = SCB->CCSIDR;
|
||||
/* clean & invalidate D-Cache */
|
||||
locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
|
||||
do {
|
||||
locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (locals.ways-- != 0U);
|
||||
} while(locals.sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_ARMV7M_CACHEL1_H */
|
||||
|
||||
+273
-273
@@ -1,273 +1,273 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv7-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv7-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+203
-203
@@ -1,203 +1,203 @@
|
||||
/*
|
||||
* Copyright (c) 2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension
|
||||
*/
|
||||
|
||||
#ifndef PAC_ARMV81_H
|
||||
#define PAC_ARMV81_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/* ################### PAC Key functions ########################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
|
||||
\brief Functions that access the PAC keys.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_P registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_P registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_U registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_U registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
|
||||
|
||||
/*@} end of CMSIS_Core_PacKeyFunctions */
|
||||
|
||||
|
||||
#endif /* PAC_ARMV81_H */
|
||||
/*
|
||||
* Copyright (c) 2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension
|
||||
*/
|
||||
|
||||
#ifndef PAC_ARMV81_H
|
||||
#define PAC_ARMV81_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/* ################### PAC Key functions ########################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_PacKeyFunctions PAC Key functions
|
||||
\brief Functions that access the PAC keys.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_P registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_P registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode
|
||||
\details Reads the PAC key stored in the PAC_KEY_U registers.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode
|
||||
\details writes the given PAC key to the PAC_KEY_U registers.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for privileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_p_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_p_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_p_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_p_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for privileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_p_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_p_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_p_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_p_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief read the PAC key used for unprivileged mode (non-secure)
|
||||
\details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [out] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"mrs r1, pac_key_u_0_ns\n"
|
||||
"str r1,[%0,#0]\n"
|
||||
"mrs r1, pac_key_u_1_ns\n"
|
||||
"str r1,[%0,#4]\n"
|
||||
"mrs r1, pac_key_u_2_ns\n"
|
||||
"str r1,[%0,#8]\n"
|
||||
"mrs r1, pac_key_u_3_ns\n"
|
||||
"str r1,[%0,#12]\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief write the PAC key used for unprivileged mode (non-secure)
|
||||
\details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode.
|
||||
\param [in] pPacKey 128bit PAC key
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) {
|
||||
__ASM volatile (
|
||||
"ldr r1,[%0,#0]\n"
|
||||
"msr pac_key_u_0_ns, r1\n"
|
||||
"ldr r1,[%0,#4]\n"
|
||||
"msr pac_key_u_1_ns, r1\n"
|
||||
"ldr r1,[%0,#8]\n"
|
||||
"msr pac_key_u_2_ns, r1\n"
|
||||
"ldr r1,[%0,#12]\n"
|
||||
"msr pac_key_u_3_ns, r1\n"
|
||||
: : "r" (pPacKey) : "memory", "r1"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */
|
||||
|
||||
#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */
|
||||
|
||||
/*@} end of CMSIS_Core_PacKeyFunctions */
|
||||
|
||||
|
||||
#endif /* PAC_ARMV81_H */
|
||||
|
||||
+421
-421
@@ -1,421 +1,421 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for Normal memory, Outer and Inner cacheability.
|
||||
* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
|
||||
* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
|
||||
* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Normal memory outer-cacheable and inner-cacheable attributes
|
||||
* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
|
||||
*/
|
||||
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
|
||||
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/* \brief Specifies MAIR_ATTR number */
|
||||
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
|
||||
|
||||
/**
|
||||
* Shareability
|
||||
*/
|
||||
/** \brief Normal memory, non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory, outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory, inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/**
|
||||
* Access permissions
|
||||
* AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
|
||||
*/
|
||||
/** \brief Normal memory, read/write */
|
||||
#define ARM_MPU_AP_RW (0U)
|
||||
|
||||
/** \brief Normal memory, read-only */
|
||||
#define ARM_MPU_AP_RO (1U)
|
||||
|
||||
/** \brief Normal memory, any privilege level */
|
||||
#define ARM_MPU_AP_NP (1U)
|
||||
|
||||
/** \brief Normal memory, privileged access only */
|
||||
#define ARM_MPU_AP_PO (0U)
|
||||
|
||||
/*
|
||||
* Execute-never
|
||||
* XN = Execute-never, EX = Executable
|
||||
*/
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_XN (1U)
|
||||
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_EX (0U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
|
||||
* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/**
|
||||
\brief Read MPU Type Register
|
||||
\return Number of MPU regions
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_MPU_TYPE()
|
||||
{
|
||||
return ((MPU->TYPE) >> 8);
|
||||
}
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Copyright (c) 2017-2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for Normal memory, Outer and Inner cacheability.
|
||||
* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
|
||||
* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
|
||||
* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Normal memory outer-cacheable and inner-cacheable attributes
|
||||
* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
|
||||
*/
|
||||
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110)
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111)
|
||||
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001)
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110)
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/* \brief Specifies MAIR_ATTR number */
|
||||
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
|
||||
|
||||
/**
|
||||
* Shareability
|
||||
*/
|
||||
/** \brief Normal memory, non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory, outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory, inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/**
|
||||
* Access permissions
|
||||
* AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
|
||||
*/
|
||||
/** \brief Normal memory, read/write */
|
||||
#define ARM_MPU_AP_RW (0U)
|
||||
|
||||
/** \brief Normal memory, read-only */
|
||||
#define ARM_MPU_AP_RO (1U)
|
||||
|
||||
/** \brief Normal memory, any privilege level */
|
||||
#define ARM_MPU_AP_NP (1U)
|
||||
|
||||
/** \brief Normal memory, privileged access only */
|
||||
#define ARM_MPU_AP_PO (0U)
|
||||
|
||||
/*
|
||||
* Execute-never
|
||||
* XN = Execute-never, EX = Executable
|
||||
*/
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_XN (1U)
|
||||
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_EX (0U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
|
||||
* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/**
|
||||
\brief Read MPU Type Register
|
||||
\return Number of MPU regions
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_MPU_TYPE()
|
||||
{
|
||||
return ((MPU->TYPE) >> 8);
|
||||
}
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
+335
-335
@@ -1,335 +1,335 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PMU API for Armv8.1-M PMU
|
||||
*/
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PMU API for Armv8.1-M PMU
|
||||
*/
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
+824
-824
File diff suppressed because it is too large
Load Diff
+717
-717
File diff suppressed because it is too large
Load Diff
+1043
-1043
File diff suppressed because it is too large
Load Diff
+1451
-1451
File diff suppressed because it is too large
Load Diff
@@ -1,232 +1,232 @@
|
||||
.syntax unified
|
||||
.cpu cortex-m23
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* necessary symbols defined in linker script to initialize data */
|
||||
.word _sidata
|
||||
.word _sdata
|
||||
.word _edata
|
||||
.word _sbss
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
/* reset Handler */
|
||||
Reset_Handler:
|
||||
ldr r0, =_sp
|
||||
mov sp, r0
|
||||
/* copy the data segment into ram */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call SystemInit function */
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/*Call the main function */
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .vectors,"a",%progbits
|
||||
.global __gVectors
|
||||
|
||||
__gVectors:
|
||||
.word _sp /* Top of Stack */
|
||||
.word Reset_Handler /* 1:Reset Handler */
|
||||
.word NMI_Handler /* 2:NMI Handler */
|
||||
.word HardFault_Handler /* 3:Hard Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* 11:SVCall Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* 14:PendSV Handler */
|
||||
.word SysTick_Handler /* 15:SysTick Handler */
|
||||
|
||||
/* external interrupts handler */
|
||||
.word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
|
||||
.word RTC_IRQHandler /* 18:RTC through EXTI Line */
|
||||
.word FMC_IRQHandler /* 19:FMC */
|
||||
.word RCU_IRQHandler /* 20:RCU */
|
||||
.word EXTI0_1_IRQHandler /* 21:EXTI Line 0 and EXTI Line 1 */
|
||||
.word EXTI2_3_IRQHandler /* 22:EXTI Line 2 and EXTI Line 3 */
|
||||
.word EXTI4_15_IRQHandler /* 23:EXTI Line 4 to EXTI Line 15 */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA_Channel0_IRQHandler /* 25:DMA Channel 0 */
|
||||
.word DMA_Channel1_2_IRQHandler /* 26:DMA Channel 1 and DMA Channel 2 */
|
||||
.word DMA_Channel3_4_IRQHandler /* 27:DMA Channel 3 and DMA Channel 4 */
|
||||
.word ADC_CMP_IRQHandler /* 28:ADC and Comparator */
|
||||
.word TIMER0_BRK_UP_TRG_COM_IRQHandler /* 29:TIMER0 Break,Update,Trigger and Commutation */
|
||||
.word TIMER0_Channel_IRQHandler /* 30:TIMER0 Channel Capture Compare */
|
||||
.word 0 /* Reserved */
|
||||
.word TIMER2_IRQHandler /* 32:TIMER2 */
|
||||
.word TIMER5_IRQHandler /* 33:TIMER5 */
|
||||
.word 0 /* Reserved */
|
||||
.word TIMER13_IRQHandler /* 35:TIMER13 */
|
||||
.word TIMER14_IRQHandler /* 36:TIMER14 */
|
||||
.word TIMER15_IRQHandler /* 37:TIMER15 */
|
||||
.word TIMER16_IRQHandler /* 38:TIMER16 */
|
||||
.word I2C0_EV_IRQHandler /* 39:I2C0 Event */
|
||||
.word I2C1_EV_IRQHandler /* 40:I2C1 Event */
|
||||
.word SPI0_IRQHandler /* 41:SPI0 */
|
||||
.word SPI1_IRQHandler /* 42:SPI1 */
|
||||
.word USART0_IRQHandler /* 43:USART0 */
|
||||
.word USART1_IRQHandler /* 44:USART1 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word I2C0_ER_IRQHandler /* 48:I2C0 Error */
|
||||
.word 0 /* Reserved */
|
||||
.word I2C1_ER_IRQHandler /* 50:I2C1 Error */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_IRQHandler
|
||||
.thumb_set RCU_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_1_IRQHandler
|
||||
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_3_IRQHandler
|
||||
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_15_IRQHandler
|
||||
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel0_IRQHandler
|
||||
.thumb_set DMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel1_2_IRQHandler
|
||||
.thumb_set DMA_Channel1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel3_4_IRQHandler
|
||||
.thumb_set DMA_Channel3_4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_CMP_IRQHandler
|
||||
.thumb_set ADC_CMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
.thumb_set TIMER0_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_IRQHandler
|
||||
.thumb_set TIMER5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER13_IRQHandler
|
||||
.thumb_set TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER14_IRQHandler
|
||||
.thumb_set TIMER14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER15_IRQHandler
|
||||
.thumb_set TIMER15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER16_IRQHandler
|
||||
.thumb_set TIMER16_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
.syntax unified
|
||||
.cpu cortex-m23
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* necessary symbols defined in linker script to initialize data */
|
||||
.word _sidata
|
||||
.word _sdata
|
||||
.word _edata
|
||||
.word _sbss
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
/* reset Handler */
|
||||
Reset_Handler:
|
||||
ldr r0, =_sp
|
||||
mov sp, r0
|
||||
/* copy the data segment into ram */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2]
|
||||
adds r2, r2, #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call SystemInit function */
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/*Call the main function */
|
||||
bl main
|
||||
|
||||
LoopForever:
|
||||
b LoopForever
|
||||
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .vectors,"a",%progbits
|
||||
.global __gVectors
|
||||
|
||||
__gVectors:
|
||||
.word _sp /* Top of Stack */
|
||||
.word Reset_Handler /* 1:Reset Handler */
|
||||
.word NMI_Handler /* 2:NMI Handler */
|
||||
.word HardFault_Handler /* 3:Hard Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* 11:SVCall Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* 14:PendSV Handler */
|
||||
.word SysTick_Handler /* 15:SysTick Handler */
|
||||
|
||||
/* external interrupts handler */
|
||||
.word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
|
||||
.word RTC_IRQHandler /* 18:RTC through EXTI Line */
|
||||
.word FMC_IRQHandler /* 19:FMC */
|
||||
.word RCU_IRQHandler /* 20:RCU */
|
||||
.word EXTI0_1_IRQHandler /* 21:EXTI Line 0 and EXTI Line 1 */
|
||||
.word EXTI2_3_IRQHandler /* 22:EXTI Line 2 and EXTI Line 3 */
|
||||
.word EXTI4_15_IRQHandler /* 23:EXTI Line 4 to EXTI Line 15 */
|
||||
.word 0 /* Reserved */
|
||||
.word DMA_Channel0_IRQHandler /* 25:DMA Channel 0 */
|
||||
.word DMA_Channel1_2_IRQHandler /* 26:DMA Channel 1 and DMA Channel 2 */
|
||||
.word DMA_Channel3_4_IRQHandler /* 27:DMA Channel 3 and DMA Channel 4 */
|
||||
.word ADC_CMP_IRQHandler /* 28:ADC and Comparator */
|
||||
.word TIMER0_BRK_UP_TRG_COM_IRQHandler /* 29:TIMER0 Break,Update,Trigger and Commutation */
|
||||
.word TIMER0_Channel_IRQHandler /* 30:TIMER0 Channel Capture Compare */
|
||||
.word 0 /* Reserved */
|
||||
.word TIMER2_IRQHandler /* 32:TIMER2 */
|
||||
.word TIMER5_IRQHandler /* 33:TIMER5 */
|
||||
.word 0 /* Reserved */
|
||||
.word TIMER13_IRQHandler /* 35:TIMER13 */
|
||||
.word TIMER14_IRQHandler /* 36:TIMER14 */
|
||||
.word TIMER15_IRQHandler /* 37:TIMER15 */
|
||||
.word TIMER16_IRQHandler /* 38:TIMER16 */
|
||||
.word I2C0_EV_IRQHandler /* 39:I2C0 Event */
|
||||
.word I2C1_EV_IRQHandler /* 40:I2C1 Event */
|
||||
.word SPI0_IRQHandler /* 41:SPI0 */
|
||||
.word SPI1_IRQHandler /* 42:SPI1 */
|
||||
.word USART0_IRQHandler /* 43:USART0 */
|
||||
.word USART1_IRQHandler /* 44:USART1 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word I2C0_ER_IRQHandler /* 48:I2C0 Error */
|
||||
.word 0 /* Reserved */
|
||||
.word I2C1_ER_IRQHandler /* 50:I2C1 Error */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_IRQHandler
|
||||
.thumb_set RCU_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_1_IRQHandler
|
||||
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_3_IRQHandler
|
||||
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_15_IRQHandler
|
||||
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel0_IRQHandler
|
||||
.thumb_set DMA_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel1_2_IRQHandler
|
||||
.thumb_set DMA_Channel1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA_Channel3_4_IRQHandler
|
||||
.thumb_set DMA_Channel3_4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_CMP_IRQHandler
|
||||
.thumb_set ADC_CMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_UP_TRG_COM_IRQHandler
|
||||
.thumb_set TIMER0_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_IRQHandler
|
||||
.thumb_set TIMER5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER13_IRQHandler
|
||||
.thumb_set TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER14_IRQHandler
|
||||
.thumb_set TIMER14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER15_IRQHandler
|
||||
.thumb_set TIMER15_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER16_IRQHandler
|
||||
.thumb_set TIMER16_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
@@ -1,30 +1,30 @@
|
||||
project(GD32E23x_standard_peripheral LANGUAGES C CXX ASM)
|
||||
|
||||
add_library(GD32E23x_standard_peripheral OBJECT
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c
|
||||
)
|
||||
|
||||
target_include_directories(GD32E23x_standard_peripheral PUBLIC
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Include
|
||||
)
|
||||
|
||||
# CMSIS header only library is linked.
|
||||
project(GD32E23x_standard_peripheral LANGUAGES C CXX ASM)
|
||||
|
||||
add_library(GD32E23x_standard_peripheral OBJECT
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c
|
||||
)
|
||||
|
||||
target_include_directories(GD32E23x_standard_peripheral PUBLIC
|
||||
${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Include
|
||||
)
|
||||
|
||||
# CMSIS header only library is linked.
|
||||
target_link_libraries(GD32E23x_standard_peripheral PUBLIC CMSIS)
|
||||
@@ -1,349 +1,349 @@
|
||||
/*!
|
||||
\file gd32e23x_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_ADC_H
|
||||
#define GD32E23X_ADC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC ADC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */
|
||||
|
||||
/* ADC_SAMPTx x=0,1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC flag definitions */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */
|
||||
|
||||
/* ADC special function */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
/* external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* ADC data offset for inserted channel x */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog high threshold */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog low threshold */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC regular channel group length */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC inserted channel group length */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC resolution definitions */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* ADC oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* ADC oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* ADC triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt definitions */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(void);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(void);
|
||||
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(void);
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(void);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(void);
|
||||
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
|
||||
/* configure ADC special function */
|
||||
void adc_special_function_config(uint32_t function, ControlStatus newvalue);
|
||||
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t data_alignment);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint8_t channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint8_t channel_group);
|
||||
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(void);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint8_t inserted_channel);
|
||||
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t flag);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint8_t channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint8_t channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(void);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(void);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(void);
|
||||
|
||||
#endif /* GD32E23X_ADC_H */
|
||||
/*!
|
||||
\file gd32e23x_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_ADC_H
|
||||
#define GD32E23X_ADC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC ADC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */
|
||||
|
||||
/* ADC_SAMPTx x=0,1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC flag definitions */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */
|
||||
|
||||
/* ADC special function */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
/* external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* ADC data offset for inserted channel x */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog high threshold */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog low threshold */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC regular channel group length */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC inserted channel group length */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC resolution definitions */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* ADC oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* ADC oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* ADC triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt definitions */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(void);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(void);
|
||||
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(void);
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(void);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(void);
|
||||
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
|
||||
/* configure ADC special function */
|
||||
void adc_special_function_config(uint32_t function, ControlStatus newvalue);
|
||||
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t data_alignment);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint8_t channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint8_t channel_group);
|
||||
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(void);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint8_t inserted_channel);
|
||||
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t flag);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint8_t channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint8_t channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(void);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(void);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(void);
|
||||
|
||||
#endif /* GD32E23X_ADC_H */
|
||||
|
||||
@@ -1,132 +1,132 @@
|
||||
/*!
|
||||
\file gd32e23x_cmp.h
|
||||
\brief definitions for the CMP
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CMP_H
|
||||
#define GD32E23X_CMP_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CMP definitions */
|
||||
#define CMP CMP_BASE /*!< CMP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CMP_CS */
|
||||
#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
|
||||
#define CMP_CS_CMP0SW BIT(1) /*!< CMP switch mode enable */
|
||||
#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
|
||||
#define CMP_CS_CMP0MSEL BITS(4,6) /*!< CMP_IM input selection */
|
||||
#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
|
||||
#define CMP_CS_CMP0PL BIT(11) /*!< CMP0 output polarity */
|
||||
#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
|
||||
#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output state bit */
|
||||
#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
|
||||
|
||||
/* constants definitions */
|
||||
/* CMP units */
|
||||
typedef enum{
|
||||
CMP0, /*!< comparator 0 */
|
||||
}cmp_enum;
|
||||
|
||||
/* CMP operating mode */
|
||||
#define CS_CMPXM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
|
||||
#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
|
||||
#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
|
||||
#define CMP_MODE_LOWSPEED CS_CMPXM(2) /*!< CMP mode low speed */
|
||||
#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
|
||||
|
||||
/* CMP hysteresis */
|
||||
#define CS_CMPXHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
|
||||
#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
|
||||
#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
|
||||
#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
|
||||
#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
|
||||
|
||||
/* CMP inverting input */
|
||||
#define CS_CMPXMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U))
|
||||
#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
|
||||
#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input PA4 */
|
||||
#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input PA5 */
|
||||
#define CMP_INVERTING_INPUT_PA0 CS_CMPXMSEL(6) /*!< CMP inverting input PA0 */
|
||||
#define CMP_INVERTING_INPUT_PA2 CS_CMPXMSEL(7) /*!< CMP inverting input PA2 */
|
||||
|
||||
/* CMP output */
|
||||
#define CS_CMPXOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
|
||||
#define CMP_OUTPUT_NONE CS_CMPXOSEL(0) /*!< CMP output none */
|
||||
#define CMP_OUTPUT_TIMER0_BKIN CS_CMPXOSEL(1) /*!< CMP output TIMER0 break input */
|
||||
#define CMP_OUTPUT_TIMER0_IC0 CS_CMPXOSEL(2) /*!< CMP output TIMER0_CH0 input capture */
|
||||
#define CMP_OUTPUT_TIMER0_OCPRECLR CS_CMPXOSEL(3) /*!< CMP output TIMER0 OCPRE_CLR input */
|
||||
#define CMP_OUTPUT_TIMER2_IC0 CS_CMPXOSEL(6) /*!< CMP output TIMER2_CH0 input capture */
|
||||
#define CMP_OUTPUT_TIMER2_OCPRECLR CS_CMPXOSEL(7) /*!< CMP output TIMER2 OCPRE_CLR input */
|
||||
|
||||
/* CMP output polarity*/
|
||||
#define CS_CMPXPL(regval) (BIT(11) & ((uint32_t)(regval) << 11U))
|
||||
#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
|
||||
#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
|
||||
|
||||
/* CMP output level */
|
||||
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< CMP output high */
|
||||
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< CMP output low */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* CMP deinit */
|
||||
void cmp_deinit(cmp_enum cmp_periph);
|
||||
/* CMP mode init */
|
||||
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
|
||||
/* CMP output init */
|
||||
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity);
|
||||
|
||||
/* enable functions */
|
||||
/* enable CMP */
|
||||
void cmp_enable(cmp_enum cmp_periph);
|
||||
/* disable CMP */
|
||||
void cmp_disable(cmp_enum cmp_periph);
|
||||
/* enable CMP switch */
|
||||
void cmp_switch_enable(void);
|
||||
/* disable CMP switch */
|
||||
void cmp_switch_disable(void);
|
||||
/* lock the CMP */
|
||||
void cmp_lock_enable(cmp_enum cmp_periph);
|
||||
|
||||
/* get state related functions */
|
||||
/* get output level */
|
||||
uint32_t cmp_output_level_get(cmp_enum cmp_periph);
|
||||
|
||||
#endif /* GD32E23X_CMP_H */
|
||||
/*!
|
||||
\file gd32e23x_cmp.h
|
||||
\brief definitions for the CMP
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CMP_H
|
||||
#define GD32E23X_CMP_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CMP definitions */
|
||||
#define CMP CMP_BASE /*!< CMP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CMP_CS */
|
||||
#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
|
||||
#define CMP_CS_CMP0SW BIT(1) /*!< CMP switch mode enable */
|
||||
#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
|
||||
#define CMP_CS_CMP0MSEL BITS(4,6) /*!< CMP_IM input selection */
|
||||
#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
|
||||
#define CMP_CS_CMP0PL BIT(11) /*!< CMP0 output polarity */
|
||||
#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
|
||||
#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output state bit */
|
||||
#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
|
||||
|
||||
/* constants definitions */
|
||||
/* CMP units */
|
||||
typedef enum{
|
||||
CMP0, /*!< comparator 0 */
|
||||
}cmp_enum;
|
||||
|
||||
/* CMP operating mode */
|
||||
#define CS_CMPXM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
|
||||
#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
|
||||
#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
|
||||
#define CMP_MODE_LOWSPEED CS_CMPXM(2) /*!< CMP mode low speed */
|
||||
#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
|
||||
|
||||
/* CMP hysteresis */
|
||||
#define CS_CMPXHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
|
||||
#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
|
||||
#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
|
||||
#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
|
||||
#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
|
||||
|
||||
/* CMP inverting input */
|
||||
#define CS_CMPXMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U))
|
||||
#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
|
||||
#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
|
||||
#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input PA4 */
|
||||
#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input PA5 */
|
||||
#define CMP_INVERTING_INPUT_PA0 CS_CMPXMSEL(6) /*!< CMP inverting input PA0 */
|
||||
#define CMP_INVERTING_INPUT_PA2 CS_CMPXMSEL(7) /*!< CMP inverting input PA2 */
|
||||
|
||||
/* CMP output */
|
||||
#define CS_CMPXOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
|
||||
#define CMP_OUTPUT_NONE CS_CMPXOSEL(0) /*!< CMP output none */
|
||||
#define CMP_OUTPUT_TIMER0_BKIN CS_CMPXOSEL(1) /*!< CMP output TIMER0 break input */
|
||||
#define CMP_OUTPUT_TIMER0_IC0 CS_CMPXOSEL(2) /*!< CMP output TIMER0_CH0 input capture */
|
||||
#define CMP_OUTPUT_TIMER0_OCPRECLR CS_CMPXOSEL(3) /*!< CMP output TIMER0 OCPRE_CLR input */
|
||||
#define CMP_OUTPUT_TIMER2_IC0 CS_CMPXOSEL(6) /*!< CMP output TIMER2_CH0 input capture */
|
||||
#define CMP_OUTPUT_TIMER2_OCPRECLR CS_CMPXOSEL(7) /*!< CMP output TIMER2 OCPRE_CLR input */
|
||||
|
||||
/* CMP output polarity*/
|
||||
#define CS_CMPXPL(regval) (BIT(11) & ((uint32_t)(regval) << 11U))
|
||||
#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
|
||||
#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
|
||||
|
||||
/* CMP output level */
|
||||
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< CMP output high */
|
||||
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< CMP output low */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* CMP deinit */
|
||||
void cmp_deinit(cmp_enum cmp_periph);
|
||||
/* CMP mode init */
|
||||
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
|
||||
/* CMP output init */
|
||||
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity);
|
||||
|
||||
/* enable functions */
|
||||
/* enable CMP */
|
||||
void cmp_enable(cmp_enum cmp_periph);
|
||||
/* disable CMP */
|
||||
void cmp_disable(cmp_enum cmp_periph);
|
||||
/* enable CMP switch */
|
||||
void cmp_switch_enable(void);
|
||||
/* disable CMP switch */
|
||||
void cmp_switch_disable(void);
|
||||
/* lock the CMP */
|
||||
void cmp_lock_enable(cmp_enum cmp_periph);
|
||||
|
||||
/* get state related functions */
|
||||
/* get output level */
|
||||
uint32_t cmp_output_level_get(cmp_enum cmp_periph);
|
||||
|
||||
#endif /* GD32E23X_CMP_H */
|
||||
|
||||
@@ -1,123 +1,123 @@
|
||||
/*!
|
||||
\file gd32e23x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CRC_H
|
||||
#define GD32E23X_CRC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE /*!< CRC bsae address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
|
||||
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
|
||||
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
|
||||
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
|
||||
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
|
||||
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
|
||||
|
||||
/* CRC_INIT */
|
||||
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
|
||||
|
||||
/* CRC_POLY */
|
||||
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* size of polynomial function */
|
||||
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
|
||||
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
|
||||
|
||||
/* input data reverse function */
|
||||
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
|
||||
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
|
||||
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
|
||||
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
|
||||
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
|
||||
|
||||
/* input data format */
|
||||
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
|
||||
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
|
||||
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* enable the reverse operation of output data */
|
||||
void crc_reverse_output_data_enable(void);
|
||||
/* disable the reverse operation of output data */
|
||||
void crc_reverse_output_data_disable(void);
|
||||
|
||||
/* reset data register to the value of initialization data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* write the initial value register */
|
||||
void crc_init_data_register_write(uint32_t init_data);
|
||||
/* configure the CRC input data function */
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse);
|
||||
|
||||
/* configure the CRC size of polynomial function */
|
||||
void crc_polynomial_size_set(uint32_t poly_size);
|
||||
/* configure the CRC polynomial value function */
|
||||
void crc_polynomial_set(uint32_t poly);
|
||||
|
||||
/* CRC calculate single data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
|
||||
/* CRC calculate a data array */
|
||||
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
|
||||
|
||||
#endif /* GD32E23X_CRC_H */
|
||||
/*!
|
||||
\file gd32e23x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CRC_H
|
||||
#define GD32E23X_CRC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE /*!< CRC bsae address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
|
||||
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
|
||||
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
|
||||
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
|
||||
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
|
||||
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
|
||||
|
||||
/* CRC_INIT */
|
||||
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
|
||||
|
||||
/* CRC_POLY */
|
||||
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* size of polynomial function */
|
||||
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
|
||||
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
|
||||
|
||||
/* input data reverse function */
|
||||
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
|
||||
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
|
||||
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
|
||||
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
|
||||
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
|
||||
|
||||
/* input data format */
|
||||
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
|
||||
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
|
||||
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* enable the reverse operation of output data */
|
||||
void crc_reverse_output_data_enable(void);
|
||||
/* disable the reverse operation of output data */
|
||||
void crc_reverse_output_data_disable(void);
|
||||
|
||||
/* reset data register to the value of initialization data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* write the initial value register */
|
||||
void crc_init_data_register_write(uint32_t init_data);
|
||||
/* configure the CRC input data function */
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse);
|
||||
|
||||
/* configure the CRC size of polynomial function */
|
||||
void crc_polynomial_size_set(uint32_t poly_size);
|
||||
/* configure the CRC polynomial value function */
|
||||
void crc_polynomial_set(uint32_t poly);
|
||||
|
||||
/* CRC calculate single data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
|
||||
/* CRC calculate a data array */
|
||||
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
|
||||
|
||||
#endif /* GD32E23X_CRC_H */
|
||||
|
||||
@@ -1,121 +1,121 @@
|
||||
/*!
|
||||
\file gd32e23x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DBG_H
|
||||
#define GD32E23X_DBG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
|
||||
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
|
||||
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U,
|
||||
DBG_IDX_CTL1 = 0x08U,
|
||||
};
|
||||
|
||||
/* peripherals hold bit */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
|
||||
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
|
||||
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
|
||||
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32E23X_DBG_H */
|
||||
/*!
|
||||
\file gd32e23x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DBG_H
|
||||
#define GD32E23X_DBG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
|
||||
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
|
||||
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U,
|
||||
DBG_IDX_CTL1 = 0x08U,
|
||||
};
|
||||
|
||||
/* peripherals hold bit */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
|
||||
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
|
||||
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
|
||||
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32E23X_DBG_H */
|
||||
|
||||
@@ -1,262 +1,262 @@
|
||||
/*!
|
||||
\file gd32e23x_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DMA_H
|
||||
#define GD32E23X_DMA_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA DMA_BASE /*!< DMA base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL,x=0..4 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT,x=0..4 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..4 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR,x=0..4 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
} dma_parameter_struct;
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
|
||||
|
||||
#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_CHCTL base address */
|
||||
#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */
|
||||
#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */
|
||||
#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA channel shift bit */
|
||||
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(dma_channel_enum channelx);
|
||||
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32E23X_DMA_H */
|
||||
/*!
|
||||
\file gd32e23x_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DMA_H
|
||||
#define GD32E23X_DMA_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA DMA_BASE /*!< DMA base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL,x=0..4 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT,x=0..4 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..4 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR,x=0..4 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
} dma_parameter_struct;
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
|
||||
|
||||
#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_CHCTL base address */
|
||||
#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */
|
||||
#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */
|
||||
#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA channel shift bit */
|
||||
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(dma_channel_enum channelx);
|
||||
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32E23X_DMA_H */
|
||||
|
||||
@@ -1,280 +1,280 @@
|
||||
/*!
|
||||
\file gd32e23x_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_EXTI_H
|
||||
#define GD32E23X_EXTI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||
#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */
|
||||
#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */
|
||||
#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */
|
||||
#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */
|
||||
#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||
#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */
|
||||
#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */
|
||||
#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */
|
||||
#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */
|
||||
#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum {
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
||||
EXTI_23 = BIT(23), /*!< EXTI line 23 */
|
||||
EXTI_24 = BIT(24), /*!< EXTI line 24 */
|
||||
EXTI_25 = BIT(25), /*!< EXTI line 25 */
|
||||
EXTI_26 = BIT(26), /*!< EXTI line 26 */
|
||||
EXTI_27 = BIT(27) /*!< EXTI line 27 */
|
||||
} exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum {
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
} exti_mode_enum;
|
||||
|
||||
/* interrupt and event trigger mode */
|
||||
typedef enum {
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
} exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, EXTI lines configuration functions */
|
||||
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* initialize the EXTI line x */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
|
||||
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
|
||||
|
||||
/* enable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32E23X_EXTI_H */
|
||||
/*!
|
||||
\file gd32e23x_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_EXTI_H
|
||||
#define GD32E23X_EXTI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||
#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */
|
||||
#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */
|
||||
#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */
|
||||
#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */
|
||||
#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||
#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */
|
||||
#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */
|
||||
#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */
|
||||
#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */
|
||||
#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum {
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
||||
EXTI_23 = BIT(23), /*!< EXTI line 23 */
|
||||
EXTI_24 = BIT(24), /*!< EXTI line 24 */
|
||||
EXTI_25 = BIT(25), /*!< EXTI line 25 */
|
||||
EXTI_26 = BIT(26), /*!< EXTI line 26 */
|
||||
EXTI_27 = BIT(27) /*!< EXTI line 27 */
|
||||
} exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum {
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
} exti_mode_enum;
|
||||
|
||||
/* interrupt and event trigger mode */
|
||||
typedef enum {
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
} exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, EXTI lines configuration functions */
|
||||
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* initialize the EXTI line x */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
|
||||
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
|
||||
|
||||
/* enable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32E23X_EXTI_H */
|
||||
|
||||
@@ -1,270 +1,270 @@
|
||||
/*!
|
||||
\file gd32e23x_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FMC_H
|
||||
#define GD32E23X_FMC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option byte base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
|
||||
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
|
||||
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */
|
||||
#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/
|
||||
#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */
|
||||
#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */
|
||||
|
||||
/* FMC_KEY */
|
||||
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT */
|
||||
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */
|
||||
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
|
||||
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL */
|
||||
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
|
||||
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
|
||||
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
|
||||
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
|
||||
|
||||
/* FMC_ADDR */
|
||||
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */
|
||||
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
|
||||
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,31) /*!< store WP[15:0] of option byte block after system reset */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_PGAERR, /*!< program alignment error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
FMC_OB_HSPC /*!< option byte security protection code high */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* wait state counter value */
|
||||
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
|
||||
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
|
||||
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */
|
||||
#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */
|
||||
#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */
|
||||
|
||||
#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */
|
||||
#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */
|
||||
|
||||
/* option byte address */
|
||||
#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */
|
||||
#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */
|
||||
#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */
|
||||
|
||||
/* option byte write protection */
|
||||
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||
|
||||
/* option byte software/hardware free watchdog timer */
|
||||
#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */
|
||||
|
||||
/* option byte reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte reset or not entering standby mode */
|
||||
#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte OB_BOOT1_n set */
|
||||
#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */
|
||||
#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */
|
||||
|
||||
/* option byte VDDA monitor enable/disable */
|
||||
#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */
|
||||
#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */
|
||||
|
||||
/* option byte SRAM parity enable/disable */
|
||||
#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */
|
||||
#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */
|
||||
|
||||
/* option byte security protection level in FMC_OBSTAT register */
|
||||
#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */
|
||||
#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x02U) /*!< low security protection */
|
||||
#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x06U) /*!< high security protection */
|
||||
|
||||
/* option byte user mask */
|
||||
#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
|
||||
|
||||
/* option byte data address */
|
||||
#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
|
||||
#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
|
||||
|
||||
/* FMC flags */
|
||||
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt flags */
|
||||
#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt enable */
|
||||
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
|
||||
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
|
||||
|
||||
/* FMC time out */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* set the wait state counter value */
|
||||
void fmc_wscnt_set(uint8_t wscnt);
|
||||
|
||||
/* pre-fetch enable */
|
||||
void fmc_prefetch_enable(void);
|
||||
/* pre-fetch disable */
|
||||
void fmc_prefetch_disable(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC program a double word at the corresponding address */
|
||||
fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* reload the option byte and generate a system reset */
|
||||
void ob_reset(void);
|
||||
/* get option byte value */
|
||||
uint32_t option_byte_value_get(uint32_t addr);
|
||||
/* erase option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable option byte write protection (OB_WP) */
|
||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* configure read out protect */
|
||||
fmc_state_enum ob_security_protection_config(uint16_t ob_spc);
|
||||
/* write the FMC option byte user */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_user);
|
||||
/* write the FMC option byte data */
|
||||
fmc_state_enum ob_data_program(uint16_t data);
|
||||
/* get the FMC option byte OB_USER */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get the FMC option byte OB_DATA */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint32_t ob_write_protection_get(void);
|
||||
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
|
||||
uint32_t ob_obstat_plevel_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* get flag set or reset */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC pending flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get intrrupt flag set or reset */
|
||||
FlagStatus fmc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear the FMC interrupt pending flag by writing 1 */
|
||||
void fmc_interrupt_flag_clear(uint32_t int_flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32E23X_FMC_H */
|
||||
/*!
|
||||
\file gd32e23x_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FMC_H
|
||||
#define GD32E23X_FMC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option byte base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
|
||||
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
|
||||
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */
|
||||
#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/
|
||||
#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */
|
||||
#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */
|
||||
|
||||
/* FMC_KEY */
|
||||
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT */
|
||||
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */
|
||||
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
|
||||
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL */
|
||||
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
|
||||
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
|
||||
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
|
||||
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
|
||||
|
||||
/* FMC_ADDR */
|
||||
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */
|
||||
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
|
||||
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,31) /*!< store WP[15:0] of option byte block after system reset */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_PGAERR, /*!< program alignment error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
FMC_OB_HSPC /*!< option byte security protection code high */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* wait state counter value */
|
||||
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
|
||||
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
|
||||
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */
|
||||
#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */
|
||||
#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */
|
||||
|
||||
#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */
|
||||
#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */
|
||||
|
||||
/* option byte address */
|
||||
#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */
|
||||
#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */
|
||||
#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */
|
||||
|
||||
/* option byte write protection */
|
||||
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||
|
||||
/* option byte software/hardware free watchdog timer */
|
||||
#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */
|
||||
|
||||
/* option byte reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte reset or not entering standby mode */
|
||||
#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte OB_BOOT1_n set */
|
||||
#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */
|
||||
#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */
|
||||
|
||||
/* option byte VDDA monitor enable/disable */
|
||||
#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */
|
||||
#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */
|
||||
|
||||
/* option byte SRAM parity enable/disable */
|
||||
#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */
|
||||
#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */
|
||||
|
||||
/* option byte security protection level in FMC_OBSTAT register */
|
||||
#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */
|
||||
#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x02U) /*!< low security protection */
|
||||
#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x06U) /*!< high security protection */
|
||||
|
||||
/* option byte user mask */
|
||||
#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
|
||||
|
||||
/* option byte data address */
|
||||
#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
|
||||
#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
|
||||
|
||||
/* FMC flags */
|
||||
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt flags */
|
||||
#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt enable */
|
||||
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
|
||||
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
|
||||
|
||||
/* FMC time out */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* set the wait state counter value */
|
||||
void fmc_wscnt_set(uint8_t wscnt);
|
||||
|
||||
/* pre-fetch enable */
|
||||
void fmc_prefetch_enable(void);
|
||||
/* pre-fetch disable */
|
||||
void fmc_prefetch_disable(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC program a double word at the corresponding address */
|
||||
fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* reload the option byte and generate a system reset */
|
||||
void ob_reset(void);
|
||||
/* get option byte value */
|
||||
uint32_t option_byte_value_get(uint32_t addr);
|
||||
/* erase option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable option byte write protection (OB_WP) */
|
||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* configure read out protect */
|
||||
fmc_state_enum ob_security_protection_config(uint16_t ob_spc);
|
||||
/* write the FMC option byte user */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_user);
|
||||
/* write the FMC option byte data */
|
||||
fmc_state_enum ob_data_program(uint16_t data);
|
||||
/* get the FMC option byte OB_USER */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get the FMC option byte OB_DATA */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint32_t ob_write_protection_get(void);
|
||||
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
|
||||
uint32_t ob_obstat_plevel_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* get flag set or reset */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC pending flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get intrrupt flag set or reset */
|
||||
FlagStatus fmc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear the FMC interrupt pending flag by writing 1 */
|
||||
void fmc_interrupt_flag_clear(uint32_t int_flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32E23X_FMC_H */
|
||||
|
||||
@@ -1,122 +1,122 @@
|
||||
/*!
|
||||
\file gd32e23x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FWDGT_H
|
||||
#define GD32E23X_FWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
|
||||
|
||||
/* FWDGT_WND */
|
||||
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
|
||||
|
||||
/* constants definitions */
|
||||
/* FWDGT_PSC register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
|
||||
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
|
||||
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_WND_WND bit field */
|
||||
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the free watchdog timer counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* configure the free watchdog timer counter window value */
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32E23X_FWDGT_H */
|
||||
/*!
|
||||
\file gd32e23x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FWDGT_H
|
||||
#define GD32E23X_FWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
|
||||
|
||||
/* FWDGT_WND */
|
||||
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
|
||||
|
||||
/* constants definitions */
|
||||
/* FWDGT_PSC register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
|
||||
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
|
||||
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_WND_WND bit field */
|
||||
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the free watchdog timer counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* configure the free watchdog timer counter window value */
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32E23X_FWDGT_H */
|
||||
|
||||
@@ -1,386 +1,386 @@
|
||||
/*!
|
||||
\file gd32e23x_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_GPIO_H
|
||||
#define GD32E23X_GPIO_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,F) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
|
||||
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
|
||||
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
|
||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
|
||||
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL */
|
||||
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_OMODE */
|
||||
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||
|
||||
/* GPIO_OSPD */
|
||||
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||
|
||||
/* GPIO_PUD */
|
||||
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* GPIO_AFSEL0 */
|
||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||
|
||||
/* GPIO_AFSEL1 */
|
||||
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_TG */
|
||||
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* output mode definitions */
|
||||
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||
|
||||
/* pull-up/pull-down definitions */
|
||||
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO mode configuration values */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO pull-up/pull-down values */
|
||||
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output speed values */
|
||||
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output type */
|
||||
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */
|
||||
#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */
|
||||
|
||||
/* GPIO alternate function values */
|
||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
|
||||
|
||||
/* GPIO alternate function */
|
||||
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */
|
||||
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */
|
||||
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */
|
||||
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* set GPIO mode */
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||
/* set GPIO output type and speed */
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* set GPIO alternate function */
|
||||
void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
/* toggle GPIO pin status */
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||
/* toggle GPIO port status */
|
||||
void gpio_port_toggle(uint32_t gpio_periph);
|
||||
|
||||
#endif /* GD32E23X_GPIO_H */
|
||||
/*!
|
||||
\file gd32e23x_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_GPIO_H
|
||||
#define GD32E23X_GPIO_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,F) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
|
||||
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
|
||||
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
|
||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
|
||||
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL */
|
||||
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_OMODE */
|
||||
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||
|
||||
/* GPIO_OSPD */
|
||||
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||
|
||||
/* GPIO_PUD */
|
||||
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* GPIO_AFSEL0 */
|
||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||
|
||||
/* GPIO_AFSEL1 */
|
||||
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_TG */
|
||||
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* output mode definitions */
|
||||
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||
|
||||
/* pull-up/pull-down definitions */
|
||||
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO mode configuration values */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO pull-up/pull-down values */
|
||||
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output speed values */
|
||||
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output type */
|
||||
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */
|
||||
#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */
|
||||
|
||||
/* GPIO alternate function values */
|
||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
|
||||
|
||||
/* GPIO alternate function */
|
||||
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */
|
||||
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */
|
||||
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */
|
||||
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* set GPIO mode */
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||
/* set GPIO output type and speed */
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* set GPIO alternate function */
|
||||
void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
/* toggle GPIO pin status */
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||
/* toggle GPIO port status */
|
||||
void gpio_port_toggle(uint32_t gpio_periph);
|
||||
|
||||
#endif /* GD32E23X_GPIO_H */
|
||||
|
||||
@@ -1,388 +1,388 @@
|
||||
/*!
|
||||
\file gd32e23x_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_I2C_H
|
||||
#define GD32E23X_I2C_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
|
||||
#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast mode plus configure register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
#define I2C_CTL1_RBNECM BIT(15) /*!< RBNE clear mode */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
|
||||
|
||||
/* I2Cx_SAMCS */
|
||||
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
|
||||
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
|
||||
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
|
||||
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
|
||||
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
|
||||
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
|
||||
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
|
||||
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
|
||||
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
|
||||
|
||||
/* I2Cx_FMPCFG */
|
||||
#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
|
||||
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum {
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
/* flags in SAMCS register */
|
||||
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||
} i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */
|
||||
/* interrupt flags in SAMCS register */
|
||||
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||
} i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt */
|
||||
typedef enum {
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */
|
||||
/* interrupt in SAMCS register */
|
||||
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */
|
||||
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */
|
||||
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */
|
||||
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */
|
||||
} i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
|
||||
/* RBNE clear mode */
|
||||
#define I2C_RBNE_CLEAR_BTC_0 ((uint32_t)0x00000000U) /*!< RBNE can be cleared when I2C_DATA is read and BTC is cleared */
|
||||
#define I2C_RBNE_CLEAR I2C_CTL1_RBNECM /*!< RBNE can be cleared when I2C_DATA is read */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode or fast mode plus */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
|
||||
/* application function declarations */
|
||||
/* select SMBus type */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* configure I2C DMA mode */
|
||||
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* configure RBNE clear mode */
|
||||
void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* configure software reset of I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
/* configure I2C PEC calculation */
|
||||
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* configure whether to transfer PEC value */
|
||||
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* get packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* configure I2C alert through SMBA pin */
|
||||
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* configure I2C ARP protocol in SMBus */
|
||||
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||
/* enable SAM_V interface */
|
||||
void i2c_sam_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface */
|
||||
void i2c_sam_disable(uint32_t i2c_periph);
|
||||
/* enable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get I2C flag status */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag status */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* get I2C interrupt flag status */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag status */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32E23X_I2C_H */
|
||||
/*!
|
||||
\file gd32e23x_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_I2C_H
|
||||
#define GD32E23X_I2C_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
|
||||
#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast mode plus configure register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
#define I2C_CTL1_RBNECM BIT(15) /*!< RBNE clear mode */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
|
||||
|
||||
/* I2Cx_SAMCS */
|
||||
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
|
||||
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
|
||||
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
|
||||
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
|
||||
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
|
||||
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
|
||||
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
|
||||
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
|
||||
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
|
||||
|
||||
/* I2Cx_FMPCFG */
|
||||
#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
|
||||
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum {
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
/* flags in SAMCS register */
|
||||
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||
} i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */
|
||||
/* interrupt flags in SAMCS register */
|
||||
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||
} i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt */
|
||||
typedef enum {
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */
|
||||
/* interrupt in SAMCS register */
|
||||
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */
|
||||
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */
|
||||
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */
|
||||
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */
|
||||
} i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
|
||||
/* RBNE clear mode */
|
||||
#define I2C_RBNE_CLEAR_BTC_0 ((uint32_t)0x00000000U) /*!< RBNE can be cleared when I2C_DATA is read and BTC is cleared */
|
||||
#define I2C_RBNE_CLEAR I2C_CTL1_RBNECM /*!< RBNE can be cleared when I2C_DATA is read */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode or fast mode plus */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
|
||||
/* application function declarations */
|
||||
/* select SMBus type */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* configure I2C DMA mode */
|
||||
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* configure RBNE clear mode */
|
||||
void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* configure software reset of I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
/* configure I2C PEC calculation */
|
||||
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* configure whether to transfer PEC value */
|
||||
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* get packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* configure I2C alert through SMBA pin */
|
||||
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* configure I2C ARP protocol in SMBus */
|
||||
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||
/* enable SAM_V interface */
|
||||
void i2c_sam_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface */
|
||||
void i2c_sam_disable(uint32_t i2c_periph);
|
||||
/* enable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get I2C flag status */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag status */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* get I2C interrupt flag status */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag status */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32E23X_I2C_H */
|
||||
|
||||
@@ -1,84 +1,84 @@
|
||||
/*!
|
||||
\file gd32e23x_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_MISC_H
|
||||
#define GD32E23X_MISC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U) /*!< NVIC vector table offset mask */
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /*!< NVIC VECTKEY mask */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(IRQn_Type nvic_irq);
|
||||
/* initiates a system reset request to reset the MCU */
|
||||
void nvic_system_reset(void);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32E23X_MISC_H */
|
||||
/*!
|
||||
\file gd32e23x_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_MISC_H
|
||||
#define GD32E23X_MISC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U) /*!< NVIC vector table offset mask */
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /*!< NVIC VECTKEY mask */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(IRQn_Type nvic_irq);
|
||||
/* initiates a system reset request to reset the MCU */
|
||||
void nvic_system_reset(void);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32E23X_MISC_H */
|
||||
|
||||
@@ -1,144 +1,144 @@
|
||||
/*!
|
||||
\file gd32e23x_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_PMU_H
|
||||
#define GD32E23X_PMU_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||
|
||||
/* PMU LDO output voltage select definitions */
|
||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||
#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */
|
||||
#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */
|
||||
|
||||
/* PMU WKUP pin definitions */
|
||||
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
|
||||
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
|
||||
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
|
||||
#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* select LDO output voltage */
|
||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work in sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work in deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work in standby mode */
|
||||
void pmu_to_standbymode(void);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable backup domain write */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable backup domain write */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32E23X_PMU_H */
|
||||
/*!
|
||||
\file gd32e23x_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_PMU_H
|
||||
#define GD32E23X_PMU_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||
|
||||
/* PMU LDO output voltage select definitions */
|
||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||
#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */
|
||||
#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */
|
||||
|
||||
/* PMU WKUP pin definitions */
|
||||
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
|
||||
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
|
||||
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
|
||||
#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* select LDO output voltage */
|
||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work in sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work in deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work in standby mode */
|
||||
void pmu_to_standbymode(void);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable backup domain write */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable backup domain write */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32E23X_PMU_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,433 +1,433 @@
|
||||
/*!
|
||||
\file gd32e23x_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SPI_H
|
||||
#define GD32E23X_SPI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SPIx(x=0,1) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI1) */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
/* only available in SPI0*/
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
/* only available in SPI1*/
|
||||
#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_CTL1_DZ BITS(8,11) /*!< data size */
|
||||
#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */
|
||||
#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */
|
||||
#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */
|
||||
#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* SPI_QCTL(only available in SPI1) */
|
||||
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct {
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transfer type */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescaler factor */
|
||||
} spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescaler factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */
|
||||
|
||||
/* SPIx frame size */
|
||||
#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */
|
||||
#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */
|
||||
#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */
|
||||
#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */
|
||||
#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */
|
||||
#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */
|
||||
#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */
|
||||
#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */
|
||||
#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */
|
||||
#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */
|
||||
#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */
|
||||
#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */
|
||||
#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */
|
||||
|
||||
/* SPIx CRC length(x=1) */
|
||||
#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */
|
||||
#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */
|
||||
|
||||
/* SPIx byte access enable(x=1) */
|
||||
#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */
|
||||
#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */
|
||||
|
||||
/* SPIx odd bytes in TX DMA channel(x=1) */
|
||||
#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */
|
||||
#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */
|
||||
|
||||
/* SPIx odd bytes in RX DMA channel(x=1) */
|
||||
#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */
|
||||
#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */
|
||||
|
||||
/* SPIx TXFIFO level(x=1) */
|
||||
#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define SPI_TXLVL_EMPTY CTL1_TXLVL(0) /*!< SPI TXFIFO is empty */
|
||||
#define SPI_TXLVL_QUARTER_FULL CTL1_TXLVL(1) /*!< SPI TXFIFO is a quarter of full */
|
||||
#define SPI_TXLVL_HAlF_FULL CTL1_TXLVL(2) /*!< SPI TXFIFO is a half of full */
|
||||
#define SPI_TXLVL_FULL CTL1_TXLVL(3) /*!< SPI TXFIFO is full */
|
||||
|
||||
/* SPIx RXFIFO level(x=1) */
|
||||
#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */
|
||||
#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */
|
||||
#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */
|
||||
#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
/* only for SPI1 */
|
||||
#define SPI_FLAG_TXLVL_EMPTY ((uint32_t)0x10000000) /*!< SPI TXFIFO is empty */
|
||||
#define SPI_FLAG_TXLVL_QUARTER_FULL SPI_TXLVL_QUARTER_FULL /*!< SPI TXFIFO is a quarter of full */
|
||||
#define SPI_FLAG_TXLVL_HAlF_FULL SPI_TXLVL_HAlF_FULL /*!< SPI TXFIFO is a half of full */
|
||||
#define SPI_FLAG_TXLVL_FULL SPI_TXLVL_FULL /*!< SPI TXFIFO is full */
|
||||
#define SPI_FLAG_RXLVL_EMPTY ((uint32_t)0x20000000) /*!< SPI RXFIFO is empty */
|
||||
#define SPI_FLAG_RXLVL_QUARTER_FULL SPI_RXLVL_QUARTER_FULL /*!< SPI RXFIFO is a quarter of full */
|
||||
#define SPI_FLAG_RXLVL_HAlF_FULL SPI_RXLVL_HAlF_FULL /*!< SPI RXFIFO is a half of full */
|
||||
#define SPI_FLAG_RXLVL_FULL SPI_RXLVL_FULL /*!< SPI RXFIFO is full */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI structure with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||
/* initialize SPI parameters */
|
||||
ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* I2S initialization functions */
|
||||
/* initialize I2S parameters */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* DMA functions */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
/* configure SPI total number of data to be transmitted by DMA is odd or not */
|
||||
void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
/* configure SPI total number of data to be received by DMA is odd or not */
|
||||
void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
|
||||
/* communication functions */
|
||||
/* configure SPI data frame format */
|
||||
ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* configure SPI access size to FIFO(8-bit or 16-bit) */
|
||||
void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* clear TI Mode Format Error flag status */
|
||||
void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* set CRC length */
|
||||
void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI NSS pulse mode functions */
|
||||
/* enable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void spi_quad_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void spi_quad_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void spi_quad_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void spi_quad_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
|
||||
#endif /* GD32E23X_SPI_H */
|
||||
/*!
|
||||
\file gd32e23x_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SPI_H
|
||||
#define GD32E23X_SPI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SPIx(x=0,1) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI1) */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
/* only available in SPI0*/
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
/* only available in SPI1*/
|
||||
#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_CTL1_DZ BITS(8,11) /*!< data size */
|
||||
#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */
|
||||
#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */
|
||||
#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */
|
||||
#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* SPI_QCTL(only available in SPI1) */
|
||||
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct {
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transfer type */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescaler factor */
|
||||
} spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescaler factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */
|
||||
|
||||
/* SPIx frame size */
|
||||
#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */
|
||||
#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */
|
||||
#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */
|
||||
#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */
|
||||
#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */
|
||||
#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */
|
||||
#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */
|
||||
#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */
|
||||
#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */
|
||||
#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */
|
||||
#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */
|
||||
#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */
|
||||
#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */
|
||||
|
||||
/* SPIx CRC length(x=1) */
|
||||
#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */
|
||||
#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */
|
||||
|
||||
/* SPIx byte access enable(x=1) */
|
||||
#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */
|
||||
#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */
|
||||
|
||||
/* SPIx odd bytes in TX DMA channel(x=1) */
|
||||
#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */
|
||||
#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */
|
||||
|
||||
/* SPIx odd bytes in RX DMA channel(x=1) */
|
||||
#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */
|
||||
#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */
|
||||
|
||||
/* SPIx TXFIFO level(x=1) */
|
||||
#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define SPI_TXLVL_EMPTY CTL1_TXLVL(0) /*!< SPI TXFIFO is empty */
|
||||
#define SPI_TXLVL_QUARTER_FULL CTL1_TXLVL(1) /*!< SPI TXFIFO is a quarter of full */
|
||||
#define SPI_TXLVL_HAlF_FULL CTL1_TXLVL(2) /*!< SPI TXFIFO is a half of full */
|
||||
#define SPI_TXLVL_FULL CTL1_TXLVL(3) /*!< SPI TXFIFO is full */
|
||||
|
||||
/* SPIx RXFIFO level(x=1) */
|
||||
#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */
|
||||
#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */
|
||||
#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */
|
||||
#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
/* only for SPI1 */
|
||||
#define SPI_FLAG_TXLVL_EMPTY ((uint32_t)0x10000000) /*!< SPI TXFIFO is empty */
|
||||
#define SPI_FLAG_TXLVL_QUARTER_FULL SPI_TXLVL_QUARTER_FULL /*!< SPI TXFIFO is a quarter of full */
|
||||
#define SPI_FLAG_TXLVL_HAlF_FULL SPI_TXLVL_HAlF_FULL /*!< SPI TXFIFO is a half of full */
|
||||
#define SPI_FLAG_TXLVL_FULL SPI_TXLVL_FULL /*!< SPI TXFIFO is full */
|
||||
#define SPI_FLAG_RXLVL_EMPTY ((uint32_t)0x20000000) /*!< SPI RXFIFO is empty */
|
||||
#define SPI_FLAG_RXLVL_QUARTER_FULL SPI_RXLVL_QUARTER_FULL /*!< SPI RXFIFO is a quarter of full */
|
||||
#define SPI_FLAG_RXLVL_HAlF_FULL SPI_RXLVL_HAlF_FULL /*!< SPI RXFIFO is a half of full */
|
||||
#define SPI_FLAG_RXLVL_FULL SPI_RXLVL_FULL /*!< SPI RXFIFO is full */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI structure with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||
/* initialize SPI parameters */
|
||||
ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* I2S initialization functions */
|
||||
/* initialize I2S parameters */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* DMA functions */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
/* configure SPI total number of data to be transmitted by DMA is odd or not */
|
||||
void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
/* configure SPI total number of data to be received by DMA is odd or not */
|
||||
void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
|
||||
/* communication functions */
|
||||
/* configure SPI data frame format */
|
||||
ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* configure SPI access size to FIFO(8-bit or 16-bit) */
|
||||
void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
/* clear TI Mode Format Error flag status */
|
||||
void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* set CRC length */
|
||||
void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI NSS pulse mode functions */
|
||||
/* enable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void spi_quad_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void spi_quad_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void spi_quad_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void spi_quad_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
|
||||
#endif /* GD32E23X_SPI_H */
|
||||
|
||||
@@ -1,185 +1,185 @@
|
||||
/*!
|
||||
\file gd32e23x_syscfg.h
|
||||
\brief definitions for the SYSCFG
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SYSCFG_H
|
||||
#define GD32E23X_SYSCFG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SYSCFG definitions */
|
||||
#define SYSCFG SYSCFG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
|
||||
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
|
||||
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
|
||||
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
|
||||
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
|
||||
#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */
|
||||
#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */
|
||||
|
||||
/* SYSCFG_CFG0 bits definitions */
|
||||
#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */
|
||||
#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */
|
||||
#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */
|
||||
#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */
|
||||
|
||||
/* SYSCFG_EXTISS0 bits definitions */
|
||||
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS1 bits definitions */
|
||||
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS2 bits definitions */
|
||||
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS3 bits definitions */
|
||||
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
|
||||
|
||||
/* SYSCFG_CFG2 bits definitions */
|
||||
#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
|
||||
#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT bits definitions */
|
||||
#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA remap definitions */
|
||||
#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */
|
||||
#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */
|
||||
|
||||
/* high current definitions */
|
||||
#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */
|
||||
#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */
|
||||
|
||||
/* EXTI source select definition */
|
||||
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
|
||||
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
|
||||
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
|
||||
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
|
||||
|
||||
/* EXTI source select mask bits definition */
|
||||
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
|
||||
|
||||
/* EXTI source select jumping step definition */
|
||||
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
|
||||
|
||||
/* EXTI source select moving step definition */
|
||||
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
|
||||
|
||||
/* EXTI source port definitions */
|
||||
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
|
||||
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
|
||||
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
|
||||
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
|
||||
|
||||
/* EXTI source pin definitions */
|
||||
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
|
||||
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
|
||||
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
|
||||
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
|
||||
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
|
||||
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
|
||||
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
|
||||
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
|
||||
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
|
||||
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
|
||||
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
|
||||
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
|
||||
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
|
||||
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
|
||||
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
|
||||
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
|
||||
|
||||
/* lock definitions */
|
||||
#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */
|
||||
#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */
|
||||
#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */
|
||||
|
||||
/* SRAM parity check error flag definitions */
|
||||
#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */
|
||||
#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit syscfg module */
|
||||
void syscfg_deinit(void);
|
||||
|
||||
/* enable the DMA channels remapping */
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
|
||||
/* disable the DMA channels remapping */
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
|
||||
|
||||
/* enable PB9 high current capability */
|
||||
void syscfg_high_current_enable(void);
|
||||
/* disable PB9 high current capability */
|
||||
void syscfg_high_current_disable(void);
|
||||
|
||||
/* configure the GPIO pin as EXTI Line */
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
|
||||
/* connect TIMER0/14/15/16 break input to the selected parameter */
|
||||
void syscfg_lock_config(uint32_t syscfg_lock);
|
||||
|
||||
/* set the IRQ_LATENCY value */
|
||||
void irq_latency_set(uint8_t irq_latency);
|
||||
|
||||
/* check if the specified flag in SYSCFG_CFG2 is set or not */
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
|
||||
/* clear the flag in SYSCFG_CFG2 by writing 1 */
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag);
|
||||
|
||||
#endif /* GD32E23X_SYSCFG_H */
|
||||
/*!
|
||||
\file gd32e23x_syscfg.h
|
||||
\brief definitions for the SYSCFG
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SYSCFG_H
|
||||
#define GD32E23X_SYSCFG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SYSCFG definitions */
|
||||
#define SYSCFG SYSCFG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
|
||||
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
|
||||
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
|
||||
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
|
||||
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
|
||||
#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */
|
||||
#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */
|
||||
|
||||
/* SYSCFG_CFG0 bits definitions */
|
||||
#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */
|
||||
#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */
|
||||
#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */
|
||||
#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */
|
||||
|
||||
/* SYSCFG_EXTISS0 bits definitions */
|
||||
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS1 bits definitions */
|
||||
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS2 bits definitions */
|
||||
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS3 bits definitions */
|
||||
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
|
||||
|
||||
/* SYSCFG_CFG2 bits definitions */
|
||||
#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
|
||||
#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT bits definitions */
|
||||
#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA remap definitions */
|
||||
#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */
|
||||
#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */
|
||||
|
||||
/* high current definitions */
|
||||
#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */
|
||||
#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */
|
||||
|
||||
/* EXTI source select definition */
|
||||
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
|
||||
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
|
||||
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
|
||||
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
|
||||
|
||||
/* EXTI source select mask bits definition */
|
||||
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
|
||||
|
||||
/* EXTI source select jumping step definition */
|
||||
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
|
||||
|
||||
/* EXTI source select moving step definition */
|
||||
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
|
||||
|
||||
/* EXTI source port definitions */
|
||||
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
|
||||
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
|
||||
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
|
||||
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
|
||||
|
||||
/* EXTI source pin definitions */
|
||||
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
|
||||
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
|
||||
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
|
||||
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
|
||||
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
|
||||
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
|
||||
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
|
||||
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
|
||||
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
|
||||
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
|
||||
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
|
||||
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
|
||||
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
|
||||
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
|
||||
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
|
||||
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
|
||||
|
||||
/* lock definitions */
|
||||
#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */
|
||||
#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */
|
||||
#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */
|
||||
|
||||
/* SRAM parity check error flag definitions */
|
||||
#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */
|
||||
#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit syscfg module */
|
||||
void syscfg_deinit(void);
|
||||
|
||||
/* enable the DMA channels remapping */
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
|
||||
/* disable the DMA channels remapping */
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
|
||||
|
||||
/* enable PB9 high current capability */
|
||||
void syscfg_high_current_enable(void);
|
||||
/* disable PB9 high current capability */
|
||||
void syscfg_high_current_disable(void);
|
||||
|
||||
/* configure the GPIO pin as EXTI Line */
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
|
||||
/* connect TIMER0/14/15/16 break input to the selected parameter */
|
||||
void syscfg_lock_config(uint32_t syscfg_lock);
|
||||
|
||||
/* set the IRQ_LATENCY value */
|
||||
void irq_latency_set(uint8_t irq_latency);
|
||||
|
||||
/* check if the specified flag in SYSCFG_CFG2 is set or not */
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
|
||||
/* clear the flag in SYSCFG_CFG2 by writing 1 */
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag);
|
||||
|
||||
#endif /* GD32E23X_SYSCFG_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,91 +1,91 @@
|
||||
/*!
|
||||
\file gd32e23x_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_WWDGT_H
|
||||
#define GD32E23X_WWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/*!< write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
/*!< write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
|
||||
#endif /* GD32E23X_WWDGT_H */
|
||||
/*!
|
||||
\file gd32e23x_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_WWDGT_H
|
||||
#define GD32E23X_WWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/*!< write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
/*!< write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
|
||||
#endif /* GD32E23X_WWDGT_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,212 +1,212 @@
|
||||
/*!
|
||||
\file gd32e23x_cmp.c
|
||||
\brief CMP driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_cmp.h"
|
||||
|
||||
/*!
|
||||
\brief CMP deinit
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_deinit(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS &= ((uint32_t)0xFFFF0000U);
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CMP mode init
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[in] operating_mode
|
||||
\arg CMP_MODE_HIGHSPEED: high speed mode
|
||||
\arg CMP_MODE_MIDDLESPEED: medium speed mode
|
||||
\arg CMP_MODE_LOWSPEED: low speed mode
|
||||
\arg CMP_MODE_VERYLOWSPEED: very-low speed mode
|
||||
\param[in] inverting_input
|
||||
\arg CMP_INVERTING_INPUT_1_4VREFINT: VREFINT *1/4 input
|
||||
\arg CMP_INVERTING_INPUT_1_2VREFINT: VREFINT *1/2 input
|
||||
\arg CMP_INVERTING_INPUT_3_4VREFINT: VREFINT *3/4 input
|
||||
\arg CMP_INVERTING_INPUT_VREFINT: VREFINT input
|
||||
\arg CMP_INVERTING_INPUT_PA4: PA4 input
|
||||
\arg CMP_INVERTING_INPUT_PA5: PA5 input
|
||||
\arg CMP_INVERTING_INPUT_PA0: PA0 input
|
||||
\arg CMP_INVERTING_INPUT_PA2: PA2 input
|
||||
\param[in] output_hysteresis
|
||||
\arg CMP_HYSTERESIS_NO: output no hysteresis
|
||||
\arg CMP_HYSTERESIS_LOW: output low hysteresis
|
||||
\arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis
|
||||
\arg CMP_HYSTERESIS_HIGH: output high hysteresis
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* initialize comparator 0 mode */
|
||||
temp = CMP_CS;
|
||||
temp &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST);
|
||||
temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis);
|
||||
CMP_CS = temp;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CMP output init
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[in] output_selection
|
||||
\arg CMP_OUTPUT_NONE: CMP output none
|
||||
\arg CMP_OUTPUT_TIMER0_BKIN: CMP output TIMER0 break input
|
||||
\arg CMP_OUTPUT_TIMER0_IC0: CMP output TIMER0_CH0 input capture
|
||||
\arg CMP_OUTPUT_TIMER0_OCPRECLR: CMP output TIMER0 OCPRE_CLR input
|
||||
\arg CMP_OUTPUT_TIMER2_IC0: CMP output TIMER2_CH0 input capture
|
||||
\arg CMP_OUTPUT_TIMER2_OCPRECLR: CMP output TIMER2 OCPRE_CLR input
|
||||
\param[in] output_polarity
|
||||
\arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted
|
||||
\arg CMP_OUTPUT_POLARITY_NONINVERTED: output is not inverted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* initialize comparator 0 output */
|
||||
temp = CMP_CS;
|
||||
temp &= ~(uint32_t)CMP_CS_CMP0OSEL;
|
||||
temp |= (uint32_t)output_selection;
|
||||
/* output polarity */
|
||||
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) {
|
||||
temp |= (uint32_t)CMP_CS_CMP0PL;
|
||||
} else {
|
||||
temp &= ~(uint32_t)CMP_CS_CMP0PL;
|
||||
}
|
||||
CMP_CS = temp;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_enable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0EN;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_disable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP0EN;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CMP switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_enable(void)
|
||||
{
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CMP switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_disable(void)
|
||||
{
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock the CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_lock_enable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* lock CMP0 */
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0LK;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get output level
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval the output level
|
||||
*/
|
||||
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
|
||||
{
|
||||
/* get output level of CMP0 */
|
||||
if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) {
|
||||
return CMP_OUTPUTLEVEL_HIGH;
|
||||
} else {
|
||||
return CMP_OUTPUTLEVEL_LOW;
|
||||
}
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_cmp.c
|
||||
\brief CMP driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_cmp.h"
|
||||
|
||||
/*!
|
||||
\brief CMP deinit
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_deinit(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS &= ((uint32_t)0xFFFF0000U);
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CMP mode init
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[in] operating_mode
|
||||
\arg CMP_MODE_HIGHSPEED: high speed mode
|
||||
\arg CMP_MODE_MIDDLESPEED: medium speed mode
|
||||
\arg CMP_MODE_LOWSPEED: low speed mode
|
||||
\arg CMP_MODE_VERYLOWSPEED: very-low speed mode
|
||||
\param[in] inverting_input
|
||||
\arg CMP_INVERTING_INPUT_1_4VREFINT: VREFINT *1/4 input
|
||||
\arg CMP_INVERTING_INPUT_1_2VREFINT: VREFINT *1/2 input
|
||||
\arg CMP_INVERTING_INPUT_3_4VREFINT: VREFINT *3/4 input
|
||||
\arg CMP_INVERTING_INPUT_VREFINT: VREFINT input
|
||||
\arg CMP_INVERTING_INPUT_PA4: PA4 input
|
||||
\arg CMP_INVERTING_INPUT_PA5: PA5 input
|
||||
\arg CMP_INVERTING_INPUT_PA0: PA0 input
|
||||
\arg CMP_INVERTING_INPUT_PA2: PA2 input
|
||||
\param[in] output_hysteresis
|
||||
\arg CMP_HYSTERESIS_NO: output no hysteresis
|
||||
\arg CMP_HYSTERESIS_LOW: output low hysteresis
|
||||
\arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis
|
||||
\arg CMP_HYSTERESIS_HIGH: output high hysteresis
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* initialize comparator 0 mode */
|
||||
temp = CMP_CS;
|
||||
temp &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST);
|
||||
temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis);
|
||||
CMP_CS = temp;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CMP output init
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[in] output_selection
|
||||
\arg CMP_OUTPUT_NONE: CMP output none
|
||||
\arg CMP_OUTPUT_TIMER0_BKIN: CMP output TIMER0 break input
|
||||
\arg CMP_OUTPUT_TIMER0_IC0: CMP output TIMER0_CH0 input capture
|
||||
\arg CMP_OUTPUT_TIMER0_OCPRECLR: CMP output TIMER0 OCPRE_CLR input
|
||||
\arg CMP_OUTPUT_TIMER2_IC0: CMP output TIMER2_CH0 input capture
|
||||
\arg CMP_OUTPUT_TIMER2_OCPRECLR: CMP output TIMER2 OCPRE_CLR input
|
||||
\param[in] output_polarity
|
||||
\arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted
|
||||
\arg CMP_OUTPUT_POLARITY_NONINVERTED: output is not inverted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity)
|
||||
{
|
||||
uint32_t temp = 0U;
|
||||
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* initialize comparator 0 output */
|
||||
temp = CMP_CS;
|
||||
temp &= ~(uint32_t)CMP_CS_CMP0OSEL;
|
||||
temp |= (uint32_t)output_selection;
|
||||
/* output polarity */
|
||||
if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) {
|
||||
temp |= (uint32_t)CMP_CS_CMP0PL;
|
||||
} else {
|
||||
temp &= ~(uint32_t)CMP_CS_CMP0PL;
|
||||
}
|
||||
CMP_CS = temp;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_enable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0EN;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_disable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP0EN;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable CMP switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_enable(void)
|
||||
{
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable CMP switch
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_switch_disable(void)
|
||||
{
|
||||
CMP_CS &= ~(uint32_t)CMP_CS_CMP0SW;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock the CMP
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void cmp_lock_enable(cmp_enum cmp_periph)
|
||||
{
|
||||
if(CMP0 == cmp_periph) {
|
||||
/* lock CMP0 */
|
||||
CMP_CS |= (uint32_t)CMP_CS_CMP0LK;
|
||||
} else {
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get output level
|
||||
\param[in] cmp_periph
|
||||
\arg CMP0: comparator 0
|
||||
\param[out] none
|
||||
\retval the output level
|
||||
*/
|
||||
uint32_t cmp_output_level_get(cmp_enum cmp_periph)
|
||||
{
|
||||
/* get output level of CMP0 */
|
||||
if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) {
|
||||
return CMP_OUTPUTLEVEL_HIGH;
|
||||
} else {
|
||||
return CMP_OUTPUTLEVEL_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,241 +1,241 @@
|
||||
/*!
|
||||
\file gd32e23x_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_crc.h"
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_DATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_FDATA = (uint32_t)0x00000000U;
|
||||
CRC_POLY = (uint32_t)0x04C11DB7U;
|
||||
CRC_CTL = CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_enable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_disable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register to the value of initializaiton data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the free data register
|
||||
\param[in] free_data: specify 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the initializaiton data register
|
||||
\param[in] init_data:specify 32-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_init_data_register_write(uint32_t init_data)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)init_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC input data function
|
||||
\param[in] data_reverse: specify input data reverse function
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_INPUT_DATA_NOT: input data is not reversed
|
||||
\arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
|
||||
\arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
|
||||
\arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
|
||||
CRC_CTL |= (uint32_t)data_reverse;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC size of polynomial function
|
||||
\param[in] poly_size: size of polynomial
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_size_set(uint32_t poly_size)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
|
||||
CRC_CTL |= (uint32_t)poly_size;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC polynomial value function
|
||||
\param[in] poly: configurable polynomial value
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_set(uint32_t poly)
|
||||
{
|
||||
CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
|
||||
CRC_POLY = poly;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate single data
|
||||
\param[in] sdata: specify input data
|
||||
\param[in] data_format: input data format
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg INPUT_FORMAT_WORD: input data in word format
|
||||
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
|
||||
\arg INPUT_FORMAT_BYTE: input data in byte format
|
||||
\param[out] none
|
||||
\retval CRC calculate value
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
|
||||
{
|
||||
if(INPUT_FORMAT_WORD == data_format) {
|
||||
REG32(CRC) = sdata;
|
||||
} else if(INPUT_FORMAT_HALFWORD == data_format) {
|
||||
REG16(CRC) = (uint16_t)sdata;
|
||||
} else {
|
||||
REG8(CRC) = (uint8_t)sdata;
|
||||
}
|
||||
|
||||
return(CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate a data array
|
||||
\param[in] array: pointer to the input data array
|
||||
\param[in] size: size of the array
|
||||
\param[in] data_format: input data format
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg INPUT_FORMAT_WORD: input data in word format
|
||||
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
|
||||
\arg INPUT_FORMAT_BYTE: input data in byte format
|
||||
\param[out] none
|
||||
\retval CRC calculate value
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format)
|
||||
{
|
||||
uint8_t *data8;
|
||||
uint16_t *data16;
|
||||
uint32_t *data32;
|
||||
uint32_t index;
|
||||
|
||||
if(INPUT_FORMAT_WORD == data_format) {
|
||||
data32 = (uint32_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG32(CRC) = data32[index];
|
||||
}
|
||||
} else if(INPUT_FORMAT_HALFWORD == data_format) {
|
||||
data16 = (uint16_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG16(CRC) = data16[index];
|
||||
}
|
||||
} else {
|
||||
data8 = (uint8_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG8(CRC) = data8[index];
|
||||
}
|
||||
}
|
||||
|
||||
return (CRC_DATA);
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_crc.c
|
||||
\brief CRC driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_crc.h"
|
||||
|
||||
/*!
|
||||
\brief deinit CRC calculation unit
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_deinit(void)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_DATA = (uint32_t)0xFFFFFFFFU;
|
||||
CRC_FDATA = (uint32_t)0x00000000U;
|
||||
CRC_POLY = (uint32_t)0x04C11DB7U;
|
||||
CRC_CTL = CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_enable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_REV_O;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the reverse operation of output data
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_reverse_output_data_disable(void)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset data register to the value of initializaiton data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_data_register_reset(void)
|
||||
{
|
||||
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 32-bit value of the data register
|
||||
*/
|
||||
uint32_t crc_data_register_read(void)
|
||||
{
|
||||
uint32_t data;
|
||||
data = CRC_DATA;
|
||||
return (data);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read the free data register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval 8-bit value of the free data register
|
||||
*/
|
||||
uint8_t crc_free_data_register_read(void)
|
||||
{
|
||||
uint8_t fdata;
|
||||
fdata = (uint8_t)CRC_FDATA;
|
||||
return (fdata);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the free data register
|
||||
\param[in] free_data: specify 8-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_free_data_register_write(uint8_t free_data)
|
||||
{
|
||||
CRC_FDATA = (uint32_t)free_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write the initializaiton data register
|
||||
\param[in] init_data:specify 32-bit data
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_init_data_register_write(uint32_t init_data)
|
||||
{
|
||||
CRC_IDATA = (uint32_t)init_data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC input data function
|
||||
\param[in] data_reverse: specify input data reverse function
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_INPUT_DATA_NOT: input data is not reversed
|
||||
\arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits
|
||||
\arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits
|
||||
\arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I);
|
||||
CRC_CTL |= (uint32_t)data_reverse;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC size of polynomial function
|
||||
\param[in] poly_size: size of polynomial
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation
|
||||
\arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_size_set(uint32_t poly_size)
|
||||
{
|
||||
CRC_CTL &= (uint32_t)(~(CRC_CTL_PS));
|
||||
CRC_CTL |= (uint32_t)poly_size;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the CRC polynomial value function
|
||||
\param[in] poly: configurable polynomial value
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void crc_polynomial_set(uint32_t poly)
|
||||
{
|
||||
CRC_POLY &= (uint32_t)(~CRC_POLY_POLY);
|
||||
CRC_POLY = poly;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate single data
|
||||
\param[in] sdata: specify input data
|
||||
\param[in] data_format: input data format
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg INPUT_FORMAT_WORD: input data in word format
|
||||
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
|
||||
\arg INPUT_FORMAT_BYTE: input data in byte format
|
||||
\param[out] none
|
||||
\retval CRC calculate value
|
||||
*/
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format)
|
||||
{
|
||||
if(INPUT_FORMAT_WORD == data_format) {
|
||||
REG32(CRC) = sdata;
|
||||
} else if(INPUT_FORMAT_HALFWORD == data_format) {
|
||||
REG16(CRC) = (uint16_t)sdata;
|
||||
} else {
|
||||
REG8(CRC) = (uint8_t)sdata;
|
||||
}
|
||||
|
||||
return(CRC_DATA);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief CRC calculate a data array
|
||||
\param[in] array: pointer to the input data array
|
||||
\param[in] size: size of the array
|
||||
\param[in] data_format: input data format
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg INPUT_FORMAT_WORD: input data in word format
|
||||
\arg INPUT_FORMAT_HALFWORD: input data in half-word format
|
||||
\arg INPUT_FORMAT_BYTE: input data in byte format
|
||||
\param[out] none
|
||||
\retval CRC calculate value
|
||||
*/
|
||||
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format)
|
||||
{
|
||||
uint8_t *data8;
|
||||
uint16_t *data16;
|
||||
uint32_t *data32;
|
||||
uint32_t index;
|
||||
|
||||
if(INPUT_FORMAT_WORD == data_format) {
|
||||
data32 = (uint32_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG32(CRC) = data32[index];
|
||||
}
|
||||
} else if(INPUT_FORMAT_HALFWORD == data_format) {
|
||||
data16 = (uint16_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG16(CRC) = data16[index];
|
||||
}
|
||||
} else {
|
||||
data8 = (uint8_t *)array;
|
||||
for(index = 0U; index < size; index++) {
|
||||
REG8(CRC) = data8[index];
|
||||
}
|
||||
}
|
||||
|
||||
return (CRC_DATA);
|
||||
}
|
||||
|
||||
@@ -1,138 +1,138 @@
|
||||
/*!
|
||||
\file gd32e23x_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_dbg.h"
|
||||
|
||||
#define DBG_RESET_VAL 0x00000000U
|
||||
|
||||
/*!
|
||||
\brief deinitialize the DBG
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_deinit(void)
|
||||
{
|
||||
DBG_CTL0 = DBG_RESET_VAL;
|
||||
DBG_CTL1 = DBG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
this parameter can be any combination of the following values:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
this parameter can be any combination of the following values:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: DBG peripheral
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
|
||||
\arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
|
||||
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||
\arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
|
||||
\arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
|
||||
\arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
|
||||
\arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
|
||||
\arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: DBG peripheral
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
|
||||
\arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
|
||||
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||
\arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
|
||||
\arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
|
||||
\arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
|
||||
\arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
|
||||
\arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_dbg.c
|
||||
\brief DBG driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_dbg.h"
|
||||
|
||||
#define DBG_RESET_VAL 0x00000000U
|
||||
|
||||
/*!
|
||||
\brief deinitialize the DBG
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_deinit(void)
|
||||
{
|
||||
DBG_CTL0 = DBG_RESET_VAL;
|
||||
DBG_CTL1 = DBG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief read DBG_ID code register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval DBG_ID code
|
||||
*/
|
||||
uint32_t dbg_id_get(void)
|
||||
{
|
||||
return DBG_ID;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
this parameter can be any combination of the following values:
|
||||
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 |= dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable low power behavior when the mcu is in debug mode
|
||||
\param[in] dbg_low_power:
|
||||
this parameter can be any combination of the following values:
|
||||
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||
{
|
||||
DBG_CTL0 &= ~dbg_low_power;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: DBG peripheral
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
|
||||
\arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
|
||||
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||
\arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
|
||||
\arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
|
||||
\arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
|
||||
\arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
|
||||
\arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable peripheral behavior when the mcu is in debug mode
|
||||
\param[in] dbg_periph: DBG peripheral
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||
\arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted
|
||||
\arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted
|
||||
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||
\arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted
|
||||
\arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted
|
||||
\arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted
|
||||
\arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted
|
||||
\arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted
|
||||
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||
{
|
||||
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,251 +1,251 @@
|
||||
/*!
|
||||
\file gd32e23x_exti.c
|
||||
\brief EXTI driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_exti.h"
|
||||
|
||||
#define EXTI_INTEN_RESET_VAL ((uint32_t)0x0F900000U)
|
||||
#define EXTI_REG_RESET_VAL ((uint32_t)0x00000000U)
|
||||
|
||||
|
||||
/*!
|
||||
\brief reset the value of all EXTI registers with initial values
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_deinit(void)
|
||||
{
|
||||
/* reset the value of the EXTI registers */
|
||||
EXTI_INTEN = EXTI_INTEN_RESET_VAL;
|
||||
EXTI_EVEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_RTEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_FTEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_SWIEV = EXTI_REG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_INTERRUPT: interrupt mode
|
||||
\arg EXTI_EVENT: event mode
|
||||
\param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_TRIG_RISING: rising edge trigger
|
||||
\arg EXTI_TRIG_FALLING: falling trigger
|
||||
\arg EXTI_TRIG_BOTH: rising and falling trigger
|
||||
\arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
|
||||
{
|
||||
/* reset the EXTI line x */
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
|
||||
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
|
||||
switch(mode) {
|
||||
case EXTI_INTERRUPT:
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_EVENT:
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the EXTI trigger type */
|
||||
switch(trig_type) {
|
||||
case EXTI_TRIG_RISING:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_FALLING:
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_BOTH:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_NONE:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the software interrupt event from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the software interrupt event from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_exti.c
|
||||
\brief EXTI driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_exti.h"
|
||||
|
||||
#define EXTI_INTEN_RESET_VAL ((uint32_t)0x0F900000U)
|
||||
#define EXTI_REG_RESET_VAL ((uint32_t)0x00000000U)
|
||||
|
||||
|
||||
/*!
|
||||
\brief reset the value of all EXTI registers with initial values
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_deinit(void)
|
||||
{
|
||||
/* reset the value of the EXTI registers */
|
||||
EXTI_INTEN = EXTI_INTEN_RESET_VAL;
|
||||
EXTI_EVEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_RTEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_FTEN = EXTI_REG_RESET_VAL;
|
||||
EXTI_SWIEV = EXTI_REG_RESET_VAL;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief initialize the EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_INTERRUPT: interrupt mode
|
||||
\arg EXTI_EVENT: event mode
|
||||
\param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_TRIG_RISING: rising edge trigger
|
||||
\arg EXTI_TRIG_FALLING: falling trigger
|
||||
\arg EXTI_TRIG_BOTH: rising and falling trigger
|
||||
\arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type)
|
||||
{
|
||||
/* reset the EXTI line x */
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
|
||||
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
|
||||
switch(mode) {
|
||||
case EXTI_INTERRUPT:
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_EVENT:
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* set the EXTI trigger type */
|
||||
switch(trig_type) {
|
||||
case EXTI_TRIG_RISING:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN &= ~(uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_FALLING:
|
||||
EXTI_RTEN &= ~(uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_BOTH:
|
||||
EXTI_RTEN |= (uint32_t)linex;
|
||||
EXTI_FTEN |= (uint32_t)linex;
|
||||
break;
|
||||
case EXTI_TRIG_NONE:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the interrupts from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_INTEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the events from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..27): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_event_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_EVEN &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the software interrupt event from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_enable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV |= (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the software interrupt event from EXTI line x
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_software_interrupt_disable(exti_line_enum linex)
|
||||
{
|
||||
EXTI_SWIEV &= ~(uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval FlagStatus: status of flag (RESET or SET)
|
||||
*/
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||
{
|
||||
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear EXTI line x interrupt pending flag
|
||||
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg EXTI_x (x=0..17,19,21): EXTI line x
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||
{
|
||||
EXTI_PD = (uint32_t)linex;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,245 +1,245 @@
|
||||
/*!
|
||||
\file gd32e23x_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_fwdgt.h"
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter prescaler value
|
||||
\param[in] prescaler_value: specify prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_value;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter reload value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
|
||||
{
|
||||
uint32_t timeout = FWDGT_RLD_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the RUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter window value
|
||||
\param[in] window_value: specify window value(0x0000 - 0x0FFF)
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value)
|
||||
{
|
||||
uint32_t time_index = FWDGT_WND_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_WND */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the WUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
|
||||
} while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_WND = WND_WND(window_value);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(RESET != (FWDGT_STAT & flag)) {
|
||||
return SET;
|
||||
}
|
||||
return RESET;
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_fwdgt.c
|
||||
\brief FWDGT driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_fwdgt.h"
|
||||
|
||||
/*!
|
||||
\brief enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_write_disable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the free watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_enable(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter prescaler value
|
||||
\param[in] prescaler_value: specify prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_value;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter reload value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
|
||||
{
|
||||
uint32_t timeout = FWDGT_RLD_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the RUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the free watchdog timer counter window value
|
||||
\param[in] window_value: specify window value(0x0000 - 0x0FFF)
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value)
|
||||
{
|
||||
uint32_t time_index = FWDGT_WND_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_WND */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the WUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_WUD;
|
||||
} while((--time_index > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_WND = WND_WND(window_value);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reload the counter of FWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void fwdgt_counter_reload(void)
|
||||
{
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter reload value, and prescaler divider value
|
||||
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||
\param[in] prescaler_div: FWDGT prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||
\param[out] none
|
||||
\retval ErrStatus: ERROR or SUCCESS
|
||||
*/
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
|
||||
{
|
||||
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||
uint32_t flag_status = RESET;
|
||||
|
||||
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||
|
||||
/* wait until the PUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/* configure FWDGT */
|
||||
FWDGT_PSC = (uint32_t)prescaler_div;
|
||||
|
||||
timeout = FWDGT_RLD_TIMEOUT;
|
||||
/* wait until the RUD flag to be reset */
|
||||
do {
|
||||
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||
} while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
|
||||
|
||||
if((uint32_t)RESET != flag_status) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
FWDGT_RLD = RLD_RLD(reload_value);
|
||||
|
||||
/* reload the counter */
|
||||
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state of FWDGT
|
||||
\param[in] flag: flag to get
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
|
||||
\arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
|
||||
\arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||
{
|
||||
if(RESET != (FWDGT_STAT & flag)) {
|
||||
return SET;
|
||||
}
|
||||
return RESET;
|
||||
}
|
||||
|
||||
@@ -1,399 +1,399 @@
|
||||
/*!
|
||||
\file gd32e23x_gpio.c
|
||||
\brief GPIO driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_gpio.h"
|
||||
|
||||
/*!
|
||||
\brief reset GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_deinit(uint32_t gpio_periph)
|
||||
{
|
||||
switch(gpio_periph) {
|
||||
case GPIOA:
|
||||
/* reset GPIOA */
|
||||
rcu_periph_reset_enable(RCU_GPIOARST);
|
||||
rcu_periph_reset_disable(RCU_GPIOARST);
|
||||
break;
|
||||
case GPIOB:
|
||||
/* reset GPIOB */
|
||||
rcu_periph_reset_enable(RCU_GPIOBRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOBRST);
|
||||
break;
|
||||
case GPIOC:
|
||||
/* reset GPIOC */
|
||||
rcu_periph_reset_enable(RCU_GPIOCRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOCRST);
|
||||
break;
|
||||
case GPIOF:
|
||||
/* reset GPIOF */
|
||||
rcu_periph_reset_enable(RCU_GPIOFRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOFRST);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO mode
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] mode: gpio pin mode
|
||||
\arg GPIO_MODE_INPUT: input mode
|
||||
\arg GPIO_MODE_OUTPUT: output mode
|
||||
\arg GPIO_MODE_AF: alternate function mode
|
||||
\arg GPIO_MODE_ANALOG: analog mode
|
||||
\param[in] pull_up_down: gpio pin with pull-up or pull-down resistor
|
||||
\arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
|
||||
\arg GPIO_PUPD_PULLUP: with pull-up resistor
|
||||
\arg GPIO_PUPD_PULLDOWN:with pull-down resistor
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ctl, pupd;
|
||||
|
||||
ctl = GPIO_CTL(gpio_periph);
|
||||
pupd = GPIO_PUD(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin mode bits */
|
||||
ctl &= ~GPIO_MODE_MASK(i);
|
||||
/* set the specified pin mode bits */
|
||||
ctl |= GPIO_MODE_SET(i, mode);
|
||||
|
||||
/* clear the specified pin pupd bits */
|
||||
pupd &= ~GPIO_PUPD_MASK(i);
|
||||
/* set the specified pin pupd bits */
|
||||
pupd |= GPIO_PUPD_SET(i, pull_up_down);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_CTL(gpio_periph) = ctl;
|
||||
GPIO_PUD(gpio_periph) = pupd;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO output type and speed
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] otype: gpio pin output mode
|
||||
\arg GPIO_OTYPE_PP: push pull mode
|
||||
\arg GPIO_OTYPE_OD: open drain mode
|
||||
\param[in] speed: gpio pin output max speed
|
||||
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
|
||||
\arg GPIO_OSPEED_10MHZ: output max speed 10MHz
|
||||
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ospeed;
|
||||
|
||||
if(GPIO_OTYPE_OD == otype) {
|
||||
GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
|
||||
} else {
|
||||
GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
|
||||
}
|
||||
|
||||
/* get the specified pin output speed bits value */
|
||||
ospeed = GPIO_OSPD(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin output speed bits */
|
||||
ospeed &= ~GPIO_OSPEED_MASK(i);
|
||||
/* set the specified pin output speed bits */
|
||||
ospeed |= GPIO_OSPEED_SET(i, speed);
|
||||
}
|
||||
}
|
||||
GPIO_OSPD(gpio_periph) = ospeed;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO pin
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[in] bit_value: SET or RESET
|
||||
\arg RESET: clear the port pin
|
||||
\arg SET: set the port pin
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
|
||||
{
|
||||
if(RESET != bit_value) {
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
} else {
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] data: specify the value to be written to the port output control register
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
|
||||
{
|
||||
GPIO_OCTL(gpio_periph) = (uint32_t)data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_ISTAT(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_OCTL(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO alternate function
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C)
|
||||
\param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet
|
||||
\arg GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0,
|
||||
I2C0, I2C1, SWDIO, SWCLK
|
||||
\arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1
|
||||
\arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
|
||||
\arg GPIO_AF_3: I2C0, TIMER14
|
||||
\arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
|
||||
\arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0
|
||||
\arg GPIO_AF_6(port A,B only): SPI1
|
||||
\arg GPIO_AF_7(port A,B only): CMP
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t afrl, afrh;
|
||||
|
||||
afrl = GPIO_AFSEL0(gpio_periph);
|
||||
afrh = GPIO_AFSEL1(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 8U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrl &= ~GPIO_AFR_MASK(i);
|
||||
afrl |= GPIO_AFR_SET(i, alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
for(i = 8U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrh &= ~GPIO_AFR_MASK(i - 8U);
|
||||
afrh |= GPIO_AFR_SET(i - 8U, alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_AFSEL0(gpio_periph) = afrl;
|
||||
GPIO_AFSEL1(gpio_periph) = afrh;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
uint32_t lock = 0x00010000U;
|
||||
lock |= pin;
|
||||
|
||||
/* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)pin;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO pin status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO port status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_toggle(uint32_t gpio_periph)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = 0x0000FFFFU;
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_gpio.c
|
||||
\brief GPIO driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_gpio.h"
|
||||
|
||||
/*!
|
||||
\brief reset GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_deinit(uint32_t gpio_periph)
|
||||
{
|
||||
switch(gpio_periph) {
|
||||
case GPIOA:
|
||||
/* reset GPIOA */
|
||||
rcu_periph_reset_enable(RCU_GPIOARST);
|
||||
rcu_periph_reset_disable(RCU_GPIOARST);
|
||||
break;
|
||||
case GPIOB:
|
||||
/* reset GPIOB */
|
||||
rcu_periph_reset_enable(RCU_GPIOBRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOBRST);
|
||||
break;
|
||||
case GPIOC:
|
||||
/* reset GPIOC */
|
||||
rcu_periph_reset_enable(RCU_GPIOCRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOCRST);
|
||||
break;
|
||||
case GPIOF:
|
||||
/* reset GPIOF */
|
||||
rcu_periph_reset_enable(RCU_GPIOFRST);
|
||||
rcu_periph_reset_disable(RCU_GPIOFRST);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO mode
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] mode: gpio pin mode
|
||||
\arg GPIO_MODE_INPUT: input mode
|
||||
\arg GPIO_MODE_OUTPUT: output mode
|
||||
\arg GPIO_MODE_AF: alternate function mode
|
||||
\arg GPIO_MODE_ANALOG: analog mode
|
||||
\param[in] pull_up_down: gpio pin with pull-up or pull-down resistor
|
||||
\arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors
|
||||
\arg GPIO_PUPD_PULLUP: with pull-up resistor
|
||||
\arg GPIO_PUPD_PULLDOWN:with pull-down resistor
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ctl, pupd;
|
||||
|
||||
ctl = GPIO_CTL(gpio_periph);
|
||||
pupd = GPIO_PUD(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin mode bits */
|
||||
ctl &= ~GPIO_MODE_MASK(i);
|
||||
/* set the specified pin mode bits */
|
||||
ctl |= GPIO_MODE_SET(i, mode);
|
||||
|
||||
/* clear the specified pin pupd bits */
|
||||
pupd &= ~GPIO_PUPD_MASK(i);
|
||||
/* set the specified pin pupd bits */
|
||||
pupd |= GPIO_PUPD_SET(i, pull_up_down);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_CTL(gpio_periph) = ctl;
|
||||
GPIO_PUD(gpio_periph) = pupd;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO output type and speed
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] otype: gpio pin output mode
|
||||
\arg GPIO_OTYPE_PP: push pull mode
|
||||
\arg GPIO_OTYPE_OD: open drain mode
|
||||
\param[in] speed: gpio pin output max speed
|
||||
\arg GPIO_OSPEED_2MHZ: output max speed 2MHz
|
||||
\arg GPIO_OSPEED_10MHZ: output max speed 10MHz
|
||||
\arg GPIO_OSPEED_50MHZ: output max speed 50MHz
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t ospeed;
|
||||
|
||||
if(GPIO_OTYPE_OD == otype) {
|
||||
GPIO_OMODE(gpio_periph) |= (uint32_t)pin;
|
||||
} else {
|
||||
GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin);
|
||||
}
|
||||
|
||||
/* get the specified pin output speed bits value */
|
||||
ospeed = GPIO_OSPD(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin output speed bits */
|
||||
ospeed &= ~GPIO_OSPEED_MASK(i);
|
||||
/* set the specified pin output speed bits */
|
||||
ospeed |= GPIO_OSPEED_SET(i, speed);
|
||||
}
|
||||
}
|
||||
GPIO_OSPD(gpio_periph) = ospeed;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO pin
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[in] bit_value: SET or RESET
|
||||
\arg RESET: clear the port pin
|
||||
\arg SET: set the port pin
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value)
|
||||
{
|
||||
if(RESET != bit_value) {
|
||||
GPIO_BOP(gpio_periph) = (uint32_t)pin;
|
||||
} else {
|
||||
GPIO_BC(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief write data to the specified GPIO port
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] data: specify the value to be written to the port output control register
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data)
|
||||
{
|
||||
GPIO_OCTL(gpio_periph) = (uint32_t)data;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins input status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_ISTAT(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO pin output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval SET or RESET
|
||||
*/
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get GPIO all pins output status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval state of GPIO all pins
|
||||
*/
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph)
|
||||
{
|
||||
return (uint16_t)GPIO_OCTL(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set GPIO alternate function
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C)
|
||||
\param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet
|
||||
\arg GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0,
|
||||
I2C0, I2C1, SWDIO, SWCLK
|
||||
\arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1
|
||||
\arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0
|
||||
\arg GPIO_AF_3: I2C0, TIMER14
|
||||
\arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13
|
||||
\arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0
|
||||
\arg GPIO_AF_6(port A,B only): SPI1
|
||||
\arg GPIO_AF_7(port A,B only): CMP
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin)
|
||||
{
|
||||
uint16_t i;
|
||||
uint32_t afrl, afrh;
|
||||
|
||||
afrl = GPIO_AFSEL0(gpio_periph);
|
||||
afrh = GPIO_AFSEL1(gpio_periph);
|
||||
|
||||
for(i = 0U; i < 8U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrl &= ~GPIO_AFR_MASK(i);
|
||||
afrl |= GPIO_AFR_SET(i, alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
for(i = 8U; i < 16U; i++) {
|
||||
if((1U << i) & pin) {
|
||||
/* clear the specified pin alternate function bits */
|
||||
afrh &= ~GPIO_AFR_MASK(i - 8U);
|
||||
afrh |= GPIO_AFR_SET(i - 8U, alt_func_num);
|
||||
}
|
||||
}
|
||||
|
||||
GPIO_AFSEL0(gpio_periph) = afrl;
|
||||
GPIO_AFSEL1(gpio_periph) = afrh;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief lock GPIO pin bit
|
||||
\param[in] gpio_periph: GPIOx(x = A,B)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
uint32_t lock = 0x00010000U;
|
||||
lock |= pin;
|
||||
|
||||
/* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)pin;
|
||||
GPIO_LOCK(gpio_periph) = (uint32_t)lock;
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
lock = GPIO_LOCK(gpio_periph);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO pin status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[in] pin: GPIO pin
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = (uint32_t)pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief toggle GPIO port status
|
||||
\param[in] gpio_periph: GPIOx(x = A,B,C,F)
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg GPIOx(x = A,B,C,F)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void gpio_port_toggle(uint32_t gpio_periph)
|
||||
{
|
||||
GPIO_TG(gpio_periph) = 0x0000FFFFU;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,141 +1,141 @@
|
||||
/*!
|
||||
\file gd32e23x_misc.c
|
||||
\brief MISC driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_misc.h"
|
||||
|
||||
/*!
|
||||
\brief enable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[in] nvic_irq_priority: the priority needed to set (0-3)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_enable(IRQn_Type nvic_irq,
|
||||
uint8_t nvic_irq_priority)
|
||||
{
|
||||
/* set the priority and enable the selected IRQ */
|
||||
NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority);
|
||||
NVIC_EnableIRQ((IRQn_Type)nvic_irq);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_disable(IRQn_Type nvic_irq)
|
||||
{
|
||||
/* disable the selected IRQ.*/
|
||||
NVIC_DisableIRQ((IRQn_Type)nvic_irq);
|
||||
}
|
||||
|
||||
/* */
|
||||
/*!
|
||||
\brief initiates a system reset request to reset the MCU
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_system_reset(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the NVIC vector table base address
|
||||
\param[in] nvic_vict_tab: the RAM or FLASH base address
|
||||
\arg NVIC_VECTTAB_RAM: RAM base address
|
||||
\arg NVIC_VECTTAB_FLASH: Flash base address
|
||||
\param[in] offset: Vector Table offset
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
||||
{
|
||||
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
|
||||
by all the enable and disable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_set(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR |= (uint32_t)lowpower_mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
|
||||
woke up by the enable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_reset(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR &= (~(uint32_t)lowpower_mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the systick clock source
|
||||
\param[in] systick_clksource: the systick clock source needed to choose
|
||||
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
|
||||
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
|
||||
void systick_clksource_set(uint32_t systick_clksource)
|
||||
{
|
||||
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
|
||||
/* set the systick clock source from HCLK */
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
} else {
|
||||
/* set the systick clock source from HCLK/8 */
|
||||
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
}
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_misc.c
|
||||
\brief MISC driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_misc.h"
|
||||
|
||||
/*!
|
||||
\brief enable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[in] nvic_irq_priority: the priority needed to set (0-3)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_enable(IRQn_Type nvic_irq,
|
||||
uint8_t nvic_irq_priority)
|
||||
{
|
||||
/* set the priority and enable the selected IRQ */
|
||||
NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority);
|
||||
NVIC_EnableIRQ((IRQn_Type)nvic_irq);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable NVIC request
|
||||
\param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_irq_disable(IRQn_Type nvic_irq)
|
||||
{
|
||||
/* disable the selected IRQ.*/
|
||||
NVIC_DisableIRQ((IRQn_Type)nvic_irq);
|
||||
}
|
||||
|
||||
/* */
|
||||
/*!
|
||||
\brief initiates a system reset request to reset the MCU
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_system_reset(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the NVIC vector table base address
|
||||
\param[in] nvic_vict_tab: the RAM or FLASH base address
|
||||
\arg NVIC_VECTTAB_RAM: RAM base address
|
||||
\arg NVIC_VECTTAB_FLASH: Flash base address
|
||||
\param[in] offset: Vector Table offset
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
|
||||
{
|
||||
SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
|
||||
__DSB();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
|
||||
by all the enable and disable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_set(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR |= (uint32_t)lowpower_mode;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief reset the state of the low power mode
|
||||
\param[in] lowpower_mode: the low power mode state
|
||||
\arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
|
||||
mode by exiting from ISR
|
||||
\arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
|
||||
\arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
|
||||
woke up by the enable interrupts
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void system_lowpower_reset(uint8_t lowpower_mode)
|
||||
{
|
||||
SCB->SCR &= (~(uint32_t)lowpower_mode);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the systick clock source
|
||||
\param[in] systick_clksource: the systick clock source needed to choose
|
||||
\arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
|
||||
\arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
|
||||
void systick_clksource_set(uint32_t systick_clksource)
|
||||
{
|
||||
if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
|
||||
/* set the systick clock source from HCLK */
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
} else {
|
||||
/* set the systick clock source from HCLK/8 */
|
||||
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,289 +1,289 @@
|
||||
/*!
|
||||
\file gd32e23x_pmu.c
|
||||
\brief PMU driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_pmu.h"
|
||||
|
||||
/*!
|
||||
\brief reset PMU register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_deinit(void)
|
||||
{
|
||||
/* reset PMU */
|
||||
rcu_periph_reset_enable(RCU_PMURST);
|
||||
rcu_periph_reset_disable(RCU_PMURST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select low voltage detector threshold
|
||||
\param[in] lvdt_n:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LVDT_0: voltage threshold is 2.1V
|
||||
\arg PMU_LVDT_1: voltage threshold is 2.3V
|
||||
\arg PMU_LVDT_2: voltage threshold is 2.4V
|
||||
\arg PMU_LVDT_3: voltage threshold is 2.6V
|
||||
\arg PMU_LVDT_4: voltage threshold is 2.7V
|
||||
\arg PMU_LVDT_5: voltage threshold is 2.9V
|
||||
\arg PMU_LVDT_6: voltage threshold is 3.0V
|
||||
\arg PMU_LVDT_7: voltage threshold is 3.1V
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_select(uint32_t lvdt_n)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
/* clear LVDT bits */
|
||||
PMU_CTL &= ~PMU_CTL_LVDT;
|
||||
/* set LVDT bits according to lvdt_n */
|
||||
PMU_CTL |= lvdt_n;
|
||||
/* enable LVD */
|
||||
PMU_CTL |= PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select LDO output voltage
|
||||
these bits set by software when the main PLL closed
|
||||
\param[in] ldo_output:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDOVS_LOW: LDO output voltage low mode
|
||||
\arg PMU_LDOVS_HIGH: LDO output voltage high mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_ldo_output_select(uint32_t ldo_output)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDOVS;
|
||||
PMU_CTL |= ldo_output;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable PMU lvd
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_disable(void)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at sleep mode
|
||||
\param[in] sleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd)
|
||||
{
|
||||
/* clear sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* select WFI or WFE command to enter sleep mode */
|
||||
if(WFI_CMD == sleepmodecmd) {
|
||||
__WFI();
|
||||
} else {
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at deepsleep mode
|
||||
\param[in] ldo:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
|
||||
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
|
||||
\param[in] deepsleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
|
||||
{
|
||||
/* clear stbmod and ldolp bits */
|
||||
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
|
||||
|
||||
/* set ldolp bit according to pmu_ldo */
|
||||
PMU_CTL |= ldo;
|
||||
|
||||
/* set sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* select WFI or WFE command to enter deepsleep mode */
|
||||
if(WFI_CMD == deepsleepmodecmd) {
|
||||
__WFI();
|
||||
} else {
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* reset sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief pmu work at standby mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_standbymode(void)
|
||||
{
|
||||
/* switch to IRC8M clock as system clock, close HXTAL */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
|
||||
|
||||
/* set stbmod bit */
|
||||
PMU_CTL |= PMU_CTL_STBMOD;
|
||||
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
|
||||
/* set sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
REG32(0xE000E010U) &= 0x00010004U;
|
||||
REG32(0xE000E180U) = 0XFFFFFFFBU;
|
||||
REG32(0xE000E184U) = 0XFFFFFFFFU;
|
||||
REG32(0xE000E188U) = 0xFFFFFFFFU;
|
||||
|
||||
/* select WFI command to enter standby mode */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS |= wakeup_pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS &= ~(wakeup_pin);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_enable(void)
|
||||
{
|
||||
PMU_CTL |= PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_disable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state
|
||||
\param[in] flag:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_FLAG_WAKEUP: wakeup flag
|
||||
\arg PMU_FLAG_STANDBY: standby flag
|
||||
\arg PMU_FLAG_LVD: lvd flag
|
||||
\param[out] none
|
||||
\retval FlagStatus SET or RESET
|
||||
*/
|
||||
FlagStatus pmu_flag_get(uint32_t flag)
|
||||
{
|
||||
FlagStatus ret_status = RESET;
|
||||
|
||||
if(PMU_CS & flag) {
|
||||
ret_status = SET;
|
||||
}
|
||||
|
||||
return ret_status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear flag bit
|
||||
\param[in] flag:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
||||
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_flag_clear(uint32_t flag)
|
||||
{
|
||||
if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)) {
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
}
|
||||
if(RESET != (flag & PMU_FLAG_RESET_STANDBY)) {
|
||||
/* reset standby flag */
|
||||
PMU_CTL |= PMU_CTL_STBRST;
|
||||
}
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_pmu.c
|
||||
\brief PMU driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_pmu.h"
|
||||
|
||||
/*!
|
||||
\brief reset PMU register
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_deinit(void)
|
||||
{
|
||||
/* reset PMU */
|
||||
rcu_periph_reset_enable(RCU_PMURST);
|
||||
rcu_periph_reset_disable(RCU_PMURST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select low voltage detector threshold
|
||||
\param[in] lvdt_n:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LVDT_0: voltage threshold is 2.1V
|
||||
\arg PMU_LVDT_1: voltage threshold is 2.3V
|
||||
\arg PMU_LVDT_2: voltage threshold is 2.4V
|
||||
\arg PMU_LVDT_3: voltage threshold is 2.6V
|
||||
\arg PMU_LVDT_4: voltage threshold is 2.7V
|
||||
\arg PMU_LVDT_5: voltage threshold is 2.9V
|
||||
\arg PMU_LVDT_6: voltage threshold is 3.0V
|
||||
\arg PMU_LVDT_7: voltage threshold is 3.1V
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_select(uint32_t lvdt_n)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
/* clear LVDT bits */
|
||||
PMU_CTL &= ~PMU_CTL_LVDT;
|
||||
/* set LVDT bits according to lvdt_n */
|
||||
PMU_CTL |= lvdt_n;
|
||||
/* enable LVD */
|
||||
PMU_CTL |= PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief select LDO output voltage
|
||||
these bits set by software when the main PLL closed
|
||||
\param[in] ldo_output:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDOVS_LOW: LDO output voltage low mode
|
||||
\arg PMU_LDOVS_HIGH: LDO output voltage high mode
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_ldo_output_select(uint32_t ldo_output)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_LDOVS;
|
||||
PMU_CTL |= ldo_output;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable PMU lvd
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_lvd_disable(void)
|
||||
{
|
||||
/* disable LVD */
|
||||
PMU_CTL &= ~PMU_CTL_LVDEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at sleep mode
|
||||
\param[in] sleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd)
|
||||
{
|
||||
/* clear sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
/* select WFI or WFE command to enter sleep mode */
|
||||
if(WFI_CMD == sleepmodecmd) {
|
||||
__WFI();
|
||||
} else {
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief PMU work at deepsleep mode
|
||||
\param[in] ldo:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode
|
||||
\arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode
|
||||
\param[in] deepsleepmodecmd:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WFI_CMD: use WFI command
|
||||
\arg WFE_CMD: use WFE command
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd)
|
||||
{
|
||||
/* clear stbmod and ldolp bits */
|
||||
PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP));
|
||||
|
||||
/* set ldolp bit according to pmu_ldo */
|
||||
PMU_CTL |= ldo;
|
||||
|
||||
/* set sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
/* select WFI or WFE command to enter deepsleep mode */
|
||||
if(WFI_CMD == deepsleepmodecmd) {
|
||||
__WFI();
|
||||
} else {
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
|
||||
/* reset sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief pmu work at standby mode
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_to_standbymode(void)
|
||||
{
|
||||
/* switch to IRC8M clock as system clock, close HXTAL */
|
||||
RCU_CFG0 &= ~RCU_CFG0_SCS;
|
||||
RCU_CTL0 &= ~RCU_CTL0_HXTALEN;
|
||||
|
||||
/* set stbmod bit */
|
||||
PMU_CTL |= PMU_CTL_STBMOD;
|
||||
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
|
||||
/* set sleepdeep bit of Cortex-M23 system control register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
|
||||
REG32(0xE000E010U) &= 0x00010004U;
|
||||
REG32(0xE000E180U) = 0XFFFFFFFBU;
|
||||
REG32(0xE000E184U) = 0XFFFFFFFFU;
|
||||
REG32(0xE000E188U) = 0xFFFFFFFFU;
|
||||
|
||||
/* select WFI command to enter standby mode */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS |= wakeup_pin;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable wakeup pin
|
||||
\param[in] wakeup_pin:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
|
||||
\arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
|
||||
\arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5)
|
||||
\arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
|
||||
{
|
||||
PMU_CS &= ~(wakeup_pin);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_enable(void)
|
||||
{
|
||||
PMU_CTL |= PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable backup domain write
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_backup_write_disable(void)
|
||||
{
|
||||
PMU_CTL &= ~PMU_CTL_BKPWEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief get flag state
|
||||
\param[in] flag:
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg PMU_FLAG_WAKEUP: wakeup flag
|
||||
\arg PMU_FLAG_STANDBY: standby flag
|
||||
\arg PMU_FLAG_LVD: lvd flag
|
||||
\param[out] none
|
||||
\retval FlagStatus SET or RESET
|
||||
*/
|
||||
FlagStatus pmu_flag_get(uint32_t flag)
|
||||
{
|
||||
FlagStatus ret_status = RESET;
|
||||
|
||||
if(PMU_CS & flag) {
|
||||
ret_status = SET;
|
||||
}
|
||||
|
||||
return ret_status;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear flag bit
|
||||
\param[in] flag:
|
||||
one or more parameters can be selected which are shown as below:
|
||||
\arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
|
||||
\arg PMU_FLAG_RESET_STANDBY: reset standby flag
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void pmu_flag_clear(uint32_t flag)
|
||||
{
|
||||
if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)) {
|
||||
/* reset wakeup flag */
|
||||
PMU_CTL |= PMU_CTL_WURST;
|
||||
}
|
||||
if(RESET != (flag & PMU_FLAG_RESET_STANDBY)) {
|
||||
/* reset standby flag */
|
||||
PMU_CTL |= PMU_CTL_STBRST;
|
||||
}
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,205 +1,205 @@
|
||||
/*!
|
||||
\file gd32e23x_syscfg.c
|
||||
\brief SYSCFG driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_syscfg.h"
|
||||
|
||||
/*!
|
||||
\brief reset the SYSCFG registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_CFGCMPRST);
|
||||
rcu_periph_reset_disable(RCU_CFGCMPRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the DMA channels remapping
|
||||
\param[in] syscfg_dma_remap: specify the DMA channels to remap
|
||||
\arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
|
||||
\arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
|
||||
\arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
|
||||
\arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
|
||||
{
|
||||
SYSCFG_CFG0 |= syscfg_dma_remap;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the DMA channels remapping
|
||||
\param[in] syscfg_dma_remap: specify the DMA channels to remap
|
||||
\arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
|
||||
\arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
|
||||
\arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
|
||||
\arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
|
||||
{
|
||||
SYSCFG_CFG0 &= ~syscfg_dma_remap;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable PB9 high current capability
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_high_current_enable(void)
|
||||
{
|
||||
SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable PB9 high current capability
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_high_current_disable(void)
|
||||
{
|
||||
SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the GPIO pin as EXTI Line
|
||||
\param[in] exti_port: specify the GPIO port used in EXTI
|
||||
\arg EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port
|
||||
\param[in] exti_pin: specify the EXTI line
|
||||
\arg EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
|
||||
{
|
||||
uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
|
||||
uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
|
||||
|
||||
switch(exti_pin / EXTI_SS_JSTEP) {
|
||||
case EXTISS0:
|
||||
/* clear EXTI source line(0..3) */
|
||||
SYSCFG_EXTISS0 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(0..3) */
|
||||
SYSCFG_EXTISS0 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS1:
|
||||
/* clear EXTI soure line(4..7) */
|
||||
SYSCFG_EXTISS1 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(4..7) */
|
||||
SYSCFG_EXTISS1 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS2:
|
||||
/* clear EXTI soure line(8..11) */
|
||||
SYSCFG_EXTISS2 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(8..11) */
|
||||
SYSCFG_EXTISS2 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS3:
|
||||
/* clear EXTI soure line(12..15) */
|
||||
SYSCFG_EXTISS3 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(12..15) */
|
||||
SYSCFG_EXTISS3 |= config_exti_mask;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief connect TIMER0/14/15/16 break input to the selected parameter
|
||||
\param[in] syscfg_lock: Specify the parameter to be connected
|
||||
\arg SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input
|
||||
\arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
|
||||
\arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_lock_config(uint32_t syscfg_lock)
|
||||
{
|
||||
SYSCFG_CFG2 |= syscfg_lock;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the wait state counter value
|
||||
\param[in] irq_latency: IRQ_LATENCY value (0x00 - 0xFF)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void irq_latency_set(uint8_t irq_latency)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = SYSCFG_CPU_IRQ_LAT & (~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY);
|
||||
reg |= (uint32_t)(IRQ_LATENCY(irq_latency));
|
||||
|
||||
SYSCFG_CPU_IRQ_LAT = (uint32_t)reg;
|
||||
}
|
||||
/*!
|
||||
\brief check if the specified flag in SYSCFG_CFG2 is set or not.
|
||||
\param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check.
|
||||
\arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
|
||||
\param[out] none
|
||||
\retval the syscfg_flag state returned (SET or RESET).
|
||||
*/
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
|
||||
{
|
||||
if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the flag in SYSCFG_CFG2 by writing 1.
|
||||
\param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear.
|
||||
\arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag)
|
||||
{
|
||||
SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
|
||||
}
|
||||
|
||||
/*!
|
||||
\file gd32e23x_syscfg.c
|
||||
\brief SYSCFG driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_syscfg.h"
|
||||
|
||||
/*!
|
||||
\brief reset the SYSCFG registers
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_CFGCMPRST);
|
||||
rcu_periph_reset_disable(RCU_CFGCMPRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable the DMA channels remapping
|
||||
\param[in] syscfg_dma_remap: specify the DMA channels to remap
|
||||
\arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
|
||||
\arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
|
||||
\arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
|
||||
\arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap)
|
||||
{
|
||||
SYSCFG_CFG0 |= syscfg_dma_remap;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable the DMA channels remapping
|
||||
\param[in] syscfg_dma_remap: specify the DMA channels to remap
|
||||
\arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0)
|
||||
\arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2)
|
||||
\arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1)
|
||||
\arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1
|
||||
\arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap)
|
||||
{
|
||||
SYSCFG_CFG0 &= ~syscfg_dma_remap;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable PB9 high current capability
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_high_current_enable(void)
|
||||
{
|
||||
SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief disable PB9 high current capability
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_high_current_disable(void)
|
||||
{
|
||||
SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the GPIO pin as EXTI Line
|
||||
\param[in] exti_port: specify the GPIO port used in EXTI
|
||||
\arg EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port
|
||||
\param[in] exti_pin: specify the EXTI line
|
||||
\arg EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
|
||||
{
|
||||
uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
|
||||
uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
|
||||
|
||||
switch(exti_pin / EXTI_SS_JSTEP) {
|
||||
case EXTISS0:
|
||||
/* clear EXTI source line(0..3) */
|
||||
SYSCFG_EXTISS0 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(0..3) */
|
||||
SYSCFG_EXTISS0 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS1:
|
||||
/* clear EXTI soure line(4..7) */
|
||||
SYSCFG_EXTISS1 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(4..7) */
|
||||
SYSCFG_EXTISS1 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS2:
|
||||
/* clear EXTI soure line(8..11) */
|
||||
SYSCFG_EXTISS2 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(8..11) */
|
||||
SYSCFG_EXTISS2 |= config_exti_mask;
|
||||
break;
|
||||
case EXTISS3:
|
||||
/* clear EXTI soure line(12..15) */
|
||||
SYSCFG_EXTISS3 &= clear_exti_mask;
|
||||
/* configure EXTI soure line(12..15) */
|
||||
SYSCFG_EXTISS3 |= config_exti_mask;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief connect TIMER0/14/15/16 break input to the selected parameter
|
||||
\param[in] syscfg_lock: Specify the parameter to be connected
|
||||
\arg SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input
|
||||
\arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input
|
||||
\arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_lock_config(uint32_t syscfg_lock)
|
||||
{
|
||||
SYSCFG_CFG2 |= syscfg_lock;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief set the wait state counter value
|
||||
\param[in] irq_latency: IRQ_LATENCY value (0x00 - 0xFF)
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void irq_latency_set(uint8_t irq_latency)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = SYSCFG_CPU_IRQ_LAT & (~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY);
|
||||
reg |= (uint32_t)(IRQ_LATENCY(irq_latency));
|
||||
|
||||
SYSCFG_CPU_IRQ_LAT = (uint32_t)reg;
|
||||
}
|
||||
/*!
|
||||
\brief check if the specified flag in SYSCFG_CFG2 is set or not.
|
||||
\param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check.
|
||||
\arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
|
||||
\param[out] none
|
||||
\retval the syscfg_flag state returned (SET or RESET).
|
||||
*/
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag)
|
||||
{
|
||||
if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) {
|
||||
return SET;
|
||||
} else {
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear the flag in SYSCFG_CFG2 by writing 1.
|
||||
\param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear.
|
||||
\arg SYSCFG_SRAM_PCEF: SRAM parity check error flag.
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag)
|
||||
{
|
||||
SYSCFG_CFG2 |= (uint32_t) syscfg_flag;
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,126 +1,126 @@
|
||||
/*!
|
||||
\file gd32e23x_wwdgt.c
|
||||
\brief WWDGT driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_wwdgt.h"
|
||||
|
||||
/*!
|
||||
\brief reset the window watchdog timer configuration
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_WWDGTRST);
|
||||
rcu_periph_reset_disable(RCU_WWDGTRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the window watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_enable(void)
|
||||
{
|
||||
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the window watchdog timer counter value
|
||||
\param[in] counter_value: 0x00000000 - 0x0000007F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_counter_update(uint16_t counter_value)
|
||||
{
|
||||
WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter value, window value, and prescaler divider value
|
||||
\param[in] counter: 0x00000000 - 0x0000007F
|
||||
\param[in] window: 0x00000000 - 0x0000007F
|
||||
\param[in] prescaler: wwdgt prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
|
||||
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
|
||||
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
|
||||
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
||||
{
|
||||
WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler);
|
||||
WWDGT_CTL = (uint32_t)(CTL_CNT(counter));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus wwdgt_flag_get(void)
|
||||
{
|
||||
if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)) {
|
||||
return SET;
|
||||
}
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_flag_clear(void)
|
||||
{
|
||||
WWDGT_STAT &= (~(uint32_t)WWDGT_STAT_EWIF);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable early wakeup interrupt of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_interrupt_enable(void)
|
||||
{
|
||||
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
||||
}
|
||||
/*!
|
||||
\file gd32e23x_wwdgt.c
|
||||
\brief WWDGT driver
|
||||
|
||||
\version 2025-02-10, V2.3.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "gd32e23x_wwdgt.h"
|
||||
|
||||
/*!
|
||||
\brief reset the window watchdog timer configuration
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_deinit(void)
|
||||
{
|
||||
rcu_periph_reset_enable(RCU_WWDGTRST);
|
||||
rcu_periph_reset_disable(RCU_WWDGTRST);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief start the window watchdog timer counter
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_enable(void)
|
||||
{
|
||||
WWDGT_CTL |= WWDGT_CTL_WDGTEN;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure the window watchdog timer counter value
|
||||
\param[in] counter_value: 0x00000000 - 0x0000007F
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_counter_update(uint16_t counter_value)
|
||||
{
|
||||
WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief configure counter value, window value, and prescaler divider value
|
||||
\param[in] counter: 0x00000000 - 0x0000007F
|
||||
\param[in] window: 0x00000000 - 0x0000007F
|
||||
\param[in] prescaler: wwdgt prescaler value
|
||||
only one parameter can be selected which is shown as below:
|
||||
\arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1
|
||||
\arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2
|
||||
\arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4
|
||||
\arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler)
|
||||
{
|
||||
WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler);
|
||||
WWDGT_CTL = (uint32_t)(CTL_CNT(counter));
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief check early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval FlagStatus: SET or RESET
|
||||
*/
|
||||
FlagStatus wwdgt_flag_get(void)
|
||||
{
|
||||
if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)) {
|
||||
return SET;
|
||||
}
|
||||
return RESET;
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief clear early wakeup interrupt state of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_flag_clear(void)
|
||||
{
|
||||
WWDGT_STAT &= (~(uint32_t)WWDGT_STAT_EWIF);
|
||||
}
|
||||
|
||||
/*!
|
||||
\brief enable early wakeup interrupt of WWDGT
|
||||
\param[in] none
|
||||
\param[out] none
|
||||
\retval none
|
||||
*/
|
||||
void wwdgt_interrupt_enable(void)
|
||||
{
|
||||
WWDGT_CFG |= WWDGT_CFG_EWIE;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user