diff --git a/.gitignore b/.gitignore index b1e9698..c69c7c5 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,6 @@ -# 忽略构建输出目录 -Build/ - -# 忽略 Toolchain 目录下所有内容，但保留目录本身 -Toolchain/* -!Toolchain/.gitkeep +# 忽略构建输出目录 +Build/ + +# 忽略 Toolchain 目录下所有内容，但保留目录本身 +Toolchain/* +!Toolchain/.gitkeep diff --git a/.vscode/extensions.json b/.vscode/extensions.json index 3243635..536a777 100644 --- a/.vscode/extensions.json +++ b/.vscode/extensions.json @@ -1,26 +1,26 @@ -{ - "recommendations": [ - "ms-vscode.cmake-tools", - "ms-vscode.cpptools", - "ms-vscode.cpptools-extension-pack", - "ms-vscode.cpptools-themes", - "ms-vscode.vscode-embedded-tools", - "ms-vscode.hexeditor", - "ms-vscode.notepadplusplus-keybindings", - "twxs.cmake", - "xaver.clang-format", - "marus25.cortex-debug", - "cheshirekow.cmake-format", - "mcu-debug.debug-tracker-vscode", - "mcu-debug.memory-view", - "mcu-debug.peripheral-viewer", - "mcu-debug.rtos-views", - "trond-snekvik.gnu-mapfiles", - "zixuanwang.linkerscript", - "gurumukhi.selected-lines-count", - "gruntfuggly.todo-tree", - "vscode-icons-team.vscode-icons", - "jeff-hykin.better-cpp-syntax", - "dan-c-underwood.arm" - ] +{ + "recommendations": [ + "ms-vscode.cmake-tools", + "ms-vscode.cpptools", + "ms-vscode.cpptools-extension-pack", + "ms-vscode.cpptools-themes", + "ms-vscode.vscode-embedded-tools", + "ms-vscode.hexeditor", + "ms-vscode.notepadplusplus-keybindings", + "twxs.cmake", + "xaver.clang-format", + "marus25.cortex-debug", + "cheshirekow.cmake-format", + "mcu-debug.debug-tracker-vscode", + "mcu-debug.memory-view", + "mcu-debug.peripheral-viewer", + "mcu-debug.rtos-views", + "trond-snekvik.gnu-mapfiles", + "zixuanwang.linkerscript", + "gurumukhi.selected-lines-count", + "gruntfuggly.todo-tree", + "vscode-icons-team.vscode-icons", + "jeff-hykin.better-cpp-syntax", + "dan-c-underwood.arm" + ] } \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json index 717cbb6..7872a68 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -1,36 +1,36 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "cwd": "${workspaceFolder}", - "executable": "${workspaceFolder}/Build/Debug/Application/Application.elf", - "name": "Debug with OpenOCD", - "request": "launch", - "type": "cortex-debug", - "runToEntryPoint": "main", - "showDevDebugOutput": "none", - "gdbPath": "${workspaceFolder}/Toolchain/xpack-arm-none-eabi-gcc-11.3.1-1.1/bin/arm-none-eabi-gdb.exe", - "servertype": "openocd", - "serverpath": "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe", - "svdFile": "${workspaceFolder}/GD32E230.svd", - "liveWatch": { - "enabled": true, - "samplesPerSecond": 1 - }, - "configFiles": [ - "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg" - ], - "serverArgs": [ - "-s", "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts" - ], - "searchDir": [ - "${workspaceFolder}" - ], - "preLaunchTask": "Build", - "preRestartCommands": [ - "load", - "continue" - ], - }, - ] +{ + "version": "0.2.0", + "configurations": [ + { + "cwd": "${workspaceFolder}", + "executable": "${workspaceFolder}/Build/Debug/Application/Application.elf", + "name": "Debug with OpenOCD", + "request": "launch", + "type": "cortex-debug", + "runToEntryPoint": "main", + "showDevDebugOutput": "none", + "gdbPath": "${workspaceFolder}/Toolchain/xpack-arm-none-eabi-gcc-11.3.1-1.1/bin/arm-none-eabi-gdb.exe", + "servertype": "openocd", + "serverpath": "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe", + "svdFile": "${workspaceFolder}/GD32E230.svd", + "liveWatch": { + "enabled": true, + "samplesPerSecond": 1 + }, + "configFiles": [ + "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg" + ], + "serverArgs": [ + "-s", "${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts" + ], + "searchDir": [ + "${workspaceFolder}" + ], + "preLaunchTask": "Build", + "preRestartCommands": [ + "load", + "continue" + ], + }, + ] } \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json index 4107651..d13f602 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -1,30 +1,26 @@ -{ - "terminal.integrated.tabs.enabled": true, - "terminal.integrated.profiles.windows": { - "Git Bash": { - "path": "C:\\Program Files\\Git\\bin\\bash.exe", - "icon": "terminal-bash" - }, - "Git-Bash": { - "path": "D:\\Git\\bin\\bash.exe", - "icon": "terminal-bash" - } - }, - "terminal.integrated.defaultProfile.windows": "Git-Bash", - "clang-format.assumeFilename": ".clang-format", - "clang-format.executable": "clang-format", - "C_Cpp.default.configurationProvider": "ms-vscode.cmake-tools", - "cmake.configureOnOpen": true, - "cmake.buildDirectory": "${workspaceFolder}/Build", - "vcpkg.storageLocation": "C:\\Dev\\Tools\\vcpkg", - "files.associations": { - "*.h": "c", - "*.c": "c", - "array": "c", - "string": "c", - "string_view": "c", - "ranges": "c", - "span": "c" - }, - "cortex-debug.variableUseNaturalFormat": true, +{ + "terminal.integrated.tabs.enabled": true, + "terminal.integrated.profiles.windows": { + "Git Bash": { + "path": "C:\\Program Files\\Git\\bin\\bash.exe", + "icon": "terminal-bash" + } + }, + "terminal.integrated.defaultProfile.windows": "Git Bash", + "clang-format.assumeFilename": ".clang-format", + "clang-format.executable": "clang-format", + "C_Cpp.default.configurationProvider": "ms-vscode.cmake-tools", + "cmake.configureOnOpen": true, + "cmake.buildDirectory": "${workspaceFolder}/Build", + "vcpkg.storageLocation": "C:\\Dev\\Tools\\vcpkg", + "files.associations": { + "*.h": "c", + "*.c": "c", + "array": "c", + "string": "c", + "string_view": "c", + "ranges": "c", + "span": "c" + }, + "cortex-debug.variableUseNaturalFormat": true, } \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json index 3c31cd0..e71d82a 100644 --- a/.vscode/tasks.json +++ b/.vscode/tasks.json @@ -1,145 +1,145 @@ -{ - "version": "2.0.0", - "tasks": [ - { - "label": "Build and Flash", - "group": { - "kind": "build", - "isDefault": true - }, - "dependsOn": [ - "Build", - "Flash MCU" - ], - "dependsOrder": "sequence", - "icon": { - "id": "insert", - "tooltip": "Build and Flash" - } - }, - { - "label": "Flash MCU", - "type": "shell", - "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset halt; flash write_image erase ${command:cmake.launchTargetFilename}; reset; exit'", - "group": { - "kind": "build", - "isDefault": true - }, - "problemMatcher": [], - "options": { - "cwd": "${command:cmake.buildDirectory}/Application", - "environment": { - "CLICOLOR_FORCE": "1", - "OPENOCD_SCRIPTS": "" - } - }, - "presentation": { - "clear": true - }, - "icon": { - "id": "gather", - "tooltip": "Flash MCU" - } - }, - { - "label": "Reset MCU", - "type": "shell", - "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset; exit'", - "group": { - "kind": "build", - "isDefault": true - }, - "problemMatcher": [], - "options": { - "cwd": "${command:cmake.buildDirectory}/Application", - "environment": { - "CLICOLOR_FORCE": "1", - "OPENOCD_SCRIPTS": "" - } - }, - "presentation": { - "clear": true - }, - "icon": { - "id": "discard", - "tooltip": "Reset MCU" - } - }, - { - "label": "Mass Erase MCU", - "type": "shell", - "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset halt; gd32e23x mass_erase 0; exit'", - "group": { - "kind": "build", - "isDefault": true - }, - "problemMatcher": [], - "options": { - "cwd": "${command:cmake.buildDirectory}/Application", - "environment": { - "CLICOLOR_FORCE": "1", - "OPENOCD_SCRIPTS": "" - } - }, - "presentation": { - "clear": true - }, - "icon": { - "id": "clear-all", - "tooltip": "Erase MCU" - } - }, - { - "label": "OpenOCD Server", - "type": "shell", - "command": [ - "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg'" - ], - "group": { - "kind": "build", - "isDefault": true - }, - "problemMatcher": [], - "options": { - "cwd": "${command:cmake.buildDirectory}/Application", - "environment": { - "CLICOLOR_FORCE": "1", - "OPENOCD_SCRIPTS": "" - } - }, - "presentation": { - "clear": true - } - }, - { - "label": "Build", - "type": "cmake", - "command": "build", - "group": { - "kind": "build", - "isDefault": true - }, - "problemMatcher": [ - { - "base": "$gcc", - "fileLocation": [ - "relative", - "${command:cmake.buildDirectory}" - ] - } - ], - "options": { - "environment": { - "CLICOLOR_FORCE": "1" - } - }, - "presentation": { - "clear": true - }, - "icon": { - "id": "code", - "tooltip": "Build" - } - } - ] +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Build and Flash", + "group": { + "kind": "build", + "isDefault": true + }, + "dependsOn": [ + "Build", + "Flash MCU" + ], + "dependsOrder": "sequence", + "icon": { + "id": "insert", + "tooltip": "Build and Flash" + } + }, + { + "label": "Flash MCU", + "type": "shell", + "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset halt; flash write_image erase ${command:cmake.launchTargetFilename}; reset; exit'", + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "options": { + "cwd": "${command:cmake.buildDirectory}/Application", + "environment": { + "CLICOLOR_FORCE": "1", + "OPENOCD_SCRIPTS": "" + } + }, + "presentation": { + "clear": true + }, + "icon": { + "id": "gather", + "tooltip": "Flash MCU" + } + }, + { + "label": "Reset MCU", + "type": "shell", + "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset; exit'", + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "options": { + "cwd": "${command:cmake.buildDirectory}/Application", + "environment": { + "CLICOLOR_FORCE": "1", + "OPENOCD_SCRIPTS": "" + } + }, + "presentation": { + "clear": true + }, + "icon": { + "id": "discard", + "tooltip": "Reset MCU" + } + }, + { + "label": "Mass Erase MCU", + "type": "shell", + "command": "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg' -c 'init; reset halt; gd32e23x mass_erase 0; exit'", + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "options": { + "cwd": "${command:cmake.buildDirectory}/Application", + "environment": { + "CLICOLOR_FORCE": "1", + "OPENOCD_SCRIPTS": "" + } + }, + "presentation": { + "clear": true + }, + "icon": { + "id": "clear-all", + "tooltip": "Erase MCU" + } + }, + { + "label": "OpenOCD Server", + "type": "shell", + "command": [ + "'${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/bin/openocd.exe' -s '${workspaceFolder}' -f '${workspaceFolder}/Toolchain/xpack-openocd-0.11.0-3/scripts/target/openocd_gdlink_gd32e23x.cfg'" + ], + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [], + "options": { + "cwd": "${command:cmake.buildDirectory}/Application", + "environment": { + "CLICOLOR_FORCE": "1", + "OPENOCD_SCRIPTS": "" + } + }, + "presentation": { + "clear": true + } + }, + { + "label": "Build", + "type": "cmake", + "command": "build", + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + { + "base": "$gcc", + "fileLocation": [ + "relative", + "${command:cmake.buildDirectory}" + ] + } + ], + "options": { + "environment": { + "CLICOLOR_FORCE": "1" + } + }, + "presentation": { + "clear": true + }, + "icon": { + "id": "code", + "tooltip": "Build" + } + } + ] } \ No newline at end of file diff --git a/CommunicationProtocol.md b/CommunicationProtocol.md index 451a69d..42a5207 100644 --- a/CommunicationProtocol.md +++ b/CommunicationProtocol.md @@ -1,62 +1,62 @@ -# 电涡流传感器模块通信协议 - -## 电涡流传感器模块通信协议 - -| **序号** | **修改内容** | **版本** | **日期** | **修改人** | -|:------:|:--------:|:------:|:----------:|:-------:| -| 1 | 初版 | V1.0 | 2024-12-25 | Hulk | -| 2 | 修改指令含义 | V1.1 | 20250822 | Hulk | -| | | | | | -| | | | | | - -### 发包格式 - -| **包头** | **类型** | **数据长度** | **数据** | **校验** | -|:------:|:------:|:-----------:|:------:|:------:| -| D5 | 0x03 | Data Length | Data | CRC | - -- 数据长度只包含数据部分，不包含包头、类型、数据长度、校验 -- CRC求和校验，包含类型、数据长度、数据 -- 数据部分为ascii码 - -### 回包格式 - -| **包头** | **状态码** | **数据长度** | **数据** | **校验** | -|:------:|:----------:|:-----------:|:------:|:------:| -| B5 | 0xF0 正常包 | Data Length | Data | CRC | -| B5 | 0xF1 CRC错误 | Data Length | Data | CRC | -| B5 | 0xF2 包头错误 | Data Length | Data | CRC | -| B5 | 0xF3 类型错误 | Data Length | Data | CRC | -| B5 | 0xF4 包长度错误 | Data Length | Data | CRC | - -- 数据长度仅包含数据部分，不包含包头状态码等 -- CRC求和校验，包含状态码数据长度和数据部分 - -------------------- - -## 电涡流传感器模块功能 - -### 1. 开启自动读取并发送电涡流传感器模块数据 - -- M1指令 开启自动读取并发送涡流传感器数据，间隔10ms左右 - - `D5 03 02 4D 31 83` -- 电涡流传感器模块涡流回复数据 - - `B5 F0 04 01 AE 1B E4 A2`, 有效数据为 `0x01AE1BE4`，转换为`28187620` - - `B5 F0 04 04 19 C1 FA CC`, 有效数据为 `0x0419C1FAD2`，转换为`17612012242` - - -### 2. 关闭自动读取并发送电涡流传感器模块数据 - -- M2 指令 关闭自动读取并发送涡流传感器数据 - - `D5 03 02 4D 32 84` - > 注：因为485总线为半双工，M1命令开启后持续自动发送数据，M2指令发送停止命令可能无法一次成功，可持续发送几次 - -### 3. 单次读取并发送电涡流传感器数据 - -- M3 指令 单次读取并发送涡流传感器数据 - - `D5 03 02 4D 33 85` - -### 4. 单次读取并发送板载温度传感器数据 - -- M3 指令 单次读取并发送板载温度传感器数据 - - `D5 03 02 4D 34 86` +# 电涡流传感器模块通信协议 + +## 电涡流传感器模块通信协议 + +| **序号** | **修改内容** | **版本** | **日期** | **修改人** | +|:------:|:--------:|:------:|:----------:|:-------:| +| 1 | 初版 | V1.0 | 2024-12-25 | Hulk | +| 2 | 修改指令含义 | V1.1 | 20250822 | Hulk | +| | | | | | +| | | | | | + +### 发包格式 + +| **包头** | **类型** | **数据长度** | **数据** | **校验** | +|:------:|:------:|:-----------:|:------:|:------:| +| D5 | 0x03 | Data Length | Data | CRC | + +- 数据长度只包含数据部分，不包含包头、类型、数据长度、校验 +- CRC求和校验，包含类型、数据长度、数据 +- 数据部分为ascii码 + +### 回包格式 + +| **包头** | **状态码** | **数据长度** | **数据** | **校验** | +|:------:|:----------:|:-----------:|:------:|:------:| +| B5 | 0xF0 正常包 | Data Length | Data | CRC | +| B5 | 0xF1 CRC错误 | Data Length | Data | CRC | +| B5 | 0xF2 包头错误 | Data Length | Data | CRC | +| B5 | 0xF3 类型错误 | Data Length | Data | CRC | +| B5 | 0xF4 包长度错误 | Data Length | Data | CRC | + +- 数据长度仅包含数据部分，不包含包头状态码等 +- CRC求和校验，包含状态码数据长度和数据部分 + +------------------- + +## 电涡流传感器模块功能 + +### 1. 开启自动读取并发送电涡流传感器模块数据 + +- M1指令 开启自动读取并发送涡流传感器数据，间隔10ms左右 + - `D5 03 02 4D 31 83` +- 电涡流传感器模块涡流回复数据 + - `B5 F0 04 01 AE 1B E4 A2`, 有效数据为 `0x01AE1BE4`，转换为`28187620` + - `B5 F0 04 04 19 C1 FA CC`, 有效数据为 `0x0419C1FAD2`，转换为`17612012242` + + +### 2. 关闭自动读取并发送电涡流传感器模块数据 + +- M2 指令 关闭自动读取并发送涡流传感器数据 + - `D5 03 02 4D 32 84` + > 注：因为485总线为半双工，M1命令开启后持续自动发送数据，M2指令发送停止命令可能无法一次成功，可持续发送几次 + +### 3. 单次读取并发送电涡流传感器数据 + +- M3 指令 单次读取并发送涡流传感器数据 + - `D5 03 02 4D 33 85` + +### 4. 单次读取并发送板载温度传感器数据 + +- M3 指令 单次读取并发送板载温度传感器数据 + - `D5 03 02 4D 34 86` diff --git a/GD32E230.svd b/GD32E230.svd index c4b95e9..b68dd9b 100644 --- a/GD32E230.svd +++ b/GD32E230.svd @@ -1,19783 +1,19783 @@ - - - GD32E230 - 1.0 - GD32E230 ARM 32-bit Cortex-M23 Microcontroller based device - - CM23 - r0p0 - little - 1 - 1 - 4 - 0 - - 8 - 32 - - - - - 0x20 - 0x0 - 0xFFFFFFFF - - - ADC - Analog to digital converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC_CMP - 12 - - - - STAT - STAT - status register - 0x0 - 0x20 - read-write - 0x00000000 - - - STRC - Start flag of regular channel group - 4 - 1 - - - STIC - Start flag of inserted channel group - 3 - 1 - - - EOIC - End of inserted group conversion flag - 2 - 1 - - - EOC - End of group conversion flag - 1 - 1 - - - WDE - Analog watchdog event flag - 0 - 1 - - - - - CTL0 - CTL0 - control register 0 - 0x4 - 0x20 - read-write - 0x00000000 - - - DRES - ADC resolution - 24 - 2 - - - RWDEN - Regular channel analog watchdog enable - 23 - 1 - - - IWDEN - Inserted channel analog watchdog enable - 22 - 1 - - - DISNUM - Number of conversions in discontinuous - mode - 13 - 3 - - - DISIC - Discontinuous mode on injected - channels - 12 - 1 - - - DISRC - Discontinuous mode on regular - channels - 11 - 1 - - - ICA - Inserted channel group convert - automatically - 10 - 1 - - - WDSC - When in scan mode, analog watchdog - is effective on a single channel - 9 - 1 - - - SM - Scan mode - 8 - 1 - - - EOICIE - Interrupt enable for EOIC - 7 - 1 - - - WDEIE - Interrupt enable for WDE - 6 - 1 - - - EOCIE - Interrupt enable for EOC - 5 - 1 - - - WDCHSEL - Analog watchdog channel select - 0 - 5 - - - - - CTL1 - CTL1 - control register 1 - 0x08 - 0x20 - read-write - 0x00000000 - - - TSVREN - Channel 16 and 17 enable of ADC - 23 - 1 - - - SWRCST - Start on regular channel - 22 - 1 - - - SWICST - Start on inserted channel - 21 - 1 - - - ETERC - External trigger enable for regular - channel - 20 - 1 - - - ETSRC - External trigger select for regular - channel - 17 - 3 - - - ETEIC - External trigger enable for - inserted channels - 15 - 1 - - - ETSIC - External trigger select for inserted - channel - 12 - 3 - - - DAL - Data alignment - 11 - 1 - - - DMA - DMA request enable - 8 - 1 - - - RSTCLB - Reset calibration - 3 - 1 - - - CLB - ADC calibration - 2 - 1 - - - CTN - Continuous mode - 1 - 1 - - - ADCON - ADC ON - 0 - 1 - - - - - SAMPT0 - SAMPT0 - Sampling time register 0 - 0x0C - 0x20 - read-write - 0x00000000 - - - SPT16 - Channel 16 sample time - selection - 18 - 3 - - - SPT17 - Channel 17 sample time - selection - 21 - 3 - - - - - SAMPT1 - SAMPT1 - Sampling time register 1 - 0x10 - 0x20 - read-write - 0x00000000 - - - SPT0 - Channel 0 sample time - selection - 0 - 3 - - - SPT1 - Channel 1 sample time - selection - 3 - 3 - - - SPT2 - Channel 2 sample time - selection - 6 - 3 - - - SPT3 - Channel 3 sample time - selection - 9 - 3 - - - SPT4 - Channel 4 sample time - selection - 12 - 3 - - - SPT5 - Channel 5 sample time - selection - 15 - 3 - - - SPT6 - Channel 6 sample time - selection - 18 - 3 - - - SPT7 - Channel 7 sample time - selection - 21 - 3 - - - SPT8 - Channel 8 sample time - selection - 24 - 3 - - - SPT9 - Channel 9 sample time - selection - 27 - 3 - - - - - IOFF0 - IOFF0 - Inserted channel data offset register - 0 - 0x14 - 0x20 - read-write - 0x00000000 - - - IOFF - Data offset for injected channel - x - 0 - 12 - - - - - IOFF1 - IOFF1 - Inserted channel data offset register - 1 - 0x18 - 0x20 - read-write - 0x00000000 - - - IOFF - Data offset for injected channel - x - 0 - 12 - - - - - IOFF2 - IOFF2 - Inserted channel data offset register - 2 - 0x1C - 0x20 - read-write - 0x00000000 - - - IOFF - Data offset for injected channel - x - 0 - 12 - - - - - IOFF3 - IOFF3 - Inserted channel data offset register - 3 - 0x20 - 0x20 - read-write - 0x00000000 - - - IOFF - Data offset for injected channel - x - 0 - 12 - - - - - WDHT - WDHT - watchdog higher threshold - register - 0x24 - 0x20 - read-write - 0x00000FFF - - - WDHT - Analog watchdog high - threshold - 0 - 12 - - - - - WDLT - WDLT - watchdog low threshold - register - 0x28 - 0x20 - read-write - 0x00000000 - - - WDLT - Analog watchdog lower - threshold - 0 - 12 - - - - - RSQ0 - RSQ0 - regular sequence register 0 - 0x2C - 0x20 - read-write - 0x00000000 - - - RL - Regular channel sequence - length - 20 - 4 - - - RSQ15 - 15th conversion in regular - sequence - 15 - 5 - - - RSQ14 - 14th conversion in regular - sequence - 10 - 5 - - - RSQ13 - 13th conversion in regular - sequence - 5 - 5 - - - RSQ12 - 12th conversion in regular - sequence - 0 - 5 - - - - - RSQ1 - RSQ1 - regular sequence register 1 - 0x30 - 0x20 - read-write - 0x00000000 - - - RSQ11 - 11th conversion in regular - sequence - 25 - 5 - - - RSQ10 - 10th conversion in regular - sequence - 20 - 5 - - - RSQ9 - 9th conversion in regular - sequence - 15 - 5 - - - RSQ8 - 8th conversion in regular - sequence - 10 - 5 - - - RSQ7 - 7th conversion in regular - sequence - 5 - 5 - - - RSQ6 - 6th conversion in regular - sequence - 0 - 5 - - - - - RSQ2 - RSQ2 - regular sequence register 2 - 0x34 - 0x20 - read-write - 0x00000000 - - - RSQ5 - 5th conversion in regular - sequence - 25 - 5 - - - RSQ4 - 4th conversion in regular - sequence - 20 - 5 - - - RSQ3 - 3rd conversion in regular - sequence - 15 - 5 - - - RSQ2 - 2nd conversion in regular - sequence - 10 - 5 - - - RSQ1 - 1st conversion in regular - sequence - 5 - 5 - - - RSQ0 - conversion in regular - sequence - 0 - 5 - - - - - ISQ - ISQ - injected sequence register - 0x38 - 0x20 - read-write - 0x00000000 - - - IL - Injected sequence length - 20 - 2 - - - ISQ3 - 3rd conversion in injected - sequence - 15 - 5 - - - ISQ2 - 2nd conversion in injected - sequence - 10 - 5 - - - ISQ1 - 1st conversion in injected - sequence - 5 - 5 - - - ISQ0 - conversion in injected - sequence - 0 - 5 - - - - - IDATA0 - IDATA0 - injected data register 0 - 0x3C - 0x20 - read-only - 0x00000000 - - - IDATAn - Injected data - 0 - 16 - - - - - IDATA1 - IDATA1 - injected data register 1 - 0x40 - 0x20 - read-only - 0x00000000 - - - IDATAn - Injected data - 0 - 16 - - - - - IDATA2 - IDATA2 - injected data register 2 - 0x44 - 0x20 - read-only - 0x00000000 - - - IDATAn - Injected data - 0 - 16 - - - - - IDATA3 - IDATA3 - injected data register 3 - 0x48 - 0x20 - read-only - 0x00000000 - - - IDATAn - Injected data - 0 - 16 - - - - - RDATA - RDATA - regular data register - 0x4C - 0x20 - read-only - 0x00000000 - - - RDATA - Regular data - 0 - 16 - - - - - OVSAMPCTL - OVSAMPCTL - ADC oversample control register - 0x80 - 0x20 - read-write - 0x00000000 - - - TOVS - Triggered Oversampling - 9 - 1 - - - OVSS - Oversampling shift - 5 - 4 - - - OVSR - Oversampling ratio - 2 - 3 - - - OVSEN - Oversampler Enable - 0 - 1 - - - - - - - CMP - Comparator - Comparator - 0x4001001C - - 0x0 - 0x80 - registers - - - - CS - CS - control and status register - 0x00 - 0x20 - 0x00000000 - - - CMPEN - Comparator enable - 0 - 1 - read-write - - - CMPSW - Comparator switch - 1 - 1 - read-write - - - CMPM - Comparator mode - 2 - 2 - read-write - - - CMPMSEL - Comparator input selection - 4 - 3 - read-write - - - CMPOSEL - Comparator output selection - 8 - 3 - read-write - - - CMPPL - Polarity of comparator output - 11 - 1 - read-write - - - CMPHST - Comparator hysteresis - 12 - 2 - read-write - - - CMPO - Comparator 0 output - 14 - 1 - read-only - - - CMPLK - Comparator 0 lock - 15 - 1 - read-write - - - - - - - CRC - cyclic redundancy check calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DATA - DATA - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DATA - CRC calculation result bits - 0 - 32 - - - - - FDATA - FDATA - Free data register - 0x04 - 0x20 - read-write - 0x00000000 - - - FDATA - General-purpose 8-bit data register - bits - 0 - 8 - - - - - CTL - CTL - Control register - 0x8 - 0x20 - read-write - 0x00000000 - - - RST - reset bit - 0 - 1 - - - PS - Size of polynomial - 3 - 2 - - - REV_I - Reverse input data - 5 - 2 - - - REV_O - Reverse output data - 7 - 1 - - - - - IDATA - IDATA - Initialization Data Register - 0x10 - 0x20 - read-write - 0xFFFFFFFF - - - IDATA - CRC calculation initial value - 0 - 32 - - - - - POLY - POLY - Polynomial register - 0x14 - 0x20 - read-write - 0x04C11DB7 - - - POLY - User configurable polynomial value - 0 - 32 - - - - - - - DBGMCU - Debug support - DBGMCU - 0x40015800 - - 0x0 - 0x400 - registers - - - - ID - ID - MCU Device ID Code Register - 0x0 - 0x20 - read-only - 0x0 - - - ID_CODE - DBG ID code register - 0 - 32 - - - - - CTL0 - CTL0 - Debug Control Register 0 - 0x4 - 0x20 - read-write - 0x0 - - - SLP_HOLD - Sleep mode hold register - 0 - 1 - - - DSLP_HOLD - DEEPSLEEP mode hold Mode - 1 - 1 - - - STB_HOLD - Standby mode hold Mode - 2 - 1 - - - FWDGT_HOLD - FWDGT hold register - 8 - 1 - - - WWDGT_HOLD - WWDGT hold register - 9 - 1 - - - TIMER0_HOLD - Timer 0 hold register - 10 - 1 - - - TIMER2_HOLD - Timer 2 hold register - 12 - 1 - - - I2C0_HOLD - I2C0 hold register - 15 - 1 - - - I2C1_HOLD - I2C1 hold register - 16 - 1 - - - TIMER5_HOLD - Timer 5 hold register - 19 - 1 - - - TIMER13_HOLD - Timer 13 hold register - 27 - 1 - - - - - CTL1 - CTL1 - Debug Control Register 1 - 0x08 - 0x20 - read-write - 0x00000000 - - - RTC_HOLD - RTC hold register - 10 - 1 - - - TIMER14_HOLD - Timer 14 hold register - 16 - 1 - - - TIMER15_HOLD - Timer 15 hold register - 17 - 1 - - - TIMER16_HOLD - Timer 16 hold register - 18 - 1 - - - - - - - DMA - DMA controller - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA_Channel0 - 9 - - - DMA_Channel1_2 - 10 - - - DMA_Channel3_4 - 11 - - - - INTF - INTF - DMA interrupt flag register - (DMA_INTF) - 0x0 - 0x20 - read-only - 0x00000000 - - - GIF0 - Channel 0 Global interrupt - flag - 0 - 1 - - - FTFIF0 - Channel 0 Full Transfer Finish - flag - 1 - 1 - - - HTFIF0 - Channel 0 Half Transfer Finish - flag - 2 - 1 - - - ERRIF0 - Channel 0 Error flag - 3 - 1 - - - GIF1 - Channel 1 Global interrupt - flag - 4 - 1 - - - FTFIF1 - Channel 1 Full Transfer Finish - flag - 5 - 1 - - - HTFIF1 - Channel 1 Half Transfer Finish - flag - 6 - 1 - - - ERRIF1 - Channel 1 Error flag - 7 - 1 - - - GIF2 - Channel 2 Global interrupt - flag - 8 - 1 - - - FTFIF2 - Channel 2 Full Transfer Finish - flag - 9 - 1 - - - HTFIF2 - Channel 2 Half Transfer Finish - flag - 10 - 1 - - - ERRIF2 - Channel 2 Error - flag - 11 - 1 - - - GIF3 - Channel 3 Global interrupt - flag - 12 - 1 - - - FTFIF3 - Channel 3 Full Transfer Finish - flag - 13 - 1 - - - HTFIF3 - Channel 3 Half Transfer Finish - flag - 14 - 1 - - - ERRIF3 - Channel 3 Error - flag - 15 - 1 - - - GIF4 - Channel 4 Global interrupt - flag - 16 - 1 - - - FTFIF4 - Channel 4 Full Transfer Finish - flag - 17 - 1 - - - HTFIF4 - Channel 4 Half Transfer Finish - flag - 18 - 1 - - - ERRIF4 - Channel 4 Error - flag - 19 - 1 - - - - - INTC - INTC - DMA interrupt flag clear register - (DMA_INTC) - 0x4 - 0x20 - write-only - 0x00000000 - - - GIFC0 - Channel 0 Global interrupt flag - clear - 0 - 1 - - - GIFC1 - Channel 1 Global interrupt flag - clear - 4 - 1 - - - GIFC2 - Channel 2 Global interrupt flag - clear - 8 - 1 - - - GIFC3 - Channel 3 Global interrupt flag - clear - 12 - 1 - - - GIFC4 - Channel 4 Global interrupt flag - clear - 16 - 1 - - - FTFIFC0 - Channel 0 Full Transfer Finish - clear - 1 - 1 - - - FTFIFC1 - Channel 1 Full Transfer Finish - clear - 5 - 1 - - - FTFIFC2 - Channel 2 Full Transfer Finish - clear - 9 - 1 - - - FTFIFC3 - Channel 3 Full Transfer Finish - clear - 13 - 1 - - - FTFIFC4 - Channel 4 Full Transfer Finish - clear - 17 - 1 - - - HTFIFC0 - Channel 0 Half Transfer - clear - 2 - 1 - - - HTFIFC1 - Channel 1 Half Transfer - clear - 6 - 1 - - - HTFIFC2 - Channel 2 Half Transfer - clear - 10 - 1 - - - HTFIFC3 - Channel 3 Half Transfer - clear - 14 - 1 - - - HTFIFC4 - Channel 4 Half Transfer - clear - 18 - 1 - - - ERRIFC0 - Channel 0 Error - clear - 3 - 1 - - - ERRIFC1 - Channel 1 Error - clear - 7 - 1 - - - ERRIFC2 - Channel 2 Error - clear - 11 - 1 - - - ERRIFC3 - Channel 3 Error - clear - 15 - 1 - - - ERRIFC4 - Channel 4 Error - clear - 19 - 1 - - - - - CH0CTL - CH0CTL - DMA channel configuration register - (DMA_CH0CTL) - 0x8 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FTFIE - Full Transfer Finish interrupt - enable - 1 - 1 - - - HTFIE - Half Transfer Finish interrupt - enable - 2 - 1 - - - ERRIE - Transfer access error interrupt - enable - 3 - 1 - - - DIR - Transfer direction - 4 - 1 - - - CMEN - Circular mode enable - 5 - 1 - - - PNAGA - Next address generation algorithm of peripheral - 6 - 1 - - - MNAGA - Next address generation algorithm of memory - 7 - 1 - - - PWIDTH - Transfer data size of peripheral - 8 - 2 - - - MWIDTH - Transfer data size of memory - 10 - 2 - - - PRIO - Priority Level of this channel - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - CH0CNT - CH0CNT - DMA channel 0 counter - register - 0x0C - 0x20 - read-write - 0x00000000 - - - CNT - Transfer counter - 0 - 16 - - - - - CH0PADDR - CH0PADDR - DMA channel 0 peripheral base address - register - 0x10 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral base address - 0 - 32 - - - - - CH0MADDR - CH0MADDR - DMA channel 0 memory base address - register - 0x14 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - CH1CTL - CH1CTL - DMA channel configuration register - (DMA_CH1CTL) - 0x1C - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FTFIE - Full Transfer Finish interrupt - enable - 1 - 1 - - - HTFIE - Half Transfer Finish interrupt - enable - 2 - 1 - - - ERRIE - Error interrupt - enable - 3 - 1 - - - DIR - Transfer direction - 4 - 1 - - - CMEN - Circular mode enable - 5 - 1 - - - PNAGA - Next address generation algorithm of peripheral - 6 - 1 - - - MNAGA - Next address generation algorithm of memory - 7 - 1 - - - PWIDTH - Transfer data size of peripheral - 8 - 2 - - - MWIDTH - Transfer data size of memory - 10 - 2 - - - PRIO - Priority Level of this channel - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - CH1CNT - CH1CNT - DMA channel 1 counter - register - 0x20 - 0x20 - read-write - 0x00000000 - - - CNT - Transfer counter - 0 - 16 - - - - - - CH1PADDR - CH1PADDR - DMA channel 1 peripheral base address - register - 0x24 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral base address - 0 - 32 - - - - - CH1MADDR - CH1MADDR - DMA channel 1 memory base address - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - CH2CTL - CH2CTL - DMA channel configuration register - (DMA_CH2CTL) - 0x30 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FTFIE - Full Transfer Finish interrupt - enable - 1 - 1 - - - HTFIE - Half Transfer Finish interrupt - enable - 2 - 1 - - - ERRIE - Error interrupt - enable - 3 - 1 - - - DIR - Transfer direction - 4 - 1 - - - CMEN - Circular mode enable - 5 - 1 - - - PNAGA - Next address generation algorithm of peripheral - 6 - 1 - - - MNAGA - Next address generation algorithm of memory - 7 - 1 - - - PWIDTH - Transfer data size of peripheral - 8 - 2 - - - MWIDTH - Transfer data size of memory - 10 - 2 - - - PRIO - Priority Level of this channel - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - CH2CNT - CH2CNT - DMA channel 2 counter - register - 0x34 - 0x20 - read-write - 0x00000000 - - - CNT - Transfer counter - 0 - 16 - - - - - - CH2PADDR - CH2PADDR - DMA channel 2 peripheral base address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral base address - 0 - 32 - - - - - CH2MADDR - CH2MADDR - DMA channel 2 memory base address - register - 0x3C - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - CH3CTL - CH3CTL - DMA channel configuration register - (DMA_CH3CTL) - 0x44 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FTFIE - Full Transfer Finish interrupt - enable - 1 - 1 - - - HTFIE - Half Transfer Finish interrupt - enable - 2 - 1 - - - ERRIE - Error interrupt - enable - 3 - 1 - - - DIR - Transfer direction - 4 - 1 - - - CMEN - Circular mode enable - 5 - 1 - - - PNAGA - Next address generation algorithm of peripheral - 6 - 1 - - - MNAGA - Next address generation algorithm of memory - 7 - 1 - - - PWIDTH - Transfer data size of peripheral - 8 - 2 - - - MWIDTH - Transfer data size of memory - 10 - 2 - - - PRIO - Priority Level of this channel - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - CH3CNT - CH3CNT - DMA channel 3 counter - register - 0x48 - 0x20 - read-write - 0x00000000 - - - CNT - Transfer counter - 0 - 16 - - - - - CH3PADDR - CH3PADDR - DMA channel 3 peripheral base address - register - 0x4C - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral base address - 0 - 32 - - - - - CH3MADDR - CH3MADDR - DMA channel 3 memory base address - register - 0x50 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - CH4CTL - CH4CTL - DMA channel configuration register - (DMA_CH4CTL) - 0x58 - 0x20 - read-write - 0x00000000 - - - CHEN - Channel enable - 0 - 1 - - - FTFIE - Full Transfer Finish interrupt - enable - 1 - 1 - - - HTFIE - Half Transfer Finish interrupt - enable - 2 - 1 - - - ERRIE - Error interrupt - enable - 3 - 1 - - - DIR - Transfer direction - 4 - 1 - - - CMEN - Circular mode enable - 5 - 1 - - - PNAGA - Next address generation algorithm of peripheral - 6 - 1 - - - MNAGA - Next address generation algorithm of memory - 7 - 1 - - - PWIDTH - Transfer data size of peripheral - 8 - 2 - - - MWIDTH - Transfer data size of memory - 10 - 2 - - - PRIO - Priority Level of this channel - 12 - 2 - - - M2M - Memory to memory mode - 14 - 1 - - - - - CH4CNT - CH4CNT - DMA channel 4 counter - register - 0x5C - 0x20 - read-write - 0x00000000 - - - CNT - Transfer counter - 0 - 16 - - - - - CH4PADDR - CH4PADDR - DMA channel 4 peripheral base address - register - 0x60 - 0x20 - read-write - 0x00000000 - - - PADDR - Peripheral base address - 0 - 32 - - - - - CH4MADDR - CH4MADDR - DMA channel 4 memory base address - register - 0x64 - 0x20 - read-write - 0x00000000 - - - MADDR - Memory address - 0 - 32 - - - - - - - EXTI - External interrupt/event - controller - EXTI - 0x40010400 - - 0x0 - 0x400 - registers - - - LVD - 1 - - - EXTI0_1 - 5 - - - EXTI2_3 - 6 - - - EXTI4_15 - 7 - - - - INTEN - INTEN - Interrupt enable register - (EXTI_INTEN) - 0x0 - 0x20 - read-write - 0x0F940000 - - - INTEN0 - Enable Interrupt on line 0 - 0 - 1 - - - INTEN1 - Enable Interrupt on line 1 - 1 - 1 - - - INTEN2 - Enable Interrupt on line 2 - 2 - 1 - - - INTEN3 - Enable Interrupt on line 3 - 3 - 1 - - - INTEN4 - Enable Interrupt on line 4 - 4 - 1 - - - INTEN5 - Enable Interrupt on line 5 - 5 - 1 - - - INTEN6 - Enable Interrupt on line 6 - 6 - 1 - - - INTEN7 - Enable Interrupt on line 7 - 7 - 1 - - - INTEN8 - Enable Interrupt on line 8 - 8 - 1 - - - INTEN9 - Enable Interrupt on line 9 - 9 - 1 - - - INTEN10 - Enable Interrupt on line 10 - 10 - 1 - - - INTEN11 - Enable Interrupt on line 11 - 11 - 1 - - - INTEN12 - Enable Interrupt on line 12 - 12 - 1 - - - INTEN13 - Enable Interrupt on line 13 - 13 - 1 - - - INTEN14 - Enable Interrupt on line 14 - 14 - 1 - - - INTEN15 - Enable Interrupt on line 15 - 15 - 1 - - - INTEN16 - Enable Interrupt on line 16 - 16 - 1 - - - INTEN17 - Enable Interrupt on line 17 - 17 - 1 - - - INTEN18 - Enable Interrupt on line 18 - 18 - 1 - - - INTEN19 - Enable Interrupt on line 19 - 19 - 1 - - - INTEN20 - Enable Interrupt on line 20 - 20 - 1 - - - INTEN21 - Enable Interrupt on line 21 - 21 - 1 - - - INTEN22 - Enable Interrupt on line 22 - 22 - 1 - - - INTEN23 - Enable Interrupt on line 23 - 23 - 1 - - - INTEN24 - Enable Interrupt on line 24 - 24 - 1 - - - INTEN25 - Enable Interrupt on line 25 - 25 - 1 - - - INTEN26 - Enable Interrupt on line 26 - 26 - 1 - - - INTEN27 - Enable Interrupt on line 27 - 27 - 1 - - - - - EVEN - EVEN - Event enable register (EXTI_EVEN) - 0x04 - 0x20 - read-write - 0x00000000 - - - EVEN0 - Enable Event on line 0 - 0 - 1 - - - EVEN1 - Enable Event on line 1 - 1 - 1 - - - EVEN2 - Enable Event on line 2 - 2 - 1 - - - EVEN3 - Enable Event on line 3 - 3 - 1 - - - EVEN4 - Enable Event on line 4 - 4 - 1 - - - EVEN5 - Enable Event on line 5 - 5 - 1 - - - EVEN6 - Enable Event on line 6 - 6 - 1 - - - EVEN7 - Enable Event on line 7 - 7 - 1 - - - EVEN8 - Enable Event on line 8 - 8 - 1 - - - EVEN9 - Enable Event on line 9 - 9 - 1 - - - EVEN10 - Enable Event on line 10 - 10 - 1 - - - EVEN11 - Enable Event on line 11 - 11 - 1 - - - EVEN12 - Enable Event on line 12 - 12 - 1 - - - EVEN13 - Enable Event on line 13 - 13 - 1 - - - EVEN14 - Enable Event on line 14 - 14 - 1 - - - EVEN15 - Enable Event on line 15 - 15 - 1 - - - EVEN16 - Enable Event on line 16 - 16 - 1 - - - EVEN17 - Enable Event on line 17 - 17 - 1 - - - EVEN18 - Enable Event on line 18 - 18 - 1 - - - EVEN19 - Enable Event on line 19 - 19 - 1 - - - EVEN20 - Enable Event on line 20 - 20 - 1 - - - EVEN21 - Enable Event on line 21 - 21 - 1 - - - EVEN22 - Enable Event on line 22 - 22 - 1 - - - EVEN23 - Enable Event on line 23 - 23 - 1 - - - EVEN24 - Enable Event on line 24 - 24 - 1 - - - EVEN25 - Enable Event on line 25 - 25 - 1 - - - EVEN26 - Enable Event on line 26 - 26 - 1 - - - EVEN27 - Enable Event on line 27 - 27 - 1 - - - - - RTEN - RTEN - Rising Edge Trigger Enable register - (EXTI_RTEN) - 0x08 - 0x20 - read-write - 0x00000000 - - - RTEN0 - Rising trigger event configuration of - line 0 - 0 - 1 - - - RTEN1 - Rising trigger event configuration of - line 1 - 1 - 1 - - - RTEN2 - Rising trigger event configuration of - line 2 - 2 - 1 - - - RTEN3 - Rising trigger event configuration of - line 3 - 3 - 1 - - - RTEN4 - Rising trigger event configuration of - line 4 - 4 - 1 - - - RTEN5 - Rising trigger event configuration of - line 5 - 5 - 1 - - - RTEN6 - Rising trigger event configuration of - line 6 - 6 - 1 - - - RTEN7 - Rising trigger event configuration of - line 7 - 7 - 1 - - - RTEN8 - Rising trigger event configuration of - line 8 - 8 - 1 - - - RTEN9 - Rising trigger event configuration of - line 9 - 9 - 1 - - - RTEN10 - Rising trigger event configuration of - line 10 - 10 - 1 - - - RTEN11 - Rising trigger event configuration of - line 11 - 11 - 1 - - - RTEN12 - Rising trigger event configuration of - line 12 - 12 - 1 - - - RTEN13 - Rising trigger event configuration of - line 13 - 13 - 1 - - - RTEN14 - Rising trigger event configuration of - line 14 - 14 - 1 - - - RTEN15 - Rising trigger event configuration of - line 15 - 15 - 1 - - - RTEN16 - Rising trigger event configuration of - line 16 - 16 - 1 - - - RTEN17 - Rising trigger event configuration of - line 17 - 17 - 1 - - - RTEN19 - Rising trigger event configuration of - line 19 - 19 - 1 - - - RTEN21 - Rising trigger event configuration of - line 21 - 21 - 1 - - - - - FTEN - FTEN - Falling Egde Trigger Enable register - (EXTI_FTEN) - 0x0C - 0x20 - read-write - 0x00000000 - - - FTEN0 - Falling trigger event configuration of - line 0 - 0 - 1 - - - FTEN1 - Falling trigger event configuration of - line 1 - 1 - 1 - - - FTEN2 - Falling trigger event configuration of - line 2 - 2 - 1 - - - FTEN3 - Falling trigger event configuration of - line 3 - 3 - 1 - - - FTEN4 - Falling trigger event configuration of - line 4 - 4 - 1 - - - FTEN5 - Falling trigger event configuration of - line 5 - 5 - 1 - - - FTEN6 - Falling trigger event configuration of - line 6 - 6 - 1 - - - FTEN7 - Falling trigger event configuration of - line 7 - 7 - 1 - - - FTEN8 - Falling trigger event configuration of - line 8 - 8 - 1 - - - FTEN9 - Falling trigger event configuration of - line 9 - 9 - 1 - - - FTEN10 - Falling trigger event configuration of - line 10 - 10 - 1 - - - FTEN11 - Falling trigger event configuration of - line 11 - 11 - 1 - - - FTEN12 - Falling trigger event configuration of - line 12 - 12 - 1 - - - FTEN13 - Falling trigger event configuration of - line 13 - 13 - 1 - - - FTEN14 - Falling trigger event configuration of - line 14 - 14 - 1 - - - FTEN15 - Falling trigger event configuration of - line 15 - 15 - 1 - - - FTEN16 - Falling trigger event configuration of - line 16 - 16 - 1 - - - FTEN17 - Falling trigger event configuration of - line 17 - 17 - 1 - - - FTEN19 - Falling trigger event configuration of - line 19 - 19 - 1 - - - FTEN21 - Falling trigger event configuration of - line 21 - 21 - 1 - - - - - SWIEV - SWIEV - Software interrupt event register - (EXTI_SWIEV) - 0x10 - 0x20 - read-write - 0x00000000 - - - SWIEV0 - Software Interrupt on line - 0 - 0 - 1 - - - SWIEV1 - Software Interrupt on line - 1 - 1 - 1 - - - SWIEV2 - Software Interrupt on line - 2 - 2 - 1 - - - SWIEV3 - Software Interrupt on line - 3 - 3 - 1 - - - SWIEV4 - Software Interrupt on line - 4 - 4 - 1 - - - SWIEV5 - Software Interrupt on line - 5 - 5 - 1 - - - SWIEV6 - Software Interrupt on line - 6 - 6 - 1 - - - SWIEV7 - Software Interrupt on line - 7 - 7 - 1 - - - SWIEV8 - Software Interrupt on line - 8 - 8 - 1 - - - SWIEV9 - Software Interrupt on line - 9 - 9 - 1 - - - SWIEV10 - Software Interrupt on line - 10 - 10 - 1 - - - SWIEV11 - Software Interrupt on line - 11 - 11 - 1 - - - SWIEV12 - Software Interrupt on line - 12 - 12 - 1 - - - SWIEV13 - Software Interrupt on line - 13 - 13 - 1 - - - SWIEV14 - Software Interrupt on line - 14 - 14 - 1 - - - SWIEV15 - Software Interrupt on line - 15 - 15 - 1 - - - SWIEV16 - Software Interrupt on line - 16 - 16 - 1 - - - SWIEV17 - Software Interrupt on line - 17 - 17 - 1 - - - SWIEV19 - Software Interrupt on line - 19 - 19 - 1 - - - SWIEV21 - Software Interrupt on line - 21 - 21 - 1 - - - - - PD - PD - Pending register (EXTI_PD) - 0x14 - 0x20 - read-write - 0x00000000 - - - PD0 - Pending bit 0 - 0 - 1 - - - PD1 - Pending bit 1 - 1 - 1 - - - PD2 - Pending bit 2 - 2 - 1 - - - PD3 - Pending bit 3 - 3 - 1 - - - PD4 - Pending bit 4 - 4 - 1 - - - PD5 - Pending bit 5 - 5 - 1 - - - PD6 - Pending bit 6 - 6 - 1 - - - PD7 - Pending bit 7 - 7 - 1 - - - PD8 - Pending bit 8 - 8 - 1 - - - PD9 - Pending bit 9 - 9 - 1 - - - PD10 - Pending bit 10 - 10 - 1 - - - PD11 - Pending bit 11 - 11 - 1 - - - PD12 - Pending bit 12 - 12 - 1 - - - PD13 - Pending bit 13 - 13 - 1 - - - PD14 - Pending bit 14 - 14 - 1 - - - PD15 - Pending bit 15 - 15 - 1 - - - PD16 - Pending bit 16 - 16 - 1 - - - PD17 - Pending bit 17 - 17 - 1 - - - PD19 - Pending bit 19 - 19 - 1 - - - PD21 - Pending bit 21 - 21 - 1 - - - - - - - FMC - FMC - FMC - 0x40022000 - - 0x0 - 0x400 - registers - - - FMC - 3 - - - - WS - WS - wait state register - 0x0 - 0x20 - read-write - 0x00000000 - - - WSCNT - wait state counter register - 0 - 3 - - - PFEN - Pre-fetch enable - 4 - 1 - - - PGW - Program width to flash memory - 15 - 1 - - - - - KEY - KEY - Unlock key register - 0x04 - 0x20 - write-only - 0x00000000 - - - KEY - FMC_CTL unlock register - 0 - 32 - - - - - OBKEY - OBKEY - Option byte unlock key register - 0x08 - 0x20 - write-only - 0x00000000 - - - OBKEY - FMC_ CTL option bytes operation unlock register - 0 - 32 - - - - - STAT - STAT - Status register - 0x0C - 0x20 - 0x00000000 - - - ENDF - End of operation flag bit - 5 - 1 - read-write - - - WPERR - Erase/Program protection error flag bit - 4 - 1 - read-write - - - PGAERR - Program alignment error flag bit - 3 - 1 - read-write - - - PGERR - Program error flag bit - 2 - 1 - read-write - - - BUSY - The flash is busy bit - 0 - 1 - read-only - - - - - CTL - CTL - Control register - 0x10 - 0x20 - read-write - 0x00000080 - - - OBRLD - Option byte reload bit - 13 - 1 - - - ENDIE - End of operation interrupt enable bit - 12 - 1 - - - ERRIE - Error interrupt enable bit - 10 - 1 - - - OBWEN - Option byte erase/program enable bit - 9 - 1 - - - LK - FMC_CTL lock bit - 7 - 1 - - - START - Send erase command to FMC bit - 6 - 1 - - - OBER - Option bytes erase command bit - 5 - 1 - - - OBPG - Option bytes program command bit - 4 - 1 - - - MER - Main flash mass erase for bank0 command bit - 2 - 1 - - - PER - Main flash page erase for bank0 command bit - 1 - 1 - - - PG - Main flash program for bank0 command bit - 0 - 1 - - - - - ADDR - ADDR - Address register - 0x14 - 0x20 - read-write - 0x00000000 - - - ADDR - Flash erase/program command address bits - 0 - 32 - - - - - OBSTAT - OBSTAT - Option byte control register - 0x1C - 0x20 - read-only - 0x00000000 - - - OBERR - Option bytes read error bit - 0 - 1 - - - PLEVEL - Option bytes security protection level - 1 - 2 - - - USER - Store USER of option bytes block after system reset - 8 - 8 - - - DATA - Store DATA[15:0] of option bytes block after system reset - 16 - 16 - - - - - WP - WP - Erase/Program Protection register - 0x20 - 0x20 - read-only - 0x00000000 - - - WP - Store WP[15:0] of option bytes block after system reset - 0 - 16 - - - - - PID - PID - Product ID register - 0x100 - 0x20 - read-only - 0x00000000 - - - PID - Product reserved ID code register - 0 - 32 - - - - - - - FWDGT - free watchdog timer - FWDGT - 0x40003000 - - 0x0 - 0x400 - registers - - - - CTL - CTL - Control register - 0x00 - 0x20 - write-only - 0x00000000 - - - CMD - Key value - 0 - 16 - - - - - PSC - PSC - Prescaler register - 0x04 - 0x20 - read-write - 0x00000000 - - - PSC - Prescaler divider - 0 - 3 - - - - - RLD - RLD - Reload register - 0x08 - 0x20 - read-write - 0x00000FFF - - - RLD - Watchdog counter reload - value - 0 - 12 - - - - - STAT - STAT - Status register - 0x0C - 0x20 - read-only - 0x00000000 - - - PUD - Watchdog prescaler value - update - 0 - 1 - - - RUD - Watchdog counter reload value - update - 1 - 1 - - - WUD - Watchdog counter window value - update - 2 - 1 - - - - - WND - WND - Window register - 0x10 - 0x20 - read-write - 0x00000FFF - - - WND - Watchdog counter window - value - 0 - 12 - - - - - - - GPIOA - General-purpose I/Os - GPIO - 0x48000000 - - 0x0 - 0x400 - registers - - - - CTL - CTL - GPIO port control register - 0x0 - 0x20 - read-write - 0x28000000 - - - CTL15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - CTL14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - CTL13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - CTL12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - CTL11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - CTL10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - CTL9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - CTL8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - CTL7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - CTL6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - CTL5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - CTL4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - CTL3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - CTL2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - CTL1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - CTL0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OMODE - OMODE - GPIO port output type register - 0x04 - 0x20 - read-write - 0x00000000 - - - OM15 - Port x configuration bit - 15 - 15 - 1 - - - OM14 - Port x configuration bit - 14 - 14 - 1 - - - OM13 - Port x configuration bit - 13 - 13 - 1 - - - OM12 - Port x configuration bit - 12 - 12 - 1 - - - OM11 - Port x configuration bit - 11 - 11 - 1 - - - OM10 - Port x configuration bit - 10 - 10 - 1 - - - OM9 - Port x configuration bit 9 - 9 - 1 - - - OM8 - Port x configuration bit 8 - 8 - 1 - - - OM7 - Port x configuration bit 7 - 7 - 1 - - - OM6 - Port x configuration bit 6 - 6 - 1 - - - OM5 - Port x configuration bit 5 - 5 - 1 - - - OM4 - Port x configuration bit 4 - 4 - 1 - - - OM3 - Port x configuration bit 3 - 3 - 1 - - - OM2 - Port x configuration bit 2 - 2 - 1 - - - OM1 - Port x configuration bit 1 - 1 - 1 - - - OM0 - Port x configuration bit 0 - 0 - 1 - - - - - OSPD - OSPD - GPIO port output speed - register - 0x08 - 0x20 - read-write - 0x0C000000 - - - OSPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUD - PUD - GPIO port pull-up/pull-down - register - 0x0C - 0x20 - read-write - 0x24000000 - - - PUD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - ISTAT - ISTAT - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ISTAT15 - Port input data (y = - 0..15) - 15 - 1 - - - ISTAT14 - Port input data (y = - 0..15) - 14 - 1 - - - ISTAT13 - Port input data (y = - 0..15) - 13 - 1 - - - ISTAT12 - Port input data (y = - 0..15) - 12 - 1 - - - ISTAT11 - Port input data (y = - 0..15) - 11 - 1 - - - ISTAT10 - Port input data (y = - 0..15) - 10 - 1 - - - ISTAT9 - Port input data (y = - 0..15) - 9 - 1 - - - ISTAT8 - Port input data (y = - 0..15) - 8 - 1 - - - ISTAT7 - Port input data (y = - 0..15) - 7 - 1 - - - ISTAT6 - Port input data (y = - 0..15) - 6 - 1 - - - ISTAT5 - Port input data (y = - 0..15) - 5 - 1 - - - ISTAT4 - Port input data (y = - 0..15) - 4 - 1 - - - ISTAT3 - Port input data (y = - 0..15) - 3 - 1 - - - ISTAT2 - Port input data (y = - 0..15) - 2 - 1 - - - ISTAT1 - Port input data (y = - 0..15) - 1 - 1 - - - ISTAT0 - Port input data (y = - 0..15) - 0 - 1 - - - - - OCTL - OCTL - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OCTL15 - Port output data (y = - 0..15) - 15 - 1 - - - OCTL14 - Port output data (y = - 0..15) - 14 - 1 - - - OCTL13 - Port output data (y = - 0..15) - 13 - 1 - - - OCTL12 - Port output data (y = - 0..15) - 12 - 1 - - - OCTL11 - Port output data (y = - 0..15) - 11 - 1 - - - OCTL10 - Port output data (y = - 0..15) - 10 - 1 - - - OCTL9 - Port output data (y = - 0..15) - 9 - 1 - - - OCTL8 - Port output data (y = - 0..15) - 8 - 1 - - - OCTL7 - Port output data (y = - 0..15) - 7 - 1 - - - OCTL6 - Port output data (y = - 0..15) - 6 - 1 - - - OCTL5 - Port output data (y = - 0..15) - 5 - 1 - - - OCTL4 - Port output data (y = - 0..15) - 4 - 1 - - - OCTL3 - Port output data (y = - 0..15) - 3 - 1 - - - OCTL2 - Port output data (y = - 0..15) - 2 - 1 - - - OCTL1 - Port output data (y = - 0..15) - 1 - 1 - - - OCTL0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BOP - BOP - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - CR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - CR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - CR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - CR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - CR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - CR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - CR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - CR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - CR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - CR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - CR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - CR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - CR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - CR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - CR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - CR0 - Port x reset bit y (y= - 0..15) - 16 - 1 - - - BOP15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BOP14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BOP13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BOP12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BOP11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BOP10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BOP9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BOP8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BOP7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BOP6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BOP5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BOP4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BOP3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BOP2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BOP1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BOP0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LOCK - LOCK - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LKK - Port x lock bit y - - 16 - 1 - - - LK15 - Port x lock bit y (y= - 0..15) - 15 - 1 - - - LK14 - Port x lock bit y (y= - 0..15) - 14 - 1 - - - LK13 - Port x lock bit y (y= - 0..15) - 13 - 1 - - - LK12 - Port x lock bit y (y= - 0..15) - 12 - 1 - - - LK11 - Port x lock bit y (y= - 0..15) - 11 - 1 - - - LK10 - Port x lock bit y (y= - 0..15) - 10 - 1 - - - LK9 - Port x lock bit y (y= - 0..15) - 9 - 1 - - - LK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFSEL0 - AFSEL0 - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - SEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - SEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - SEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - SEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - SEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - SEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - SEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - SEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFSEL1 - AFSEL1 - GPIO alternate function - register 1 - 0x24 - 0x20 - read-write - 0x00000000 - - - SEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - SEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - SEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - SEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - SEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - SEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - SEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - SEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BC - BC - Port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - CR0 - Port cleat bit - 0 - 1 - - - CR1 - Port cleat bit - 1 - 1 - - - CR2 - Port cleat bit - 2 - 1 - - - CR3 - Port cleat bit - 3 - 1 - - - CR4 - Port cleat bit - 4 - 1 - - - CR5 - Port cleat bit - 5 - 1 - - - CR6 - Port cleat bit - 6 - 1 - - - CR7 - Port cleat bit - 7 - 1 - - - CR8 - Port cleat bit - 8 - 1 - - - CR9 - Port cleat bit - 9 - 1 - - - CR10 - Port cleat bit - 10 - 1 - - - CR11 - Port cleat bit - 11 - 1 - - - CR12 - Port cleat bit - 12 - 1 - - - CR13 - Port cleat bit - 13 - 1 - - - CR14 - Port cleat bit - 14 - 1 - - - CR15 - Port cleat bit - 15 - 1 - - - - - TG - TG - Port bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - TG0 - Port toggle bit - 0 - 1 - - - TG1 - Port toggle bit - 1 - 1 - - - TG2 - Port toggle bit - 2 - 1 - - - TG3 - Port toggle bit - 3 - 1 - - - TG4 - Port toggle bit - 4 - 1 - - - TG5 - Port toggle bit - 5 - 1 - - - TG6 - Port toggle bit - 6 - 1 - - - TG7 - Port toggle bit - 7 - 1 - - - TG8 - Port toggle bit - 8 - 1 - - - TG9 - Port toggle bit - 9 - 1 - - - TG10 - Port toggle bit - 10 - 1 - - - TG11 - Port toggle bit - 11 - 1 - - - TG12 - Port toggle bit - 12 - 1 - - - TG13 - Port toggle bit - 13 - 1 - - - TG14 - Port toggle bit - 14 - 1 - - - TG15 - Port toggle bit - 15 - 1 - - - - - - - GPIOB - General-purpose I/Os - GPIO - 0x48000400 - - 0x0 - 0x400 - registers - - - - CTL - CTL - GPIO port control register - 0x0 - 0x20 - read-write - 0x00000000 - - - CTL15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - CTL14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - CTL13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - CTL12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - CTL11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - CTL10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - CTL9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - CTL8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - CTL7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - CTL6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - CTL5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - CTL4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - CTL3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - CTL2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - CTL1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - CTL0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OMODE - OMODE - GPIO port output type register - 0x04 - 0x20 - read-write - 0x00000000 - - - OM15 - Port x configuration bit - 15 - 15 - 1 - - - OM14 - Port x configuration bit - 14 - 14 - 1 - - - OM13 - Port x configuration bit - 13 - 13 - 1 - - - OM12 - Port x configuration bit - 12 - 12 - 1 - - - OM11 - Port x configuration bit - 11 - 11 - 1 - - - OM10 - Port x configuration bit - 10 - 10 - 1 - - - OM9 - Port x configuration bit 9 - 9 - 1 - - - OM8 - Port x configuration bit 8 - 8 - 1 - - - OM7 - Port x configuration bit 7 - 7 - 1 - - - OM6 - Port x configuration bit 6 - 6 - 1 - - - OM5 - Port x configuration bit 5 - 5 - 1 - - - OM4 - Port x configuration bit 4 - 4 - 1 - - - OM3 - Port x configuration bit 3 - 3 - 1 - - - OM2 - Port x configuration bit 2 - 2 - 1 - - - OM1 - Port x configuration bit 1 - 1 - 1 - - - OM0 - Port x configuration bit 0 - 0 - 1 - - - - - OSPD - OSPD - GPIO port output speed - register - 0x08 - 0x20 - read-write - 0x00000000 - - - OSPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUD - PUD - GPIO port pull-up/pull-down - register - 0x0C - 0x20 - read-write - 0x00000000 - - - PUD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - ISTAT - ISTAT - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ISTAT15 - Port input data (y = - 0..15) - 15 - 1 - - - ISTAT14 - Port input data (y = - 0..15) - 14 - 1 - - - ISTAT13 - Port input data (y = - 0..15) - 13 - 1 - - - ISTAT12 - Port input data (y = - 0..15) - 12 - 1 - - - ISTAT11 - Port input data (y = - 0..15) - 11 - 1 - - - ISTAT10 - Port input data (y = - 0..15) - 10 - 1 - - - ISTAT9 - Port input data (y = - 0..15) - 9 - 1 - - - ISTAT8 - Port input data (y = - 0..15) - 8 - 1 - - - ISTAT7 - Port input data (y = - 0..15) - 7 - 1 - - - ISTAT6 - Port input data (y = - 0..15) - 6 - 1 - - - ISTAT5 - Port input data (y = - 0..15) - 5 - 1 - - - ISTAT4 - Port input data (y = - 0..15) - 4 - 1 - - - ISTAT3 - Port input data (y = - 0..15) - 3 - 1 - - - ISTAT2 - Port input data (y = - 0..15) - 2 - 1 - - - ISTAT1 - Port input data (y = - 0..15) - 1 - 1 - - - ISTAT0 - Port input data (y = - 0..15) - 0 - 1 - - - - - OCTL - OCTL - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OCTL15 - Port output data (y = - 0..15) - 15 - 1 - - - OCTL14 - Port output data (y = - 0..15) - 14 - 1 - - - OCTL13 - Port output data (y = - 0..15) - 13 - 1 - - - OCTL12 - Port output data (y = - 0..15) - 12 - 1 - - - OCTL11 - Port output data (y = - 0..15) - 11 - 1 - - - OCTL10 - Port output data (y = - 0..15) - 10 - 1 - - - OCTL9 - Port output data (y = - 0..15) - 9 - 1 - - - OCTL8 - Port output data (y = - 0..15) - 8 - 1 - - - OCTL7 - Port output data (y = - 0..15) - 7 - 1 - - - OCTL6 - Port output data (y = - 0..15) - 6 - 1 - - - OCTL5 - Port output data (y = - 0..15) - 5 - 1 - - - OCTL4 - Port output data (y = - 0..15) - 4 - 1 - - - OCTL3 - Port output data (y = - 0..15) - 3 - 1 - - - OCTL2 - Port output data (y = - 0..15) - 2 - 1 - - - OCTL1 - Port output data (y = - 0..15) - 1 - 1 - - - OCTL0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BOP - BOP - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - CR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - CR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - CR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - CR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - CR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - CR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - CR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - CR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - CR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - CR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - CR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - CR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - CR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - CR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - CR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - CR0 - Port x reset bit y (y= - 0..15) - 16 - 1 - - - BOP15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BOP14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BOP13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BOP12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BOP11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BOP10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BOP9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BOP8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BOP7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BOP6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BOP5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BOP4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BOP3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BOP2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BOP1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BOP0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LOCK - LOCK - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LKK - Port x lock bit y - - 16 - 1 - - - LK15 - Port x lock bit y (y= - 0..15) - 15 - 1 - - - LK14 - Port x lock bit y (y= - 0..15) - 14 - 1 - - - LK13 - Port x lock bit y (y= - 0..15) - 13 - 1 - - - LK12 - Port x lock bit y (y= - 0..15) - 12 - 1 - - - LK11 - Port x lock bit y (y= - 0..15) - 11 - 1 - - - LK10 - Port x lock bit y (y= - 0..15) - 10 - 1 - - - LK9 - Port x lock bit y (y= - 0..15) - 9 - 1 - - - LK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFSEL0 - AFSEL0 - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - SEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - SEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - SEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - SEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - SEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - SEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - SEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - SEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFSEL1 - AFSEL1 - GPIO alternate function - register 1 - 0x24 - 0x20 - read-write - 0x00000000 - - - SEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - SEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - SEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - SEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - SEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - SEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - SEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - SEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BC - BC - Port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - CR0 - Port cleat bit - 0 - 1 - - - CR1 - Port cleat bit - 1 - 1 - - - CR2 - Port cleat bit - 2 - 1 - - - CR3 - Port cleat bit - 3 - 1 - - - CR4 - Port cleat bit - 4 - 1 - - - CR5 - Port cleat bit - 5 - 1 - - - CR6 - Port cleat bit - 6 - 1 - - - CR7 - Port cleat bit - 7 - 1 - - - CR8 - Port cleat bit - 8 - 1 - - - CR9 - Port cleat bit - 9 - 1 - - - CR10 - Port cleat bit - 10 - 1 - - - CR11 - Port cleat bit - 11 - 1 - - - CR12 - Port cleat bit - 12 - 1 - - - CR13 - Port cleat bit - 13 - 1 - - - CR14 - Port cleat bit - 14 - 1 - - - CR15 - Port cleat bit - 15 - 1 - - - - - TG - TG - Port bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - TG0 - Port toggle bit - 0 - 1 - - - TG1 - Port toggle bit - 1 - 1 - - - TG2 - Port toggle bit - 2 - 1 - - - TG3 - Port toggle bit - 3 - 1 - - - TG4 - Port toggle bit - 4 - 1 - - - TG5 - Port toggle bit - 5 - 1 - - - TG6 - Port toggle bit - 6 - 1 - - - TG7 - Port toggle bit - 7 - 1 - - - TG8 - Port toggle bit - 8 - 1 - - - TG9 - Port toggle bit - 9 - 1 - - - TG10 - Port toggle bit - 10 - 1 - - - TG11 - Port toggle bit - 11 - 1 - - - TG12 - Port toggle bit - 12 - 1 - - - TG13 - Port toggle bit - 13 - 1 - - - TG14 - Port toggle bit - 14 - 1 - - - TG15 - Port toggle bit - 15 - 1 - - - - - - - GPIOC - General-purpose I/Os - GPIO - 0x48000800 - - 0x0 - 0x400 - registers - - - - CTL - CTL - GPIO port control register - 0x0 - 0x20 - read-write - 0x00000000 - - - CTL15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - CTL14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - CTL13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - CTL12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - CTL11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - CTL10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - CTL9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - CTL8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - CTL7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - CTL6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - CTL5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - CTL4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - CTL3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - CTL2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - CTL1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - CTL0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OMODE - OMODE - GPIO port output type register - 0x04 - 0x20 - read-write - 0x00000000 - - - OM15 - Port x configuration bit - 15 - 15 - 1 - - - OM14 - Port x configuration bit - 14 - 14 - 1 - - - OM13 - Port x configuration bit - 13 - 13 - 1 - - - OM12 - Port x configuration bit - 12 - 12 - 1 - - - OM11 - Port x configuration bit - 11 - 11 - 1 - - - OM10 - Port x configuration bit - 10 - 10 - 1 - - - OM9 - Port x configuration bit 9 - 9 - 1 - - - OM8 - Port x configuration bit 8 - 8 - 1 - - - OM7 - Port x configuration bit 7 - 7 - 1 - - - OM6 - Port x configuration bit 6 - 6 - 1 - - - OM5 - Port x configuration bit 5 - 5 - 1 - - - OM4 - Port x configuration bit 4 - 4 - 1 - - - OM3 - Port x configuration bit 3 - 3 - 1 - - - OM2 - Port x configuration bit 2 - 2 - 1 - - - OM1 - Port x configuration bit 1 - 1 - 1 - - - OM0 - Port x configuration bit 0 - 0 - 1 - - - - - OSPD - OSPD - GPIO port output speed - register - 0x08 - 0x20 - read-write - 0x00000000 - - - OSPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUD - PUD - GPIO port pull-up/pull-down - register - 0x0C - 0x20 - read-write - 0x00000000 - - - PUD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - ISTAT - ISTAT - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ISTAT15 - Port input data (y = - 0..15) - 15 - 1 - - - ISTAT14 - Port input data (y = - 0..15) - 14 - 1 - - - ISTAT13 - Port input data (y = - 0..15) - 13 - 1 - - - ISTAT12 - Port input data (y = - 0..15) - 12 - 1 - - - ISTAT11 - Port input data (y = - 0..15) - 11 - 1 - - - ISTAT10 - Port input data (y = - 0..15) - 10 - 1 - - - ISTAT9 - Port input data (y = - 0..15) - 9 - 1 - - - ISTAT8 - Port input data (y = - 0..15) - 8 - 1 - - - ISTAT7 - Port input data (y = - 0..15) - 7 - 1 - - - ISTAT6 - Port input data (y = - 0..15) - 6 - 1 - - - ISTAT5 - Port input data (y = - 0..15) - 5 - 1 - - - ISTAT4 - Port input data (y = - 0..15) - 4 - 1 - - - ISTAT3 - Port input data (y = - 0..15) - 3 - 1 - - - ISTAT2 - Port input data (y = - 0..15) - 2 - 1 - - - ISTAT1 - Port input data (y = - 0..15) - 1 - 1 - - - ISTAT0 - Port input data (y = - 0..15) - 0 - 1 - - - - - OCTL - OCTL - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OCTL15 - Port output data (y = - 0..15) - 15 - 1 - - - OCTL14 - Port output data (y = - 0..15) - 14 - 1 - - - OCTL13 - Port output data (y = - 0..15) - 13 - 1 - - - OCTL12 - Port output data (y = - 0..15) - 12 - 1 - - - OCTL11 - Port output data (y = - 0..15) - 11 - 1 - - - OCTL10 - Port output data (y = - 0..15) - 10 - 1 - - - OCTL9 - Port output data (y = - 0..15) - 9 - 1 - - - OCTL8 - Port output data (y = - 0..15) - 8 - 1 - - - OCTL7 - Port output data (y = - 0..15) - 7 - 1 - - - OCTL6 - Port output data (y = - 0..15) - 6 - 1 - - - OCTL5 - Port output data (y = - 0..15) - 5 - 1 - - - OCTL4 - Port output data (y = - 0..15) - 4 - 1 - - - OCTL3 - Port output data (y = - 0..15) - 3 - 1 - - - OCTL2 - Port output data (y = - 0..15) - 2 - 1 - - - OCTL1 - Port output data (y = - 0..15) - 1 - 1 - - - OCTL0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BOP - BOP - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - CR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - CR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - CR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - CR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - CR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - CR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - CR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - CR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - CR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - CR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - CR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - CR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - CR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - CR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - CR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - CR0 - Port x reset bit y (y= - 0..15) - 16 - 1 - - - BOP15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BOP14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BOP13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BOP12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BOP11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BOP10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BOP9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BOP8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BOP7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BOP6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BOP5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BOP4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BOP3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BOP2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BOP1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BOP0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - AFSEL0 - AFSEL0 - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - SEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - SEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - SEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - SEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - SEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - SEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - SEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - SEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFSEL1 - AFSEL1 - GPIO alternate function - register 1 - 0x24 - 0x20 - read-write - 0x00000000 - - - SEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - SEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - SEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - SEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - SEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - SEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - SEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - SEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BC - BC - Port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - CR0 - Port cleat bit - 0 - 1 - - - CR1 - Port cleat bit - 1 - 1 - - - CR2 - Port cleat bit - 2 - 1 - - - CR3 - Port cleat bit - 3 - 1 - - - CR4 - Port cleat bit - 4 - 1 - - - CR5 - Port cleat bit - 5 - 1 - - - CR6 - Port cleat bit - 6 - 1 - - - CR7 - Port cleat bit - 7 - 1 - - - CR8 - Port cleat bit - 8 - 1 - - - CR9 - Port cleat bit - 9 - 1 - - - CR10 - Port cleat bit - 10 - 1 - - - CR11 - Port cleat bit - 11 - 1 - - - CR12 - Port cleat bit - 12 - 1 - - - CR13 - Port cleat bit - 13 - 1 - - - CR14 - Port cleat bit - 14 - 1 - - - CR15 - Port cleat bit - 15 - 1 - - - - - TG - TG - Port bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - TG0 - Port toggle bit - 0 - 1 - - - TG1 - Port toggle bit - 1 - 1 - - - TG2 - Port toggle bit - 2 - 1 - - - TG3 - Port toggle bit - 3 - 1 - - - TG4 - Port toggle bit - 4 - 1 - - - TG5 - Port toggle bit - 5 - 1 - - - TG6 - Port toggle bit - 6 - 1 - - - TG7 - Port toggle bit - 7 - 1 - - - TG8 - Port toggle bit - 8 - 1 - - - TG9 - Port toggle bit - 9 - 1 - - - TG10 - Port toggle bit - 10 - 1 - - - TG11 - Port toggle bit - 11 - 1 - - - TG12 - Port toggle bit - 12 - 1 - - - TG13 - Port toggle bit - 13 - 1 - - - TG14 - Port toggle bit - 14 - 1 - - - TG15 - Port toggle bit - 15 - 1 - - - - - - - GPIOF - General-purpose I/Os - GPIO - 0x48001400 - - 0x0 - 0x400 - registers - - - - CTL - CTL - GPIOF port control register - 0x0 - 0x20 - read-write - 0x00000000 - - - CTL15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - CTL14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - CTL13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - CTL12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - CTL11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - CTL10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - CTL9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - CTL8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - CTL7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - CTL6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - CTL5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - CTL4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - CTL3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - CTL2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - CTL1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - CTL0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OMODE - OMODE - GPIO port output type register - 0x04 - 0x20 - read-write - 0x00000000 - - - OM15 - Port x configuration bit - 15 - 15 - 1 - - - OM14 - Port x configuration bit - 14 - 14 - 1 - - - OM13 - Port x configuration bit - 13 - 13 - 1 - - - OM12 - Port x configuration bit - 12 - 12 - 1 - - - OM11 - Port x configuration bit - 11 - 11 - 1 - - - OM10 - Port x configuration bit - 10 - 10 - 1 - - - OM9 - Port x configuration bit 9 - 9 - 1 - - - OM8 - Port x configuration bit 8 - 8 - 1 - - - OM7 - Port x configuration bit 7 - 7 - 1 - - - OM6 - Port x configuration bit 6 - 6 - 1 - - - OM5 - Port x configuration bit 5 - 5 - 1 - - - OM4 - Port x configuration bit 4 - 4 - 1 - - - OM3 - Port x configuration bit 3 - 3 - 1 - - - OM2 - Port x configuration bit 2 - 2 - 1 - - - OM1 - Port x configuration bit 1 - 1 - 1 - - - OM0 - Port x configuration bit 0 - 0 - 1 - - - - - OSPD - OSPD - GPIO port output speed - register - 0x08 - 0x20 - read-write - 0x00000000 - - - OSPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUD - PUD - GPIO port pull-up/pull-down - register - 0x0C - 0x20 - read-write - 0x00000000 - - - PUD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - ISTAT - ISTAT - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ISTAT15 - Port input data (y = - 0..15) - 15 - 1 - - - ISTAT14 - Port input data (y = - 0..15) - 14 - 1 - - - ISTAT13 - Port input data (y = - 0..15) - 13 - 1 - - - ISTAT12 - Port input data (y = - 0..15) - 12 - 1 - - - ISTAT11 - Port input data (y = - 0..15) - 11 - 1 - - - ISTAT10 - Port input data (y = - 0..15) - 10 - 1 - - - ISTAT9 - Port input data (y = - 0..15) - 9 - 1 - - - ISTAT8 - Port input data (y = - 0..15) - 8 - 1 - - - ISTAT7 - Port input data (y = - 0..15) - 7 - 1 - - - ISTAT6 - Port input data (y = - 0..15) - 6 - 1 - - - ISTAT5 - Port input data (y = - 0..15) - 5 - 1 - - - ISTAT4 - Port input data (y = - 0..15) - 4 - 1 - - - ISTAT3 - Port input data (y = - 0..15) - 3 - 1 - - - ISTAT2 - Port input data (y = - 0..15) - 2 - 1 - - - ISTAT1 - Port input data (y = - 0..15) - 1 - 1 - - - ISTAT0 - Port input data (y = - 0..15) - 0 - 1 - - - - - OCTL - OCTL - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OCTL15 - Port output data (y = - 0..15) - 15 - 1 - - - OCTL14 - Port output data (y = - 0..15) - 14 - 1 - - - OCTL13 - Port output data (y = - 0..15) - 13 - 1 - - - OCTL12 - Port output data (y = - 0..15) - 12 - 1 - - - OCTL11 - Port output data (y = - 0..15) - 11 - 1 - - - OCTL10 - Port output data (y = - 0..15) - 10 - 1 - - - OCTL9 - Port output data (y = - 0..15) - 9 - 1 - - - OCTL8 - Port output data (y = - 0..15) - 8 - 1 - - - OCTL7 - Port output data (y = - 0..15) - 7 - 1 - - - OCTL6 - Port output data (y = - 0..15) - 6 - 1 - - - OCTL5 - Port output data (y = - 0..15) - 5 - 1 - - - OCTL4 - Port output data (y = - 0..15) - 4 - 1 - - - OCTL3 - Port output data (y = - 0..15) - 3 - 1 - - - OCTL2 - Port output data (y = - 0..15) - 2 - 1 - - - OCTL1 - Port output data (y = - 0..15) - 1 - 1 - - - OCTL0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BOP - BOP - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - CR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - CR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - CR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - CR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - CR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - CR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - CR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - CR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - CR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - CR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - CR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - CR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - CR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - CR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - CR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - CR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BOP15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BOP14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BOP13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BOP12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BOP11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BOP10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BOP9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BOP8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BOP7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BOP6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BOP5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BOP4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BOP3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BOP2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BOP1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BOP0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - BC - BC - Port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - CR0 - Port x Reset bit y - 0 - 1 - - - CR1 - Port x Reset bit y - 1 - 1 - - - CR2 - Port x Reset bit y - 2 - 1 - - - CR3 - Port x Reset bit y - 3 - 1 - - - CR4 - Port x Reset bit y - 4 - 1 - - - CR5 - Port x Reset bit y - 5 - 1 - - - CR6 - Port x Reset bit y - 6 - 1 - - - CR7 - Port x Reset bit y - 7 - 1 - - - CR8 - Port x Reset bit y - 8 - 1 - - - CR9 - Port x Reset bit y - 9 - 1 - - - CR10 - Port x Reset bit y - 10 - 1 - - - CR11 - Port x Reset bit y - 11 - 1 - - - CR12 - Port x Reset bit y - 12 - 1 - - - CR13 - Port x Reset bit y - 13 - 1 - - - CR14 - Port x Reset bit y - 14 - 1 - - - CR15 - Port x Reset bit y - 15 - 1 - - - - - TG - TG - Port bit toggle register - 0x2C - 0x20 - write-only - 0x00000000 - - - TG0 - Port toggle bit - 0 - 1 - - - TG1 - Port toggle bit - 1 - 1 - - - TG2 - Port toggle bit - 2 - 1 - - - TG3 - Port toggle bit - 3 - 1 - - - TG4 - Port toggle bit - 4 - 1 - - - TG5 - Port toggle bit - 5 - 1 - - - TG6 - Port toggle bit - 6 - 1 - - - TG7 - Port toggle bit - 7 - 1 - - - TG8 - Port toggle bit - 8 - 1 - - - TG9 - Port toggle bit - 9 - 1 - - - TG10 - Port toggle bit - 10 - 1 - - - TG11 - Port toggle bit - 11 - 1 - - - TG12 - Port toggle bit - 12 - 1 - - - TG13 - Port toggle bit - 13 - 1 - - - TG14 - Port toggle bit - 14 - 1 - - - TG15 - Port toggle bit - 15 - 1 - - - - - - - I2C0 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C0_EV - 23 - - - I2C0_ER - 32 - - - - CTL0 - CTL0 - Control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - SRESET - Software reset - 15 - 1 - - - SALT - SMBus alert - 13 - 1 - - - PECTRANS - Packet error checking - 12 - 1 - - - POAP - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACKEN - Acknowledge enable - 10 - 1 - - - STOP - Stop condition - 9 - 1 - - - START - Start generation - 8 - 1 - - - SS - SCL Stretching(Slave - mode) - 7 - 1 - - - GCEN - General call enable - 6 - 1 - - - PECEN - PEC enable - 5 - 1 - - - ARPEN - ARP enable - 4 - 1 - - - SMBSEL - SMBus type - 3 - 1 - - - SMBEN - SMBus mode - 1 - 1 - - - I2CEN - Peripheral enable - 0 - 1 - - - - - CTL1 - CTL1 - Control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - DMALST - Flag indicating DMA last transfer - 12 - 1 - - - DMAON - DMA mode switch - 11 - 1 - - - BUFIE - Buffer interrupt enable - 10 - 1 - - - EVIE - Event interrupt enable - 9 - 1 - - - ERRIE - Error interrupt enable - 8 - 1 - - - I2CCLK - Peripheral clock frequency - 0 - 7 - - - - - SADDR0 - SADDR0 - Own address register 0 - 0x08 - 0x20 - read-write - 0x0000 - - - ADDFORMAT - Addressing mode (slave - mode) - 15 - 1 - - - ADDRESS - Interface address - 0 - 10 - - - - - SADDR1 - SADDR1 - Own address register 1 - 0x0C - 0x20 - read-write - 0x0000 - - - ADDRESS2 - Interface address - 1 - 7 - - - DUADEN - Dual addressing mode - enable - 0 - 1 - - - - - DATA - DATA - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - TRB - Transmission or reception data buffer - 0 - 8 - - - - - STAT0 - STAT0 - Transfer status register 0 - 0x14 - 0x20 - 0x0000 - - - SMBALT - SMBus alert - 15 - 1 - read-write - - - SMBTO - Timeout signal in SMBus mode - 14 - 1 - read-write - - - PECERR - PEC error when receiving data - 12 - 1 - read-write - - - OUERR - Overrun/Underrun occurs in slave mode - 11 - 1 - read-write - - - AERR - Acknowledge error - 10 - 1 - read-write - - - LOSTARB - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TBE - I2C_DATA is Empty during transmitting - 7 - 1 - read-only - - - RBNE - I2C_DATA is not Empty during receiving - 6 - 1 - read-only - - - STPDET - Stop detection (slave - mode) - 4 - 1 - read-only - - - ADD10SEND - Header of 10-bit address is sent in master mode - 3 - 1 - read-only - - - BTC - Byte transmission completed - 2 - 1 - read-only - - - ADDSEND - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SBSEND - Start bit (Master mode) - 0 - 1 - read-only - - - - - STAT1 - STAT1 - Transfer status register 1 - 0x18 - 0x20 - read-only - 0x0000 - - - PECV - Packet error checking - register - 8 - 8 - - - DUMODF - Dual flag (Slave mode) - 7 - 1 - - - HSTSMB - SMBus host header (Slave - mode) - 6 - 1 - - - DEFSMB - SMBus device default address (Slave - mode) - 5 - 1 - - - RXGC - General call address (Slave - mode) - 4 - 1 - - - TR - Transmitter/receiver - 2 - 1 - - - I2CBSY - Bus busy - 1 - 1 - - - MASTER - Master/slave - 0 - 1 - - - - - CKCFG - CKCFG - Clock configure register - 0x1C - 0x20 - read-write - 0x0000 - - - FAST - I2C master mode selection - 15 - 1 - - - DTCY - Fast mode duty cycle - 14 - 1 - - - CLKC - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - RT - RT - Rise time register - 0x20 - 0x20 - read-write - 0x0002 - - - RISETIME - Maximum rise time in master mode - 0 - 7 - - - - - SAMCS - SAMCS - SAM control and status register - 0x80 - 0x20 - read-write - 0x0000 - - - RFR - Rxframe rise flag - 15 - 1 - - - RFF - Rxframe fall flag - 14 - 1 - - - TFR - Txframe rise flag - 13 - 1 - - - TFF - Txframe fall flag - 12 - 1 - - - RXF - level of rx frame signal - 9 - 1 - - - TXF - level of tx frame signal - 8 - 1 - - - RFRIE - Rx frame rise interrupt enable - 7 - 1 - - - RFFIE - Rx frame fall interrupt enable - 6 - 1 - - - TFRIE - Tx frame rise interrupt enable - 5 - 1 - - - TFFIE - Tx frame fall interrupt enable - 4 - 1 - - - STOEN - SAM_V interface timeout detect enable - 1 - 1 - - - SAMEN - SAM_V interface enable - 0 - 1 - - - - - FMPCFG - FMPCFG - Fast-mode-plus configure register - 0x90 - 0x20 - read-write - 0x0000 - - - FMPEN - Fast-mode-plus enable - 0 - 1 - - - - - - - I2C1 - 0x40005800 - - I2C1_EV - 24 - - - I2C1_ER - 34 - - - - NVIC - Nested Vectored Interrupt - Controller - NVIC - 0xE000E100 - - 0x0 - 0xF00 - registers - - - 0x33D - 0xC3 - reserved - - - - ISER0 - ISER0 - Interrupt Set Enable Register - 0x0 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER1 - ISER1 - Interrupt Set Enable Register - 0x04 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER2 - ISER2 - Interrupt Set Enable Register - 0x08 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER3 - ISER3 - Interrupt Set Enable Register - 0x0C - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER4 - ISER4 - Interrupt Set Enable Register - 0x10 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER5 - ISER5 - Interrupt Set Enable Register - 0x14 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER6 - ISER6 - Interrupt Set Enable Register - 0x18 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER7 - ISER7 - Interrupt Set Enable Register - 0x1C - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER8 - ISER8 - Interrupt Set Enable Register - 0x20 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER9 - ISER9 - Interrupt Set Enable Register - 0x24 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER10 - ISER10 - Interrupt Set Enable Register - 0x28 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER11 - ISER11 - Interrupt Set Enable Register - 0x2C - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER12 - ISER12 - Interrupt Set Enable Register - 0x30 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER13 - ISER13 - Interrupt Set Enable Register - 0x34 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER14 - ISER14 - Interrupt Set Enable Register - 0x38 - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ISER15 - ISER15 - Interrupt Set Enable Register - 0x3C - 0x20 - read-write - 0x00000000 - - - SETENA - SETENA - 0 - 32 - - - - - ICER0 - ICER0 - Interrupt Clear Enable - Register - 0x80 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER1 - ICER1 - Interrupt Clear Enable - Register - 0x84 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER2 - ICER2 - Interrupt Clear Enable - Register - 0x8C - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER3 - ICER3 - Interrupt Clear Enable - Register - 0x90 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER4 - ICER4 - Interrupt Clear Enable - Register - 0x94 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER5 - ICER5 - Interrupt Clear Enable - Register - 0x98 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER6 - ICER6 - Interrupt Clear Enable - Register - 0x9C - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER7 - ICER7 - Interrupt Clear Enable - Register - 0xA0 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER8 - ICER8 - Interrupt Clear Enable - Register - 0xA4 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER9 - ICER9 - Interrupt Clear Enable - Register - 0xA8 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER10 - ICER10 - Interrupt Clear Enable - Register - 0xAC - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER11 - ICER11 - Interrupt Clear Enable - Register - 0xB0 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER12 - ICER12 - Interrupt Clear Enable - Register - 0xB4 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER13 - ICER13 - Interrupt Clear Enable - Register - 0xB8 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER14 - ICER14 - Interrupt Clear Enable - Register - 0xBC - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ICER15 - ICER15 - Interrupt Clear Enable - Register - 0xC0 - 0x20 - read-write - 0x00000000 - - - CLRENA - CLRENA - 0 - 32 - - - - - ISPR0 - ISPR0 - Interrupt Set-Pending Register - 0x100 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR1 - ISPR1 - Interrupt Set-Pending Register - 0x104 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR2 - ISPR2 - Interrupt Set-Pending Register - 0x108 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR3 - ISPR3 - Interrupt Set-Pending Register - 0x10C - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR4 - ISPR4 - Interrupt Set-Pending Register - 0x110 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR5 - ISPR5 - Interrupt Set-Pending Register - 0x114 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR6 - ISPR6 - Interrupt Set-Pending Register - 0x118 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR7 - ISPR7 - Interrupt Set-Pending Register - 0x11C - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR8 - ISPR8 - Interrupt Set-Pending Register - 0x120 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR9 - ISPR9 - Interrupt Set-Pending Register - 0x124 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR10 - ISPR10 - Interrupt Set-Pending Register - 0x128 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR11 - ISPR11 - Interrupt Set-Pending Register - 0x12C - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR12 - ISPR12 - Interrupt Set-Pending Register - 0x130 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR13 - ISPR13 - Interrupt Set-Pending Register - 0x134 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR14 - ISPR14 - Interrupt Set-Pending Register - 0x138 - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ISPR15 - ISPR15 - Interrupt Set-Pending Register - 0x13C - 0x20 - read-write - 0x00000000 - - - SETPEND - SETPEND - 0 - 32 - - - - - ICPR0 - ICPR0 - Interrupt Clear-Pending - Register - 0x180 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR1 - ICPR1 - Interrupt Clear-Pending - Register - 0x184 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR2 - ICPR2 - Interrupt Clear-Pending - Register - 0x188 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR3 - ICPR3 - Interrupt Clear-Pending - Register - 0x18C - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR4 - ICPR4 - Interrupt Clear-Pending - Register - 0x190 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR5 - ICPR5 - Interrupt Clear-Pending - Register - 0x194 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR6 - ICPR6 - Interrupt Clear-Pending - Register - 0x198 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR7 - ICPR7 - Interrupt Clear-Pending - Register - 0x19C - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR8 - ICPR8 - Interrupt Clear-Pending - Register - 0x1A0 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR9 - ICPR9 - Interrupt Clear-Pending - Register - 0x1A4 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR10 - ICPR10 - Interrupt Clear-Pending - Register - 0x1A8 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR11 - ICPR11 - Interrupt Clear-Pending - Register - 0x1AC - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR12 - ICPR12 - Interrupt Clear-Pending - Register - 0x1B0 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR13 - ICPR13 - Interrupt Clear-Pending - Register - 0x1B4 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR14 - ICPR14 - Interrupt Clear-Pending - Register - 0x1B8 - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - ICPR15 - ICPR15 - Interrupt Clear-Pending - Register - 0x1BC - 0x20 - read-write - 0x00000000 - - - CLRPEND - CLRPEND - 0 - 32 - - - - - IABR0 - IABR0 - Interrupt Active bit - Register - 0x200 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR1 - IABR1 - Interrupt Active bit - Register - 0x204 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR2 - IABR2 - Interrupt Active bit - Register - 0x208 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR3 - IABR3 - Interrupt Active bit - Register - 0x20C - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR4 - IABR4 - Interrupt Active bit - Register - 0x210 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR5 - IABR5 - Interrupt Active bit - Register - 0x214 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR6 - IABR6 - Interrupt Active bit - Register - 0x218 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR7 - IABR7 - Interrupt Active bit - Register - 0x21C - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR8 - IABR8 - Interrupt Active bit - Register - 0x220 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR9 - IABR9 - Interrupt Active bit - Register - 0x224 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR10 - IABR10 - Interrupt Active bit - Register - 0x228 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR11 - IABR11 - Interrupt Active bit - Register - 0x22C - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR12 - IABR12 - Interrupt Active bit - Register - 0x230 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR13 - IABR13 - Interrupt Active bit - Register - 0x234 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR14 - IABR14 - Interrupt Active bit - Register - 0x238 - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - IABR15 - IABR15 - Interrupt Active bit - Register - 0x23C - 0x20 - read-write - 0x00000000 - - - IABR - IABR - 0 - 32 - - - - - ITNS0 - ITNS0 - Interrupt Active bit - Register - 0x280 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS1 - ITNS1 - Interrupt Active bit - Register - 0x284 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS2 - ITNS2 - Interrupt Active bit - Register - 0x288 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS3 - ITNS3 - Interrupt Active bit - Register - 0x28C - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS4 - ITNS4 - Interrupt Active bit - Register - 0x290 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS5 - ITNS5 - Interrupt Active bit - Register - 0x294 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS6 - ITNS6 - Interrupt Active bit - Register - 0x298 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS7 - ITNS7 - Interrupt Active bit - Register - 0x29C - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS8 - ITNS8 - Interrupt Active bit - Register - 0x2A0 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS9 - ITNS9 - Interrupt Active bit - Register - 0x2A4 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS10 - ITNS10 - Interrupt Active bit - Register - 0x2A8 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS11 - ITNS11 - Interrupt Active bit - Register - 0x2AC - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS12 - ITNS12 - Interrupt Active bit - Register - 0x2B0 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS13 - ITNS13 - Interrupt Active bit - Register - 0x2B4 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS14 - ITNS14 - Interrupt Active bit - Register - 0x2B8 - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - ITNS15 - ITNS15 - Interrupt Active bit - Register - 0x2BC - 0x20 - read-write - 0x00000000 - - - ITNS - ITNS - 0 - 32 - - - - - IPR0 - IPR0 - Interrupt Priority Register 0 - 0x300 - 0x08 - read-write - 0x00 - - - PRI_00 - PRI_00 - 0 - 8 - - - - - IPR1 - IPR1 - Interrupt Priority Register 1 - 0x301 - 0x08 - read-write - 0x00 - - - PRI_01 - PRI_01 - 0 - 8 - - - - - IPR2 - IPR2 - Interrupt Priority Register 2 - 0x302 - 0x08 - read-write - 0x00 - - - PRI_02 - PRI_02 - 0 - 8 - - - - - IPR3 - IPR3 - Interrupt Priority Register 3 - 0x303 - 0x08 - read-write - 0x00 - - - PRI_03 - PRI_03 - 0 - 8 - - - - - IPR4 - IPR4 - Interrupt Priority Register 4 - 0x304 - 0x08 - read-write - 0x00 - - - PRI_04 - PRI_04 - 0 - 8 - - - - - IPR5 - IPR5 - Interrupt Priority Register 5 - 0x305 - 0x08 - read-write - 0x00 - - - PRI_05 - PRI_05 - 0 - 8 - - - - - IPR6 - IPR6 - Interrupt Priority Register 6 - 0x306 - 0x08 - read-write - 0x00 - - - PRI_06 - PRI_06 - 0 - 8 - - - - - IPR7 - IPR7 - Interrupt Priority Register 7 - 0x307 - 0x08 - read-write - 0x00 - - - PRI_07 - PRI_07 - 0 - 8 - - - - - IPR8 - IPR8 - Interrupt Priority Register 8 - 0x308 - 0x08 - read-write - 0x00 - - - PRI_08 - PRI_08 - 0 - 8 - - - - - IPR9 - IPR9 - Interrupt Priority Register 9 - 0x309 - 0x08 - read-write - 0x00 - - - PRI_09 - PRI_09 - 0 - 8 - - - - - IPR10 - IPR10 - Interrupt Priority Register 10 - 0x30A - 0x08 - read-write - 0x00 - - - PRI_10 - PRI_10 - 0 - 8 - - - - - IPR11 - IPR11 - Interrupt Priority Register 11 - 0x30B - 0x08 - read-write - 0x00 - - - PRI_11 - PRI_11 - 0 - 8 - - - - - IPR12 - IPR12 - Interrupt Priority Register 12 - 0x30C - 0x08 - read-write - 0x00 - - - PRI_12 - PRI_12 - 0 - 8 - - - - - IPR13 - IPR13 - Interrupt Priority Register 13 - 0x30D - 0x08 - read-write - 0x00 - - - PRI_13 - PRI_13 - 0 - 8 - - - - - IPR14 - IPR14 - Interrupt Priority Register 14 - 0x30E - 0x08 - read-write - 0x00 - - - PRI_14 - PRI_14 - 0 - 8 - - - - - IPR15 - IPR15 - Interrupt Priority Register 15 - 0x30F - 0x08 - read-write - 0x00 - - - PRI_15 - PRI_15 - 0 - 8 - - - - - IPR16 - IPR16 - Interrupt Priority Register 16 - 0x310 - 0x08 - read-write - 0x00 - - - PRI_16 - PRI_16 - 0 - 8 - - - - - IPR17 - IPR17 - Interrupt Priority Register 17 - 0x311 - 0x08 - read-write - 0x00 - - - PRI_17 - PRI_17 - 0 - 8 - - - - - IPR18 - IPR18 - Interrupt Priority Register 18 - 0x312 - 0x08 - read-write - 0x00 - - - PRI_18 - PRI_18 - 0 - 8 - - - - - IPR19 - IPR19 - Interrupt Priority Register 19 - 0x313 - 0x08 - read-write - 0x00 - - - PRI_19 - PRI_19 - 0 - 8 - - - - - IPR20 - IPR20 - Interrupt Priority Register 20 - 0x314 - 0x08 - read-write - 0x00 - - - PRI_20 - PRI_20 - 0 - 8 - - - - - IPR21 - IPR21 - Interrupt Priority Register 21 - 0x315 - 0x08 - read-write - 0x00 - - - PRI_21 - PRI_21 - 0 - 8 - - - - - IPR22 - IPR22 - Interrupt Priority Register 22 - 0x316 - 0x08 - read-write - 0x00 - - - PRI_22 - PRI_22 - 0 - 8 - - - - - IPR23 - IPR23 - Interrupt Priority Register 23 - 0x317 - 0x08 - read-write - 0x00 - - - PRI_23 - PRI_23 - 0 - 8 - - - - - IPR24 - IPR24 - Interrupt Priority Register 24 - 0x318 - 0x08 - read-write - 0x00 - - - PRI_24 - PRI_24 - 0 - 8 - - - - - IPR25 - IPR25 - Interrupt Priority Register 25 - 0x319 - 0x08 - read-write - 0x00 - - - PRI_25 - PRI_25 - 0 - 8 - - - - - IPR26 - IPR26 - Interrupt Priority Register 26 - 0x31A - 0x08 - read-write - 0x00 - - - PRI_26 - PRI_26 - 0 - 8 - - - - - IPR27 - IPR27 - Interrupt Priority Register 27 - 0x31B - 0x08 - read-write - 0x00 - - - PRI_27 - PRI_27 - 0 - 8 - - - - - IPR28 - IPR28 - Interrupt Priority Register 28 - 0x31C - 0x08 - read-write - 0x00 - - - PRI_28 - PRI_28 - 0 - 8 - - - - - IPR29 - IPR29 - Interrupt Priority Register 29 - 0x31D - 0x08 - read-write - 0x00 - - - PRI_29 - PRI_29 - 0 - 8 - - - - - IPR30 - IPR30 - Interrupt Priority Register 30 - 0x31E - 0x08 - read-write - 0x00 - - - PRI_30 - PRI_30 - 0 - 8 - - - - - IPR31 - IPR31 - Interrupt Priority Register 31 - 0x31F - 0x08 - read-write - 0x00 - - - PRI_31 - PRI_31 - 0 - 8 - - - - - - - PMU - Power management unit - PMU - 0x40007000 - - 0x0 - 0x400 - registers - - - - CTL - CTL - power control register - 0x0 - 0x20 - read-write - 0x00004000 - - - LDOVS - LDO output voltage select - 14 - 2 - - - BKPWEN - Backup Domain Write Enable - 8 - 1 - - - LVDT - Low Voltage Detector Threshold - 5 - 3 - - - LVDEN - Low Voltage Detector Enable - 4 - 1 - - - STBRST - Standby Flag Reset - 3 - 1 - - - WURST - Wakeup Flag Reset - 2 - 1 - - - STBMOD - Standby Mode - 1 - 1 - - - LDOLP - LDO Low Power Mode - 0 - 1 - - - - - CS - CS - power control/status register - 0x04 - 0x20 - 0x00000000 - - - WUPEN6 - WKUP pin6 Enable - 14 - 1 - read-write - - - WUPEN5 - WKUP pin5 Enable - 13 - 1 - read-write - - - WUPEN1 - WKUP pin1 Enable - 9 - 1 - read-write - - - WUPEN0 - WKUP pin0 Enable - 8 - 1 - read-write - - - LVDF - Low Voltage Detector Status Flag - 2 - 1 - read-only - - - STBF - Standby flag - 1 - 1 - read-only - - - WUF - Wakeup flag - 0 - 1 - read-only - - - - - - - RCU - Reset and clock unit - RCU - 0x40021000 - - 0x0 - 0x400 - registers - - - RCU - 4 - - - - CTL0 - CTL0 - Control register 0 - 0x0 - 0x20 - 0x00000083 - - - PLLSTB - PLL Clock Stabilization Flag - 25 - 1 - read-only - - - PLLEN - PLL enable - 24 - 1 - read-write - - - CKMEN - HXTAL Clock Monitor Enable - 19 - 1 - read-write - - - HXTALBPS - External crystal oscillator (HXTAL) clock bypass mode enable - 18 - 1 - read-write - - - HXTALSTB - External crystal oscillator (HXTAL) clock stabilization flag - 17 - 1 - read-only - - - HXTALEN - External High Speed oscillator Enable - 16 - 1 - read-write - - - IRC8MCALIB - High Speed Internal Oscillator calibration value register - 8 - 8 - read-only - - - IRC8MADJ - High Speed Internal Oscillator clock trim adjust value - 3 - 5 - read-write - - - IRC8MSTB - IRC8M High Speed Internal Oscillator stabilization Flag - 1 - 1 - read-only - - - IRC8MEN - Internal High Speed oscillator Enable - 0 - 1 - read-write - - - - - CFG0 - CFG0 - Clock configuration register 0 - (RCU_CFG0) - 0x04 - 0x20 - 0x00000000 - - - PLLDV - The CK_PLL divide by 1 or 2 for CK_OUT - - 31 - 1 - read-write - - - CKOUTDIV - The CK_OUT divider which the CK_OUT frequency can be reduced - 28 - 3 - read-write - - - PLLMF_MSB - Bit 4 of PLLMF register - 27 - 1 - read-write - - - CKOUTSEL - CK_OUT Clock Source Selection - 24 - 3 - read-write - - - PLLMF - PLL multiply factor - 18 - 4 - read-write - - - PLLPREDV - HXTAL divider for PLL source clock selection. - 17 - 1 - read-write - - - PLLSEL - PLL Clock Source Selection - 16 - 1 - read-write - - - ADCPSC - ADC clock prescaler selection - 14 - 2 - read-write - - - APB2PSC - APB2 prescaler selection - 11 - 3 - read-write - - - APB1PSC - APB1 prescaler selection - 8 - 3 - read-write - - - AHBPSC - AHB prescaler selection - 4 - 4 - read-write - - - SCSS - System clock switch status - 2 - 2 - read-only - - - SCS - System clock switch - 0 - 2 - read-write - - - - - INT - INT - Clock interrupt register - (RCU_INT) - 0x08 - 0x20 - 0x00000000 - - - CKMIC - HXTAL Clock Stuck Interrupt Clear - 23 - 1 - write-only - - - IRC28MSTBIC - IRC28M stabilization Interrupt Clear - 21 - 1 - write-only - - - PLLSTBIC - PLL stabilization Interrupt Clear - 20 - 1 - write-only - - - HXTALSTBIC - HXTAL Stabilization Interrupt Clear - 19 - 1 - write-only - - - IRC8MSTBIC - IRC8M Stabilization Interrupt Clear - 18 - 1 - write-only - - - LXTALSTBIC - LXTAL Stabilization Interrupt Clear - 17 - 1 - write-only - - - IRC40KSTBIC - IRC40K Stabilization Interrupt Clear - 16 - 1 - write-only - - - IRC28MSTBIE - IRC28M Stabilization Interrupt Enable - 13 - 1 - read-write - - - PLLSTBIE - PLL Stabilization Interrupt Enable - 12 - 1 - read-write - - - HXTALSTBIE - HXTAL Stabilization Interrupt Enable - 11 - 1 - read-write - - - IRC8MSTBIE - IRC8M Stabilization Interrupt Enable - 10 - 1 - read-write - - - LXTALSTBIE - LXTAL Stabilization Interrupt Enable - 9 - 1 - read-write - - - IRC40KSTBIE - IRC40K Stabilization interrupt enable - 8 - 1 - read-write - - - CKMIF - HXTAL Clock Stuck Interrupt Flag - 7 - 1 - read-only - - - IRC28MSTBIF - IRC28M stabilization interrupt flag - 5 - 1 - read-only - - - PLLSTBIF - PLL stabilization interrupt flag - 4 - 1 - read-only - - - HXTALSTBIF - HXTAL stabilization interrupt flag - 3 - 1 - read-only - - - IRC8MSTBIF - IRC8M stabilization interrupt flag - 2 - 1 - read-only - - - LXTALSTBIF - LXTAL stabilization interrupt flag - 1 - 1 - read-only - - - IRC40KSTBIF - IRC40K stabilization interrupt flag - 0 - 1 - read-only - - - - - APB2RST - APB2RST - APB2 reset register - (RCU_APB2RST) - 0x0C - 0x20 - read-write - 0x00000000 - - - TIMER16RST - TIMER16 reset - 18 - 1 - - - TIMER15RST - TIMER15 reset - 17 - 1 - - - TIMER14RST - TIMER14 reset - 16 - 1 - - - USART0RST - USART0 Reset - 14 - 1 - - - SPI0RST - SPI0 Reset - 12 - 1 - - - TIMER0RST - TIMER0 reset - 11 - 1 - - - ADCRST - ADC reset - 9 - 1 - - - CFGCMPRST - System configuration and comparator reset - 0 - 1 - - - - - APB1RST - APB1RST - APB1 reset register - (RCU_APB1RST) - 0x10 - 0x20 - read-write - 0x00000000 - - - PMURST - Power control reset - 28 - 1 - - - I2C1RST - I2C1 reset - 22 - 1 - - - I2C0RST - I2C0 reset - 21 - 1 - - - USART1RST - USART1 reset - 17 - 1 - - - SPI1RST - SPI1 reset - 14 - 1 - - - WWDGTRST - Window watchdog timer reset - 11 - 1 - - - TIMER13RST - TIMER13 timer reset - 8 - 1 - - - TIMER5RST - TIMER5 timer reset - 4 - 1 - - - TIMER2RST - TIMER2 timer reset - 1 - 1 - - - - - AHBEN - AHBEN - AHB enable register - (RCU_AHBEN) - 0x14 - 0x20 - read-write - 0x00000014 - - - PFEN - GPIO port F clock enable - 22 - 1 - - - PCEN - GPIO port C clock enable - 19 - 1 - - - PBEN - GPIO port B clock enable - 18 - 1 - - - PAEN - GPIO port A clock enable - 17 - 1 - - - CRCEN - CRC clock enable - 6 - 1 - - - FMCSPEN - FMC clock during sleep mode enable - 4 - 1 - - - SRAMSPEN - SRAM interface clock during sleep mode enable - 2 - 1 - - - DMAEN - DMA clock enable - 0 - 1 - - - - - APB2EN - APB2EN - APB2 enable register - (RCU_APB2EN) - 0x18 - 0x20 - read-write - 0x00000000 - - - DBGMCUEN - DBGMCU clock enable - 22 - 1 - - - TIMER16EN - TIMER16 timer clock enable - 18 - 1 - - - TIMER15EN - TIMER15 timer clock enable - 17 - 1 - - - TIMER14EN - TIMER14 timer clock enable - 16 - 1 - - - USART0EN - USART0 clock enable - 14 - 1 - - - SPI0EN - SPI0 clock enable - 12 - 1 - - - TIMER0EN - TIMER0 timer clock enable - 11 - 1 - - - ADCEN - ADC interface clock enable - 9 - 1 - - - CFGCMPEN - System configuration and comparator clock enable - 0 - 1 - - - - - APB1EN - APB1EN - APB1 enable register - (RCU_APB1EN) - 0x1C - 0x20 - read-write - 0x00000000 - - - PMUEN - Power interface clock enable - 28 - 1 - - - I2C1EN - I2C1 clock enable - 22 - 1 - - - I2C0EN - I2C0 clock enable - 21 - 1 - - - USART1EN - USART1 clock enable - 17 - 1 - - - SPI1EN - SPI1 clock enable - 14 - 1 - - - WWDGTEN - Window watchdog timer clock enable - 11 - 1 - - - TIMER13EN - TIMER13 timer clock enable - 8 - 1 - - - TIMER5EN - TIMER5 timer clock enable - 4 - 1 - - - TIMER2EN - TIMER2 timer clock enable - 1 - 1 - - - - - BDCTL - BDCTL - Backup domain control register - (RCU_BDCTL) - 0x20 - 0x20 - 0x00000018 - - - BKPRST - Backup domain reset - 16 - 1 - read-write - - - RTCEN - RTC clock enable - 15 - 1 - read-write - - - RTCSRC - RTC clock entry selection - 8 - 2 - read-write - - - LXTALDRI - LXTAL drive capability - 3 - 2 - read-write - - - LXTALBPS - LXTAL bypass mode enable - 2 - 1 - read-write - - - LXTALSTB - External low-speed oscillator stabilization - 1 - 1 - read-only - - - LXTALEN - LXTAL enable - 0 - 1 - read-write - - - - - RSTSCK - RSTSCK - Reset source /clock register - (RCU_RSTSCK) - 0x24 - 0x20 - 0x0C000000 - - - LPRSTF - Low-power reset flag - 31 - 1 - read-write - - - WWDGTRSTF - Window watchdog timer reset flag - 30 - 1 - read-write - - - FWDGTRSTF - Free Watchdog timer reset flag - 29 - 1 - read-write - - - SWRSTF - Software reset flag - 28 - 1 - read-write - - - PORRSTF - Power reset flag - 27 - 1 - read-write - - - EPRSTF - External PIN reset flag - 26 - 1 - read-write - - - OBLRSTF - Option byte loader reset flag - 25 - 1 - read-write - - - RSTFC - Reset flag clear - 24 - 1 - read-write - - - V12RSTF - V12 domain Power reset flag - 23 - 1 - read-write - - - IRC40KSTB - IRC40K stabilization - 1 - 1 - read-only - - - IRC40KEN - IRC40K enable - 0 - 1 - read-write - - - - - AHBRST - AHBRST - AHB reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - PFRST - GPIO port F reset - 22 - 1 - - - PCRST - GPIO port C reset - 19 - 1 - - - PBRST - GPIO port B reset - 18 - 1 - - - PARST - GPIO port A reset - 17 - 1 - - - - - CFG1 - CFG1 - Configuration register 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - PREDV - CK_HXTAL or CK_IRC48M divider previous PLL - 0 - 4 - - - - - CFG2 - CFG2 - Configuration register 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - ADCPSC - Bit 2 of ADCPSC - 31 - 1 - - - IRC28MDIV - CK_IRC28M divider 2 or not - 16 - 1 - - - ADCSEL - CK_ADC clock source selection - 8 - 1 - - - USART0SEL - CK_USART0 clock source selection - 0 - 2 - - - - - CTL1 - CTL1 - Control register 1 - 0x34 - 0x20 - 0x00000080 - - - IRC28MCALIB - Internal 28M RC Oscillator calibration value register - 8 - 8 - read-only - - - IRC28MADJ - Internal 28M RC Oscillator clock trim adjust value - 3 - 5 - read-write - - - IRC28MSTB - IRC28M Internal 28M RC Oscillator stabilization Flag - 1 - 1 - read-only - - - IRC28MEN - IRC28M Internal 28M RC oscillator Enable - 0 - 1 - read-write - - - - - VKEY - VKEY - Voltage key register - 0x100 - 0x20 - 0x00000000 - - - KEY - The key of RCU_DSV register - 0 - 32 - write - - - - - DSV - DSV - Deep-sleep mode voltage register - 0x134 - 0x20 - 0x00000000 - - - DSLPVS - Deep-sleep mode voltage select - 0 - 2 - read-write - - - - - - - RTC - Real-time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - 2 - - - - TIME - TIME - time register - 0x0 - 0x20 - read-write - 0x00000000 - - - PM - AM/PM mark - 22 - 1 - - - HRT - Hour tens in BCD code - 20 - 2 - - - HRU - Hour units in BCD format - 16 - 4 - - - MNT - Minute tens in BCD code - 12 - 3 - - - MNU - Minute units in BCD code - 8 - 4 - - - SCT - Second tens in BCD code - 4 - 3 - - - SCU - Second units in BCD code - 0 - 4 - - - - - DATE - DATE - date register - 0x4 - 0x20 - read-write - 0x00002101 - - - YRT - Year tens in BCD code - 20 - 4 - - - YRU - Year units in BCD code - 16 - 4 - - - DOW - Days of the week - 13 - 3 - - - MONT - Month tens in BCD code - 12 - 1 - - - MONU - Month units in BCD code - 8 - 4 - - - DAYT - Date tens in BCD code - 4 - 2 - - - DAYU - Date units in BCD code - 0 - 4 - - - - - CTL - CTL - control register - 0x8 - 0x20 - 0x00000000 - - - COEN - Calibration output enable - 23 - 1 - read-write - - - OS - Output selection - 21 - 2 - read-write - - - OPOL - Output polarity - 20 - 1 - read-write - - - COS - Calibration output - selection - 19 - 1 - read-write - - - DSM - Backup - 18 - 1 - read-write - - - S1H - Subtract 1 hour (winter time - change) - 17 - 1 - write-only - - - A1H - Add 1 hour (summer time - change) - 16 - 1 - write-only - - - TSIE - Time-stamp interrupt - enable - 15 - 1 - read-write - - - ALRM0IE - Alarm A interrupt enable - 12 - 1 - read-write - - - TSEN - timestamp enable - 11 - 1 - read-write - - - ALRM0EN - Alarm A enable - 8 - 1 - read-write - - - CS - Hour format - 6 - 1 - read-write - - - BPSHAD - Bypass the shadow - registers - 5 - 1 - read-write - - - REFEN - RTC_REFIN reference clock detection - enable (50 or 60 Hz) - 4 - 1 - read-write - - - TSEG - Time-stamp event active - edge - 3 - 1 - read-write - - - - - STAT - STAT - initialization and status - register - 0xC - 0x20 - 0x00000007 - - - SCPF - Recalibration pending Flag - 16 - 1 - read-only - - - TP1F - RTC_TAMP1 detection flag - 14 - 1 - read-write - - - TP0F - RTC_TAMP0 detection flag - 13 - 1 - read-write - - - TSOVRF - Time-stamp overflow flag - 12 - 1 - read-write - - - TSF - Time-stamp flag - 11 - 1 - read-write - - - ALRM0F - Alarm A flag - 8 - 1 - read-write - - - INITM - Initialization mode - 7 - 1 - read-write - - - INITF - Initialization flag - 6 - 1 - read-only - - - RSYNF - Registers synchronization - flag - 5 - 1 - read-write - - - YCM - Initialization status flag - 4 - 1 - read-only - - - SOPF - Shift operation pending - 3 - 1 - read-only - - - ALRM0WF - Alarm A write flag - 0 - 1 - read-only - - - - - PSC - PSC - prescaler register - 0x10 - 0x20 - read-write - 0x007F00FF - - - FACTOR_A - Asynchronous prescaler - factor - 16 - 7 - - - FACTOR_S - Synchronous prescaler - factor - 0 - 15 - - - - - ALRM0TD - ALRM0TD - alarm A register - 0x1C - 0x20 - read-write - 0x00000000 - - - MSKD - Alarm date mask - 31 - 1 - - - DOWS - Week day selection - 30 - 1 - - - DAYT - Date tens in BCD format. - 28 - 2 - - - DAYU - Date units or day in BCD - format. - 24 - 4 - - - MSKH - Alarm hours mask - 23 - 1 - - - PM - AM/PM notation - 22 - 1 - - - HRT - Hour tens in BCD format. - 20 - 2 - - - HRU - Hour units in BCD format. - 16 - 4 - - - MSKM - Alarm minutes mask - 15 - 1 - - - MNT - Minute tens in BCD format. - 12 - 3 - - - MNU - Minute units in BCD - format. - 8 - 4 - - - MSKS - Alarm seconds mask - 7 - 1 - - - SCT - Second tens in BCD format. - 4 - 3 - - - SCU - Second units in BCD - format. - 0 - 4 - - - - - WPK - WPK - write protection register - 0x24 - 0x20 - write-only - 0x00000000 - - - WPK - Write protection key - 0 - 8 - - - - - SS - SS - sub second register - 0x28 - 0x20 - read-only - 0x00000000 - - - SSC - Sub second value - 0 - 16 - - - - - SHIFTCTL - SHIFTCTL - shift control register - 0x2C - 0x20 - write-only - 0x00000000 - - - A1S - One second add - 31 - 1 - - - SFS - Subtract a fraction of a - second - 0 - 15 - - - - - TTS - TTS - timestamp time register - 0x30 - 0x20 - read-only - 0x00000000 - - - PM - AM/PM mark - 22 - 1 - - - HRT - Hour tens in BCD code - 20 - 2 - - - HRU - Hour units in BCD code - 16 - 4 - - - MNT - Minute tens in BCD code - 12 - 3 - - - MNU - Minute units in BCD code - 8 - 4 - - - SCT - Second tens in BCD code - 4 - 3 - - - SCU - Second units in BCD code - 0 - 4 - - - - - DTS - DTS - Date of time stamp register - 0x34 - 0x20 - read-only - 0x00000000 - - - DOW - Week day units - 13 - 3 - - - MONT - Month tens in BCD code - 12 - 1 - - - MONU - Month units in BCD code - 8 - 4 - - - DAYT - Date tens in BCD code - 5 - 2 - - - DAYU - Date units in BCD code - 0 - 5 - - - - - SSTS - SSTS - time-stamp sub second register - 0x38 - 0x20 - read-only - 0x00000000 - - - SSC - Sub second value - 0 - 16 - - - - - HRFC - HRFC - High resolution frequency compensation register - 0x3C - 0x20 - read-write - 0x00000000 - - - FREQI - Increase RTC frequency by 488.5PPM - 15 - 1 - - - CWND8 - Frequency compensation window 8 second selected - 14 - 1 - - - CWND16 - Frequency compensation window 16 second selected - 13 - 1 - - - CMSK - Calibration mask number - 0 - 9 - - - - - TAMP - TAMP - tamper and alternate function configuration - register - 0x40 - 0x20 - read-write - 0x00000000 - - - PC15MDE - PC15 mode - 23 - 1 - - - PC15VAL - PC15 value - 22 - 1 - - - PC14MDE - PC14 mode - 21 - 1 - - - PC14VAL - PC14 value - 20 - 1 - - - PC13MDE - PC13 mode - 19 - 1 - - - PC13VAL - RTC_ALARM output type/PC13 - value - 18 - 1 - - - DISPU - RTC_TAMPx pull-up disable - 15 - 1 - - - PRCH - RTC_TAMPx precharge - duration - 13 - 2 - - - FLT - RTC_TAMPx filter count - 11 - 2 - - - FREQ - Tamper sampling frequency - 8 - 3 - - - TPTS - Activate timestamp on tamper detection - event - 7 - 1 - - - TP1EG - Tamper 1 event trigger edge - 4 - 1 - - - TP1EN - Tamper 1 detection enable - 3 - 1 - - - TPIE - Tamper detection interrupt enable - 2 - 1 - - - TP0EG - Active level for RTC_TAMP1 - input - 1 - 1 - - - TP0EN - Tamper 0 event trigger edge - 0 - 1 - - - - - ALRM0SS - ALRM0SS - alarm 0 sub second register - 0x44 - 0x20 - read-write - 0x00000000 - - - MSKSSC - Mask control bit of SSC - 24 - 4 - - - SSC - Alarm sub second value - 0 - 15 - - - - - BKP0 - BKP0 - backup register - 0x50 - 0x20 - read-write - 0x00000000 - - - DATA - BKP data - 0 - 32 - - - - - BKP1 - BKP1 - backup register - 0x54 - 0x20 - read-write - 0x00000000 - - - DATA - BKP data - 0 - 32 - - - - - BKP2 - BKP2 - backup register - 0x58 - 0x20 - read-write - 0x00000000 - - - DATA - BKP data - 0 - 32 - - - - - BKP3 - BKP3 - backup register - 0x5C - 0x20 - read-write - 0x00000000 - - - DATA - BKP data - 0 - 32 - - - - - BKP4 - BKP4 - backup register - 0x60 - 0x20 - read-write - 0x00000000 - - - DATA - BKP data - 0 - 32 - - - - - - - SPI0 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI0 - 25 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - BDEN - Bidirectional enable - 15 - 1 - - - BDOEN - Bidirectional Transmit output enable - 14 - 1 - - - CRCEN - Hardware CRC calculation enable - 13 - 1 - - - CRCNT - CRC transfer next - 12 - 1 - - - FF16 - Data frame format - 11 - 1 - - - RO - Receive only - 10 - 1 - - - SWNSSEN - NSS Software Mode Selection - 9 - 1 - - - SWNSS - NSS Pin Selection In NSS Software Mode - 8 - 1 - - - LF - LSB First Mode - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - PSC - Master Clock Prescaler Selection - 3 - 3 - - - MSTMOD - Master Mode Enable - 2 - 1 - - - CKPL - Clock Polarity Selection - 1 - 1 - - - CKPH - Clock Phase Selection - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - TBEIE - Transmit Buffer Empty Interrupt Enable - 7 - 1 - - - RBNEIE - Receive Buffer Not Empty Interrupt Enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TMOD - SPI TI Mode Enable - 4 - 1 - - - NSSP - SPI NSS Pulse Mode Enable - 3 - 1 - - - NSSDRV - NSS output enable - 2 - 1 - - - DMATEN - Tx buffer DMA enable - 1 - 1 - - - DMAREN - Rx buffer DMA enable - 0 - 1 - - - - - STAT - STAT - status register - 0x08 - 0x20 - 0x0002 - - - FERR - Format Error - 8 - 1 - read-write - - - TRANS - Transmitting On-going Bit - 7 - 1 - read-only - - - RXORERR - Reception Overrun Error Bit - 6 - 1 - read-only - - - CONFERR - SPI Configuration error - 5 - 1 - read-only - - - CRCERR - SPI CRC Error Bit - 4 - 1 - read-write - - - TXURERR - Transmission underrun error bit - 3 - 1 - read-only - - - I2SCH - I2S channel side - 2 - 1 - read-only - - - TBE - Transmit Buffer Empty - 1 - 1 - read-only - - - RBNE - Receive Buffer Not Empty - 0 - 1 - read-only - - - - - DATA - DATA - data register - 0x0C - 0x20 - read-write - 0x0000 - - - DATA - Data register - 0 - 16 - - - - - CPCPOLY - CPCPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CRCPOLY - CRC polynomial register - 0 - 16 - - - - - RCRC - RCRC - RX CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - RX RCR register - 0 - 16 - - - - - TCRC - TCRC - TX CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Tx CRC register - 0 - 16 - - - - - I2SCTL - I2SCTL - I2S configuration register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SSEL - I2S mode selection - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - I2SOPMOD - I2S configuration mode - 8 - 2 - - - PCMSMOD - PCM frame synchronization - 7 - 1 - - - I2SSTD - I2S standard selection - 4 - 2 - - - CKPL - Idle state clock polarity - 3 - 1 - - - DTLEN - Data length to be - transferred - 1 - 2 - - - CHLEN - Channel length (number of bits per audio - channel) - 0 - 1 - - - - - I2SPSC - I2SPSC - I2S prescaler register - 0x20 - 0x20 - read-write - 0x0002 - - - MCKOEN - I2S_MCK output enable - 9 - 1 - - - OF - Odd factor for the - prescaler - 8 - 1 - - - DIV - Dividing factor for the prescaler - 0 - 8 - - - - - - - SPI1 - Serial Peripheral Interface 1 - 0x40003800 - - 0x0 - 0x400 - registers - - - SPI1 - 26 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - BDEN - Bidirectional enable - 15 - 1 - - - BDOEN - Bidirectional Transmit output enable - 14 - 1 - - - CRCEN - Hardware CRC calculation enable - 13 - 1 - - - CRCNT - CRC transfer next - 12 - 1 - - - CRCL - CRC length - 11 - 1 - - - RO - Receive only - 10 - 1 - - - SWNSSEN - NSS Software Mode Selection - 9 - 1 - - - SWNSS - NSS Pin Selection In NSS Software Mode - 8 - 1 - - - LF - LSB First Mode - 7 - 1 - - - SPIEN - SPI enable - 6 - 1 - - - PSC - Master Clock Prescaler Selection - 3 - 3 - - - MSTMOD - Master Mode Enable - 2 - 1 - - - CKPL - Clock Polarity Selection - 1 - 1 - - - CKPH - Clock Phase Selection - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - TXDMA_ODD - Odd bytes in TX DMA channel - 14 - 1 - - - RXDMA_ODD - Odd bytes in RX DMA channel - 13 - 1 - - - BYTEN - Byte access enable - 12 - 1 - - - DZ - Date size - 8 - 4 - - - TBEIE - Transmit Buffer Empty Interrupt Enable - 7 - 1 - - - RBNEIE - Receive Buffer Not Empty Interrupt Enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - TMOD - SPI TI Mode Enable - 4 - 1 - - - NSSP - SPI NSS Pulse Mode Enable - 3 - 1 - - - NSSDRV - NSS output enable - 2 - 1 - - - DMATEN - Tx buffer DMA enable - 1 - 1 - - - DMAREN - Rx buffer DMA enable - 0 - 1 - - - - - STAT - STAT - status register - 0x08 - 0x20 - 0x0002 - - - TXLVL - Tx FIFO level - 11 - 2 - read-only - - - RXLVL - Rx FIFO level - 9 - 2 - read-only - - - FERR - Format Error - 8 - 1 - read-write - - - TRANS - Transmitting On-going Bit - 7 - 1 - read-only - - - RXORERR - Reception Overrun Error Bit - 6 - 1 - read-only - - - CONFERR - SPI Configuration error - 5 - 1 - read-only - - - CRCERR - SPI CRC Error Bit - 4 - 1 - read-write - - - TBE - Transmit Buffer Empty - 1 - 1 - read-only - - - RBNE - Receive Buffer Not Empty - 0 - 1 - read-only - - - - - DATA - DATA - data register - 0x0C - 0x20 - read-write - 0x0000 - - - DATA - Data register - 0 - 16 - - - - - CPCPOLY - CPCPOLY - CRC polynomial register - 0x10 - 0x20 - read-write - 0x0007 - - - CRCPOLY - CRC polynomial register - 0 - 16 - - - - - RCRC - RCRC - RX CRC register - 0x14 - 0x20 - read-only - 0x0000 - - - RCRC - RX RCR register - 0 - 16 - - - - - TCRC - TCRC - TX CRC register - 0x18 - 0x20 - read-only - 0x0000 - - - TCRC - Tx CRC register - 0 - 16 - - - - - I2SCTL - I2SCTL - I2S configuration register - 0x1C - 0x20 - read-write - 0x0000 - - - I2SSEL - I2S mode selection - 11 - 1 - - - I2SEN - I2S Enable - 10 - 1 - - - I2SOPMOD - I2S configuration mode - 8 - 2 - - - PCMSMOD - PCM frame synchronization - 7 - 1 - - - I2SSTD - I2S standard selection - 4 - 2 - - - CKPL - Idle state clock polarity - 3 - 1 - - - DTLEN - Data length to be - transferred - 1 - 2 - - - CHLEN - Channel length (number of bits per audio - channel) - 0 - 1 - - - - - I2SPSC - I2SPSC - I2S prescaler register - 0x20 - 0x20 - read-write - 0x0002 - - - MCKOEN - I2S_MCK output enable - 9 - 1 - - - OF - Odd factor for the - prescaler - 8 - 1 - - - DIV - Dividing factor for the prescaler - 0 - 8 - - - - - QCTL - QCTL - SPI quad wird control register - 0x80 - 0x20 - read-write - 0000 - - - IO23_DRV - Drive IO2 and IO3 enable - 2 - 1 - - - QRD - Quad wire read select - 1 - 1 - - - QMOD - Quad wire mode enable - 0 - 1 - - - - - - - - SYSCFG - System configuration controller - SYSCFG - 0x40010000 - - 0x0 - 0x0400 - registers - - - - CFG0 - CFG0 - System configuration register 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - PB9_HCCE - PB9 pin high current capability enable - 19 - 1 - - - TIMER16_DMA_RMP - Timer 16 DMA request remapping enable - 12 - 1 - - - TIMER15_DMA_RMP - Timer 15 DMA request remapping enable - 11 - 1 - - - USART0_RX_DMA_RMP - USART0_RX DMA request remapping enable - 10 - 1 - - - USART0_TX_DMA_RMP - USART0_TX DMA request remapping enable - 9 - 1 - - - ADC_DMA_RMP - ADC DMA request remapping enable - 8 - 1 - - - PA11_PA12_RMP - PA11 and PA12 remapping bit for small packages - 4 - 1 - - - BOOT_MODE - Boot mode - 0 - 2 - read-only - - - - - EXTISS0 - EXTISS0 - EXTI sources selection register - 0 - 0x8 - 0x20 - read-write - 0x00000000 - - - EXTI3_SS - EXTI 3 sources selection - 12 - 4 - - - EXTI2_SS - EXTI 2 sources selection - 8 - 4 - - - EXTI1_SS - EXTI 1 sources selection - 4 - 4 - - - EXTI0_SS - EXTI 0 sources selection - 0 - 4 - - - - - EXTISS1 - EXTISS1 - EXTI sources selection register - 1 - 0xC - 0x20 - read-write - 0x00000000 - - - EXTI7_SS - EXTI 7 sources selection - 12 - 4 - - - EXTI6_SS - EXTI 6 sources selection - 8 - 4 - - - EXTI5_SS - EXTI 5 sources selection - 4 - 4 - - - EXTI4_SS - EXTI 4 sources selection - 0 - 4 - - - - - EXTISS2 - EXTISS2 - EXTI sources selection register - 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - EXTI11_SS - EXTI 11 sources selection - 12 - 4 - - - EXTI10_SS - EXTI 10 sources selection - 8 - 4 - - - EXTI9_SS - EXTI 9 sources selection - 4 - 4 - - - EXTI8_SS - EXTI 8 sources selection - 0 - 4 - - - - - EXTISS3 - EXTISS3 - EXTI sources selection register - 3 - 0x14 - 0x20 - read-write - 0x00000000 - - - EXTI15_SS - EXTI 15 sources selection - 12 - 4 - - - EXTI14_SS - EXTI 14 sources selection - 8 - 4 - - - EXTI13_SS - EXTI 13 sources selection - 4 - 4 - - - EXTI12_SS - EXTI 12 sources selection - 0 - 4 - - - - - CFG2 - CFG2 - System configuration register 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - SRAM_PCEF - SRAM parity check error flag - 8 - 1 - - - LVD_LOCK - LVD lock - 2 - 1 - - - SRAM_PARITY_ERROR_LOCK - SRAM parity check error lock - 1 - 1 - - - LOCKUP_LOCK - Cortex-M4 LOCKUP output lock - 0 - 1 - - - - - CPU_IRQ_LAT - CPU_IRQ_LAT - IRQ Latency register - 0x100 - 0x20 - read-write - 0x00000000 - - - IRQ_LATENCY - specifies the minimum number of cycles between an interrupt - 0 - 8 - - - - - - - TIMER0 - Advanced-timers - TIMER - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIMER0_BRK_UP_TRG_COM - 13 - - - TIMER0_CC - 14 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - CKDIV - Clock division - 8 - 2 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - CAM - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - SPM - One-pulse mode - 3 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - ISO3 - Idle state of channel 3 output - 14 - 1 - - - ISO2N - Idle state of channel 2 complementary output - 13 - 1 - - - ISO2 - Idle state of channel 2 output - 12 - 1 - - - ISO1N - Idle state of channel 1 complementary output - 11 - 1 - - - ISO1 - Idle state of channel 1 output - 10 - 1 - - - ISO0N - Idle state of channel 0 complementary output - 9 - 1 - - - ISO0 - Idle state of channel 0 output - 8 - 1 - - - TI0S - Channel 0 trigger input selection - 7 - 1 - - - MMC - Master mode control - 4 - 3 - - - DMAS - DMA request source selection - 3 - 1 - - - CCUC - Commutation control shadow register update control - 2 - 1 - - - CCSE - Commutation control shadow enable - 0 - 1 - - - - - SMCFG - SMCFG - slave mode configuration register - 0x08 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - SCM1 - Part of SMC for enable External clock mode1 - 14 - 1 - - - ETPSC - External trigger prescaler - 12 - 2 - - - ETFC - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TRGS - Trigger selection - 4 - 3 - - - OCRC - Trigger selection - 3 - 1 - - - SMC - Slave mode selection - 0 - 3 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - TRGDEN - Trigger DMA request enable - 14 - 1 - - - CMTDEN - Reserved - 13 - 1 - - - CH3DEN - Capture/Compare 3 DMA request - enable - 12 - 1 - - - CH2DEN - Capture/Compare 2 DMA request - enable - 11 - 1 - - - CH1DEN - Capture/Compare 1 DMA request - enable - 10 - 1 - - - CH0DEN - Capture/Compare 0 DMA request - enable - 9 - 1 - - - UPDEN - Update DMA request enable - 8 - 1 - - - BRKIE - Break interrupt enable - 7 - 1 - - - TRGIE - Trigger interrupt enable - 6 - 1 - - - CMTIE - COM interrupt enable - 5 - 1 - - - CH3IE - Capture/Compare 3 interrupt - enable - 4 - 1 - - - CH2IE - Capture/Compare 2 interrupt - enable - 3 - 1 - - - CH1IE - Capture/Compare 1 interrupt - enable - 2 - 1 - - - CH0IE - Capture/Compare 0 interrupt - enable - 1 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CH3OF - Channel 3 over capture flag - 12 - 1 - - - CH2OF - Channel 2 over capture flag - 11 - 1 - - - CH1OF - Channel 1 over capture flag - 10 - 1 - - - CH0OF - Channel 0 over capture flag - 9 - 1 - - - BRKIF - Break interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - CMTIF - COM interrupt flag - 5 - 1 - - - CH3IF - Capture/Compare 3 interrupt - flag - 4 - 1 - - - CH2IF - Capture/Compare 2 interrupt - flag - 3 - 1 - - - CH1IF - Capture/Compare 1 interrupt - flag - 2 - 1 - - - CH0IF - Capture/compare 0 interrupt - flag - 1 - 1 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - Software event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BRKG - Break event generation - 7 - 1 - - - TRGG - Trigger event generation - 6 - 1 - - - CMTG - Channel commutation event generation - 5 - 1 - - - CH3G - Channel 3's capture or compare event generation - 4 - 1 - - - CH2G - Channel 2's capture or compare event generation - 3 - 1 - - - CH1G - Channel 1's capture or compare event generation - 2 - 1 - - - CH0G - Channel 0's capture or compare event generation - 1 - 1 - - - UPG - Update event generation - 0 - 1 - - - - - CHCTL0_Output - CHCTL0_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x0000 - - - CH1COMCEN - Channel 1 output compare clear enable - 15 - 1 - - - CH1COMCTL - Channel 1 compare output control - 12 - 3 - - - CH1COMSEN - Channel 1 output compare shadow enable - 11 - 1 - - - CH1COMFEN - Channel 1 output compare fast enable - 10 - 1 - - - CH1MS - Channel 1 mode selection - 8 - 2 - - - CH0COMCEN - Channel 0 output compare clear enable - 7 - 1 - - - CH0COMCTL - Channel 0 compare output control - 4 - 3 - - - CH0COMSEN - Channel 0 compare output shadow enable - 3 - 1 - - - CH0COMFEN - Channel 0 output compare fast enable - 2 - 1 - - - CH0MS - Channel 0 I/O mode selection - 0 - 2 - - - - - CHCTL0_Input - CHCTL0_Input - capture/compare mode register 0 (input - mode) - CHCTL0_Output - 0x18 - 0x20 - read-write - 0x0000 - - - CH1CAPFLT - Channel 1 input capture filter control - 12 - 4 - - - CH1CAPPSC - Channel 1 input capture prescaler - 10 - 2 - - - CH1MS - Channel 1 mode selection - 8 - 2 - - - CH0CAPFLT - Channel 0 input capture filter control - 4 - 4 - - - CH0CAPPSC - Channel 0 input capture prescaler - 2 - 2 - - - CH0MS - Channel 0 mode selection - 0 - 2 - - - - - CHCTL1_Output - CHCTL1_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x0000 - - - CH3COMCEN - Channel 3 output compare clear enable - 15 - 1 - - - CH3COMCTL - Channel 3 compare output control - 12 - 3 - - - CH3COMSEN - Channel 3 output compare shadow enable - 11 - 1 - - - CH3COMFEN - Channel 3 output compare fast enable - 10 - 1 - - - CH3MS - Channel 3 mode selection - 8 - 2 - - - CH2COMCEN - Channel 2 output compare clear enable - 7 - 1 - - - CH2COMCTL - Channel 2 compare output control - 4 - 3 - - - CH2COMSEN - Channel 2 compare output shadow enable - 3 - 1 - - - CH2COMFEN - Channel 2 output compare fast enable - 2 - 1 - - - CH2MS - Channel 2 I/O mode selection - 0 - 2 - - - - - CHCTL1_Input - CHCTL1_Input - capture/compare mode register 1 (input - mode) - CHCTL1_Output - 0x1C - 0x20 - read-write - 0x0000 - - - CH3CAPFLT - Channel 3 input capture filter control - 12 - 4 - - - CH3CAPPSC - Channel 3 input capture prescaler - 10 - 2 - - - CH3MS - Channel 3 mode selection - 8 - 2 - - - CH2CAPFLT - Input capture 2 filter - 4 - 4 - - - CH2CAPPSC - Input capture 2 prescaler - 2 - 2 - - - CH2MS - Capture/compare 2 - selection - 0 - 2 - - - - - CHCTL2 - CHCTL2 - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CH3P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CH3EN - Capture/Compare 3 output - enable - 12 - 1 - - - CH2NP - Capture/Compare 2 output - Polarity - 11 - 1 - - - CH2NEN - Capture/Compare 2 complementary output - enable - 10 - 1 - - - CH2P - Capture/Compare 2 output - Polarity - 9 - 1 - - - CH2EN - Capture/Compare 2 output - enable - 8 - 1 - - - CH1NP - Capture/Compare 1 output - Polarity - 7 - 1 - - - CH1NEN - Capture/Compare 1 complementary output - enable - 6 - 1 - - - CH1P - Capture/Compare 1 output - Polarity - 5 - 1 - - - CH1EN - Capture/Compare 1 output - enable - 4 - 1 - - - CH0NP - Capture/Compare 0 output - Polarity - 3 - 1 - - - CH0NEN - Capture/Compare 0 complementary output - enable - 2 - 1 - - - CH0P - Capture/Compare 0 output - Polarity - 1 - 1 - - - CH0EN - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x0000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x0000 - - - CARL - Counter auto reload value - 0 - 16 - - - - - CREP - CREP - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - CREP - Repetition counter value - 0 - 8 - - - - - CH0CV - CH0CV - capture/compare register 0 - 0x34 - 0x20 - read-write - 0x0000 - - - CH0VAL - Capture/Compare 0 value - 0 - 16 - - - - - CH1CV - CH1CV - capture/compare register 1 - 0x38 - 0x20 - read-write - 0x0000 - - - CH1VAL - Capture/Compare 1 value - 0 - 16 - - - - - CH2CV - CH2CV - capture/compare register 2 - 0x3C - 0x20 - read-write - 0x0000 - - - CH2VAL - Capture/Compare 2 value - 0 - 16 - - - - - CH3CV - CH3CV - capture/compare register 3 - 0x40 - 0x20 - read-write - 0x0000 - - - CH3VAL - Capture/Compare 3 value - 0 - 16 - - - - - CCHP - CCHP - channel complementary protection register - 0x44 - 0x20 - read-write - 0x0000 - - - POEN - Main output enable - 15 - 1 - - - OAEN - Automatic output enable - 14 - 1 - - - BRKP - Break polarity - 13 - 1 - - - BRKEN - Break enable - 12 - 1 - - - ROS - Off-state selection for Run - mode - 11 - 1 - - - IOS - Off-state selection for Idle - mode - 10 - 1 - - - PROT - Lock configuration - 8 - 2 - - - DTCFG - Dead-time generator setup - 0 - 8 - - - - - DMACFG - DMACFG - DMA configuration register - 0x48 - 0x20 - read-write - 0x0000 - - - DMATC - DMA transfer count - 8 - 5 - - - DMATA - DMA transfer access start address - 0 - 5 - - - - - DMATB - DMATB - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMATB - DMA register for burst - accesses - 0 - 16 - - - - - CFG - CFG - Configuration register - 0xFC - 0x20 - read-write - 0x0000 - - - CHVSEL - Write CHxVAL register selection - 1 - 1 - - - OUTSEL - The output value selection - 0 - 1 - - - - - - - TIMER2 - General-purpose-timers - TIMER - 0x40000400 - - 0x0 - 0x400 - registers - - - TIMER2 - 16 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - CKDIV - Clock division - 8 - 2 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - CAM - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - SPM - One-pulse mode - 3 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - TI0S - TI0 selection - 7 - 1 - - - MMC - Master mode selection - 4 - 3 - - - DMAS - Capture/compare DMA - selection - 3 - 1 - - - - - SMCFG - SMCFG - slave mode control register - 0x08 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - SMC1 - External clock enable - 14 - 1 - - - ETPSC - External trigger prescaler - 12 - 2 - - - ETFC - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TRGS - Trigger selection - 4 - 3 - - - OCRC - OCREF clear source selection - 3 - 1 - - - SMC - Slave mode selection - 0 - 3 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - TRGDEN - Trigger DMA request enable - 14 - 1 - - - CH3DEN - Capture/Compare 3 DMA request - enable - 12 - 1 - - - CH2DEN - Capture/Compare 2 DMA request - enable - 11 - 1 - - - CH1DEN - Capture/Compare 1 DMA request - enable - 10 - 1 - - - CH0DEN - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UPDEN - Update DMA request enable - 8 - 1 - - - TRGIE - Trigger interrupt enable - 6 - 1 - - - CH3IE - Capture/Compare 3 interrupt - enable - 4 - 1 - - - CH2IE - Capture/Compare 2 interrupt - enable - 3 - 1 - - - CH1IE - Capture/Compare 1 interrupt - enable - 2 - 1 - - - CH0IE - Capture/Compare 0 interrupt - enable - 1 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - interrupt flag register - 0x10 - 0x20 - read-write - 0x0000 - - - CH3OF - Capture/Compare 3 overcapture - flag - 12 - 1 - - - CH2OF - Capture/Compare 2 overcapture - flag - 11 - 1 - - - CH1OF - Capture/compare 1 overcapture - flag - 10 - 1 - - - CH0OF - Capture/Compare 0 overcapture - flag - 9 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - CH3IF - Capture/Compare 3 interrupt - flag - 4 - 1 - - - CH2IF - Capture/Compare 2 interrupt - flag - 3 - 1 - - - CH1IF - Capture/Compare 1 interrupt - flag - 2 - 1 - - - CH0IF - Capture/compare 0 interrupt - flag - 1 - 1 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TRGG - Trigger generation - 6 - 1 - - - CH3G - Capture/compare 3 - generation - 4 - 1 - - - CH2G - Capture/compare 2 - generation - 3 - 1 - - - CH1G - Capture/compare 1 - generation - 2 - 1 - - - CH0G - Capture/compare 0 - generation - 1 - 1 - - - UPG - Update generation - 0 - 1 - - - - - CHCTL0_Output - CHCTL0_Output - capture/compare mode register 0 (output - mode) - 0x18 - 0x20 - read-write - 0x0000 - - - CH1COMCEN - Output compare 1 clear - enable - 15 - 1 - - - CH1COMCTL - Output compare 1 mode - 12 - 3 - - - CH1COMSEN - Output compare 1 preload - enable - 11 - 1 - - - CH1COMFEN - Output compare 1 fast - enable - 10 - 1 - - - CH1MS - Capture/Compare 1 - selection - 8 - 2 - - - CH0COMCEN - Output compare 0 clear - enable - 7 - 1 - - - CH0COMCTL - Output compare 0 mode - 4 - 3 - - - CH0COMSEN - Output compare 0 preload - enable - 3 - 1 - - - CH0COMFEN - Output compare 0 fast - enable - 2 - 1 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL0_Input - CHCTL0_Input - capture/compare mode register 0 (input - mode) - CHCTL0_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - CH1CAPFLT - Input capture 1 filter - 12 - 4 - - - CH1CAPPSC - Input capture 1 prescaler - 10 - 2 - - - CH1MS - Capture/compare 1 - selection - 8 - 2 - - - CH0CAPFLT - Input capture 0 filter - 4 - 4 - - - CH0CAPPSC - Input capture 0 prescaler - 2 - 2 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL1_Output - CHCTL1_Output - capture/compare mode register 1 (output - mode) - 0x1C - 0x20 - read-write - 0x0000 - - - CH3COMCEN - Output compare 3 clear - enable - 15 - 1 - - - CH3COMCTL - Output compare 3 mode - 12 - 3 - - - CH3COMSEN - Output compare 3 preload - enable - 11 - 1 - - - CH3COMFEN - Output compare 3 fast - enable - 10 - 1 - - - CH3MS - Capture/Compare 3 - selection - 8 - 2 - - - CH2COMCEN - Output compare 2 clear - enable - 7 - 1 - - - CH2COMCTL - Output compare 2 mode - 4 - 3 - - - CH2COMSEN - Output compare 2 preload - enable - 3 - 1 - - - CH2COMFEN - Output compare 2 fast - enable - 2 - 1 - - - CH2MS - Capture/Compare 2 - selection - 0 - 2 - - - - - CHCTL1_Input - CHCTL1_Input - capture/compare mode register 1 (input - mode) - CHCTL1_Output - 0x1C - 0x20 - read-write - 0x0000 - - - CH3CAPFLT - Input capture 3 filter - 12 - 4 - - - CH3CAPPSC - Input capture 3 prescaler - 10 - 2 - - - CH3MS - Capture/Compare 3 - selection - 8 - 2 - - - CH2CAPFLT - Input capture 2 filter - 4 - 4 - - - CH2CAPPSC - Input capture 2 prescaler - 2 - 2 - - - CH2MS - Capture/Compare 2 - selection - 0 - 2 - - - - - CHCTL2 - CHCTL2 - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CH3NP - Capture/Compare 3 output - Polarity - 15 - 1 - - - CH3P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CH3EN - Capture/Compare 3 output - enable - 12 - 1 - - - CH2NP - Capture/Compare 2 output - Polarity - 11 - 1 - - - CH2P - Capture/Compare 2 output - Polarity - 9 - 1 - - - CH2EN - Capture/Compare 2 output - enable - 8 - 1 - - - CH1NP - Capture/Compare 1 output - Polarity - 7 - 1 - - - CH1P - Capture/Compare 1 output - Polarity - 5 - 1 - - - CH1EN - Capture/Compare 1 output - enable - 4 - 1 - - - CH0NP - Capture/Compare 0 output - Polarity - 3 - 1 - - - CH0P - Capture/Compare 0 output - Polarity - 1 - 1 - - - CH0EN - Capture/Compare 0 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x0000 - - - CARL - Low Auto-reload value - 0 - 16 - - - - - CH0CV - CH0CV - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CH0VAL - Low Capture/Compare 1 - value - 0 - 16 - - - - - CH1CV - CH1CV - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CH1VAL - Low Capture/Compare 2 - value - 0 - 16 - - - - - CH2CV - CH2CV - capture/compare register 2 - 0x3C - 0x20 - read-write - 0x00000000 - - - CH2VAL - High Capture/Compare value (TIM2 - only) - 0 - 16 - - - - - CH3CV - CH3CV - capture/compare register 3 - 0x40 - 0x20 - read-write - 0x00000000 - - - CH3VAL - High Capture/Compare value (TIM2 - only) - 0 - 16 - - - - - DMACFG - DMACFG - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DMATC - DMA burst length - 8 - 5 - - - DMATA - DMA base address - 0 - 5 - - - - - DMATB - DMATB - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMATB - DMA register for burst - accesses - 0 - 16 - - - - - CFG - CFG - Configuration - 0xFC - 0x20 - read-write - 0x0000 - - - CHVSEL - Write CHxVAL register selection - 1 - 1 - - - - - - - TIMER5 - Basic-timers - TIMER - 0x40001000 - - 0x0 - 0x400 - registers - - - TIMER5 - 17 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - SPM - One-pulse mode - 3 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - MMC - Master mode selection - 4 - 3 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - UPDEN - Update DMA request enable - 8 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - status register - 0x10 - 0x20 - read-write - 0x0000 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - UPG - Update generation - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - Low counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - CARL - Low Auto-reload value - 0 - 16 - - - - - - - TIMER13 - General-purpose-timers - TIMER - 0x40002000 - - 0x0 - 0x400 - registers - - - TIMER13 - 19 - - - - CTL0 - CTL0 - control register 1 - 0x00 - 0x20 - read-write - 0x0000 - - - CKDIV - Clock division - 8 - 2 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - CH0IE - Capture/Compare 0 interrupt - enable - 1 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - interrupt flag register - 0x10 - 0x20 - read-write - 0x0000 - - - CH0OF - Capture/Compare 0 overcapture - flag - 9 - 1 - - - CH0IF - Capture/compare 0 interrupt - flag - 1 - 1 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - CH0G - Capture/compare 0 - generation - 1 - 1 - - - UPG - Update generation - 0 - 1 - - - - - CHCTL0_Output - CHCTL0_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x0000 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - CH0COMFEN - Output compare 0 fast - enable - 2 - 1 - - - CH0COMSEN - Output Compare 0 preload - enable - 3 - 1 - - - CH0COMCTL - Output Compare 0 mode - 4 - 3 - - - - - CHCTL0_Input - CHCTL0_Input - capture/compare mode register (input - mode) - CHCTL0_Output - 0x18 - 0x20 - read-write - 0x0000 - - - CH0CAPFLT - Input capture 0 filter - 4 - 4 - - - CH0CAPPSC - Input capture 0 prescaler - 2 - 2 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL2 - CHCTL2 - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CH0NP - Capture/Compare 0 output - Polarity - 3 - 1 - - - CH0P - Capture/Compare 0 output - Polarity - 1 - 1 - - - CH0EN - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x0000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x0000 - - - CARL - Auto-reload value - 0 - 16 - - - - - CH0CV - CH0CV - capture/compare register 0 - 0x34 - 0x20 - read-write - 0x0000 - - - CH0VAL - Capture/Compare 1 value - 0 - 16 - - - - - IRMP - IRMP - channel input remap register - 0x50 - 0x20 - read-write - 0x0000 - - - CI0_RMP - Timer input 0 remap - 0 - 2 - - - - - CFG - CFG - configuration register - 0xFC - 0x20 - read-write - 0x0000 - - - CHVSEL - Write CHxVAL register selection - 1 - 1 - - - - - - - TIMER14 - General-purpose-timers - TIMER - 0x40014000 - - 0x0 - 0x400 - registers - - - TIMER14 - 20 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - CKDIV - Clock division - 8 - 2 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - SPM - One-pulse mode - 3 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x4 - 0x20 - read-write - 0x0000 - - - ISO1 - Output Idle state 1 - 10 - 1 - - - ISO0N - Output Idle state 0 - 9 - 1 - - - ISO0 - Output Idle state 0 - 8 - 1 - - - MMC - Master mode selection - 4 - 3 - - - DMAS - Capture/compare DMA - selection - 3 - 1 - - - CCUC - Capture/compare control update - selection - 2 - 1 - - - CCSE - Capture/compare preloaded - control - 0 - 1 - - - - - SMCFG - SMCFG - slave mode configuration register - 0x08 - 0x20 - read-write - 0x0000 - - - MSM - Master/Slave mode - 7 - 1 - - - TRGS - Trigger selection - 4 - 3 - - - SMC - Slave mode selection - 0 - 3 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - TRGDEN - Trigger DMA request enable - 14 - 1 - - - CMTDEN - Commutation DMA request enable - 13 - 1 - - - CH1DEN - Capture/Compare 1 DMA request - enable - 10 - 1 - - - CH0DEN - Capture/Compare 0 DMA request - enable - 9 - 1 - - - UPDEN - Update DMA request enable - 8 - 1 - - - BRKIE - Break interrupt enable - 7 - 1 - - - TRGIE - Trigger interrupt enable - 6 - 1 - - - CMTIE - COM interrupt enable - 5 - 1 - - - CH1IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CH0IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - interrupt flag register - 0x10 - 0x20 - read-write - 0x0000 - - - CH1OF - Capture/compare 1 overcapture - flag - 10 - 1 - - - CH0OF - Capture/Compare 0 overcapture - flag - 9 - 1 - - - BRKIF - Break interrupt flag - 7 - 1 - - - TRGIF - Trigger interrupt flag - 6 - 1 - - - CMTIF - COM interrupt flag - 5 - 1 - - - CH1IF - Capture/Compare 1 interrupt - flag - 2 - 1 - - - CH0IF - Capture/compare 0 interrupt - flag - 1 - 1 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BRKG - Break generation - 7 - 1 - - - TRGG - Trigger generation - 6 - 1 - - - CMTG - Capture/Compare control update - generation - 5 - 1 - - - CH1G - Capture/compare 1 - generation - 2 - 1 - - - CH0G - Capture/compare 0 - generation - 1 - 1 - - - UPG - Update generation - 0 - 1 - - - - - CHCTL0_Output - CHCTL0_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - CH1COMCTL - Output Compare 1 mode - 12 - 3 - - - CH1COMSEN - Output Compare 1 preload - enable - 11 - 1 - - - CH1COMFEN - Output Compare 1 fast - enable - 10 - 1 - - - CH1MS - Capture/Compare 1 - selection - 8 - 2 - - - CH0COMCTL - Output Compare 0 mode - 4 - 3 - - - CH0COMSEN - Output Compare 0 preload - enable - 3 - 1 - - - CH0COMFEN - Output Compare 0 fast - enable - 2 - 1 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL0_Input - CHCTL0_Input - capture/compare mode register 0 (input - mode) - CHCTL0_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - CH1CAPFLT - Input capture 1 filter - 12 - 4 - - - CH1CAPPSC - Input capture 1 prescaler - 10 - 2 - - - CH1MS - Capture/Compare 1 - selection - 8 - 2 - - - CH0CAPFLT - Input capture 0 filter - 4 - 4 - - - CH0CAPPSC - Input capture 0 prescaler - 2 - 2 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL2 - CHCTL2 - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CH1NP - Capture/Compare 1 output - Polarity - 7 - 1 - - - CH1P - Capture/Compare 1 output - Polarity - 5 - 1 - - - CH1EN - Capture/Compare 1 output - enable - 4 - 1 - - - CH0NP - Capture/Compare 0 output - Polarity - 3 - 1 - - - CH0NEN - Capture/Compare 0 complementary output - enable - 2 - 1 - - - CH0P - Capture/Compare 0 output - Polarity - 1 - 1 - - - CH0EN - Capture/Compare 0 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x0000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - CARL - Auto-reload value - 0 - 16 - - - - - CREP - CREP - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - CREP - Repetition counter value - 0 - 8 - - - - - CH0CV - CH0CV - capture/compare register 0 - 0x34 - 0x20 - read-write - 0x00000000 - - - CH0VAL - Capture/Compare 0 value - 0 - 16 - - - - - CH1CV - CH1CV - capture/compare register 1 - 0x38 - 0x20 - read-write - 0x00000000 - - - CH1VAL - Capture/Compare 1 value - 0 - 16 - - - - - CCHP - CCHP - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - POEN - Main output enable - 15 - 1 - - - OAEN - Automatic output enable - 14 - 1 - - - BRKP - Break polarity - 13 - 1 - - - BRKEN - Break enable - 12 - 1 - - - ROS - Off-state selection for Run - mode - 11 - 1 - - - IOS - Off-state selection for Idle - mode - 10 - 1 - - - PROT - complementary register protect control - 8 - 2 - - - DTCFG - Dead-time generator configure - 0 - 8 - - - - - DMACFG - DMACFG - DMA configuration register - 0x48 - 0x20 - read-write - 0x0000 - - - DMATC - DMA burst length - 8 - 5 - - - DMATA - DMA base address - 0 - 5 - - - - - DMATB - DMATB - DMA transfer buffer register - 0x4C - 0x20 - read-write - 0x0000 - - - DMATB - DMA register for burst - accesses - 0 - 16 - - - - - CFG - CFG - configuration register - 0xFC - 0x20 - read-write - 0x0000 - - - CHVSEL - Write CHxVAL register selection - 1 - 1 - - - OUTSEL - The output value selection - 0 - 1 - - - - - - - TIMER15 - General-purpose-timers - TIMER - 0x40014400 - - 0x0 - 0x400 - registers - - - TIMER15 - 21 - - - - CTL0 - CTL0 - control register 0 - 0x0 - 0x20 - read-write - 0x0000 - - - CKDIV - Clock division - 8 - 2 - - - ARSE - Auto-reload preload enable - 7 - 1 - - - SPM - One-pulse mode - 3 - 1 - - - UPS - Update request source - 2 - 1 - - - UPDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CTL1 - CTL1 - control register 1 - 0x04 - 0x20 - read-write - 0x0000 - - - ISO0N - Output Idle state 0 - 9 - 1 - - - ISO0 - Output Idle state 0 - 8 - 1 - - - DMAS - Capture/compare DMA - selection - 3 - 1 - - - CCUC - Capture/compare control update - selection - 2 - 1 - - - CCSE - Capture/compare preloaded - control - 0 - 1 - - - - - DMAINTEN - DMAINTEN - DMA/Interrupt enable register - 0x0C - 0x20 - read-write - 0x0000 - - - CH0DEN - Capture/Compare 0 DMA request - enable - 9 - 1 - - - UPDEN - Update DMA request enable - 8 - 1 - - - BRKIE - Break interrupt enable - 7 - 1 - - - CMTIE - COM interrupt enable - 5 - 1 - - - CH0IE - Capture/Compare 0 interrupt - enable - 1 - 1 - - - UPIE - Update interrupt enable - 0 - 1 - - - - - INTF - INTF - interrupt flag register - 0x10 - 0x20 - read-write - 0x0000 - - - CH0OF - Capture/Compare 0 overcapture - flag - 9 - 1 - - - BRKIF - Break interrupt flag - 7 - 1 - - - CMTIF - COM interrupt flag - 5 - 1 - - - CH0IF - Capture/compare 0 interrupt - flag - 1 - 1 - - - UPIF - Update interrupt flag - 0 - 1 - - - - - SWEVG - SWEVG - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BRKG - Break generation - 7 - 1 - - - CMTG - Capture/Compare control update - generation - 5 - 1 - - - CH0G - Capture/compare 0 - generation - 1 - 1 - - - UPG - Update generation - 0 - 1 - - - - - CHCTL0_Output - CHCTL0_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - CH0COMCTL - Output Compare 0 mode - 4 - 3 - - - CH0COMSEN - Output Compare 0 preload - enable - 3 - 1 - - - CH0COMFEN - Output Compare 0 fast - enable - 2 - 1 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL0_Input - CHCTL0_Input - capture/compare mode register 0 (input - mode) - CHCTL0_Output - 0x18 - 0x20 - read-write - 0x0000 - - - CH0CAPFLT - Input capture 0 filter - 4 - 4 - - - CH0CAPPSC - Input capture 0 prescaler - 2 - 2 - - - CH0MS - Capture/Compare 0 - selection - 0 - 2 - - - - - CHCTL2 - CHCTL2 - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CH0NP - Capture/Compare 0 output - Polarity - 3 - 1 - - - CH0NEN - Capture/Compare 0 complementary output - enable - 2 - 1 - - - CH0P - Capture/Compare 0 output - Polarity - 1 - 1 - - - CH0EN - Capture/Compare 0 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x0000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - CAR - CAR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - CARL - Auto-reload value - 0 - 16 - - - - - CREP - CREP - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - CREP - Repetition counter value - 0 - 8 - - - - - CH0CV - CH0CV - capture/compare register 0 - 0x34 - 0x20 - read-write - 0x0000 - - - CH0VAL - Capture/Compare 0 value - 0 - 16 - - - - - CCHP - CCHP - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - POEN - Main output enable - 15 - 1 - - - OAEN - Automatic output enable - 14 - 1 - - - BRKP - Break polarity - 13 - 1 - - - BRKEN - Break enable - 12 - 1 - - - ROS - Off-state selection for Run - mode - 11 - 1 - - - IOS - Off-state selection for Idle - mode - 10 - 1 - - - PROT - complementary register protect control - 8 - 2 - - - DTCFG - Dead-time generator setup - 0 - 8 - - - - - DMACFG - DMACFG - DMA configuration register - 0x48 - 0x20 - read-write - 0x0000 - - - DMATC - DMA transfer count - 8 - 5 - - - DMATA - DMA transfer access start address - 0 - 5 - - - - - DMATB - DMATB - DMA transfer buffer register - 0x4C - 0x20 - read-write - 0x0000 - - - DMATB - DMA register for burst - accesses - 0 - 16 - - - - - CFG - CFG - configuration register - 0xFC - 0x20 - read-write - 0x0000 - - - OUTSEL - The output value selection - 0 - 1 - - - CHVSEL - Write CHxVAL register selection - 1 - 1 - - - - - - - TIMER16 - 0x40014800 - - TIMER16 - 22 - - - - USART0 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART0 - 27 - - - - CTL0 - CTL0 - Control register 0 - 0x0 - 0x20 - read-write - 0x00000000 - - - EBIE - End of Block interrupt - enable - 27 - 1 - - - RTIE - Receiver timeout interrupt - enable - 26 - 1 - - - DEA - Driver Enable assertion - time - 21 - 5 - - - DED - Driver Enable deassertion - time - 16 - 5 - - - OVSMOD - Oversampling mode - 15 - 1 - - - AMIE - Character match interrupt - enable - 14 - 1 - - - MEN - Mute mode enable - 13 - 1 - - - WL - Word length - 12 - 1 - - - WM - Receiver wakeup method - 11 - 1 - - - PCEN - Parity control enable - 10 - 1 - - - PM - Parity selection - 9 - 1 - - - PERRIE - PE interrupt enable - 8 - 1 - - - TBEIE - interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RBNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TEN - Transmitter enable - 3 - 1 - - - REN - Receiver enable - 2 - 1 - - - UESM - USART enable in Stop mode - 1 - 1 - - - UEN - USART enable - 0 - 1 - - - - - CTL1 - CTL1 - Control register 1 - 0x4 - 0x20 - read-write - 0x00000000 - - - ADDR - Address of the USART node - 24 - 8 - - - RTEN - Receiver timeout enable - 23 - 1 - - - ABDM - Auto baud rate mode - 21 - 2 - - - ABDEN - Auto baud rate enable - 20 - 1 - - - MSBF - Most significant bit first - 19 - 1 - - - DINV - Binary data inversion - 18 - 1 - - - TINV - TX pin active level - inversion - 17 - 1 - - - RINV - RX pin active level - inversion - 16 - 1 - - - STRP - Swap TX/RX pins - 15 - 1 - - - LMEN - LIN mode enable - 14 - 1 - - - STB - STOP bits - 12 - 2 - - - CKEN - Clock enable - 11 - 1 - - - CPL - Clock polarity - 10 - 1 - - - CPH - Clock phase - 9 - 1 - - - CLEN - Last bit clock pulse - 8 - 1 - - - LBDIE - LIN break detection interrupt - enable - 6 - 1 - - - LBLEN - LIN break detection length - 5 - 1 - - - ADDM - 7-bit Address Detection/4-bit Address - Detection - 4 - 1 - - - - - CTL2 - CTL2 - Control register 2 - 0x8 - 0x20 - read-write - 0x00000000 - - - WUIE - Wakeup from Stop mode interrupt - enable - 22 - 1 - - - WUM - Wakeup from Stop mode interrupt flag - selection - 20 - 2 - - - SCRTNUM - Smartcard auto-retry count - 17 - 3 - - - DEP - Driver enable polarity - selection - 15 - 1 - - - DEM - Driver enable mode - 14 - 1 - - - DDRE - DMA Disable on Reception - Error - 13 - 1 - - - OVRD - Overrun Disable - 12 - 1 - - - OSB - One sample bit method - enable - 11 - 1 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSEN - CTS enable - 9 - 1 - - - RTSEN - RTS enable - 8 - 1 - - - DENT - DMA enable transmitter - 7 - 1 - - - DENR - DMA enable receiver - 6 - 1 - - - SCEN - Smartcard mode enable - 5 - 1 - - - NKEN - Smartcard NACK enable - 4 - 1 - - - HDEN - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - ERRIE - Error interrupt enable - 0 - 1 - - - - - BAUD - BAUD - Baud rate register - 0xC - 0x20 - read-write - 0x00000000 - - - BRR_INT - integer of baud-rate divider - 4 - 12 - - - BRR_FRA - integer of baud-rate divider - 0 - 4 - - - - - GP - GP - Guard time and prescaler - register - 0x10 - 0x20 - read-write - 0x00000000 - - - GUAT - Guard time value - 8 - 8 - - - PSC - Prescaler value - 0 - 8 - - - - - RT - RT - Receiver timeout register - 0x14 - 0x20 - read-write - 0x00000000 - - - BL - Block Length - 24 - 8 - - - RT - Receiver timeout value - 0 - 24 - - - - - CMD - CMD - Request register - 0x18 - 0x20 - write-only - 0x00000000 - - - TXFCMD - Transmit data flush - request - 4 - 1 - - - RXFCMD - Receive data flush request - 3 - 1 - - - MMCMD - Mute mode request - 2 - 1 - - - SBKCMD - Send break request - 1 - 1 - - - ABDCMD - Auto baud rate request - 0 - 1 - - - - - STAT - STAT - Interrupt & status - register - 0x1C - 0x20 - read-only - 0x000000C0 - - - REA - Receive enable acknowledge - flag - 22 - 1 - - - TEA - Transmit enable acknowledge - flag - 21 - 1 - - - WUF - Wakeup from Stop mode flag - 20 - 1 - - - RWU - Receiver wakeup from Mute - mode - 19 - 1 - - - SBF - Send break flag - 18 - 1 - - - AMF - character match flag - 17 - 1 - - - BSY - Busy flag - 16 - 1 - - - ABDF - Auto baud rate flag - 15 - 1 - - - ABDE - Auto baud rate error - 14 - 1 - - - EBF - End of block flag - 12 - 1 - - - RTF - Receiver timeout - 11 - 1 - - - CTS - CTS flag - 10 - 1 - - - CTSF - CTS interrupt flag - 9 - 1 - - - LBDF - LIN break detection flag - 8 - 1 - - - TBE - Transmit data register - empty - 7 - 1 - - - TC - Transmission complete - 6 - 1 - - - RBNE - Read data register not - empty - 5 - 1 - - - IDLEF - Idle line detected - 4 - 1 - - - ORERR - Overrun error - 3 - 1 - - - NERR - Noise detected flag - 2 - 1 - - - FERR - Framing error - 1 - 1 - - - PERR - Parity error - 0 - 1 - - - - - INTC - INTC - Interrupt flag clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - WUC - Wakeup from Stop mode clear - flag - 20 - 1 - - - AMC - Character match clear flag - 17 - 1 - - - EBC - End of timeout clear flag - 12 - 1 - - - RTC - Receiver timeout clear - flag - 11 - 1 - - - CTSC - CTS clear flag - 9 - 1 - - - LBDC - LIN break detection clear - flag - 8 - 1 - - - TCC - Transmission complete clear - flag - 6 - 1 - - - IDLEC - Idle line detected clear - flag - 4 - 1 - - - OREC - Overrun error clear flag - 3 - 1 - - - NEC - Noise detected clear flag - 2 - 1 - - - FEC - Framing error clear flag - 1 - 1 - - - PEC - Parity error clear flag - 0 - 1 - - - - - RDATA - RDATA - Receive data register - 0x24 - 0x20 - read-only - 0x00000000 - - - RDATA - Receive data value - 0 - 9 - - - - - TDATA - TDATA - Transmit data register - 0x28 - 0x20 - read-write - 0x00000000 - - - TDATA - Transmit data value - 0 - 9 - - - - - CHC - CHC - coherence control register - 0xC0 - 0x20 - read-write - 0x00000000 - - - EPERR - Early parity error flag - 8 - 1 - - - HCM - Hardware flow control coherence mode - 0 - 1 - - - - - RFCS - RFCS - USART receive FIFO control and status register - 0xD0 - 0x20 - 0x00000400 - - - RFFINT - Receive FIFO full interrupt flag - 15 - 1 - read-write - - - RFCNT - Receive FIFO count number - 12 - 3 - read-only - - - RFF - Receive FIFO full flag - 11 - 1 - read-only - - - RFE - Receive FIFO empty flag - 10 - 1 - read-only - - - RFFIE - Receive FIFO full interrupt enable - 9 - 1 - read-write - - - RFEN - Receive FIFO enable - 8 - 1 - read-write - - - ELNACK - Early NKEN when smartcard mode is selected - 0 - 1 - read-write - - - - - - - USART1 - 0x40004400 - - USART1 - 28 - - - - WWDGT - Window watchdog timer - WWDGT - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDGT - 0 - - - - CTL - CTL - Control register - 0x0 - 0x20 - read-write - 0x0000007F - - - WDGTEN - Activation bit - 7 - 1 - - - CNT - 7-bit counter - 0 - 7 - - - - - CFG - CFG - Configuration register - 0x04 - 0x20 - read-write - 0x0000007F - - - EWIE - Early wakeup interrupt - 9 - 1 - - - PSC - Prescaler - 7 - 2 - - - WIN - 7-bit window value - 0 - 7 - - - - - STAT - STAT - Status register - 0x08 - 0x20 - read-write - 0x00000000 - - - EWIF - Early wakeup interrupt - flag - 0 - 1 - - - - - - - - - + + + GD32E230 + 1.0 + GD32E230 ARM 32-bit Cortex-M23 Microcontroller based device + + CM23 + r0p0 + little + 1 + 1 + 4 + 0 + + 8 + 32 + + + + + 0x20 + 0x0 + 0xFFFFFFFF + + + ADC + Analog to digital converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_CMP + 12 + + + + STAT + STAT + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRC + Start flag of regular channel group + 4 + 1 + + + STIC + Start flag of inserted channel group + 3 + 1 + + + EOIC + End of inserted group conversion flag + 2 + 1 + + + EOC + End of group conversion flag + 1 + 1 + + + WDE + Analog watchdog event flag + 0 + 1 + + + + + CTL0 + CTL0 + control register 0 + 0x4 + 0x20 + read-write + 0x00000000 + + + DRES + ADC resolution + 24 + 2 + + + RWDEN + Regular channel analog watchdog enable + 23 + 1 + + + IWDEN + Inserted channel analog watchdog enable + 22 + 1 + + + DISNUM + Number of conversions in discontinuous + mode + 13 + 3 + + + DISIC + Discontinuous mode on injected + channels + 12 + 1 + + + DISRC + Discontinuous mode on regular + channels + 11 + 1 + + + ICA + Inserted channel group convert + automatically + 10 + 1 + + + WDSC + When in scan mode, analog watchdog + is effective on a single channel + 9 + 1 + + + SM + Scan mode + 8 + 1 + + + EOICIE + Interrupt enable for EOIC + 7 + 1 + + + WDEIE + Interrupt enable for WDE + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + WDCHSEL + Analog watchdog channel select + 0 + 5 + + + + + CTL1 + CTL1 + control register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + TSVREN + Channel 16 and 17 enable of ADC + 23 + 1 + + + SWRCST + Start on regular channel + 22 + 1 + + + SWICST + Start on inserted channel + 21 + 1 + + + ETERC + External trigger enable for regular + channel + 20 + 1 + + + ETSRC + External trigger select for regular + channel + 17 + 3 + + + ETEIC + External trigger enable for + inserted channels + 15 + 1 + + + ETSIC + External trigger select for inserted + channel + 12 + 3 + + + DAL + Data alignment + 11 + 1 + + + DMA + DMA request enable + 8 + 1 + + + RSTCLB + Reset calibration + 3 + 1 + + + CLB + ADC calibration + 2 + 1 + + + CTN + Continuous mode + 1 + 1 + + + ADCON + ADC ON + 0 + 1 + + + + + SAMPT0 + SAMPT0 + Sampling time register 0 + 0x0C + 0x20 + read-write + 0x00000000 + + + SPT16 + Channel 16 sample time + selection + 18 + 3 + + + SPT17 + Channel 17 sample time + selection + 21 + 3 + + + + + SAMPT1 + SAMPT1 + Sampling time register 1 + 0x10 + 0x20 + read-write + 0x00000000 + + + SPT0 + Channel 0 sample time + selection + 0 + 3 + + + SPT1 + Channel 1 sample time + selection + 3 + 3 + + + SPT2 + Channel 2 sample time + selection + 6 + 3 + + + SPT3 + Channel 3 sample time + selection + 9 + 3 + + + SPT4 + Channel 4 sample time + selection + 12 + 3 + + + SPT5 + Channel 5 sample time + selection + 15 + 3 + + + SPT6 + Channel 6 sample time + selection + 18 + 3 + + + SPT7 + Channel 7 sample time + selection + 21 + 3 + + + SPT8 + Channel 8 sample time + selection + 24 + 3 + + + SPT9 + Channel 9 sample time + selection + 27 + 3 + + + + + IOFF0 + IOFF0 + Inserted channel data offset register + 0 + 0x14 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for injected channel + x + 0 + 12 + + + + + IOFF1 + IOFF1 + Inserted channel data offset register + 1 + 0x18 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for injected channel + x + 0 + 12 + + + + + IOFF2 + IOFF2 + Inserted channel data offset register + 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for injected channel + x + 0 + 12 + + + + + IOFF3 + IOFF3 + Inserted channel data offset register + 3 + 0x20 + 0x20 + read-write + 0x00000000 + + + IOFF + Data offset for injected channel + x + 0 + 12 + + + + + WDHT + WDHT + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + WDHT + Analog watchdog high + threshold + 0 + 12 + + + + + WDLT + WDLT + watchdog low threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + WDLT + Analog watchdog lower + threshold + 0 + 12 + + + + + RSQ0 + RSQ0 + regular sequence register 0 + 0x2C + 0x20 + read-write + 0x00000000 + + + RL + Regular channel sequence + length + 20 + 4 + + + RSQ15 + 15th conversion in regular + sequence + 15 + 5 + + + RSQ14 + 14th conversion in regular + sequence + 10 + 5 + + + RSQ13 + 13th conversion in regular + sequence + 5 + 5 + + + RSQ12 + 12th conversion in regular + sequence + 0 + 5 + + + + + RSQ1 + RSQ1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + RSQ11 + 11th conversion in regular + sequence + 25 + 5 + + + RSQ10 + 10th conversion in regular + sequence + 20 + 5 + + + RSQ9 + 9th conversion in regular + sequence + 15 + 5 + + + RSQ8 + 8th conversion in regular + sequence + 10 + 5 + + + RSQ7 + 7th conversion in regular + sequence + 5 + 5 + + + RSQ6 + 6th conversion in regular + sequence + 0 + 5 + + + + + RSQ2 + RSQ2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + RSQ5 + 5th conversion in regular + sequence + 25 + 5 + + + RSQ4 + 4th conversion in regular + sequence + 20 + 5 + + + RSQ3 + 3rd conversion in regular + sequence + 15 + 5 + + + RSQ2 + 2nd conversion in regular + sequence + 10 + 5 + + + RSQ1 + 1st conversion in regular + sequence + 5 + 5 + + + RSQ0 + conversion in regular + sequence + 0 + 5 + + + + + ISQ + ISQ + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + IL + Injected sequence length + 20 + 2 + + + ISQ3 + 3rd conversion in injected + sequence + 15 + 5 + + + ISQ2 + 2nd conversion in injected + sequence + 10 + 5 + + + ISQ1 + 1st conversion in injected + sequence + 5 + 5 + + + ISQ0 + conversion in injected + sequence + 0 + 5 + + + + + IDATA0 + IDATA0 + injected data register 0 + 0x3C + 0x20 + read-only + 0x00000000 + + + IDATAn + Injected data + 0 + 16 + + + + + IDATA1 + IDATA1 + injected data register 1 + 0x40 + 0x20 + read-only + 0x00000000 + + + IDATAn + Injected data + 0 + 16 + + + + + IDATA2 + IDATA2 + injected data register 2 + 0x44 + 0x20 + read-only + 0x00000000 + + + IDATAn + Injected data + 0 + 16 + + + + + IDATA3 + IDATA3 + injected data register 3 + 0x48 + 0x20 + read-only + 0x00000000 + + + IDATAn + Injected data + 0 + 16 + + + + + RDATA + RDATA + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + RDATA + Regular data + 0 + 16 + + + + + OVSAMPCTL + OVSAMPCTL + ADC oversample control register + 0x80 + 0x20 + read-write + 0x00000000 + + + TOVS + Triggered Oversampling + 9 + 1 + + + OVSS + Oversampling shift + 5 + 4 + + + OVSR + Oversampling ratio + 2 + 3 + + + OVSEN + Oversampler Enable + 0 + 1 + + + + + + + CMP + Comparator + Comparator + 0x4001001C + + 0x0 + 0x80 + registers + + + + CS + CS + control and status register + 0x00 + 0x20 + 0x00000000 + + + CMPEN + Comparator enable + 0 + 1 + read-write + + + CMPSW + Comparator switch + 1 + 1 + read-write + + + CMPM + Comparator mode + 2 + 2 + read-write + + + CMPMSEL + Comparator input selection + 4 + 3 + read-write + + + CMPOSEL + Comparator output selection + 8 + 3 + read-write + + + CMPPL + Polarity of comparator output + 11 + 1 + read-write + + + CMPHST + Comparator hysteresis + 12 + 2 + read-write + + + CMPO + Comparator 0 output + 14 + 1 + read-only + + + CMPLK + Comparator 0 lock + 15 + 1 + read-write + + + + + + + CRC + cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DATA + DATA + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DATA + CRC calculation result bits + 0 + 32 + + + + + FDATA + FDATA + Free data register + 0x04 + 0x20 + read-write + 0x00000000 + + + FDATA + General-purpose 8-bit data register + bits + 0 + 8 + + + + + CTL + CTL + Control register + 0x8 + 0x20 + read-write + 0x00000000 + + + RST + reset bit + 0 + 1 + + + PS + Size of polynomial + 3 + 2 + + + REV_I + Reverse input data + 5 + 2 + + + REV_O + Reverse output data + 7 + 1 + + + + + IDATA + IDATA + Initialization Data Register + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + IDATA + CRC calculation initial value + 0 + 32 + + + + + POLY + POLY + Polynomial register + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POLY + User configurable polynomial value + 0 + 32 + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + ID + ID + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + ID_CODE + DBG ID code register + 0 + 32 + + + + + CTL0 + CTL0 + Debug Control Register 0 + 0x4 + 0x20 + read-write + 0x0 + + + SLP_HOLD + Sleep mode hold register + 0 + 1 + + + DSLP_HOLD + DEEPSLEEP mode hold Mode + 1 + 1 + + + STB_HOLD + Standby mode hold Mode + 2 + 1 + + + FWDGT_HOLD + FWDGT hold register + 8 + 1 + + + WWDGT_HOLD + WWDGT hold register + 9 + 1 + + + TIMER0_HOLD + Timer 0 hold register + 10 + 1 + + + TIMER2_HOLD + Timer 2 hold register + 12 + 1 + + + I2C0_HOLD + I2C0 hold register + 15 + 1 + + + I2C1_HOLD + I2C1 hold register + 16 + 1 + + + TIMER5_HOLD + Timer 5 hold register + 19 + 1 + + + TIMER13_HOLD + Timer 13 hold register + 27 + 1 + + + + + CTL1 + CTL1 + Debug Control Register 1 + 0x08 + 0x20 + read-write + 0x00000000 + + + RTC_HOLD + RTC hold register + 10 + 1 + + + TIMER14_HOLD + Timer 14 hold register + 16 + 1 + + + TIMER15_HOLD + Timer 15 hold register + 17 + 1 + + + TIMER16_HOLD + Timer 16 hold register + 18 + 1 + + + + + + + DMA + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_Channel0 + 9 + + + DMA_Channel1_2 + 10 + + + DMA_Channel3_4 + 11 + + + + INTF + INTF + DMA interrupt flag register + (DMA_INTF) + 0x0 + 0x20 + read-only + 0x00000000 + + + GIF0 + Channel 0 Global interrupt + flag + 0 + 1 + + + FTFIF0 + Channel 0 Full Transfer Finish + flag + 1 + 1 + + + HTFIF0 + Channel 0 Half Transfer Finish + flag + 2 + 1 + + + ERRIF0 + Channel 0 Error flag + 3 + 1 + + + GIF1 + Channel 1 Global interrupt + flag + 4 + 1 + + + FTFIF1 + Channel 1 Full Transfer Finish + flag + 5 + 1 + + + HTFIF1 + Channel 1 Half Transfer Finish + flag + 6 + 1 + + + ERRIF1 + Channel 1 Error flag + 7 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 8 + 1 + + + FTFIF2 + Channel 2 Full Transfer Finish + flag + 9 + 1 + + + HTFIF2 + Channel 2 Half Transfer Finish + flag + 10 + 1 + + + ERRIF2 + Channel 2 Error + flag + 11 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 12 + 1 + + + FTFIF3 + Channel 3 Full Transfer Finish + flag + 13 + 1 + + + HTFIF3 + Channel 3 Half Transfer Finish + flag + 14 + 1 + + + ERRIF3 + Channel 3 Error + flag + 15 + 1 + + + GIF4 + Channel 4 Global interrupt + flag + 16 + 1 + + + FTFIF4 + Channel 4 Full Transfer Finish + flag + 17 + 1 + + + HTFIF4 + Channel 4 Half Transfer Finish + flag + 18 + 1 + + + ERRIF4 + Channel 4 Error + flag + 19 + 1 + + + + + INTC + INTC + DMA interrupt flag clear register + (DMA_INTC) + 0x4 + 0x20 + write-only + 0x00000000 + + + GIFC0 + Channel 0 Global interrupt flag + clear + 0 + 1 + + + GIFC1 + Channel 1 Global interrupt flag + clear + 4 + 1 + + + GIFC2 + Channel 2 Global interrupt flag + clear + 8 + 1 + + + GIFC3 + Channel 3 Global interrupt flag + clear + 12 + 1 + + + GIFC4 + Channel 4 Global interrupt flag + clear + 16 + 1 + + + FTFIFC0 + Channel 0 Full Transfer Finish + clear + 1 + 1 + + + FTFIFC1 + Channel 1 Full Transfer Finish + clear + 5 + 1 + + + FTFIFC2 + Channel 2 Full Transfer Finish + clear + 9 + 1 + + + FTFIFC3 + Channel 3 Full Transfer Finish + clear + 13 + 1 + + + FTFIFC4 + Channel 4 Full Transfer Finish + clear + 17 + 1 + + + HTFIFC0 + Channel 0 Half Transfer + clear + 2 + 1 + + + HTFIFC1 + Channel 1 Half Transfer + clear + 6 + 1 + + + HTFIFC2 + Channel 2 Half Transfer + clear + 10 + 1 + + + HTFIFC3 + Channel 3 Half Transfer + clear + 14 + 1 + + + HTFIFC4 + Channel 4 Half Transfer + clear + 18 + 1 + + + ERRIFC0 + Channel 0 Error + clear + 3 + 1 + + + ERRIFC1 + Channel 1 Error + clear + 7 + 1 + + + ERRIFC2 + Channel 2 Error + clear + 11 + 1 + + + ERRIFC3 + Channel 3 Error + clear + 15 + 1 + + + ERRIFC4 + Channel 4 Error + clear + 19 + 1 + + + + + CH0CTL + CH0CTL + DMA channel configuration register + (DMA_CH0CTL) + 0x8 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Full Transfer Finish interrupt + enable + 1 + 1 + + + HTFIE + Half Transfer Finish interrupt + enable + 2 + 1 + + + ERRIE + Transfer access error interrupt + enable + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority Level of this channel + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + CH0CNT + CH0CNT + DMA channel 0 counter + register + 0x0C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH0PADDR + CH0PADDR + DMA channel 0 peripheral base address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH0MADDR + CH0MADDR + DMA channel 0 memory base address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + CH1CTL + CH1CTL + DMA channel configuration register + (DMA_CH1CTL) + 0x1C + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Full Transfer Finish interrupt + enable + 1 + 1 + + + HTFIE + Half Transfer Finish interrupt + enable + 2 + 1 + + + ERRIE + Error interrupt + enable + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority Level of this channel + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + CH1CNT + CH1CNT + DMA channel 1 counter + register + 0x20 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + + CH1PADDR + CH1PADDR + DMA channel 1 peripheral base address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH1MADDR + CH1MADDR + DMA channel 1 memory base address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + CH2CTL + CH2CTL + DMA channel configuration register + (DMA_CH2CTL) + 0x30 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Full Transfer Finish interrupt + enable + 1 + 1 + + + HTFIE + Half Transfer Finish interrupt + enable + 2 + 1 + + + ERRIE + Error interrupt + enable + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority Level of this channel + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + CH2CNT + CH2CNT + DMA channel 2 counter + register + 0x34 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + + CH2PADDR + CH2PADDR + DMA channel 2 peripheral base address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH2MADDR + CH2MADDR + DMA channel 2 memory base address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + CH3CTL + CH3CTL + DMA channel configuration register + (DMA_CH3CTL) + 0x44 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Full Transfer Finish interrupt + enable + 1 + 1 + + + HTFIE + Half Transfer Finish interrupt + enable + 2 + 1 + + + ERRIE + Error interrupt + enable + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority Level of this channel + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + CH3CNT + CH3CNT + DMA channel 3 counter + register + 0x48 + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH3PADDR + CH3PADDR + DMA channel 3 peripheral base address + register + 0x4C + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH3MADDR + CH3MADDR + DMA channel 3 memory base address + register + 0x50 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + CH4CTL + CH4CTL + DMA channel configuration register + (DMA_CH4CTL) + 0x58 + 0x20 + read-write + 0x00000000 + + + CHEN + Channel enable + 0 + 1 + + + FTFIE + Full Transfer Finish interrupt + enable + 1 + 1 + + + HTFIE + Half Transfer Finish interrupt + enable + 2 + 1 + + + ERRIE + Error interrupt + enable + 3 + 1 + + + DIR + Transfer direction + 4 + 1 + + + CMEN + Circular mode enable + 5 + 1 + + + PNAGA + Next address generation algorithm of peripheral + 6 + 1 + + + MNAGA + Next address generation algorithm of memory + 7 + 1 + + + PWIDTH + Transfer data size of peripheral + 8 + 2 + + + MWIDTH + Transfer data size of memory + 10 + 2 + + + PRIO + Priority Level of this channel + 12 + 2 + + + M2M + Memory to memory mode + 14 + 1 + + + + + CH4CNT + CH4CNT + DMA channel 4 counter + register + 0x5C + 0x20 + read-write + 0x00000000 + + + CNT + Transfer counter + 0 + 16 + + + + + CH4PADDR + CH4PADDR + DMA channel 4 peripheral base address + register + 0x60 + 0x20 + read-write + 0x00000000 + + + PADDR + Peripheral base address + 0 + 32 + + + + + CH4MADDR + CH4MADDR + DMA channel 4 memory base address + register + 0x64 + 0x20 + read-write + 0x00000000 + + + MADDR + Memory address + 0 + 32 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + LVD + 1 + + + EXTI0_1 + 5 + + + EXTI2_3 + 6 + + + EXTI4_15 + 7 + + + + INTEN + INTEN + Interrupt enable register + (EXTI_INTEN) + 0x0 + 0x20 + read-write + 0x0F940000 + + + INTEN0 + Enable Interrupt on line 0 + 0 + 1 + + + INTEN1 + Enable Interrupt on line 1 + 1 + 1 + + + INTEN2 + Enable Interrupt on line 2 + 2 + 1 + + + INTEN3 + Enable Interrupt on line 3 + 3 + 1 + + + INTEN4 + Enable Interrupt on line 4 + 4 + 1 + + + INTEN5 + Enable Interrupt on line 5 + 5 + 1 + + + INTEN6 + Enable Interrupt on line 6 + 6 + 1 + + + INTEN7 + Enable Interrupt on line 7 + 7 + 1 + + + INTEN8 + Enable Interrupt on line 8 + 8 + 1 + + + INTEN9 + Enable Interrupt on line 9 + 9 + 1 + + + INTEN10 + Enable Interrupt on line 10 + 10 + 1 + + + INTEN11 + Enable Interrupt on line 11 + 11 + 1 + + + INTEN12 + Enable Interrupt on line 12 + 12 + 1 + + + INTEN13 + Enable Interrupt on line 13 + 13 + 1 + + + INTEN14 + Enable Interrupt on line 14 + 14 + 1 + + + INTEN15 + Enable Interrupt on line 15 + 15 + 1 + + + INTEN16 + Enable Interrupt on line 16 + 16 + 1 + + + INTEN17 + Enable Interrupt on line 17 + 17 + 1 + + + INTEN18 + Enable Interrupt on line 18 + 18 + 1 + + + INTEN19 + Enable Interrupt on line 19 + 19 + 1 + + + INTEN20 + Enable Interrupt on line 20 + 20 + 1 + + + INTEN21 + Enable Interrupt on line 21 + 21 + 1 + + + INTEN22 + Enable Interrupt on line 22 + 22 + 1 + + + INTEN23 + Enable Interrupt on line 23 + 23 + 1 + + + INTEN24 + Enable Interrupt on line 24 + 24 + 1 + + + INTEN25 + Enable Interrupt on line 25 + 25 + 1 + + + INTEN26 + Enable Interrupt on line 26 + 26 + 1 + + + INTEN27 + Enable Interrupt on line 27 + 27 + 1 + + + + + EVEN + EVEN + Event enable register (EXTI_EVEN) + 0x04 + 0x20 + read-write + 0x00000000 + + + EVEN0 + Enable Event on line 0 + 0 + 1 + + + EVEN1 + Enable Event on line 1 + 1 + 1 + + + EVEN2 + Enable Event on line 2 + 2 + 1 + + + EVEN3 + Enable Event on line 3 + 3 + 1 + + + EVEN4 + Enable Event on line 4 + 4 + 1 + + + EVEN5 + Enable Event on line 5 + 5 + 1 + + + EVEN6 + Enable Event on line 6 + 6 + 1 + + + EVEN7 + Enable Event on line 7 + 7 + 1 + + + EVEN8 + Enable Event on line 8 + 8 + 1 + + + EVEN9 + Enable Event on line 9 + 9 + 1 + + + EVEN10 + Enable Event on line 10 + 10 + 1 + + + EVEN11 + Enable Event on line 11 + 11 + 1 + + + EVEN12 + Enable Event on line 12 + 12 + 1 + + + EVEN13 + Enable Event on line 13 + 13 + 1 + + + EVEN14 + Enable Event on line 14 + 14 + 1 + + + EVEN15 + Enable Event on line 15 + 15 + 1 + + + EVEN16 + Enable Event on line 16 + 16 + 1 + + + EVEN17 + Enable Event on line 17 + 17 + 1 + + + EVEN18 + Enable Event on line 18 + 18 + 1 + + + EVEN19 + Enable Event on line 19 + 19 + 1 + + + EVEN20 + Enable Event on line 20 + 20 + 1 + + + EVEN21 + Enable Event on line 21 + 21 + 1 + + + EVEN22 + Enable Event on line 22 + 22 + 1 + + + EVEN23 + Enable Event on line 23 + 23 + 1 + + + EVEN24 + Enable Event on line 24 + 24 + 1 + + + EVEN25 + Enable Event on line 25 + 25 + 1 + + + EVEN26 + Enable Event on line 26 + 26 + 1 + + + EVEN27 + Enable Event on line 27 + 27 + 1 + + + + + RTEN + RTEN + Rising Edge Trigger Enable register + (EXTI_RTEN) + 0x08 + 0x20 + read-write + 0x00000000 + + + RTEN0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + RTEN1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + RTEN2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + RTEN3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + RTEN4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + RTEN5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + RTEN6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + RTEN7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + RTEN8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + RTEN9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + RTEN10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + RTEN11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + RTEN12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + RTEN13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + RTEN14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + RTEN15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + RTEN16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + RTEN17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + RTEN19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + RTEN21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + + + FTEN + FTEN + Falling Egde Trigger Enable register + (EXTI_FTEN) + 0x0C + 0x20 + read-write + 0x00000000 + + + FTEN0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + FTEN1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + FTEN2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + FTEN3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + FTEN4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + FTEN5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + FTEN6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + FTEN7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + FTEN8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + FTEN9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + FTEN10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + FTEN11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + FTEN12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + FTEN13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + FTEN14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + FTEN15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + FTEN16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + FTEN17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + FTEN19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + FTEN21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + + + SWIEV + SWIEV + Software interrupt event register + (EXTI_SWIEV) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIEV0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIEV1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIEV2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIEV3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIEV4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIEV5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIEV6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIEV7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIEV8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIEV9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIEV10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIEV11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIEV12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIEV13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIEV14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIEV15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIEV16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIEV17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIEV19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIEV21 + Software Interrupt on line + 21 + 21 + 1 + + + + + PD + PD + Pending register (EXTI_PD) + 0x14 + 0x20 + read-write + 0x00000000 + + + PD0 + Pending bit 0 + 0 + 1 + + + PD1 + Pending bit 1 + 1 + 1 + + + PD2 + Pending bit 2 + 2 + 1 + + + PD3 + Pending bit 3 + 3 + 1 + + + PD4 + Pending bit 4 + 4 + 1 + + + PD5 + Pending bit 5 + 5 + 1 + + + PD6 + Pending bit 6 + 6 + 1 + + + PD7 + Pending bit 7 + 7 + 1 + + + PD8 + Pending bit 8 + 8 + 1 + + + PD9 + Pending bit 9 + 9 + 1 + + + PD10 + Pending bit 10 + 10 + 1 + + + PD11 + Pending bit 11 + 11 + 1 + + + PD12 + Pending bit 12 + 12 + 1 + + + PD13 + Pending bit 13 + 13 + 1 + + + PD14 + Pending bit 14 + 14 + 1 + + + PD15 + Pending bit 15 + 15 + 1 + + + PD16 + Pending bit 16 + 16 + 1 + + + PD17 + Pending bit 17 + 17 + 1 + + + PD19 + Pending bit 19 + 19 + 1 + + + PD21 + Pending bit 21 + 21 + 1 + + + + + + + FMC + FMC + FMC + 0x40022000 + + 0x0 + 0x400 + registers + + + FMC + 3 + + + + WS + WS + wait state register + 0x0 + 0x20 + read-write + 0x00000000 + + + WSCNT + wait state counter register + 0 + 3 + + + PFEN + Pre-fetch enable + 4 + 1 + + + PGW + Program width to flash memory + 15 + 1 + + + + + KEY + KEY + Unlock key register + 0x04 + 0x20 + write-only + 0x00000000 + + + KEY + FMC_CTL unlock register + 0 + 32 + + + + + OBKEY + OBKEY + Option byte unlock key register + 0x08 + 0x20 + write-only + 0x00000000 + + + OBKEY + FMC_ CTL option bytes operation unlock register + 0 + 32 + + + + + STAT + STAT + Status register + 0x0C + 0x20 + 0x00000000 + + + ENDF + End of operation flag bit + 5 + 1 + read-write + + + WPERR + Erase/Program protection error flag bit + 4 + 1 + read-write + + + PGAERR + Program alignment error flag bit + 3 + 1 + read-write + + + PGERR + Program error flag bit + 2 + 1 + read-write + + + BUSY + The flash is busy bit + 0 + 1 + read-only + + + + + CTL + CTL + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + OBRLD + Option byte reload bit + 13 + 1 + + + ENDIE + End of operation interrupt enable bit + 12 + 1 + + + ERRIE + Error interrupt enable bit + 10 + 1 + + + OBWEN + Option byte erase/program enable bit + 9 + 1 + + + LK + FMC_CTL lock bit + 7 + 1 + + + START + Send erase command to FMC bit + 6 + 1 + + + OBER + Option bytes erase command bit + 5 + 1 + + + OBPG + Option bytes program command bit + 4 + 1 + + + MER + Main flash mass erase for bank0 command bit + 2 + 1 + + + PER + Main flash page erase for bank0 command bit + 1 + 1 + + + PG + Main flash program for bank0 command bit + 0 + 1 + + + + + ADDR + ADDR + Address register + 0x14 + 0x20 + read-write + 0x00000000 + + + ADDR + Flash erase/program command address bits + 0 + 32 + + + + + OBSTAT + OBSTAT + Option byte control register + 0x1C + 0x20 + read-only + 0x00000000 + + + OBERR + Option bytes read error bit + 0 + 1 + + + PLEVEL + Option bytes security protection level + 1 + 2 + + + USER + Store USER of option bytes block after system reset + 8 + 8 + + + DATA + Store DATA[15:0] of option bytes block after system reset + 16 + 16 + + + + + WP + WP + Erase/Program Protection register + 0x20 + 0x20 + read-only + 0x00000000 + + + WP + Store WP[15:0] of option bytes block after system reset + 0 + 16 + + + + + PID + PID + Product ID register + 0x100 + 0x20 + read-only + 0x00000000 + + + PID + Product reserved ID code register + 0 + 32 + + + + + + + FWDGT + free watchdog timer + FWDGT + 0x40003000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + Control register + 0x00 + 0x20 + write-only + 0x00000000 + + + CMD + Key value + 0 + 16 + + + + + PSC + PSC + Prescaler register + 0x04 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler divider + 0 + 3 + + + + + RLD + RLD + Reload register + 0x08 + 0x20 + read-write + 0x00000FFF + + + RLD + Watchdog counter reload + value + 0 + 12 + + + + + STAT + STAT + Status register + 0x0C + 0x20 + read-only + 0x00000000 + + + PUD + Watchdog prescaler value + update + 0 + 1 + + + RUD + Watchdog counter reload value + update + 1 + 1 + + + WUD + Watchdog counter window value + update + 2 + 1 + + + + + WND + WND + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WND + Watchdog counter window + value + 0 + 12 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + GPIO port control register + 0x0 + 0x20 + read-write + 0x28000000 + + + CTL15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + CTL14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + CTL13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + CTL12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + CTL11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + CTL10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + CTL9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + CTL8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + CTL7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + CTL6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + CTL5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + CTL4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + CTL3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + CTL2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + CTL1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + CTL0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OMODE + OMODE + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + + + OM15 + Port x configuration bit + 15 + 15 + 1 + + + OM14 + Port x configuration bit + 14 + 14 + 1 + + + OM13 + Port x configuration bit + 13 + 13 + 1 + + + OM12 + Port x configuration bit + 12 + 12 + 1 + + + OM11 + Port x configuration bit + 11 + 11 + 1 + + + OM10 + Port x configuration bit + 10 + 10 + 1 + + + OM9 + Port x configuration bit 9 + 9 + 1 + + + OM8 + Port x configuration bit 8 + 8 + 1 + + + OM7 + Port x configuration bit 7 + 7 + 1 + + + OM6 + Port x configuration bit 6 + 6 + 1 + + + OM5 + Port x configuration bit 5 + 5 + 1 + + + OM4 + Port x configuration bit 4 + 4 + 1 + + + OM3 + Port x configuration bit 3 + 3 + 1 + + + OM2 + Port x configuration bit 2 + 2 + 1 + + + OM1 + Port x configuration bit 1 + 1 + 1 + + + OM0 + Port x configuration bit 0 + 0 + 1 + + + + + OSPD + OSPD + GPIO port output speed + register + 0x08 + 0x20 + read-write + 0x0C000000 + + + OSPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUD + PUD + GPIO port pull-up/pull-down + register + 0x0C + 0x20 + read-write + 0x24000000 + + + PUD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + ISTAT + ISTAT + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input data (y = + 0..15) + 15 + 1 + + + ISTAT14 + Port input data (y = + 0..15) + 14 + 1 + + + ISTAT13 + Port input data (y = + 0..15) + 13 + 1 + + + ISTAT12 + Port input data (y = + 0..15) + 12 + 1 + + + ISTAT11 + Port input data (y = + 0..15) + 11 + 1 + + + ISTAT10 + Port input data (y = + 0..15) + 10 + 1 + + + ISTAT9 + Port input data (y = + 0..15) + 9 + 1 + + + ISTAT8 + Port input data (y = + 0..15) + 8 + 1 + + + ISTAT7 + Port input data (y = + 0..15) + 7 + 1 + + + ISTAT6 + Port input data (y = + 0..15) + 6 + 1 + + + ISTAT5 + Port input data (y = + 0..15) + 5 + 1 + + + ISTAT4 + Port input data (y = + 0..15) + 4 + 1 + + + ISTAT3 + Port input data (y = + 0..15) + 3 + 1 + + + ISTAT2 + Port input data (y = + 0..15) + 2 + 1 + + + ISTAT1 + Port input data (y = + 0..15) + 1 + 1 + + + ISTAT0 + Port input data (y = + 0..15) + 0 + 1 + + + + + OCTL + OCTL + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output data (y = + 0..15) + 15 + 1 + + + OCTL14 + Port output data (y = + 0..15) + 14 + 1 + + + OCTL13 + Port output data (y = + 0..15) + 13 + 1 + + + OCTL12 + Port output data (y = + 0..15) + 12 + 1 + + + OCTL11 + Port output data (y = + 0..15) + 11 + 1 + + + OCTL10 + Port output data (y = + 0..15) + 10 + 1 + + + OCTL9 + Port output data (y = + 0..15) + 9 + 1 + + + OCTL8 + Port output data (y = + 0..15) + 8 + 1 + + + OCTL7 + Port output data (y = + 0..15) + 7 + 1 + + + OCTL6 + Port output data (y = + 0..15) + 6 + 1 + + + OCTL5 + Port output data (y = + 0..15) + 5 + 1 + + + OCTL4 + Port output data (y = + 0..15) + 4 + 1 + + + OCTL3 + Port output data (y = + 0..15) + 3 + 1 + + + OCTL2 + Port output data (y = + 0..15) + 2 + 1 + + + OCTL1 + Port output data (y = + 0..15) + 1 + 1 + + + OCTL0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BOP + BOP + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + CR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + CR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + CR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + CR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + CR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + CR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + CR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + CR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + CR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + CR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + CR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + CR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + CR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + CR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + CR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + CR0 + Port x reset bit y (y= + 0..15) + 16 + 1 + + + BOP15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BOP14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BOP13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BOP12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BOP11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BOP10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BOP9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BOP8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BOP7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BOP6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BOP5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BOP4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BOP3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BOP2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BOP1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BOP0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LOCK + LOCK + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LKK + Port x lock bit y + + 16 + 1 + + + LK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFSEL0 + AFSEL0 + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + SEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + SEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + SEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + SEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + SEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + SEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + SEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + SEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFSEL1 + AFSEL1 + GPIO alternate function + register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + SEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + SEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + SEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + SEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + SEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + SEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + SEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + SEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BC + BC + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + CR0 + Port cleat bit + 0 + 1 + + + CR1 + Port cleat bit + 1 + 1 + + + CR2 + Port cleat bit + 2 + 1 + + + CR3 + Port cleat bit + 3 + 1 + + + CR4 + Port cleat bit + 4 + 1 + + + CR5 + Port cleat bit + 5 + 1 + + + CR6 + Port cleat bit + 6 + 1 + + + CR7 + Port cleat bit + 7 + 1 + + + CR8 + Port cleat bit + 8 + 1 + + + CR9 + Port cleat bit + 9 + 1 + + + CR10 + Port cleat bit + 10 + 1 + + + CR11 + Port cleat bit + 11 + 1 + + + CR12 + Port cleat bit + 12 + 1 + + + CR13 + Port cleat bit + 13 + 1 + + + CR14 + Port cleat bit + 14 + 1 + + + CR15 + Port cleat bit + 15 + 1 + + + + + TG + TG + Port bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + TG0 + Port toggle bit + 0 + 1 + + + TG1 + Port toggle bit + 1 + 1 + + + TG2 + Port toggle bit + 2 + 1 + + + TG3 + Port toggle bit + 3 + 1 + + + TG4 + Port toggle bit + 4 + 1 + + + TG5 + Port toggle bit + 5 + 1 + + + TG6 + Port toggle bit + 6 + 1 + + + TG7 + Port toggle bit + 7 + 1 + + + TG8 + Port toggle bit + 8 + 1 + + + TG9 + Port toggle bit + 9 + 1 + + + TG10 + Port toggle bit + 10 + 1 + + + TG11 + Port toggle bit + 11 + 1 + + + TG12 + Port toggle bit + 12 + 1 + + + TG13 + Port toggle bit + 13 + 1 + + + TG14 + Port toggle bit + 14 + 1 + + + TG15 + Port toggle bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + CTL + CTL + GPIO port control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTL15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + CTL14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + CTL13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + CTL12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + CTL11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + CTL10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + CTL9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + CTL8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + CTL7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + CTL6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + CTL5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + CTL4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + CTL3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + CTL2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + CTL1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + CTL0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OMODE + OMODE + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + + + OM15 + Port x configuration bit + 15 + 15 + 1 + + + OM14 + Port x configuration bit + 14 + 14 + 1 + + + OM13 + Port x configuration bit + 13 + 13 + 1 + + + OM12 + Port x configuration bit + 12 + 12 + 1 + + + OM11 + Port x configuration bit + 11 + 11 + 1 + + + OM10 + Port x configuration bit + 10 + 10 + 1 + + + OM9 + Port x configuration bit 9 + 9 + 1 + + + OM8 + Port x configuration bit 8 + 8 + 1 + + + OM7 + Port x configuration bit 7 + 7 + 1 + + + OM6 + Port x configuration bit 6 + 6 + 1 + + + OM5 + Port x configuration bit 5 + 5 + 1 + + + OM4 + Port x configuration bit 4 + 4 + 1 + + + OM3 + Port x configuration bit 3 + 3 + 1 + + + OM2 + Port x configuration bit 2 + 2 + 1 + + + OM1 + Port x configuration bit 1 + 1 + 1 + + + OM0 + Port x configuration bit 0 + 0 + 1 + + + + + OSPD + OSPD + GPIO port output speed + register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUD + PUD + GPIO port pull-up/pull-down + register + 0x0C + 0x20 + read-write + 0x00000000 + + + PUD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + ISTAT + ISTAT + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input data (y = + 0..15) + 15 + 1 + + + ISTAT14 + Port input data (y = + 0..15) + 14 + 1 + + + ISTAT13 + Port input data (y = + 0..15) + 13 + 1 + + + ISTAT12 + Port input data (y = + 0..15) + 12 + 1 + + + ISTAT11 + Port input data (y = + 0..15) + 11 + 1 + + + ISTAT10 + Port input data (y = + 0..15) + 10 + 1 + + + ISTAT9 + Port input data (y = + 0..15) + 9 + 1 + + + ISTAT8 + Port input data (y = + 0..15) + 8 + 1 + + + ISTAT7 + Port input data (y = + 0..15) + 7 + 1 + + + ISTAT6 + Port input data (y = + 0..15) + 6 + 1 + + + ISTAT5 + Port input data (y = + 0..15) + 5 + 1 + + + ISTAT4 + Port input data (y = + 0..15) + 4 + 1 + + + ISTAT3 + Port input data (y = + 0..15) + 3 + 1 + + + ISTAT2 + Port input data (y = + 0..15) + 2 + 1 + + + ISTAT1 + Port input data (y = + 0..15) + 1 + 1 + + + ISTAT0 + Port input data (y = + 0..15) + 0 + 1 + + + + + OCTL + OCTL + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output data (y = + 0..15) + 15 + 1 + + + OCTL14 + Port output data (y = + 0..15) + 14 + 1 + + + OCTL13 + Port output data (y = + 0..15) + 13 + 1 + + + OCTL12 + Port output data (y = + 0..15) + 12 + 1 + + + OCTL11 + Port output data (y = + 0..15) + 11 + 1 + + + OCTL10 + Port output data (y = + 0..15) + 10 + 1 + + + OCTL9 + Port output data (y = + 0..15) + 9 + 1 + + + OCTL8 + Port output data (y = + 0..15) + 8 + 1 + + + OCTL7 + Port output data (y = + 0..15) + 7 + 1 + + + OCTL6 + Port output data (y = + 0..15) + 6 + 1 + + + OCTL5 + Port output data (y = + 0..15) + 5 + 1 + + + OCTL4 + Port output data (y = + 0..15) + 4 + 1 + + + OCTL3 + Port output data (y = + 0..15) + 3 + 1 + + + OCTL2 + Port output data (y = + 0..15) + 2 + 1 + + + OCTL1 + Port output data (y = + 0..15) + 1 + 1 + + + OCTL0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BOP + BOP + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + CR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + CR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + CR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + CR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + CR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + CR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + CR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + CR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + CR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + CR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + CR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + CR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + CR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + CR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + CR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + CR0 + Port x reset bit y (y= + 0..15) + 16 + 1 + + + BOP15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BOP14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BOP13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BOP12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BOP11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BOP10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BOP9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BOP8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BOP7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BOP6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BOP5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BOP4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BOP3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BOP2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BOP1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BOP0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LOCK + LOCK + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LKK + Port x lock bit y + + 16 + 1 + + + LK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFSEL0 + AFSEL0 + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + SEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + SEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + SEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + SEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + SEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + SEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + SEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + SEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFSEL1 + AFSEL1 + GPIO alternate function + register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + SEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + SEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + SEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + SEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + SEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + SEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + SEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + SEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BC + BC + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + CR0 + Port cleat bit + 0 + 1 + + + CR1 + Port cleat bit + 1 + 1 + + + CR2 + Port cleat bit + 2 + 1 + + + CR3 + Port cleat bit + 3 + 1 + + + CR4 + Port cleat bit + 4 + 1 + + + CR5 + Port cleat bit + 5 + 1 + + + CR6 + Port cleat bit + 6 + 1 + + + CR7 + Port cleat bit + 7 + 1 + + + CR8 + Port cleat bit + 8 + 1 + + + CR9 + Port cleat bit + 9 + 1 + + + CR10 + Port cleat bit + 10 + 1 + + + CR11 + Port cleat bit + 11 + 1 + + + CR12 + Port cleat bit + 12 + 1 + + + CR13 + Port cleat bit + 13 + 1 + + + CR14 + Port cleat bit + 14 + 1 + + + CR15 + Port cleat bit + 15 + 1 + + + + + TG + TG + Port bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + TG0 + Port toggle bit + 0 + 1 + + + TG1 + Port toggle bit + 1 + 1 + + + TG2 + Port toggle bit + 2 + 1 + + + TG3 + Port toggle bit + 3 + 1 + + + TG4 + Port toggle bit + 4 + 1 + + + TG5 + Port toggle bit + 5 + 1 + + + TG6 + Port toggle bit + 6 + 1 + + + TG7 + Port toggle bit + 7 + 1 + + + TG8 + Port toggle bit + 8 + 1 + + + TG9 + Port toggle bit + 9 + 1 + + + TG10 + Port toggle bit + 10 + 1 + + + TG11 + Port toggle bit + 11 + 1 + + + TG12 + Port toggle bit + 12 + 1 + + + TG13 + Port toggle bit + 13 + 1 + + + TG14 + Port toggle bit + 14 + 1 + + + TG15 + Port toggle bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + CTL + CTL + GPIO port control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTL15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + CTL14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + CTL13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + CTL12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + CTL11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + CTL10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + CTL9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + CTL8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + CTL7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + CTL6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + CTL5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + CTL4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + CTL3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + CTL2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + CTL1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + CTL0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OMODE + OMODE + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + + + OM15 + Port x configuration bit + 15 + 15 + 1 + + + OM14 + Port x configuration bit + 14 + 14 + 1 + + + OM13 + Port x configuration bit + 13 + 13 + 1 + + + OM12 + Port x configuration bit + 12 + 12 + 1 + + + OM11 + Port x configuration bit + 11 + 11 + 1 + + + OM10 + Port x configuration bit + 10 + 10 + 1 + + + OM9 + Port x configuration bit 9 + 9 + 1 + + + OM8 + Port x configuration bit 8 + 8 + 1 + + + OM7 + Port x configuration bit 7 + 7 + 1 + + + OM6 + Port x configuration bit 6 + 6 + 1 + + + OM5 + Port x configuration bit 5 + 5 + 1 + + + OM4 + Port x configuration bit 4 + 4 + 1 + + + OM3 + Port x configuration bit 3 + 3 + 1 + + + OM2 + Port x configuration bit 2 + 2 + 1 + + + OM1 + Port x configuration bit 1 + 1 + 1 + + + OM0 + Port x configuration bit 0 + 0 + 1 + + + + + OSPD + OSPD + GPIO port output speed + register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUD + PUD + GPIO port pull-up/pull-down + register + 0x0C + 0x20 + read-write + 0x00000000 + + + PUD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + ISTAT + ISTAT + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input data (y = + 0..15) + 15 + 1 + + + ISTAT14 + Port input data (y = + 0..15) + 14 + 1 + + + ISTAT13 + Port input data (y = + 0..15) + 13 + 1 + + + ISTAT12 + Port input data (y = + 0..15) + 12 + 1 + + + ISTAT11 + Port input data (y = + 0..15) + 11 + 1 + + + ISTAT10 + Port input data (y = + 0..15) + 10 + 1 + + + ISTAT9 + Port input data (y = + 0..15) + 9 + 1 + + + ISTAT8 + Port input data (y = + 0..15) + 8 + 1 + + + ISTAT7 + Port input data (y = + 0..15) + 7 + 1 + + + ISTAT6 + Port input data (y = + 0..15) + 6 + 1 + + + ISTAT5 + Port input data (y = + 0..15) + 5 + 1 + + + ISTAT4 + Port input data (y = + 0..15) + 4 + 1 + + + ISTAT3 + Port input data (y = + 0..15) + 3 + 1 + + + ISTAT2 + Port input data (y = + 0..15) + 2 + 1 + + + ISTAT1 + Port input data (y = + 0..15) + 1 + 1 + + + ISTAT0 + Port input data (y = + 0..15) + 0 + 1 + + + + + OCTL + OCTL + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output data (y = + 0..15) + 15 + 1 + + + OCTL14 + Port output data (y = + 0..15) + 14 + 1 + + + OCTL13 + Port output data (y = + 0..15) + 13 + 1 + + + OCTL12 + Port output data (y = + 0..15) + 12 + 1 + + + OCTL11 + Port output data (y = + 0..15) + 11 + 1 + + + OCTL10 + Port output data (y = + 0..15) + 10 + 1 + + + OCTL9 + Port output data (y = + 0..15) + 9 + 1 + + + OCTL8 + Port output data (y = + 0..15) + 8 + 1 + + + OCTL7 + Port output data (y = + 0..15) + 7 + 1 + + + OCTL6 + Port output data (y = + 0..15) + 6 + 1 + + + OCTL5 + Port output data (y = + 0..15) + 5 + 1 + + + OCTL4 + Port output data (y = + 0..15) + 4 + 1 + + + OCTL3 + Port output data (y = + 0..15) + 3 + 1 + + + OCTL2 + Port output data (y = + 0..15) + 2 + 1 + + + OCTL1 + Port output data (y = + 0..15) + 1 + 1 + + + OCTL0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BOP + BOP + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + CR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + CR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + CR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + CR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + CR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + CR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + CR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + CR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + CR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + CR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + CR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + CR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + CR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + CR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + CR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + CR0 + Port x reset bit y (y= + 0..15) + 16 + 1 + + + BOP15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BOP14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BOP13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BOP12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BOP11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BOP10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BOP9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BOP8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BOP7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BOP6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BOP5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BOP4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BOP3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BOP2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BOP1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BOP0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + AFSEL0 + AFSEL0 + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + SEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + SEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + SEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + SEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + SEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + SEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + SEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + SEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFSEL1 + AFSEL1 + GPIO alternate function + register 1 + 0x24 + 0x20 + read-write + 0x00000000 + + + SEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + SEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + SEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + SEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + SEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + SEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + SEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + SEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BC + BC + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + CR0 + Port cleat bit + 0 + 1 + + + CR1 + Port cleat bit + 1 + 1 + + + CR2 + Port cleat bit + 2 + 1 + + + CR3 + Port cleat bit + 3 + 1 + + + CR4 + Port cleat bit + 4 + 1 + + + CR5 + Port cleat bit + 5 + 1 + + + CR6 + Port cleat bit + 6 + 1 + + + CR7 + Port cleat bit + 7 + 1 + + + CR8 + Port cleat bit + 8 + 1 + + + CR9 + Port cleat bit + 9 + 1 + + + CR10 + Port cleat bit + 10 + 1 + + + CR11 + Port cleat bit + 11 + 1 + + + CR12 + Port cleat bit + 12 + 1 + + + CR13 + Port cleat bit + 13 + 1 + + + CR14 + Port cleat bit + 14 + 1 + + + CR15 + Port cleat bit + 15 + 1 + + + + + TG + TG + Port bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + TG0 + Port toggle bit + 0 + 1 + + + TG1 + Port toggle bit + 1 + 1 + + + TG2 + Port toggle bit + 2 + 1 + + + TG3 + Port toggle bit + 3 + 1 + + + TG4 + Port toggle bit + 4 + 1 + + + TG5 + Port toggle bit + 5 + 1 + + + TG6 + Port toggle bit + 6 + 1 + + + TG7 + Port toggle bit + 7 + 1 + + + TG8 + Port toggle bit + 8 + 1 + + + TG9 + Port toggle bit + 9 + 1 + + + TG10 + Port toggle bit + 10 + 1 + + + TG11 + Port toggle bit + 11 + 1 + + + TG12 + Port toggle bit + 12 + 1 + + + TG13 + Port toggle bit + 13 + 1 + + + TG14 + Port toggle bit + 14 + 1 + + + TG15 + Port toggle bit + 15 + 1 + + + + + + + GPIOF + General-purpose I/Os + GPIO + 0x48001400 + + 0x0 + 0x400 + registers + + + + CTL + CTL + GPIOF port control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CTL15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + CTL14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + CTL13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + CTL12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + CTL11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + CTL10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + CTL9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + CTL8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + CTL7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + CTL6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + CTL5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + CTL4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + CTL3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + CTL2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + CTL1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + CTL0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OMODE + OMODE + GPIO port output type register + 0x04 + 0x20 + read-write + 0x00000000 + + + OM15 + Port x configuration bit + 15 + 15 + 1 + + + OM14 + Port x configuration bit + 14 + 14 + 1 + + + OM13 + Port x configuration bit + 13 + 13 + 1 + + + OM12 + Port x configuration bit + 12 + 12 + 1 + + + OM11 + Port x configuration bit + 11 + 11 + 1 + + + OM10 + Port x configuration bit + 10 + 10 + 1 + + + OM9 + Port x configuration bit 9 + 9 + 1 + + + OM8 + Port x configuration bit 8 + 8 + 1 + + + OM7 + Port x configuration bit 7 + 7 + 1 + + + OM6 + Port x configuration bit 6 + 6 + 1 + + + OM5 + Port x configuration bit 5 + 5 + 1 + + + OM4 + Port x configuration bit 4 + 4 + 1 + + + OM3 + Port x configuration bit 3 + 3 + 1 + + + OM2 + Port x configuration bit 2 + 2 + 1 + + + OM1 + Port x configuration bit 1 + 1 + 1 + + + OM0 + Port x configuration bit 0 + 0 + 1 + + + + + OSPD + OSPD + GPIO port output speed + register + 0x08 + 0x20 + read-write + 0x00000000 + + + OSPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUD + PUD + GPIO port pull-up/pull-down + register + 0x0C + 0x20 + read-write + 0x00000000 + + + PUD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + ISTAT + ISTAT + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ISTAT15 + Port input data (y = + 0..15) + 15 + 1 + + + ISTAT14 + Port input data (y = + 0..15) + 14 + 1 + + + ISTAT13 + Port input data (y = + 0..15) + 13 + 1 + + + ISTAT12 + Port input data (y = + 0..15) + 12 + 1 + + + ISTAT11 + Port input data (y = + 0..15) + 11 + 1 + + + ISTAT10 + Port input data (y = + 0..15) + 10 + 1 + + + ISTAT9 + Port input data (y = + 0..15) + 9 + 1 + + + ISTAT8 + Port input data (y = + 0..15) + 8 + 1 + + + ISTAT7 + Port input data (y = + 0..15) + 7 + 1 + + + ISTAT6 + Port input data (y = + 0..15) + 6 + 1 + + + ISTAT5 + Port input data (y = + 0..15) + 5 + 1 + + + ISTAT4 + Port input data (y = + 0..15) + 4 + 1 + + + ISTAT3 + Port input data (y = + 0..15) + 3 + 1 + + + ISTAT2 + Port input data (y = + 0..15) + 2 + 1 + + + ISTAT1 + Port input data (y = + 0..15) + 1 + 1 + + + ISTAT0 + Port input data (y = + 0..15) + 0 + 1 + + + + + OCTL + OCTL + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OCTL15 + Port output data (y = + 0..15) + 15 + 1 + + + OCTL14 + Port output data (y = + 0..15) + 14 + 1 + + + OCTL13 + Port output data (y = + 0..15) + 13 + 1 + + + OCTL12 + Port output data (y = + 0..15) + 12 + 1 + + + OCTL11 + Port output data (y = + 0..15) + 11 + 1 + + + OCTL10 + Port output data (y = + 0..15) + 10 + 1 + + + OCTL9 + Port output data (y = + 0..15) + 9 + 1 + + + OCTL8 + Port output data (y = + 0..15) + 8 + 1 + + + OCTL7 + Port output data (y = + 0..15) + 7 + 1 + + + OCTL6 + Port output data (y = + 0..15) + 6 + 1 + + + OCTL5 + Port output data (y = + 0..15) + 5 + 1 + + + OCTL4 + Port output data (y = + 0..15) + 4 + 1 + + + OCTL3 + Port output data (y = + 0..15) + 3 + 1 + + + OCTL2 + Port output data (y = + 0..15) + 2 + 1 + + + OCTL1 + Port output data (y = + 0..15) + 1 + 1 + + + OCTL0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BOP + BOP + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + CR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + CR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + CR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + CR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + CR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + CR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + CR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + CR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + CR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + CR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + CR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + CR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + CR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + CR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + CR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + CR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BOP15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BOP14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BOP13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BOP12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BOP11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BOP10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BOP9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BOP8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BOP7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BOP6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BOP5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BOP4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BOP3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BOP2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BOP1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BOP0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + BC + BC + Port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + CR0 + Port x Reset bit y + 0 + 1 + + + CR1 + Port x Reset bit y + 1 + 1 + + + CR2 + Port x Reset bit y + 2 + 1 + + + CR3 + Port x Reset bit y + 3 + 1 + + + CR4 + Port x Reset bit y + 4 + 1 + + + CR5 + Port x Reset bit y + 5 + 1 + + + CR6 + Port x Reset bit y + 6 + 1 + + + CR7 + Port x Reset bit y + 7 + 1 + + + CR8 + Port x Reset bit y + 8 + 1 + + + CR9 + Port x Reset bit y + 9 + 1 + + + CR10 + Port x Reset bit y + 10 + 1 + + + CR11 + Port x Reset bit y + 11 + 1 + + + CR12 + Port x Reset bit y + 12 + 1 + + + CR13 + Port x Reset bit y + 13 + 1 + + + CR14 + Port x Reset bit y + 14 + 1 + + + CR15 + Port x Reset bit y + 15 + 1 + + + + + TG + TG + Port bit toggle register + 0x2C + 0x20 + write-only + 0x00000000 + + + TG0 + Port toggle bit + 0 + 1 + + + TG1 + Port toggle bit + 1 + 1 + + + TG2 + Port toggle bit + 2 + 1 + + + TG3 + Port toggle bit + 3 + 1 + + + TG4 + Port toggle bit + 4 + 1 + + + TG5 + Port toggle bit + 5 + 1 + + + TG6 + Port toggle bit + 6 + 1 + + + TG7 + Port toggle bit + 7 + 1 + + + TG8 + Port toggle bit + 8 + 1 + + + TG9 + Port toggle bit + 9 + 1 + + + TG10 + Port toggle bit + 10 + 1 + + + TG11 + Port toggle bit + 11 + 1 + + + TG12 + Port toggle bit + 12 + 1 + + + TG13 + Port toggle bit + 13 + 1 + + + TG14 + Port toggle bit + 14 + 1 + + + TG15 + Port toggle bit + 15 + 1 + + + + + + + I2C0 + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C0_EV + 23 + + + I2C0_ER + 32 + + + + CTL0 + CTL0 + Control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + SRESET + Software reset + 15 + 1 + + + SALT + SMBus alert + 13 + 1 + + + PECTRANS + Packet error checking + 12 + 1 + + + POAP + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACKEN + Acknowledge enable + 10 + 1 + + + STOP + Stop condition + 9 + 1 + + + START + Start generation + 8 + 1 + + + SS + SCL Stretching(Slave + mode) + 7 + 1 + + + GCEN + General call enable + 6 + 1 + + + PECEN + PEC enable + 5 + 1 + + + ARPEN + ARP enable + 4 + 1 + + + SMBSEL + SMBus type + 3 + 1 + + + SMBEN + SMBus mode + 1 + 1 + + + I2CEN + Peripheral enable + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + DMALST + Flag indicating DMA last transfer + 12 + 1 + + + DMAON + DMA mode switch + 11 + 1 + + + BUFIE + Buffer interrupt enable + 10 + 1 + + + EVIE + Event interrupt enable + 9 + 1 + + + ERRIE + Error interrupt enable + 8 + 1 + + + I2CCLK + Peripheral clock frequency + 0 + 7 + + + + + SADDR0 + SADDR0 + Own address register 0 + 0x08 + 0x20 + read-write + 0x0000 + + + ADDFORMAT + Addressing mode (slave + mode) + 15 + 1 + + + ADDRESS + Interface address + 0 + 10 + + + + + SADDR1 + SADDR1 + Own address register 1 + 0x0C + 0x20 + read-write + 0x0000 + + + ADDRESS2 + Interface address + 1 + 7 + + + DUADEN + Dual addressing mode + enable + 0 + 1 + + + + + DATA + DATA + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + TRB + Transmission or reception data buffer + 0 + 8 + + + + + STAT0 + STAT0 + Transfer status register 0 + 0x14 + 0x20 + 0x0000 + + + SMBALT + SMBus alert + 15 + 1 + read-write + + + SMBTO + Timeout signal in SMBus mode + 14 + 1 + read-write + + + PECERR + PEC error when receiving data + 12 + 1 + read-write + + + OUERR + Overrun/Underrun occurs in slave mode + 11 + 1 + read-write + + + AERR + Acknowledge error + 10 + 1 + read-write + + + LOSTARB + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TBE + I2C_DATA is Empty during transmitting + 7 + 1 + read-only + + + RBNE + I2C_DATA is not Empty during receiving + 6 + 1 + read-only + + + STPDET + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10SEND + Header of 10-bit address is sent in master mode + 3 + 1 + read-only + + + BTC + Byte transmission completed + 2 + 1 + read-only + + + ADDSEND + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SBSEND + Start bit (Master mode) + 0 + 1 + read-only + + + + + STAT1 + STAT1 + Transfer status register 1 + 0x18 + 0x20 + read-only + 0x0000 + + + PECV + Packet error checking + register + 8 + 8 + + + DUMODF + Dual flag (Slave mode) + 7 + 1 + + + HSTSMB + SMBus host header (Slave + mode) + 6 + 1 + + + DEFSMB + SMBus device default address (Slave + mode) + 5 + 1 + + + RXGC + General call address (Slave + mode) + 4 + 1 + + + TR + Transmitter/receiver + 2 + 1 + + + I2CBSY + Bus busy + 1 + 1 + + + MASTER + Master/slave + 0 + 1 + + + + + CKCFG + CKCFG + Clock configure register + 0x1C + 0x20 + read-write + 0x0000 + + + FAST + I2C master mode selection + 15 + 1 + + + DTCY + Fast mode duty cycle + 14 + 1 + + + CLKC + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + RT + RT + Rise time register + 0x20 + 0x20 + read-write + 0x0002 + + + RISETIME + Maximum rise time in master mode + 0 + 7 + + + + + SAMCS + SAMCS + SAM control and status register + 0x80 + 0x20 + read-write + 0x0000 + + + RFR + Rxframe rise flag + 15 + 1 + + + RFF + Rxframe fall flag + 14 + 1 + + + TFR + Txframe rise flag + 13 + 1 + + + TFF + Txframe fall flag + 12 + 1 + + + RXF + level of rx frame signal + 9 + 1 + + + TXF + level of tx frame signal + 8 + 1 + + + RFRIE + Rx frame rise interrupt enable + 7 + 1 + + + RFFIE + Rx frame fall interrupt enable + 6 + 1 + + + TFRIE + Tx frame rise interrupt enable + 5 + 1 + + + TFFIE + Tx frame fall interrupt enable + 4 + 1 + + + STOEN + SAM_V interface timeout detect enable + 1 + 1 + + + SAMEN + SAM_V interface enable + 0 + 1 + + + + + FMPCFG + FMPCFG + Fast-mode-plus configure register + 0x90 + 0x20 + read-write + 0x0000 + + + FMPEN + Fast-mode-plus enable + 0 + 1 + + + + + + + I2C1 + 0x40005800 + + I2C1_EV + 24 + + + I2C1_ER + 34 + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0xF00 + registers + + + 0x33D + 0xC3 + reserved + + + + ISER0 + ISER0 + Interrupt Set Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set Enable Register + 0x04 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set Enable Register + 0x08 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER3 + ISER3 + Interrupt Set Enable Register + 0x0C + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER4 + ISER4 + Interrupt Set Enable Register + 0x10 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER5 + ISER5 + Interrupt Set Enable Register + 0x14 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER6 + ISER6 + Interrupt Set Enable Register + 0x18 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER7 + ISER7 + Interrupt Set Enable Register + 0x1C + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER8 + ISER8 + Interrupt Set Enable Register + 0x20 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER9 + ISER9 + Interrupt Set Enable Register + 0x24 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER10 + ISER10 + Interrupt Set Enable Register + 0x28 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER11 + ISER11 + Interrupt Set Enable Register + 0x2C + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER12 + ISER12 + Interrupt Set Enable Register + 0x30 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER13 + ISER13 + Interrupt Set Enable Register + 0x34 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER14 + ISER14 + Interrupt Set Enable Register + 0x38 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER15 + ISER15 + Interrupt Set Enable Register + 0x3C + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear Enable + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER3 + ICER3 + Interrupt Clear Enable + Register + 0x90 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER4 + ICER4 + Interrupt Clear Enable + Register + 0x94 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER5 + ICER5 + Interrupt Clear Enable + Register + 0x98 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER6 + ICER6 + Interrupt Clear Enable + Register + 0x9C + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER7 + ICER7 + Interrupt Clear Enable + Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER8 + ICER8 + Interrupt Clear Enable + Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER9 + ICER9 + Interrupt Clear Enable + Register + 0xA8 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER10 + ICER10 + Interrupt Clear Enable + Register + 0xAC + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER11 + ICER11 + Interrupt Clear Enable + Register + 0xB0 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER12 + ICER12 + Interrupt Clear Enable + Register + 0xB4 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER13 + ICER13 + Interrupt Clear Enable + Register + 0xB8 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER14 + ICER14 + Interrupt Clear Enable + Register + 0xBC + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER15 + ICER15 + Interrupt Clear Enable + Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR4 + ISPR4 + Interrupt Set-Pending Register + 0x110 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR5 + ISPR5 + Interrupt Set-Pending Register + 0x114 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR6 + ISPR6 + Interrupt Set-Pending Register + 0x118 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR7 + ISPR7 + Interrupt Set-Pending Register + 0x11C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR8 + ISPR8 + Interrupt Set-Pending Register + 0x120 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR9 + ISPR9 + Interrupt Set-Pending Register + 0x124 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR10 + ISPR10 + Interrupt Set-Pending Register + 0x128 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR11 + ISPR11 + Interrupt Set-Pending Register + 0x12C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR12 + ISPR12 + Interrupt Set-Pending Register + 0x130 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR13 + ISPR13 + Interrupt Set-Pending Register + 0x134 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR14 + ISPR14 + Interrupt Set-Pending Register + 0x138 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR15 + ISPR15 + Interrupt Set-Pending Register + 0x13C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR3 + ICPR3 + Interrupt Clear-Pending + Register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR4 + ICPR4 + Interrupt Clear-Pending + Register + 0x190 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR5 + ICPR5 + Interrupt Clear-Pending + Register + 0x194 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR6 + ICPR6 + Interrupt Clear-Pending + Register + 0x198 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR7 + ICPR7 + Interrupt Clear-Pending + Register + 0x19C + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR8 + ICPR8 + Interrupt Clear-Pending + Register + 0x1A0 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR9 + ICPR9 + Interrupt Clear-Pending + Register + 0x1A4 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR10 + ICPR10 + Interrupt Clear-Pending + Register + 0x1A8 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR11 + ICPR11 + Interrupt Clear-Pending + Register + 0x1AC + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR12 + ICPR12 + Interrupt Clear-Pending + Register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR13 + ICPR13 + Interrupt Clear-Pending + Register + 0x1B4 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR14 + ICPR14 + Interrupt Clear-Pending + Register + 0x1B8 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR15 + ICPR15 + Interrupt Clear-Pending + Register + 0x1BC + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active bit + Register + 0x200 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active bit + Register + 0x204 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active bit + Register + 0x208 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR3 + IABR3 + Interrupt Active bit + Register + 0x20C + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR4 + IABR4 + Interrupt Active bit + Register + 0x210 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR5 + IABR5 + Interrupt Active bit + Register + 0x214 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR6 + IABR6 + Interrupt Active bit + Register + 0x218 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR7 + IABR7 + Interrupt Active bit + Register + 0x21C + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR8 + IABR8 + Interrupt Active bit + Register + 0x220 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR9 + IABR9 + Interrupt Active bit + Register + 0x224 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR10 + IABR10 + Interrupt Active bit + Register + 0x228 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR11 + IABR11 + Interrupt Active bit + Register + 0x22C + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR12 + IABR12 + Interrupt Active bit + Register + 0x230 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR13 + IABR13 + Interrupt Active bit + Register + 0x234 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR14 + IABR14 + Interrupt Active bit + Register + 0x238 + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + IABR15 + IABR15 + Interrupt Active bit + Register + 0x23C + 0x20 + read-write + 0x00000000 + + + IABR + IABR + 0 + 32 + + + + + ITNS0 + ITNS0 + Interrupt Active bit + Register + 0x280 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS1 + ITNS1 + Interrupt Active bit + Register + 0x284 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS2 + ITNS2 + Interrupt Active bit + Register + 0x288 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS3 + ITNS3 + Interrupt Active bit + Register + 0x28C + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS4 + ITNS4 + Interrupt Active bit + Register + 0x290 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS5 + ITNS5 + Interrupt Active bit + Register + 0x294 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS6 + ITNS6 + Interrupt Active bit + Register + 0x298 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS7 + ITNS7 + Interrupt Active bit + Register + 0x29C + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS8 + ITNS8 + Interrupt Active bit + Register + 0x2A0 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS9 + ITNS9 + Interrupt Active bit + Register + 0x2A4 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS10 + ITNS10 + Interrupt Active bit + Register + 0x2A8 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS11 + ITNS11 + Interrupt Active bit + Register + 0x2AC + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS12 + ITNS12 + Interrupt Active bit + Register + 0x2B0 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS13 + ITNS13 + Interrupt Active bit + Register + 0x2B4 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS14 + ITNS14 + Interrupt Active bit + Register + 0x2B8 + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + ITNS15 + ITNS15 + Interrupt Active bit + Register + 0x2BC + 0x20 + read-write + 0x00000000 + + + ITNS + ITNS + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register 0 + 0x300 + 0x08 + read-write + 0x00 + + + PRI_00 + PRI_00 + 0 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register 1 + 0x301 + 0x08 + read-write + 0x00 + + + PRI_01 + PRI_01 + 0 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register 2 + 0x302 + 0x08 + read-write + 0x00 + + + PRI_02 + PRI_02 + 0 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register 3 + 0x303 + 0x08 + read-write + 0x00 + + + PRI_03 + PRI_03 + 0 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register 4 + 0x304 + 0x08 + read-write + 0x00 + + + PRI_04 + PRI_04 + 0 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register 5 + 0x305 + 0x08 + read-write + 0x00 + + + PRI_05 + PRI_05 + 0 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register 6 + 0x306 + 0x08 + read-write + 0x00 + + + PRI_06 + PRI_06 + 0 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register 7 + 0x307 + 0x08 + read-write + 0x00 + + + PRI_07 + PRI_07 + 0 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register 8 + 0x308 + 0x08 + read-write + 0x00 + + + PRI_08 + PRI_08 + 0 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register 9 + 0x309 + 0x08 + read-write + 0x00 + + + PRI_09 + PRI_09 + 0 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register 10 + 0x30A + 0x08 + read-write + 0x00 + + + PRI_10 + PRI_10 + 0 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register 11 + 0x30B + 0x08 + read-write + 0x00 + + + PRI_11 + PRI_11 + 0 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register 12 + 0x30C + 0x08 + read-write + 0x00 + + + PRI_12 + PRI_12 + 0 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register 13 + 0x30D + 0x08 + read-write + 0x00 + + + PRI_13 + PRI_13 + 0 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register 14 + 0x30E + 0x08 + read-write + 0x00 + + + PRI_14 + PRI_14 + 0 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register 15 + 0x30F + 0x08 + read-write + 0x00 + + + PRI_15 + PRI_15 + 0 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register 16 + 0x310 + 0x08 + read-write + 0x00 + + + PRI_16 + PRI_16 + 0 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register 17 + 0x311 + 0x08 + read-write + 0x00 + + + PRI_17 + PRI_17 + 0 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register 18 + 0x312 + 0x08 + read-write + 0x00 + + + PRI_18 + PRI_18 + 0 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register 19 + 0x313 + 0x08 + read-write + 0x00 + + + PRI_19 + PRI_19 + 0 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register 20 + 0x314 + 0x08 + read-write + 0x00 + + + PRI_20 + PRI_20 + 0 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register 21 + 0x315 + 0x08 + read-write + 0x00 + + + PRI_21 + PRI_21 + 0 + 8 + + + + + IPR22 + IPR22 + Interrupt Priority Register 22 + 0x316 + 0x08 + read-write + 0x00 + + + PRI_22 + PRI_22 + 0 + 8 + + + + + IPR23 + IPR23 + Interrupt Priority Register 23 + 0x317 + 0x08 + read-write + 0x00 + + + PRI_23 + PRI_23 + 0 + 8 + + + + + IPR24 + IPR24 + Interrupt Priority Register 24 + 0x318 + 0x08 + read-write + 0x00 + + + PRI_24 + PRI_24 + 0 + 8 + + + + + IPR25 + IPR25 + Interrupt Priority Register 25 + 0x319 + 0x08 + read-write + 0x00 + + + PRI_25 + PRI_25 + 0 + 8 + + + + + IPR26 + IPR26 + Interrupt Priority Register 26 + 0x31A + 0x08 + read-write + 0x00 + + + PRI_26 + PRI_26 + 0 + 8 + + + + + IPR27 + IPR27 + Interrupt Priority Register 27 + 0x31B + 0x08 + read-write + 0x00 + + + PRI_27 + PRI_27 + 0 + 8 + + + + + IPR28 + IPR28 + Interrupt Priority Register 28 + 0x31C + 0x08 + read-write + 0x00 + + + PRI_28 + PRI_28 + 0 + 8 + + + + + IPR29 + IPR29 + Interrupt Priority Register 29 + 0x31D + 0x08 + read-write + 0x00 + + + PRI_29 + PRI_29 + 0 + 8 + + + + + IPR30 + IPR30 + Interrupt Priority Register 30 + 0x31E + 0x08 + read-write + 0x00 + + + PRI_30 + PRI_30 + 0 + 8 + + + + + IPR31 + IPR31 + Interrupt Priority Register 31 + 0x31F + 0x08 + read-write + 0x00 + + + PRI_31 + PRI_31 + 0 + 8 + + + + + + + PMU + Power management unit + PMU + 0x40007000 + + 0x0 + 0x400 + registers + + + + CTL + CTL + power control register + 0x0 + 0x20 + read-write + 0x00004000 + + + LDOVS + LDO output voltage select + 14 + 2 + + + BKPWEN + Backup Domain Write Enable + 8 + 1 + + + LVDT + Low Voltage Detector Threshold + 5 + 3 + + + LVDEN + Low Voltage Detector Enable + 4 + 1 + + + STBRST + Standby Flag Reset + 3 + 1 + + + WURST + Wakeup Flag Reset + 2 + 1 + + + STBMOD + Standby Mode + 1 + 1 + + + LDOLP + LDO Low Power Mode + 0 + 1 + + + + + CS + CS + power control/status register + 0x04 + 0x20 + 0x00000000 + + + WUPEN6 + WKUP pin6 Enable + 14 + 1 + read-write + + + WUPEN5 + WKUP pin5 Enable + 13 + 1 + read-write + + + WUPEN1 + WKUP pin1 Enable + 9 + 1 + read-write + + + WUPEN0 + WKUP pin0 Enable + 8 + 1 + read-write + + + LVDF + Low Voltage Detector Status Flag + 2 + 1 + read-only + + + STBF + Standby flag + 1 + 1 + read-only + + + WUF + Wakeup flag + 0 + 1 + read-only + + + + + + + RCU + Reset and clock unit + RCU + 0x40021000 + + 0x0 + 0x400 + registers + + + RCU + 4 + + + + CTL0 + CTL0 + Control register 0 + 0x0 + 0x20 + 0x00000083 + + + PLLSTB + PLL Clock Stabilization Flag + 25 + 1 + read-only + + + PLLEN + PLL enable + 24 + 1 + read-write + + + CKMEN + HXTAL Clock Monitor Enable + 19 + 1 + read-write + + + HXTALBPS + External crystal oscillator (HXTAL) clock bypass mode enable + 18 + 1 + read-write + + + HXTALSTB + External crystal oscillator (HXTAL) clock stabilization flag + 17 + 1 + read-only + + + HXTALEN + External High Speed oscillator Enable + 16 + 1 + read-write + + + IRC8MCALIB + High Speed Internal Oscillator calibration value register + 8 + 8 + read-only + + + IRC8MADJ + High Speed Internal Oscillator clock trim adjust value + 3 + 5 + read-write + + + IRC8MSTB + IRC8M High Speed Internal Oscillator stabilization Flag + 1 + 1 + read-only + + + IRC8MEN + Internal High Speed oscillator Enable + 0 + 1 + read-write + + + + + CFG0 + CFG0 + Clock configuration register 0 + (RCU_CFG0) + 0x04 + 0x20 + 0x00000000 + + + PLLDV + The CK_PLL divide by 1 or 2 for CK_OUT + + 31 + 1 + read-write + + + CKOUTDIV + The CK_OUT divider which the CK_OUT frequency can be reduced + 28 + 3 + read-write + + + PLLMF_MSB + Bit 4 of PLLMF register + 27 + 1 + read-write + + + CKOUTSEL + CK_OUT Clock Source Selection + 24 + 3 + read-write + + + PLLMF + PLL multiply factor + 18 + 4 + read-write + + + PLLPREDV + HXTAL divider for PLL source clock selection. + 17 + 1 + read-write + + + PLLSEL + PLL Clock Source Selection + 16 + 1 + read-write + + + ADCPSC + ADC clock prescaler selection + 14 + 2 + read-write + + + APB2PSC + APB2 prescaler selection + 11 + 3 + read-write + + + APB1PSC + APB1 prescaler selection + 8 + 3 + read-write + + + AHBPSC + AHB prescaler selection + 4 + 4 + read-write + + + SCSS + System clock switch status + 2 + 2 + read-only + + + SCS + System clock switch + 0 + 2 + read-write + + + + + INT + INT + Clock interrupt register + (RCU_INT) + 0x08 + 0x20 + 0x00000000 + + + CKMIC + HXTAL Clock Stuck Interrupt Clear + 23 + 1 + write-only + + + IRC28MSTBIC + IRC28M stabilization Interrupt Clear + 21 + 1 + write-only + + + PLLSTBIC + PLL stabilization Interrupt Clear + 20 + 1 + write-only + + + HXTALSTBIC + HXTAL Stabilization Interrupt Clear + 19 + 1 + write-only + + + IRC8MSTBIC + IRC8M Stabilization Interrupt Clear + 18 + 1 + write-only + + + LXTALSTBIC + LXTAL Stabilization Interrupt Clear + 17 + 1 + write-only + + + IRC40KSTBIC + IRC40K Stabilization Interrupt Clear + 16 + 1 + write-only + + + IRC28MSTBIE + IRC28M Stabilization Interrupt Enable + 13 + 1 + read-write + + + PLLSTBIE + PLL Stabilization Interrupt Enable + 12 + 1 + read-write + + + HXTALSTBIE + HXTAL Stabilization Interrupt Enable + 11 + 1 + read-write + + + IRC8MSTBIE + IRC8M Stabilization Interrupt Enable + 10 + 1 + read-write + + + LXTALSTBIE + LXTAL Stabilization Interrupt Enable + 9 + 1 + read-write + + + IRC40KSTBIE + IRC40K Stabilization interrupt enable + 8 + 1 + read-write + + + CKMIF + HXTAL Clock Stuck Interrupt Flag + 7 + 1 + read-only + + + IRC28MSTBIF + IRC28M stabilization interrupt flag + 5 + 1 + read-only + + + PLLSTBIF + PLL stabilization interrupt flag + 4 + 1 + read-only + + + HXTALSTBIF + HXTAL stabilization interrupt flag + 3 + 1 + read-only + + + IRC8MSTBIF + IRC8M stabilization interrupt flag + 2 + 1 + read-only + + + LXTALSTBIF + LXTAL stabilization interrupt flag + 1 + 1 + read-only + + + IRC40KSTBIF + IRC40K stabilization interrupt flag + 0 + 1 + read-only + + + + + APB2RST + APB2RST + APB2 reset register + (RCU_APB2RST) + 0x0C + 0x20 + read-write + 0x00000000 + + + TIMER16RST + TIMER16 reset + 18 + 1 + + + TIMER15RST + TIMER15 reset + 17 + 1 + + + TIMER14RST + TIMER14 reset + 16 + 1 + + + USART0RST + USART0 Reset + 14 + 1 + + + SPI0RST + SPI0 Reset + 12 + 1 + + + TIMER0RST + TIMER0 reset + 11 + 1 + + + ADCRST + ADC reset + 9 + 1 + + + CFGCMPRST + System configuration and comparator reset + 0 + 1 + + + + + APB1RST + APB1RST + APB1 reset register + (RCU_APB1RST) + 0x10 + 0x20 + read-write + 0x00000000 + + + PMURST + Power control reset + 28 + 1 + + + I2C1RST + I2C1 reset + 22 + 1 + + + I2C0RST + I2C0 reset + 21 + 1 + + + USART1RST + USART1 reset + 17 + 1 + + + SPI1RST + SPI1 reset + 14 + 1 + + + WWDGTRST + Window watchdog timer reset + 11 + 1 + + + TIMER13RST + TIMER13 timer reset + 8 + 1 + + + TIMER5RST + TIMER5 timer reset + 4 + 1 + + + TIMER2RST + TIMER2 timer reset + 1 + 1 + + + + + AHBEN + AHBEN + AHB enable register + (RCU_AHBEN) + 0x14 + 0x20 + read-write + 0x00000014 + + + PFEN + GPIO port F clock enable + 22 + 1 + + + PCEN + GPIO port C clock enable + 19 + 1 + + + PBEN + GPIO port B clock enable + 18 + 1 + + + PAEN + GPIO port A clock enable + 17 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + FMCSPEN + FMC clock during sleep mode enable + 4 + 1 + + + SRAMSPEN + SRAM interface clock during sleep mode enable + 2 + 1 + + + DMAEN + DMA clock enable + 0 + 1 + + + + + APB2EN + APB2EN + APB2 enable register + (RCU_APB2EN) + 0x18 + 0x20 + read-write + 0x00000000 + + + DBGMCUEN + DBGMCU clock enable + 22 + 1 + + + TIMER16EN + TIMER16 timer clock enable + 18 + 1 + + + TIMER15EN + TIMER15 timer clock enable + 17 + 1 + + + TIMER14EN + TIMER14 timer clock enable + 16 + 1 + + + USART0EN + USART0 clock enable + 14 + 1 + + + SPI0EN + SPI0 clock enable + 12 + 1 + + + TIMER0EN + TIMER0 timer clock enable + 11 + 1 + + + ADCEN + ADC interface clock enable + 9 + 1 + + + CFGCMPEN + System configuration and comparator clock enable + 0 + 1 + + + + + APB1EN + APB1EN + APB1 enable register + (RCU_APB1EN) + 0x1C + 0x20 + read-write + 0x00000000 + + + PMUEN + Power interface clock enable + 28 + 1 + + + I2C1EN + I2C1 clock enable + 22 + 1 + + + I2C0EN + I2C0 clock enable + 21 + 1 + + + USART1EN + USART1 clock enable + 17 + 1 + + + SPI1EN + SPI1 clock enable + 14 + 1 + + + WWDGTEN + Window watchdog timer clock enable + 11 + 1 + + + TIMER13EN + TIMER13 timer clock enable + 8 + 1 + + + TIMER5EN + TIMER5 timer clock enable + 4 + 1 + + + TIMER2EN + TIMER2 timer clock enable + 1 + 1 + + + + + BDCTL + BDCTL + Backup domain control register + (RCU_BDCTL) + 0x20 + 0x20 + 0x00000018 + + + BKPRST + Backup domain reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSRC + RTC clock entry selection + 8 + 2 + read-write + + + LXTALDRI + LXTAL drive capability + 3 + 2 + read-write + + + LXTALBPS + LXTAL bypass mode enable + 2 + 1 + read-write + + + LXTALSTB + External low-speed oscillator stabilization + 1 + 1 + read-only + + + LXTALEN + LXTAL enable + 0 + 1 + read-write + + + + + RSTSCK + RSTSCK + Reset source /clock register + (RCU_RSTSCK) + 0x24 + 0x20 + 0x0C000000 + + + LPRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGTRSTF + Window watchdog timer reset flag + 30 + 1 + read-write + + + FWDGTRSTF + Free Watchdog timer reset flag + 29 + 1 + read-write + + + SWRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + Power reset flag + 27 + 1 + read-write + + + EPRSTF + External PIN reset flag + 26 + 1 + read-write + + + OBLRSTF + Option byte loader reset flag + 25 + 1 + read-write + + + RSTFC + Reset flag clear + 24 + 1 + read-write + + + V12RSTF + V12 domain Power reset flag + 23 + 1 + read-write + + + IRC40KSTB + IRC40K stabilization + 1 + 1 + read-only + + + IRC40KEN + IRC40K enable + 0 + 1 + read-write + + + + + AHBRST + AHBRST + AHB reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + PFRST + GPIO port F reset + 22 + 1 + + + PCRST + GPIO port C reset + 19 + 1 + + + PBRST + GPIO port B reset + 18 + 1 + + + PARST + GPIO port A reset + 17 + 1 + + + + + CFG1 + CFG1 + Configuration register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDV + CK_HXTAL or CK_IRC48M divider previous PLL + 0 + 4 + + + + + CFG2 + CFG2 + Configuration register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + ADCPSC + Bit 2 of ADCPSC + 31 + 1 + + + IRC28MDIV + CK_IRC28M divider 2 or not + 16 + 1 + + + ADCSEL + CK_ADC clock source selection + 8 + 1 + + + USART0SEL + CK_USART0 clock source selection + 0 + 2 + + + + + CTL1 + CTL1 + Control register 1 + 0x34 + 0x20 + 0x00000080 + + + IRC28MCALIB + Internal 28M RC Oscillator calibration value register + 8 + 8 + read-only + + + IRC28MADJ + Internal 28M RC Oscillator clock trim adjust value + 3 + 5 + read-write + + + IRC28MSTB + IRC28M Internal 28M RC Oscillator stabilization Flag + 1 + 1 + read-only + + + IRC28MEN + IRC28M Internal 28M RC oscillator Enable + 0 + 1 + read-write + + + + + VKEY + VKEY + Voltage key register + 0x100 + 0x20 + 0x00000000 + + + KEY + The key of RCU_DSV register + 0 + 32 + write + + + + + DSV + DSV + Deep-sleep mode voltage register + 0x134 + 0x20 + 0x00000000 + + + DSLPVS + Deep-sleep mode voltage select + 0 + 2 + read-write + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + 2 + + + + TIME + TIME + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM mark + 22 + 1 + + + HRT + Hour tens in BCD code + 20 + 2 + + + HRU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD code + 12 + 3 + + + MNU + Minute units in BCD code + 8 + 4 + + + SCT + Second tens in BCD code + 4 + 3 + + + SCU + Second units in BCD code + 0 + 4 + + + + + DATE + DATE + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YRT + Year tens in BCD code + 20 + 4 + + + YRU + Year units in BCD code + 16 + 4 + + + DOW + Days of the week + 13 + 3 + + + MONT + Month tens in BCD code + 12 + 1 + + + MONU + Month units in BCD code + 8 + 4 + + + DAYT + Date tens in BCD code + 4 + 2 + + + DAYU + Date units in BCD code + 0 + 4 + + + + + CTL + CTL + control register + 0x8 + 0x20 + 0x00000000 + + + COEN + Calibration output enable + 23 + 1 + read-write + + + OS + Output selection + 21 + 2 + read-write + + + OPOL + Output polarity + 20 + 1 + read-write + + + COS + Calibration output + selection + 19 + 1 + read-write + + + DSM + Backup + 18 + 1 + read-write + + + S1H + Subtract 1 hour (winter time + change) + 17 + 1 + write-only + + + A1H + Add 1 hour (summer time + change) + 16 + 1 + write-only + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + read-write + + + ALRM0IE + Alarm A interrupt enable + 12 + 1 + read-write + + + TSEN + timestamp enable + 11 + 1 + read-write + + + ALRM0EN + Alarm A enable + 8 + 1 + read-write + + + CS + Hour format + 6 + 1 + read-write + + + BPSHAD + Bypass the shadow + registers + 5 + 1 + read-write + + + REFEN + RTC_REFIN reference clock detection + enable (50 or 60 Hz) + 4 + 1 + read-write + + + TSEG + Time-stamp event active + edge + 3 + 1 + read-write + + + + + STAT + STAT + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + SCPF + Recalibration pending Flag + 16 + 1 + read-only + + + TP1F + RTC_TAMP1 detection flag + 14 + 1 + read-write + + + TP0F + RTC_TAMP0 detection flag + 13 + 1 + read-write + + + TSOVRF + Time-stamp overflow flag + 12 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + ALRM0F + Alarm A flag + 8 + 1 + read-write + + + INITM + Initialization mode + 7 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + RSYNF + Registers synchronization + flag + 5 + 1 + read-write + + + YCM + Initialization status flag + 4 + 1 + read-only + + + SOPF + Shift operation pending + 3 + 1 + read-only + + + ALRM0WF + Alarm A write flag + 0 + 1 + read-only + + + + + PSC + PSC + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + FACTOR_A + Asynchronous prescaler + factor + 16 + 7 + + + FACTOR_S + Synchronous prescaler + factor + 0 + 15 + + + + + ALRM0TD + ALRM0TD + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSKD + Alarm date mask + 31 + 1 + + + DOWS + Week day selection + 30 + 1 + + + DAYT + Date tens in BCD format. + 28 + 2 + + + DAYU + Date units or day in BCD + format. + 24 + 4 + + + MSKH + Alarm hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HRT + Hour tens in BCD format. + 20 + 2 + + + HRU + Hour units in BCD format. + 16 + 4 + + + MSKM + Alarm minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format. + 12 + 3 + + + MNU + Minute units in BCD + format. + 8 + 4 + + + MSKS + Alarm seconds mask + 7 + 1 + + + SCT + Second tens in BCD format. + 4 + 3 + + + SCU + Second units in BCD + format. + 0 + 4 + + + + + WPK + WPK + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + WPK + Write protection key + 0 + 8 + + + + + SS + SS + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SSC + Sub second value + 0 + 16 + + + + + SHIFTCTL + SHIFTCTL + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + A1S + One second add + 31 + 1 + + + SFS + Subtract a fraction of a + second + 0 + 15 + + + + + TTS + TTS + timestamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + PM + AM/PM mark + 22 + 1 + + + HRT + Hour tens in BCD code + 20 + 2 + + + HRU + Hour units in BCD code + 16 + 4 + + + MNT + Minute tens in BCD code + 12 + 3 + + + MNU + Minute units in BCD code + 8 + 4 + + + SCT + Second tens in BCD code + 4 + 3 + + + SCU + Second units in BCD code + 0 + 4 + + + + + DTS + DTS + Date of time stamp register + 0x34 + 0x20 + read-only + 0x00000000 + + + DOW + Week day units + 13 + 3 + + + MONT + Month tens in BCD code + 12 + 1 + + + MONU + Month units in BCD code + 8 + 4 + + + DAYT + Date tens in BCD code + 5 + 2 + + + DAYU + Date units in BCD code + 0 + 5 + + + + + SSTS + SSTS + time-stamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SSC + Sub second value + 0 + 16 + + + + + HRFC + HRFC + High resolution frequency compensation register + 0x3C + 0x20 + read-write + 0x00000000 + + + FREQI + Increase RTC frequency by 488.5PPM + 15 + 1 + + + CWND8 + Frequency compensation window 8 second selected + 14 + 1 + + + CWND16 + Frequency compensation window 16 second selected + 13 + 1 + + + CMSK + Calibration mask number + 0 + 9 + + + + + TAMP + TAMP + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + PC15MDE + PC15 mode + 23 + 1 + + + PC15VAL + PC15 value + 22 + 1 + + + PC14MDE + PC14 mode + 21 + 1 + + + PC14VAL + PC14 value + 20 + 1 + + + PC13MDE + PC13 mode + 19 + 1 + + + PC13VAL + RTC_ALARM output type/PC13 + value + 18 + 1 + + + DISPU + RTC_TAMPx pull-up disable + 15 + 1 + + + PRCH + RTC_TAMPx precharge + duration + 13 + 2 + + + FLT + RTC_TAMPx filter count + 11 + 2 + + + FREQ + Tamper sampling frequency + 8 + 3 + + + TPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TP1EG + Tamper 1 event trigger edge + 4 + 1 + + + TP1EN + Tamper 1 detection enable + 3 + 1 + + + TPIE + Tamper detection interrupt enable + 2 + 1 + + + TP0EG + Active level for RTC_TAMP1 + input + 1 + 1 + + + TP0EN + Tamper 0 event trigger edge + 0 + 1 + + + + + ALRM0SS + ALRM0SS + alarm 0 sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MSKSSC + Mask control bit of SSC + 24 + 4 + + + SSC + Alarm sub second value + 0 + 15 + + + + + BKP0 + BKP0 + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + DATA + BKP data + 0 + 32 + + + + + BKP1 + BKP1 + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + DATA + BKP data + 0 + 32 + + + + + BKP2 + BKP2 + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + DATA + BKP data + 0 + 32 + + + + + BKP3 + BKP3 + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + DATA + BKP data + 0 + 32 + + + + + BKP4 + BKP4 + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + DATA + BKP data + 0 + 32 + + + + + + + SPI0 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI0 + 25 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + BDEN + Bidirectional enable + 15 + 1 + + + BDOEN + Bidirectional Transmit output enable + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNT + CRC transfer next + 12 + 1 + + + FF16 + Data frame format + 11 + 1 + + + RO + Receive only + 10 + 1 + + + SWNSSEN + NSS Software Mode Selection + 9 + 1 + + + SWNSS + NSS Pin Selection In NSS Software Mode + 8 + 1 + + + LF + LSB First Mode + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + PSC + Master Clock Prescaler Selection + 3 + 3 + + + MSTMOD + Master Mode Enable + 2 + 1 + + + CKPL + Clock Polarity Selection + 1 + 1 + + + CKPH + Clock Phase Selection + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + TBEIE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + + + RBNEIE + Receive Buffer Not Empty Interrupt Enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TMOD + SPI TI Mode Enable + 4 + 1 + + + NSSP + SPI NSS Pulse Mode Enable + 3 + 1 + + + NSSDRV + NSS output enable + 2 + 1 + + + DMATEN + Tx buffer DMA enable + 1 + 1 + + + DMAREN + Rx buffer DMA enable + 0 + 1 + + + + + STAT + STAT + status register + 0x08 + 0x20 + 0x0002 + + + FERR + Format Error + 8 + 1 + read-write + + + TRANS + Transmitting On-going Bit + 7 + 1 + read-only + + + RXORERR + Reception Overrun Error Bit + 6 + 1 + read-only + + + CONFERR + SPI Configuration error + 5 + 1 + read-only + + + CRCERR + SPI CRC Error Bit + 4 + 1 + read-write + + + TXURERR + Transmission underrun error bit + 3 + 1 + read-only + + + I2SCH + I2S channel side + 2 + 1 + read-only + + + TBE + Transmit Buffer Empty + 1 + 1 + read-only + + + RBNE + Receive Buffer Not Empty + 0 + 1 + read-only + + + + + DATA + DATA + data register + 0x0C + 0x20 + read-write + 0x0000 + + + DATA + Data register + 0 + 16 + + + + + CPCPOLY + CPCPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRC + RCRC + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + RX RCR register + 0 + 16 + + + + + TCRC + TCRC + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Tx CRC register + 0 + 16 + + + + + I2SCTL + I2SCTL + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SSEL + I2S mode selection + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + I2SOPMOD + I2S configuration mode + 8 + 2 + + + PCMSMOD + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPL + Idle state clock polarity + 3 + 1 + + + DTLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPSC + I2SPSC + I2S prescaler register + 0x20 + 0x20 + read-write + 0x0002 + + + MCKOEN + I2S_MCK output enable + 9 + 1 + + + OF + Odd factor for the + prescaler + 8 + 1 + + + DIV + Dividing factor for the prescaler + 0 + 8 + + + + + + + SPI1 + Serial Peripheral Interface 1 + 0x40003800 + + 0x0 + 0x400 + registers + + + SPI1 + 26 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + BDEN + Bidirectional enable + 15 + 1 + + + BDOEN + Bidirectional Transmit output enable + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNT + CRC transfer next + 12 + 1 + + + CRCL + CRC length + 11 + 1 + + + RO + Receive only + 10 + 1 + + + SWNSSEN + NSS Software Mode Selection + 9 + 1 + + + SWNSS + NSS Pin Selection In NSS Software Mode + 8 + 1 + + + LF + LSB First Mode + 7 + 1 + + + SPIEN + SPI enable + 6 + 1 + + + PSC + Master Clock Prescaler Selection + 3 + 3 + + + MSTMOD + Master Mode Enable + 2 + 1 + + + CKPL + Clock Polarity Selection + 1 + 1 + + + CKPH + Clock Phase Selection + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + TXDMA_ODD + Odd bytes in TX DMA channel + 14 + 1 + + + RXDMA_ODD + Odd bytes in RX DMA channel + 13 + 1 + + + BYTEN + Byte access enable + 12 + 1 + + + DZ + Date size + 8 + 4 + + + TBEIE + Transmit Buffer Empty Interrupt Enable + 7 + 1 + + + RBNEIE + Receive Buffer Not Empty Interrupt Enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + TMOD + SPI TI Mode Enable + 4 + 1 + + + NSSP + SPI NSS Pulse Mode Enable + 3 + 1 + + + NSSDRV + NSS output enable + 2 + 1 + + + DMATEN + Tx buffer DMA enable + 1 + 1 + + + DMAREN + Rx buffer DMA enable + 0 + 1 + + + + + STAT + STAT + status register + 0x08 + 0x20 + 0x0002 + + + TXLVL + Tx FIFO level + 11 + 2 + read-only + + + RXLVL + Rx FIFO level + 9 + 2 + read-only + + + FERR + Format Error + 8 + 1 + read-write + + + TRANS + Transmitting On-going Bit + 7 + 1 + read-only + + + RXORERR + Reception Overrun Error Bit + 6 + 1 + read-only + + + CONFERR + SPI Configuration error + 5 + 1 + read-only + + + CRCERR + SPI CRC Error Bit + 4 + 1 + read-write + + + TBE + Transmit Buffer Empty + 1 + 1 + read-only + + + RBNE + Receive Buffer Not Empty + 0 + 1 + read-only + + + + + DATA + DATA + data register + 0x0C + 0x20 + read-write + 0x0000 + + + DATA + Data register + 0 + 16 + + + + + CPCPOLY + CPCPOLY + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RCRC + RCRC + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RCRC + RX RCR register + 0 + 16 + + + + + TCRC + TCRC + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TCRC + Tx CRC register + 0 + 16 + + + + + I2SCTL + I2SCTL + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SSEL + I2S mode selection + 11 + 1 + + + I2SEN + I2S Enable + 10 + 1 + + + I2SOPMOD + I2S configuration mode + 8 + 2 + + + PCMSMOD + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPL + Idle state clock polarity + 3 + 1 + + + DTLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPSC + I2SPSC + I2S prescaler register + 0x20 + 0x20 + read-write + 0x0002 + + + MCKOEN + I2S_MCK output enable + 9 + 1 + + + OF + Odd factor for the + prescaler + 8 + 1 + + + DIV + Dividing factor for the prescaler + 0 + 8 + + + + + QCTL + QCTL + SPI quad wird control register + 0x80 + 0x20 + read-write + 0000 + + + IO23_DRV + Drive IO2 and IO3 enable + 2 + 1 + + + QRD + Quad wire read select + 1 + 1 + + + QMOD + Quad wire mode enable + 0 + 1 + + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x0400 + registers + + + + CFG0 + CFG0 + System configuration register 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + PB9_HCCE + PB9 pin high current capability enable + 19 + 1 + + + TIMER16_DMA_RMP + Timer 16 DMA request remapping enable + 12 + 1 + + + TIMER15_DMA_RMP + Timer 15 DMA request remapping enable + 11 + 1 + + + USART0_RX_DMA_RMP + USART0_RX DMA request remapping enable + 10 + 1 + + + USART0_TX_DMA_RMP + USART0_TX DMA request remapping enable + 9 + 1 + + + ADC_DMA_RMP + ADC DMA request remapping enable + 8 + 1 + + + PA11_PA12_RMP + PA11 and PA12 remapping bit for small packages + 4 + 1 + + + BOOT_MODE + Boot mode + 0 + 2 + read-only + + + + + EXTISS0 + EXTISS0 + EXTI sources selection register + 0 + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI3_SS + EXTI 3 sources selection + 12 + 4 + + + EXTI2_SS + EXTI 2 sources selection + 8 + 4 + + + EXTI1_SS + EXTI 1 sources selection + 4 + 4 + + + EXTI0_SS + EXTI 0 sources selection + 0 + 4 + + + + + EXTISS1 + EXTISS1 + EXTI sources selection register + 1 + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI7_SS + EXTI 7 sources selection + 12 + 4 + + + EXTI6_SS + EXTI 6 sources selection + 8 + 4 + + + EXTI5_SS + EXTI 5 sources selection + 4 + 4 + + + EXTI4_SS + EXTI 4 sources selection + 0 + 4 + + + + + EXTISS2 + EXTISS2 + EXTI sources selection register + 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI11_SS + EXTI 11 sources selection + 12 + 4 + + + EXTI10_SS + EXTI 10 sources selection + 8 + 4 + + + EXTI9_SS + EXTI 9 sources selection + 4 + 4 + + + EXTI8_SS + EXTI 8 sources selection + 0 + 4 + + + + + EXTISS3 + EXTISS3 + EXTI sources selection register + 3 + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI15_SS + EXTI 15 sources selection + 12 + 4 + + + EXTI14_SS + EXTI 14 sources selection + 8 + 4 + + + EXTI13_SS + EXTI 13 sources selection + 4 + 4 + + + EXTI12_SS + EXTI 12 sources selection + 0 + 4 + + + + + CFG2 + CFG2 + System configuration register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SRAM_PCEF + SRAM parity check error flag + 8 + 1 + + + LVD_LOCK + LVD lock + 2 + 1 + + + SRAM_PARITY_ERROR_LOCK + SRAM parity check error lock + 1 + 1 + + + LOCKUP_LOCK + Cortex-M4 LOCKUP output lock + 0 + 1 + + + + + CPU_IRQ_LAT + CPU_IRQ_LAT + IRQ Latency register + 0x100 + 0x20 + read-write + 0x00000000 + + + IRQ_LATENCY + specifies the minimum number of cycles between an interrupt + 0 + 8 + + + + + + + TIMER0 + Advanced-timers + TIMER + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIMER0_BRK_UP_TRG_COM + 13 + + + TIMER0_CC + 14 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + CAM + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + One-pulse mode + 3 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + ISO3 + Idle state of channel 3 output + 14 + 1 + + + ISO2N + Idle state of channel 2 complementary output + 13 + 1 + + + ISO2 + Idle state of channel 2 output + 12 + 1 + + + ISO1N + Idle state of channel 1 complementary output + 11 + 1 + + + ISO1 + Idle state of channel 1 output + 10 + 1 + + + ISO0N + Idle state of channel 0 complementary output + 9 + 1 + + + ISO0 + Idle state of channel 0 output + 8 + 1 + + + TI0S + Channel 0 trigger input selection + 7 + 1 + + + MMC + Master mode control + 4 + 3 + + + DMAS + DMA request source selection + 3 + 1 + + + CCUC + Commutation control shadow register update control + 2 + 1 + + + CCSE + Commutation control shadow enable + 0 + 1 + + + + + SMCFG + SMCFG + slave mode configuration register + 0x08 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SCM1 + Part of SMC for enable External clock mode1 + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + OCRC + Trigger selection + 3 + 1 + + + SMC + Slave mode selection + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CMTDEN + Reserved + 13 + 1 + + + CH3DEN + Capture/Compare 3 DMA request + enable + 12 + 1 + + + CH2DEN + Capture/Compare 2 DMA request + enable + 11 + 1 + + + CH1DEN + Capture/Compare 1 DMA request + enable + 10 + 1 + + + CH0DEN + Capture/Compare 0 DMA request + enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + BRKIE + Break interrupt enable + 7 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CMTIE + COM interrupt enable + 5 + 1 + + + CH3IE + Capture/Compare 3 interrupt + enable + 4 + 1 + + + CH2IE + Capture/Compare 2 interrupt + enable + 3 + 1 + + + CH1IE + Capture/Compare 1 interrupt + enable + 2 + 1 + + + CH0IE + Capture/Compare 0 interrupt + enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CH3OF + Channel 3 over capture flag + 12 + 1 + + + CH2OF + Channel 2 over capture flag + 11 + 1 + + + CH1OF + Channel 1 over capture flag + 10 + 1 + + + CH0OF + Channel 0 over capture flag + 9 + 1 + + + BRKIF + Break interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CMTIF + COM interrupt flag + 5 + 1 + + + CH3IF + Capture/Compare 3 interrupt + flag + 4 + 1 + + + CH2IF + Capture/Compare 2 interrupt + flag + 3 + 1 + + + CH1IF + Capture/Compare 1 interrupt + flag + 2 + 1 + + + CH0IF + Capture/compare 0 interrupt + flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + Software event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BRKG + Break event generation + 7 + 1 + + + TRGG + Trigger event generation + 6 + 1 + + + CMTG + Channel commutation event generation + 5 + 1 + + + CH3G + Channel 3's capture or compare event generation + 4 + 1 + + + CH2G + Channel 2's capture or compare event generation + 3 + 1 + + + CH1G + Channel 1's capture or compare event generation + 2 + 1 + + + CH0G + Channel 0's capture or compare event generation + 1 + 1 + + + UPG + Update event generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + CH1COMCEN + Channel 1 output compare clear enable + 15 + 1 + + + CH1COMCTL + Channel 1 compare output control + 12 + 3 + + + CH1COMSEN + Channel 1 output compare shadow enable + 11 + 1 + + + CH1COMFEN + Channel 1 output compare fast enable + 10 + 1 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0COMCEN + Channel 0 output compare clear enable + 7 + 1 + + + CH0COMCTL + Channel 0 compare output control + 4 + 3 + + + CH0COMSEN + Channel 0 compare output shadow enable + 3 + 1 + + + CH0COMFEN + Channel 0 output compare fast enable + 2 + 1 + + + CH0MS + Channel 0 I/O mode selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + capture/compare mode register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x20 + read-write + 0x0000 + + + CH1CAPFLT + Channel 1 input capture filter control + 12 + 4 + + + CH1CAPPSC + Channel 1 input capture prescaler + 10 + 2 + + + CH1MS + Channel 1 mode selection + 8 + 2 + + + CH0CAPFLT + Channel 0 input capture filter control + 4 + 4 + + + CH0CAPPSC + Channel 0 input capture prescaler + 2 + 2 + + + CH0MS + Channel 0 mode selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + CH3COMCEN + Channel 3 output compare clear enable + 15 + 1 + + + CH3COMCTL + Channel 3 compare output control + 12 + 3 + + + CH3COMSEN + Channel 3 output compare shadow enable + 11 + 1 + + + CH3COMFEN + Channel 3 output compare fast enable + 10 + 1 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2COMCEN + Channel 2 output compare clear enable + 7 + 1 + + + CH2COMCTL + Channel 2 compare output control + 4 + 3 + + + CH2COMSEN + Channel 2 compare output shadow enable + 3 + 1 + + + CH2COMFEN + Channel 2 output compare fast enable + 2 + 1 + + + CH2MS + Channel 2 I/O mode selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + capture/compare mode register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x20 + read-write + 0x0000 + + + CH3CAPFLT + Channel 3 input capture filter control + 12 + 4 + + + CH3CAPPSC + Channel 3 input capture prescaler + 10 + 2 + + + CH3MS + Channel 3 mode selection + 8 + 2 + + + CH2CAPFLT + Input capture 2 filter + 4 + 4 + + + CH2CAPPSC + Input capture 2 prescaler + 2 + 2 + + + CH2MS + Capture/compare 2 + selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CH3P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CH3EN + Capture/Compare 3 output + enable + 12 + 1 + + + CH2NP + Capture/Compare 2 output + Polarity + 11 + 1 + + + CH2NEN + Capture/Compare 2 complementary output + enable + 10 + 1 + + + CH2P + Capture/Compare 2 output + Polarity + 9 + 1 + + + CH2EN + Capture/Compare 2 output + enable + 8 + 1 + + + CH1NP + Capture/Compare 1 output + Polarity + 7 + 1 + + + CH1NEN + Capture/Compare 1 complementary output + enable + 6 + 1 + + + CH1P + Capture/Compare 1 output + Polarity + 5 + 1 + + + CH1EN + Capture/Compare 1 output + enable + 4 + 1 + + + CH0NP + Capture/Compare 0 output + Polarity + 3 + 1 + + + CH0NEN + Capture/Compare 0 complementary output + enable + 2 + 1 + + + CH0P + Capture/Compare 0 output + Polarity + 1 + 1 + + + CH0EN + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + CARL + Counter auto reload value + 0 + 16 + + + + + CREP + CREP + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + CREP + Repetition counter value + 0 + 8 + + + + + CH0CV + CH0CV + capture/compare register 0 + 0x34 + 0x20 + read-write + 0x0000 + + + CH0VAL + Capture/Compare 0 value + 0 + 16 + + + + + CH1CV + CH1CV + capture/compare register 1 + 0x38 + 0x20 + read-write + 0x0000 + + + CH1VAL + Capture/Compare 1 value + 0 + 16 + + + + + CH2CV + CH2CV + capture/compare register 2 + 0x3C + 0x20 + read-write + 0x0000 + + + CH2VAL + Capture/Compare 2 value + 0 + 16 + + + + + CH3CV + CH3CV + capture/compare register 3 + 0x40 + 0x20 + read-write + 0x0000 + + + CH3VAL + Capture/Compare 3 value + 0 + 16 + + + + + CCHP + CCHP + channel complementary protection register + 0x44 + 0x20 + read-write + 0x0000 + + + POEN + Main output enable + 15 + 1 + + + OAEN + Automatic output enable + 14 + 1 + + + BRKP + Break polarity + 13 + 1 + + + BRKEN + Break enable + 12 + 1 + + + ROS + Off-state selection for Run + mode + 11 + 1 + + + IOS + Off-state selection for Idle + mode + 10 + 1 + + + PROT + Lock configuration + 8 + 2 + + + DTCFG + Dead-time generator setup + 0 + 8 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x20 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA register for burst + accesses + 0 + 16 + + + + + CFG + CFG + Configuration register + 0xFC + 0x20 + read-write + 0x0000 + + + CHVSEL + Write CHxVAL register selection + 1 + 1 + + + OUTSEL + The output value selection + 0 + 1 + + + + + + + TIMER2 + General-purpose-timers + TIMER + 0x40000400 + + 0x0 + 0x400 + registers + + + TIMER2 + 16 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + CAM + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + SPM + One-pulse mode + 3 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + TI0S + TI0 selection + 7 + 1 + + + MMC + Master mode selection + 4 + 3 + + + DMAS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCFG + SMCFG + slave mode control register + 0x08 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + SMC1 + External clock enable + 14 + 1 + + + ETPSC + External trigger prescaler + 12 + 2 + + + ETFC + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + OCRC + OCREF clear source selection + 3 + 1 + + + SMC + Slave mode selection + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CH3DEN + Capture/Compare 3 DMA request + enable + 12 + 1 + + + CH2DEN + Capture/Compare 2 DMA request + enable + 11 + 1 + + + CH1DEN + Capture/Compare 1 DMA request + enable + 10 + 1 + + + CH0DEN + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CH3IE + Capture/Compare 3 interrupt + enable + 4 + 1 + + + CH2IE + Capture/Compare 2 interrupt + enable + 3 + 1 + + + CH1IE + Capture/Compare 1 interrupt + enable + 2 + 1 + + + CH0IE + Capture/Compare 0 interrupt + enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x20 + read-write + 0x0000 + + + CH3OF + Capture/Compare 3 overcapture + flag + 12 + 1 + + + CH2OF + Capture/Compare 2 overcapture + flag + 11 + 1 + + + CH1OF + Capture/compare 1 overcapture + flag + 10 + 1 + + + CH0OF + Capture/Compare 0 overcapture + flag + 9 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CH3IF + Capture/Compare 3 interrupt + flag + 4 + 1 + + + CH2IF + Capture/Compare 2 interrupt + flag + 3 + 1 + + + CH1IF + Capture/Compare 1 interrupt + flag + 2 + 1 + + + CH0IF + Capture/compare 0 interrupt + flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TRGG + Trigger generation + 6 + 1 + + + CH3G + Capture/compare 3 + generation + 4 + 1 + + + CH2G + Capture/compare 2 + generation + 3 + 1 + + + CH1G + Capture/compare 1 + generation + 2 + 1 + + + CH0G + Capture/compare 0 + generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + capture/compare mode register 0 (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + CH1COMCEN + Output compare 1 clear + enable + 15 + 1 + + + CH1COMCTL + Output compare 1 mode + 12 + 3 + + + CH1COMSEN + Output compare 1 preload + enable + 11 + 1 + + + CH1COMFEN + Output compare 1 fast + enable + 10 + 1 + + + CH1MS + Capture/Compare 1 + selection + 8 + 2 + + + CH0COMCEN + Output compare 0 clear + enable + 7 + 1 + + + CH0COMCTL + Output compare 0 mode + 4 + 3 + + + CH0COMSEN + Output compare 0 preload + enable + 3 + 1 + + + CH0COMFEN + Output compare 0 fast + enable + 2 + 1 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + capture/compare mode register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + CH1CAPFLT + Input capture 1 filter + 12 + 4 + + + CH1CAPPSC + Input capture 1 prescaler + 10 + 2 + + + CH1MS + Capture/compare 1 + selection + 8 + 2 + + + CH0CAPFLT + Input capture 0 filter + 4 + 4 + + + CH0CAPPSC + Input capture 0 prescaler + 2 + 2 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL1_Output + CHCTL1_Output + capture/compare mode register 1 (output + mode) + 0x1C + 0x20 + read-write + 0x0000 + + + CH3COMCEN + Output compare 3 clear + enable + 15 + 1 + + + CH3COMCTL + Output compare 3 mode + 12 + 3 + + + CH3COMSEN + Output compare 3 preload + enable + 11 + 1 + + + CH3COMFEN + Output compare 3 fast + enable + 10 + 1 + + + CH3MS + Capture/Compare 3 + selection + 8 + 2 + + + CH2COMCEN + Output compare 2 clear + enable + 7 + 1 + + + CH2COMCTL + Output compare 2 mode + 4 + 3 + + + CH2COMSEN + Output compare 2 preload + enable + 3 + 1 + + + CH2COMFEN + Output compare 2 fast + enable + 2 + 1 + + + CH2MS + Capture/Compare 2 + selection + 0 + 2 + + + + + CHCTL1_Input + CHCTL1_Input + capture/compare mode register 1 (input + mode) + CHCTL1_Output + 0x1C + 0x20 + read-write + 0x0000 + + + CH3CAPFLT + Input capture 3 filter + 12 + 4 + + + CH3CAPPSC + Input capture 3 prescaler + 10 + 2 + + + CH3MS + Capture/Compare 3 + selection + 8 + 2 + + + CH2CAPFLT + Input capture 2 filter + 4 + 4 + + + CH2CAPPSC + Input capture 2 prescaler + 2 + 2 + + + CH2MS + Capture/Compare 2 + selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CH3NP + Capture/Compare 3 output + Polarity + 15 + 1 + + + CH3P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CH3EN + Capture/Compare 3 output + enable + 12 + 1 + + + CH2NP + Capture/Compare 2 output + Polarity + 11 + 1 + + + CH2P + Capture/Compare 2 output + Polarity + 9 + 1 + + + CH2EN + Capture/Compare 2 output + enable + 8 + 1 + + + CH1NP + Capture/Compare 1 output + Polarity + 7 + 1 + + + CH1P + Capture/Compare 1 output + Polarity + 5 + 1 + + + CH1EN + Capture/Compare 1 output + enable + 4 + 1 + + + CH0NP + Capture/Compare 0 output + Polarity + 3 + 1 + + + CH0P + Capture/Compare 0 output + Polarity + 1 + 1 + + + CH0EN + Capture/Compare 0 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + CARL + Low Auto-reload value + 0 + 16 + + + + + CH0CV + CH0CV + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CH0VAL + Low Capture/Compare 1 + value + 0 + 16 + + + + + CH1CV + CH1CV + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CH1VAL + Low Capture/Compare 2 + value + 0 + 16 + + + + + CH2CV + CH2CV + capture/compare register 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + CH2VAL + High Capture/Compare value (TIM2 + only) + 0 + 16 + + + + + CH3CV + CH3CV + capture/compare register 3 + 0x40 + 0x20 + read-write + 0x00000000 + + + CH3VAL + High Capture/Compare value (TIM2 + only) + 0 + 16 + + + + + DMACFG + DMACFG + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DMATC + DMA burst length + 8 + 5 + + + DMATA + DMA base address + 0 + 5 + + + + + DMATB + DMATB + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA register for burst + accesses + 0 + 16 + + + + + CFG + CFG + Configuration + 0xFC + 0x20 + read-write + 0x0000 + + + CHVSEL + Write CHxVAL register selection + 1 + 1 + + + + + + + TIMER5 + Basic-timers + TIMER + 0x40001000 + + 0x0 + 0x400 + registers + + + TIMER5 + 17 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + SPM + One-pulse mode + 3 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + MMC + Master mode selection + 4 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + UPDEN + Update DMA request enable + 8 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UPG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + CARL + Low Auto-reload value + 0 + 16 + + + + + + + TIMER13 + General-purpose-timers + TIMER + 0x40002000 + + 0x0 + 0x400 + registers + + + TIMER13 + 19 + + + + CTL0 + CTL0 + control register 1 + 0x00 + 0x20 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + CH0IE + Capture/Compare 0 interrupt + enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x20 + read-write + 0x0000 + + + CH0OF + Capture/Compare 0 overcapture + flag + 9 + 1 + + + CH0IF + Capture/compare 0 interrupt + flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CH0G + Capture/compare 0 + generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x0000 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + CH0COMFEN + Output compare 0 fast + enable + 2 + 1 + + + CH0COMSEN + Output Compare 0 preload + enable + 3 + 1 + + + CH0COMCTL + Output Compare 0 mode + 4 + 3 + + + + + CHCTL0_Input + CHCTL0_Input + capture/compare mode register (input + mode) + CHCTL0_Output + 0x18 + 0x20 + read-write + 0x0000 + + + CH0CAPFLT + Input capture 0 filter + 4 + 4 + + + CH0CAPPSC + Input capture 0 prescaler + 2 + 2 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CH0NP + Capture/Compare 0 output + Polarity + 3 + 1 + + + CH0P + Capture/Compare 0 output + Polarity + 1 + 1 + + + CH0EN + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000 + + + CARL + Auto-reload value + 0 + 16 + + + + + CH0CV + CH0CV + capture/compare register 0 + 0x34 + 0x20 + read-write + 0x0000 + + + CH0VAL + Capture/Compare 1 value + 0 + 16 + + + + + IRMP + IRMP + channel input remap register + 0x50 + 0x20 + read-write + 0x0000 + + + CI0_RMP + Timer input 0 remap + 0 + 2 + + + + + CFG + CFG + configuration register + 0xFC + 0x20 + read-write + 0x0000 + + + CHVSEL + Write CHxVAL register selection + 1 + 1 + + + + + + + TIMER14 + General-purpose-timers + TIMER + 0x40014000 + + 0x0 + 0x400 + registers + + + TIMER14 + 20 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + SPM + One-pulse mode + 3 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x4 + 0x20 + read-write + 0x0000 + + + ISO1 + Output Idle state 1 + 10 + 1 + + + ISO0N + Output Idle state 0 + 9 + 1 + + + ISO0 + Output Idle state 0 + 8 + 1 + + + MMC + Master mode selection + 4 + 3 + + + DMAS + Capture/compare DMA + selection + 3 + 1 + + + CCUC + Capture/compare control update + selection + 2 + 1 + + + CCSE + Capture/compare preloaded + control + 0 + 1 + + + + + SMCFG + SMCFG + slave mode configuration register + 0x08 + 0x20 + read-write + 0x0000 + + + MSM + Master/Slave mode + 7 + 1 + + + TRGS + Trigger selection + 4 + 3 + + + SMC + Slave mode selection + 0 + 3 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + TRGDEN + Trigger DMA request enable + 14 + 1 + + + CMTDEN + Commutation DMA request enable + 13 + 1 + + + CH1DEN + Capture/Compare 1 DMA request + enable + 10 + 1 + + + CH0DEN + Capture/Compare 0 DMA request + enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + BRKIE + Break interrupt enable + 7 + 1 + + + TRGIE + Trigger interrupt enable + 6 + 1 + + + CMTIE + COM interrupt enable + 5 + 1 + + + CH1IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CH0IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x20 + read-write + 0x0000 + + + CH1OF + Capture/compare 1 overcapture + flag + 10 + 1 + + + CH0OF + Capture/Compare 0 overcapture + flag + 9 + 1 + + + BRKIF + Break interrupt flag + 7 + 1 + + + TRGIF + Trigger interrupt flag + 6 + 1 + + + CMTIF + COM interrupt flag + 5 + 1 + + + CH1IF + Capture/Compare 1 interrupt + flag + 2 + 1 + + + CH0IF + Capture/compare 0 interrupt + flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BRKG + Break generation + 7 + 1 + + + TRGG + Trigger generation + 6 + 1 + + + CMTG + Capture/Compare control update + generation + 5 + 1 + + + CH1G + Capture/compare 1 + generation + 2 + 1 + + + CH0G + Capture/compare 0 + generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CH1COMCTL + Output Compare 1 mode + 12 + 3 + + + CH1COMSEN + Output Compare 1 preload + enable + 11 + 1 + + + CH1COMFEN + Output Compare 1 fast + enable + 10 + 1 + + + CH1MS + Capture/Compare 1 + selection + 8 + 2 + + + CH0COMCTL + Output Compare 0 mode + 4 + 3 + + + CH0COMSEN + Output Compare 0 preload + enable + 3 + 1 + + + CH0COMFEN + Output Compare 0 fast + enable + 2 + 1 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + capture/compare mode register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + CH1CAPFLT + Input capture 1 filter + 12 + 4 + + + CH1CAPPSC + Input capture 1 prescaler + 10 + 2 + + + CH1MS + Capture/Compare 1 + selection + 8 + 2 + + + CH0CAPFLT + Input capture 0 filter + 4 + 4 + + + CH0CAPPSC + Input capture 0 prescaler + 2 + 2 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CH1NP + Capture/Compare 1 output + Polarity + 7 + 1 + + + CH1P + Capture/Compare 1 output + Polarity + 5 + 1 + + + CH1EN + Capture/Compare 1 output + enable + 4 + 1 + + + CH0NP + Capture/Compare 0 output + Polarity + 3 + 1 + + + CH0NEN + Capture/Compare 0 complementary output + enable + 2 + 1 + + + CH0P + Capture/Compare 0 output + Polarity + 1 + 1 + + + CH0EN + Capture/Compare 0 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + CARL + Auto-reload value + 0 + 16 + + + + + CREP + CREP + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + CREP + Repetition counter value + 0 + 8 + + + + + CH0CV + CH0CV + capture/compare register 0 + 0x34 + 0x20 + read-write + 0x00000000 + + + CH0VAL + Capture/Compare 0 value + 0 + 16 + + + + + CH1CV + CH1CV + capture/compare register 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + CH1VAL + Capture/Compare 1 value + 0 + 16 + + + + + CCHP + CCHP + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + POEN + Main output enable + 15 + 1 + + + OAEN + Automatic output enable + 14 + 1 + + + BRKP + Break polarity + 13 + 1 + + + BRKEN + Break enable + 12 + 1 + + + ROS + Off-state selection for Run + mode + 11 + 1 + + + IOS + Off-state selection for Idle + mode + 10 + 1 + + + PROT + complementary register protect control + 8 + 2 + + + DTCFG + Dead-time generator configure + 0 + 8 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x20 + read-write + 0x0000 + + + DMATC + DMA burst length + 8 + 5 + + + DMATA + DMA base address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA register for burst + accesses + 0 + 16 + + + + + CFG + CFG + configuration register + 0xFC + 0x20 + read-write + 0x0000 + + + CHVSEL + Write CHxVAL register selection + 1 + 1 + + + OUTSEL + The output value selection + 0 + 1 + + + + + + + TIMER15 + General-purpose-timers + TIMER + 0x40014400 + + 0x0 + 0x400 + registers + + + TIMER15 + 21 + + + + CTL0 + CTL0 + control register 0 + 0x0 + 0x20 + read-write + 0x0000 + + + CKDIV + Clock division + 8 + 2 + + + ARSE + Auto-reload preload enable + 7 + 1 + + + SPM + One-pulse mode + 3 + 1 + + + UPS + Update request source + 2 + 1 + + + UPDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CTL1 + CTL1 + control register 1 + 0x04 + 0x20 + read-write + 0x0000 + + + ISO0N + Output Idle state 0 + 9 + 1 + + + ISO0 + Output Idle state 0 + 8 + 1 + + + DMAS + Capture/compare DMA + selection + 3 + 1 + + + CCUC + Capture/compare control update + selection + 2 + 1 + + + CCSE + Capture/compare preloaded + control + 0 + 1 + + + + + DMAINTEN + DMAINTEN + DMA/Interrupt enable register + 0x0C + 0x20 + read-write + 0x0000 + + + CH0DEN + Capture/Compare 0 DMA request + enable + 9 + 1 + + + UPDEN + Update DMA request enable + 8 + 1 + + + BRKIE + Break interrupt enable + 7 + 1 + + + CMTIE + COM interrupt enable + 5 + 1 + + + CH0IE + Capture/Compare 0 interrupt + enable + 1 + 1 + + + UPIE + Update interrupt enable + 0 + 1 + + + + + INTF + INTF + interrupt flag register + 0x10 + 0x20 + read-write + 0x0000 + + + CH0OF + Capture/Compare 0 overcapture + flag + 9 + 1 + + + BRKIF + Break interrupt flag + 7 + 1 + + + CMTIF + COM interrupt flag + 5 + 1 + + + CH0IF + Capture/compare 0 interrupt + flag + 1 + 1 + + + UPIF + Update interrupt flag + 0 + 1 + + + + + SWEVG + SWEVG + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BRKG + Break generation + 7 + 1 + + + CMTG + Capture/Compare control update + generation + 5 + 1 + + + CH0G + Capture/compare 0 + generation + 1 + 1 + + + UPG + Update generation + 0 + 1 + + + + + CHCTL0_Output + CHCTL0_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + CH0COMCTL + Output Compare 0 mode + 4 + 3 + + + CH0COMSEN + Output Compare 0 preload + enable + 3 + 1 + + + CH0COMFEN + Output Compare 0 fast + enable + 2 + 1 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL0_Input + CHCTL0_Input + capture/compare mode register 0 (input + mode) + CHCTL0_Output + 0x18 + 0x20 + read-write + 0x0000 + + + CH0CAPFLT + Input capture 0 filter + 4 + 4 + + + CH0CAPPSC + Input capture 0 prescaler + 2 + 2 + + + CH0MS + Capture/Compare 0 + selection + 0 + 2 + + + + + CHCTL2 + CHCTL2 + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CH0NP + Capture/Compare 0 output + Polarity + 3 + 1 + + + CH0NEN + Capture/Compare 0 complementary output + enable + 2 + 1 + + + CH0P + Capture/Compare 0 output + Polarity + 1 + 1 + + + CH0EN + Capture/Compare 0 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x0000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + CAR + CAR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + CARL + Auto-reload value + 0 + 16 + + + + + CREP + CREP + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + CREP + Repetition counter value + 0 + 8 + + + + + CH0CV + CH0CV + capture/compare register 0 + 0x34 + 0x20 + read-write + 0x0000 + + + CH0VAL + Capture/Compare 0 value + 0 + 16 + + + + + CCHP + CCHP + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + POEN + Main output enable + 15 + 1 + + + OAEN + Automatic output enable + 14 + 1 + + + BRKP + Break polarity + 13 + 1 + + + BRKEN + Break enable + 12 + 1 + + + ROS + Off-state selection for Run + mode + 11 + 1 + + + IOS + Off-state selection for Idle + mode + 10 + 1 + + + PROT + complementary register protect control + 8 + 2 + + + DTCFG + Dead-time generator setup + 0 + 8 + + + + + DMACFG + DMACFG + DMA configuration register + 0x48 + 0x20 + read-write + 0x0000 + + + DMATC + DMA transfer count + 8 + 5 + + + DMATA + DMA transfer access start address + 0 + 5 + + + + + DMATB + DMATB + DMA transfer buffer register + 0x4C + 0x20 + read-write + 0x0000 + + + DMATB + DMA register for burst + accesses + 0 + 16 + + + + + CFG + CFG + configuration register + 0xFC + 0x20 + read-write + 0x0000 + + + OUTSEL + The output value selection + 0 + 1 + + + CHVSEL + Write CHxVAL register selection + 1 + 1 + + + + + + + TIMER16 + 0x40014800 + + TIMER16 + 22 + + + + USART0 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART0 + 27 + + + + CTL0 + CTL0 + Control register 0 + 0x0 + 0x20 + read-write + 0x00000000 + + + EBIE + End of Block interrupt + enable + 27 + 1 + + + RTIE + Receiver timeout interrupt + enable + 26 + 1 + + + DEA + Driver Enable assertion + time + 21 + 5 + + + DED + Driver Enable deassertion + time + 16 + 5 + + + OVSMOD + Oversampling mode + 15 + 1 + + + AMIE + Character match interrupt + enable + 14 + 1 + + + MEN + Mute mode enable + 13 + 1 + + + WL + Word length + 12 + 1 + + + WM + Receiver wakeup method + 11 + 1 + + + PCEN + Parity control enable + 10 + 1 + + + PM + Parity selection + 9 + 1 + + + PERRIE + PE interrupt enable + 8 + 1 + + + TBEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RBNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TEN + Transmitter enable + 3 + 1 + + + REN + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UEN + USART enable + 0 + 1 + + + + + CTL1 + CTL1 + Control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDR + Address of the USART node + 24 + 8 + + + RTEN + Receiver timeout enable + 23 + 1 + + + ABDM + Auto baud rate mode + 21 + 2 + + + ABDEN + Auto baud rate enable + 20 + 1 + + + MSBF + Most significant bit first + 19 + 1 + + + DINV + Binary data inversion + 18 + 1 + + + TINV + TX pin active level + inversion + 17 + 1 + + + RINV + RX pin active level + inversion + 16 + 1 + + + STRP + Swap TX/RX pins + 15 + 1 + + + LMEN + LIN mode enable + 14 + 1 + + + STB + STOP bits + 12 + 2 + + + CKEN + Clock enable + 11 + 1 + + + CPL + Clock polarity + 10 + 1 + + + CPH + Clock phase + 9 + 1 + + + CLEN + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBLEN + LIN break detection length + 5 + 1 + + + ADDM + 7-bit Address Detection/4-bit Address + Detection + 4 + 1 + + + + + CTL2 + CTL2 + Control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + WUIE + Wakeup from Stop mode interrupt + enable + 22 + 1 + + + WUM + Wakeup from Stop mode interrupt flag + selection + 20 + 2 + + + SCRTNUM + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity + selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception + Error + 13 + 1 + + + OVRD + Overrun Disable + 12 + 1 + + + OSB + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSEN + CTS enable + 9 + 1 + + + RTSEN + RTS enable + 8 + 1 + + + DENT + DMA enable transmitter + 7 + 1 + + + DENR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NKEN + Smartcard NACK enable + 4 + 1 + + + HDEN + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + ERRIE + Error interrupt enable + 0 + 1 + + + + + BAUD + BAUD + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + BRR_INT + integer of baud-rate divider + 4 + 12 + + + BRR_FRA + integer of baud-rate divider + 0 + 4 + + + + + GP + GP + Guard time and prescaler + register + 0x10 + 0x20 + read-write + 0x00000000 + + + GUAT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RT + RT + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BL + Block Length + 24 + 8 + + + RT + Receiver timeout value + 0 + 24 + + + + + CMD + CMD + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFCMD + Transmit data flush + request + 4 + 1 + + + RXFCMD + Receive data flush request + 3 + 1 + + + MMCMD + Mute mode request + 2 + 1 + + + SBKCMD + Send break request + 1 + 1 + + + ABDCMD + Auto baud rate request + 0 + 1 + + + + + STAT + STAT + Interrupt & status + register + 0x1C + 0x20 + read-only + 0x000000C0 + + + REA + Receive enable acknowledge + flag + 22 + 1 + + + TEA + Transmit enable acknowledge + flag + 21 + 1 + + + WUF + Wakeup from Stop mode flag + 20 + 1 + + + RWU + Receiver wakeup from Mute + mode + 19 + 1 + + + SBF + Send break flag + 18 + 1 + + + AMF + character match flag + 17 + 1 + + + BSY + Busy flag + 16 + 1 + + + ABDF + Auto baud rate flag + 15 + 1 + + + ABDE + Auto baud rate error + 14 + 1 + + + EBF + End of block flag + 12 + 1 + + + RTF + Receiver timeout + 11 + 1 + + + CTS + CTS flag + 10 + 1 + + + CTSF + CTS interrupt flag + 9 + 1 + + + LBDF + LIN break detection flag + 8 + 1 + + + TBE + Transmit data register + empty + 7 + 1 + + + TC + Transmission complete + 6 + 1 + + + RBNE + Read data register not + empty + 5 + 1 + + + IDLEF + Idle line detected + 4 + 1 + + + ORERR + Overrun error + 3 + 1 + + + NERR + Noise detected flag + 2 + 1 + + + FERR + Framing error + 1 + 1 + + + PERR + Parity error + 0 + 1 + + + + + INTC + INTC + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUC + Wakeup from Stop mode clear + flag + 20 + 1 + + + AMC + Character match clear flag + 17 + 1 + + + EBC + End of timeout clear flag + 12 + 1 + + + RTC + Receiver timeout clear + flag + 11 + 1 + + + CTSC + CTS clear flag + 9 + 1 + + + LBDC + LIN break detection clear + flag + 8 + 1 + + + TCC + Transmission complete clear + flag + 6 + 1 + + + IDLEC + Idle line detected clear + flag + 4 + 1 + + + OREC + Overrun error clear flag + 3 + 1 + + + NEC + Noise detected clear flag + 2 + 1 + + + FEC + Framing error clear flag + 1 + 1 + + + PEC + Parity error clear flag + 0 + 1 + + + + + RDATA + RDATA + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDATA + Receive data value + 0 + 9 + + + + + TDATA + TDATA + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDATA + Transmit data value + 0 + 9 + + + + + CHC + CHC + coherence control register + 0xC0 + 0x20 + read-write + 0x00000000 + + + EPERR + Early parity error flag + 8 + 1 + + + HCM + Hardware flow control coherence mode + 0 + 1 + + + + + RFCS + RFCS + USART receive FIFO control and status register + 0xD0 + 0x20 + 0x00000400 + + + RFFINT + Receive FIFO full interrupt flag + 15 + 1 + read-write + + + RFCNT + Receive FIFO count number + 12 + 3 + read-only + + + RFF + Receive FIFO full flag + 11 + 1 + read-only + + + RFE + Receive FIFO empty flag + 10 + 1 + read-only + + + RFFIE + Receive FIFO full interrupt enable + 9 + 1 + read-write + + + RFEN + Receive FIFO enable + 8 + 1 + read-write + + + ELNACK + Early NKEN when smartcard mode is selected + 0 + 1 + read-write + + + + + + + USART1 + 0x40004400 + + USART1 + 28 + + + + WWDGT + Window watchdog timer + WWDGT + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDGT + 0 + + + + CTL + CTL + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGTEN + Activation bit + 7 + 1 + + + CNT + 7-bit counter + 0 + 7 + + + + + CFG + CFG + Configuration register + 0x04 + 0x20 + read-write + 0x0000007F + + + EWIE + Early wakeup interrupt + 9 + 1 + + + PSC + Prescaler + 7 + 2 + + + WIN + 7-bit window value + 0 + 7 + + + + + STAT + STAT + Status register + 0x08 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + + + diff --git a/Inc/board_config.h b/Inc/board_config.h index 006612d..164c619 100644 --- a/Inc/board_config.h +++ b/Inc/board_config.h @@ -1,92 +1,86 @@ -#ifndef BOARD_CONFIG_H -#define BOARD_CONFIG_H - -#include "version.h" - -#define GD32E23XF4 0x10 -#define GD32E23XF6 0x20 -#define GD32E23XF8 0x40 - -/* >>>>>>>>>>>>>>>>>>>>[RS485 PHY DEFINE]<<<<<<<<<<<<<<<<<<<< */ - -// #define RS485_MAX13487 // RS485 PHY : MAX13487 (AutoDir) -#undef RS485_MAX13487 // RS485 PHY : SP3487 (no AutoDir) - -/* >>>>>>>>>>>>>>>>>>>>[IIC TYPE DEFINE]<<<<<<<<<<<<<<<<<<<< */ - -// #define SOFTWARE_IIC // IIC Type : Software IIC -#undef SOFTWARE_IIC // IIC Type : Hardware IIC - -/* >>>>>>>>>>>>>>>>>>>>[DEBUG ASSERTIONS DEFINE]<<<<<<<<<<<<<<<<<<<< */ - -// #define DEBUG_VERBOSE // Debug Assertions Status : Debug Verbose Information -#undef DEBUG_VERBOSE // Debug Assertions Status : No Debug Verbose Information - -/* >>>>>>>>>>>>>>>>>>>>[EDDY DRIVE CURRENT DETECTION]<<<<<<<<<<<<<<<<<<<< */ - -// #define EDDY_DRIVE_CURRENT_DETECTION // Eddy Drive Current Detection : Enable -#undef EDDY_DRIVE_CURRENT_DETECTION // Eddy Drive Current Detection : Disable - -/* >>>>>>>>>>>>>>>>>>>>[COMMAND DEBUG]<<<<<<<<<<<<<<<<<<<< */ - -// #define COM_DEBUG // Enable Command Debug Information -#undef COM_DEBUG // Disable Command Debug Information - -/* >>>>>>>>>>>>>>>>>>>>>[LDC1612 DEBUG]<<<<<<<<<<<<<<<<<<<< */ - -// #define LDC_DEBUG // LDC1612 Driver Debug : Enable -#undef LDC_DEBUG // LDC1612 Driver Debug : Disable - -/******************************************************************************/ - -/* Dynamic USART Configuration Structure */ -typedef struct { - uint32_t rcu_usart; - uint32_t usart_periph; - IRQn_Type irq_type; - void (*irq_handler)(void); // 函数指针：指向中断处理函数 -} usart_config_t; - -extern usart_config_t g_usart_config; -extern uint8_t g_mcu_flash_size; - -/* USART中断处理函数声明 */ -void usart0_irq_handler(void); -void usart1_irq_handler(void); - -/******************************************************************************/ - -#define RCU_GPIO_I2C RCU_GPIOF -#define RCU_I2C RCU_I2C0 -#define I2C_SCL_PORT GPIOF -#define I2C_SCL_PIN GPIO_PIN_1 -#define I2C_SDA_PORT GPIOF -#define I2C_SDA_PIN GPIO_PIN_0 -#define I2C_GPIO_AF GPIO_AF_1 - -#define I2C_DEBUG_UART USART0 - -/******************************************************************************/ - -#define LED_RCU RCU_GPIOA -#define LED_PORT GPIOA -#define LED_PIN GPIO_PIN_7 - -/******************************************************************************/ - -#define RS485_RCU (g_usart_config.rcu_usart) -#define RS485_PHY (g_usart_config.usart_periph) -#define RS485_IRQ (g_usart_config.irq_type) -#define RS485_GPIO_RCU RCU_GPIOA -#define RS485_GPIO_PORT GPIOA -#define RS485_EN_PIN GPIO_PIN_1 -#define RS485_TX_PIN GPIO_PIN_2 -#define RS485_RX_PIN GPIO_PIN_3 -#define RS485_BAUDRATE 115200U - -/******************************************************************************/ - -void mcu_detect_and_config(void); -uint8_t get_flash_size(void); - -#endif //BOARD_CONFIG_H +#ifndef BOARD_CONFIG_H +#define BOARD_CONFIG_H + +#define GD32E23XF4 0x10 +#define GD32E23XF6 0x20 +#define GD32E23XF8 0x40 + +/* >>>>>>>>>>>>>>>>>>>>[RS485 PHY DEFINE]<<<<<<<<<<<<<<<<<<<< */ + +// #define RS485_MAX13487 // RS485 PHY : MAX13487 (AutoDir) +#undef RS485_MAX13487 // RS485 PHY : SP3487 (no AutoDir) + +/* >>>>>>>>>>>>>>>>>>>>[IIC TYPE DEFINE]<<<<<<<<<<<<<<<<<<<< */ + +// #define SOFTWARE_IIC // IIC Type : Software IIC +#undef SOFTWARE_IIC // IIC Type : Hardware IIC + +/* >>>>>>>>>>>>>>>>>>>>[DEBUG ASSERTIONS DEFINE]<<<<<<<<<<<<<<<<<<<< */ + +// #define DEBUG_VERBOSE // Debug Assertions Status : Debug Verbose Information +#undef DEBUG_VERBOSE // Debug Assertions Status : No Debug Verbose Information + +/* >>>>>>>>>>>>>>>>>>>>[EDDY DRIVE CURRENT DETECTION]<<<<<<<<<<<<<<<<<<<< */ + +// #define EDDY_DRIVE_CURRENT_DETECTION // Eddy Drive Current Detection : Enable +#undef EDDY_DRIVE_CURRENT_DETECTION // Eddy Drive Current Detection : Disable + +/******************************************************************************/ + +#define MCU_CODE 24U + +#define FW_VERSION_MAJOR 1 +#define FW_VERSION_MINOR 1 +#define FW_VERSION_PATCH 3 + +/* Dynamic USART Configuration Structure */ +typedef struct { + uint32_t rcu_usart; + uint32_t usart_periph; + IRQn_Type irq_type; + void (*irq_handler)(void); // 函数指针：指向中断处理函数 +} usart_config_t; + +extern usart_config_t g_usart_config; +extern uint8_t g_mcu_flash_size; + +/* USART中断处理函数声明 */ +void usart0_irq_handler(void); +void usart1_irq_handler(void); + +/******************************************************************************/ + +#define RCU_GPIO_I2C RCU_GPIOF +#define RCU_I2C RCU_I2C0 +#define I2C_SCL_PORT GPIOF +#define I2C_SCL_PIN GPIO_PIN_1 +#define I2C_SDA_PORT GPIOF +#define I2C_SDA_PIN GPIO_PIN_0 +#define I2C_GPIO_AF GPIO_AF_1 + +#define I2C_DEBUG_UART USART0 + +/******************************************************************************/ + +#define LED_RCU RCU_GPIOA +#define LED_PORT GPIOA +#define LED_PIN GPIO_PIN_7 + +/******************************************************************************/ + +#define RS485_RCU (g_usart_config.rcu_usart) +#define RS485_PHY (g_usart_config.usart_periph) +#define RS485_IRQ (g_usart_config.irq_type) +#define RS485_GPIO_RCU RCU_GPIOA +#define RS485_GPIO_PORT GPIOA +#define RS485_EN_PIN GPIO_PIN_1 +#define RS485_TX_PIN GPIO_PIN_2 +#define RS485_RX_PIN GPIO_PIN_3 +#define RS485_BAUDRATE 115200U + +/******************************************************************************/ + +void mcu_detect_and_config(void); +uint8_t get_flash_size(void); + +#endif //BOARD_CONFIG_H diff --git a/Inc/command.h b/Inc/command.h index 7541fc9..8aec02d 100644 --- a/Inc/command.h +++ b/Inc/command.h @@ -1,112 +1,108 @@ -/** - * @file command.h - * @brief 串口命令解析与处理模块接口声明。 - * @details 提供基于环形缓冲区的串口协议解析、命令处理及状态管理功能， - * 支持格式为 D5 03 LEN [cmd] CRC 的命令帧解析与响应。 - */ -#ifndef COMMAND_H -#define COMMAND_H - -#include -#include - -/** - * @defgroup Command 命令处理模块 - * @brief 串口命令解析与处理 - * @{ - */ - -/** @brief 传感器周期上报使能标志 */ -extern volatile bool g_eddy_current_sensor_report_enabled; - -/** - * @section Command_Protocol 协议格式 - * 接收命令帧格式： - * @code - * [0] HEADER = 0xD5 // 包头标识 - * [1] BOARD_TYPE = 0x03 // 板卡类型标识 - * [2] LEN = 数据区字节数 // 有效载荷长度 - * [3..(3+LEN-1)] 数据 // 命令数据 - * [last] CRC // 校验码（从索引1累加到len-2的低8位） - * @endcode - * - * 响应帧格式： - * @code - * [0] HEADER = 0xB5 // 响应包头 - * [1] TYPE // 响应类型（0xF0=成功，0xF1..=错误类型） - * [2] LEN // 响应数据长度 - * [3..(3+LEN-1)] 数据 // 响应数据 - * [last] CRC // 校验码 - * @endcode - * - * @section Command_Usage 使用说明 - * 1) 初始化环形缓冲区： - * @code{.c} - * uart_ring_buffer_init(); - * @endcode - * - * 2) 在主循环中调用命令处理： - * @code{.c} - * while(1) { - * command_process(); // 处理接收到的命令 - * // 其他业务逻辑 - * } - * @endcode - * - * 3) 查询传感器上报状态： - * @code{.c} - * if(get_sensor_report_enabled()) { - * // 执行传感器数据上报 - * } - * @endcode - */ - -/** - * @brief 获取电涡流传感器周期上报使能状态。 - * @return bool 上报状态。 - * @retval true 传感器周期上报已启用。 - * @retval false 传感器周期上报已禁用。 - * @ingroup Command - */ -bool get_eddy_sensor_report_enabled(void); - -/** - * @brief 设置电涡流传感器周期上报使能状态。 - * @param enabled 上报使能标志。 - * @arg true 启用传感器周期上报。 - * @arg false 禁用传感器周期上报。 - * @note 推荐通过此函数修改状态，便于后续功能扩展。 - * @ingroup Command - */ -void set_eddy_sensor_report_status(bool enabled); - -/** - * @brief 处理串口环形缓冲区中的命令数据。 - * @details 基于状态机的非阻塞协议解析器，处理完整的命令帧并自动响应。 - * 每次调用处理缓冲区中所有可用数据，遇到错误时自动重置状态机。 - * @note 使用静态变量维护解析状态，函数不可重入。 - * @warning 依赖环形缓冲区正确实现，建议在主循环中周期调用。 - * @ingroup Command - */ -void command_process(void); - -/** - * @brief 解析并处理完整的命令帧。 - * @param cmd 指向完整命令帧的缓冲区（从包头0xD5开始）。 - * @param len 命令帧总长度（字节）。 - * @note 内部函数，由 command_process() 调用，一般不直接使用。 - * @ingroup Command - */ -void handle_command(const uint8_t *cmd, uint8_t len); - -/** @} */ // end of Command group - -void eddy_current_report(void); - -void temperature_raw_value_report(void); - -void eddy_current_compensated_report(void); - -void calibration_data_report(void); - -#endif // COMMAND_H +/** + * @file command.h + * @brief 串口命令解析与处理模块接口声明。 + * @details 提供基于环形缓冲区的串口协议解析、命令处理及状态管理功能， + * 支持格式为 D5 03 LEN [cmd] CRC 的命令帧解析与响应。 + */ +#ifndef COMMAND_H +#define COMMAND_H + +#include +#include + +/** + * @defgroup Command 命令处理模块 + * @brief 串口命令解析与处理 + * @{ + */ + +/** @brief 传感器周期上报使能标志 */ +extern volatile bool g_eddy_current_sensor_report_enabled; + +/** + * @section Command_Protocol 协议格式 + * 接收命令帧格式： + * @code + * [0] HEADER = 0xD5 // 包头标识 + * [1] BOARD_TYPE = 0x03 // 板卡类型标识 + * [2] LEN = 数据区字节数 // 有效载荷长度 + * [3..(3+LEN-1)] 数据 // 命令数据 + * [last] CRC // 校验码（从索引1累加到len-2的低8位） + * @endcode + * + * 响应帧格式： + * @code + * [0] HEADER = 0xB5 // 响应包头 + * [1] TYPE // 响应类型（0xF0=成功，0xF1..=错误类型） + * [2] LEN // 响应数据长度 + * [3..(3+LEN-1)] 数据 // 响应数据 + * [last] CRC // 校验码 + * @endcode + * + * @section Command_Usage 使用说明 + * 1) 初始化环形缓冲区： + * @code{.c} + * uart_ring_buffer_init(); + * @endcode + * + * 2) 在主循环中调用命令处理： + * @code{.c} + * while(1) { + * command_process(); // 处理接收到的命令 + * // 其他业务逻辑 + * } + * @endcode + * + * 3) 查询传感器上报状态： + * @code{.c} + * if(get_sensor_report_enabled()) { + * // 执行传感器数据上报 + * } + * @endcode + */ + +/** + * @brief 获取电涡流传感器周期上报使能状态。 + * @return bool 上报状态。 + * @retval true 传感器周期上报已启用。 + * @retval false 传感器周期上报已禁用。 + * @ingroup Command + */ +bool get_eddy_sensor_report_enabled(void); + +/** + * @brief 设置电涡流传感器周期上报使能状态。 + * @param enabled 上报使能标志。 + * @arg true 启用传感器周期上报。 + * @arg false 禁用传感器周期上报。 + * @note 推荐通过此函数修改状态，便于后续功能扩展。 + * @ingroup Command + */ +void set_eddy_sensor_report_status(bool enabled); + +/** + * @brief 处理串口环形缓冲区中的命令数据。 + * @details 基于状态机的非阻塞协议解析器，处理完整的命令帧并自动响应。 + * 每次调用处理缓冲区中所有可用数据，遇到错误时自动重置状态机。 + * @note 使用静态变量维护解析状态，函数不可重入。 + * @warning 依赖环形缓冲区正确实现，建议在主循环中周期调用。 + * @ingroup Command + */ +void command_process(void); + +/** + * @brief 解析并处理完整的命令帧。 + * @param cmd 指向完整命令帧的缓冲区（从包头0xD5开始）。 + * @param len 命令帧总长度（字节）。 + * @note 内部函数，由 command_process() 调用，一般不直接使用。 + * @ingroup Command + */ +void handle_command(const uint8_t *cmd, uint8_t len); + +/** @} */ // end of Command group + +void eddy_current_report(void); + +void temperature_raw_value_report(void); + +#endif // COMMAND_H diff --git a/Inc/gd32e23x_it.h b/Inc/gd32e23x_it.h index 04a9d99..171ecfb 100644 --- a/Inc/gd32e23x_it.h +++ b/Inc/gd32e23x_it.h @@ -1,52 +1,52 @@ -/*! - \file gd32e23x_it.h - \brief the header file of the ISR - - \version 2025-02-10, V2.4.0, demo for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_IT_H -#define GD32E23X_IT_H - -#include "gd32e23x.h" - -/* function declarations */ -/* this function handles NMI exception */ -void NMI_Handler(void); -/* this function handles HardFault exception */ -void HardFault_Handler(void); -/* this function handles SVC exception */ -void SVC_Handler(void); -/* this function handles PendSV exception */ -void PendSV_Handler(void); -/* this function handles SysTick exception */ -void SysTick_Handler(void); - -#endif /* GD32E23X_IT_H */ +/*! + \file gd32e23x_it.h + \brief the header file of the ISR + + \version 2025-02-10, V2.4.0, demo for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_IT_H +#define GD32E23X_IT_H + +#include "gd32e23x.h" + +/* function declarations */ +/* this function handles NMI exception */ +void NMI_Handler(void); +/* this function handles HardFault exception */ +void HardFault_Handler(void); +/* this function handles SVC exception */ +void SVC_Handler(void); +/* this function handles PendSV exception */ +void PendSV_Handler(void); +/* this function handles SysTick exception */ +void SysTick_Handler(void); + +#endif /* GD32E23X_IT_H */ diff --git a/Inc/gd32e23x_libopt.h b/Inc/gd32e23x_libopt.h index 197ebde..14b89e8 100644 --- a/Inc/gd32e23x_libopt.h +++ b/Inc/gd32e23x_libopt.h @@ -1,58 +1,58 @@ -/*! - \file gd32e23x_libopt.h - \brief library optional for gd32e23x - - \version 2025-02-10, V2.4.0, demo for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_LIBOPT_H -#define GD32E23X_LIBOPT_H - -#include "gd32e23x_adc.h" -#include "gd32e23x_crc.h" -#include "gd32e23x_dbg.h" -#include "gd32e23x_dma.h" -#include "gd32e23x_exti.h" -#include "gd32e23x_fmc.h" -#include "gd32e23x_gpio.h" -#include "gd32e23x_syscfg.h" -#include "gd32e23x_i2c.h" -#include "gd32e23x_fwdgt.h" -#include "gd32e23x_pmu.h" -#include "gd32e23x_rcu.h" -#include "gd32e23x_rtc.h" -#include "gd32e23x_spi.h" -#include "gd32e23x_timer.h" -#include "gd32e23x_usart.h" -#include "gd32e23x_wwdgt.h" -#include "gd32e23x_misc.h" -#include "gd32e23x_cmp.h" - -#endif /* GD32E23X_LIBOPT_H */ +/*! + \file gd32e23x_libopt.h + \brief library optional for gd32e23x + + \version 2025-02-10, V2.4.0, demo for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_LIBOPT_H +#define GD32E23X_LIBOPT_H + +#include "gd32e23x_adc.h" +#include "gd32e23x_crc.h" +#include "gd32e23x_dbg.h" +#include "gd32e23x_dma.h" +#include "gd32e23x_exti.h" +#include "gd32e23x_fmc.h" +#include "gd32e23x_gpio.h" +#include "gd32e23x_syscfg.h" +#include "gd32e23x_i2c.h" +#include "gd32e23x_fwdgt.h" +#include "gd32e23x_pmu.h" +#include "gd32e23x_rcu.h" +#include "gd32e23x_rtc.h" +#include "gd32e23x_spi.h" +#include "gd32e23x_timer.h" +#include "gd32e23x_usart.h" +#include "gd32e23x_wwdgt.h" +#include "gd32e23x_misc.h" +#include "gd32e23x_cmp.h" + +#endif /* GD32E23X_LIBOPT_H */ diff --git a/Inc/i2c.h b/Inc/i2c.h index eaa7097..874b7cd 100644 --- a/Inc/i2c.h +++ b/Inc/i2c.h @@ -1,189 +1,127 @@ -// -// Created by dell on 24-12-20. -// - -#ifndef I2C_H -#define I2C_H - -#include "gd32e23x_it.h" -#include "gd32e23x.h" -#include "systick.h" -#include -#include -#include -#include -#include - -#include "board_config.h" - -/******************************************************************************/ - -#define I2C_SPEED 100000U /* 100kHz */ -#define I2C_TIME_OUT 5000U /* 5000 loops timeout */ -#define I2C_MAX_RETRY 3U /* Maximum retry attempts */ -#define I2C_DELAY_10US 10U /* Delay in microseconds for bus reset */ -#define I2C_RECOVERY_CLOCKS 9U /* Clock pulses for bus recovery */ -#define I2C_MASTER_ADDRESS 0x00U /* Master address (not used) */ - -/* Legacy compatibility */ -#define I2C_OK 1 -#define I2C_FAIL 0 -#define I2C_END 1 - -/******************************************************************************/ - -/* I2C result enumeration */ -typedef enum { - I2C_RESULT_SUCCESS = 0, /* Operation successful */ - I2C_RESULT_TIMEOUT, /* Timeout occurred */ - I2C_RESULT_NACK, /* No acknowledge received */ - I2C_RESULT_BUS_BUSY, /* Bus is busy */ - I2C_RESULT_ERROR, /* General error */ - I2C_RESULT_INVALID_PARAM, /* Invalid parameter */ - I2C_RECOVERY_OK, - I2C_RECOVERY_SDA_STUCK_LOW, - I2C_RECOVERY_SCL_STUCK_LOW -} i2c_result_t; - -/* I2C state machine enumeration */ -typedef enum { - I2C_STATE_IDLE = 0, /* Idle state */ - I2C_STATE_START, /* Generate start condition */ - I2C_STATE_SEND_ADDRESS, /* Send slave address */ - I2C_STATE_CLEAR_ADDRESS, /* Clear address flag */ - I2C_STATE_TRANSMIT_REG, /* Transmit register address */ - I2C_STATE_TRANSMIT_DATA, /* Transmit data */ - I2C_STATE_RESTART, /* Generate restart condition */ - I2C_STATE_RECEIVE_DATA, /* Receive data */ - I2C_STATE_STOP, /* Generate stop condition */ - I2C_STATE_ERROR, /* Error state */ - I2C_STATE_END -} i2c_state_t; - -/******************************************************************************/ - - -/* Function declarations */ -/*! - \brief configure the I2C interface - \param[in] none - \param[out] none - \retval i2c_result_t -*/ -i2c_result_t i2c_config(void); - -/*! - \brief reset I2C bus with proper recovery - \param[in] none - \param[out] none - \retval i2c_result_t -*/ -i2c_result_t i2c_bus_reset(void); - -/*! - \brief scan I2C bus for devices - \param[in] none - \param[out] none - \retval none -*/ -void i2c_scan(void); - -/*! - \brief write 16-bit data to I2C device - \param[in] slave_addr: 7-bit slave address - \param[in] reg_addr: register address - \param[in] data: pointer to 2-byte data array - \param[out] none - \retval i2c_result_t -*/ -i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]); - -/*! - \brief read 16-bit data from I2C device - \param[in] slave_addr: 7-bit slave address - \param[in] reg_addr: register address - \param[out] data: pointer to 2-byte data buffer - \retval i2c_result_t -*/ -i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); - -/* Generic read/write functions with configurable length */ -/*! - \brief write data to I2C device with configurable length - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[in] data: pointer to data buffer - \param[in] length: number of bytes to write (1-255) - \param[out] none - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_write(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length); - -/*! - \brief read data from I2C device with configurable length - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[out] data: pointer to data buffer - \param[in] length: number of bytes to read (1-255) - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_read(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length); - -/* Convenience functions for common operations */ -/*! - \brief write single byte to I2C device - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[in] data: data byte to write - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_write_8bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data); - -/*! - \brief read single byte from I2C device - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[out] data: pointer to data byte - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_read_8bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); - -/*! - \brief write 32-bit data to I2C device - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[in] data: pointer to 4-byte data array - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_write_32bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[4]); - -/*! - \brief read 32-bit data from I2C device - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[out] data: pointer to 4-byte data buffer - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_read_32bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); - -/*! - \brief read display panel parameters (multi-byte) - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[out] data: pointer to data buffer - \param[in] length: number of bytes to read (1-13) - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_read_display_params(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length); - -#ifdef DEBUG_VERBOSE -/*! - \brief get status string for debugging - \param[in] status: i2c_result_t value - \param[out] none - \retval const char* status string -*/ -const char* i2c_get_status_string(i2c_result_t status); -#endif - -#endif //I2C_H +// +// Created by dell on 24-12-20. +// + +#ifndef I2C_H +#define I2C_H + +#include "gd32e23x_it.h" +#include "gd32e23x.h" +#include "systick.h" +#include +#include +#include +#include +#include + +#include "board_config.h" + +/******************************************************************************/ + +#define I2C_SPEED 100000U /* 100kHz */ +#define I2C_TIME_OUT 5000U /* 5000 loops timeout */ +#define I2C_MAX_RETRY 3U /* Maximum retry attempts */ +#define I2C_DELAY_10US 10U /* Delay in microseconds for bus reset */ +#define I2C_RECOVERY_CLOCKS 9U /* Clock pulses for bus recovery */ +#define I2C_MASTER_ADDRESS 0x00U /* Master address (not used) */ + +/* Legacy compatibility */ +#define I2C_OK 1 +#define I2C_FAIL 0 +#define I2C_END 1 + +/******************************************************************************/ + +/* I2C result enumeration */ +typedef enum { + I2C_RESULT_SUCCESS = 0, /* Operation successful */ + I2C_RESULT_TIMEOUT, /* Timeout occurred */ + I2C_RESULT_NACK, /* No acknowledge received */ + I2C_RESULT_BUS_BUSY, /* Bus is busy */ + I2C_RESULT_ERROR, /* General error */ + I2C_RESULT_INVALID_PARAM, /* Invalid parameter */ + I2C_RECOVERY_OK, + I2C_RECOVERY_SDA_STUCK_LOW, + I2C_RECOVERY_SCL_STUCK_LOW +} i2c_result_t; + +/* I2C state machine enumeration */ +typedef enum { + I2C_STATE_IDLE = 0, /* Idle state */ + I2C_STATE_START, /* Generate start condition */ + I2C_STATE_SEND_ADDRESS, /* Send slave address */ + I2C_STATE_CLEAR_ADDRESS, /* Clear address flag */ + I2C_STATE_TRANSMIT_REG, /* Transmit register address */ + I2C_STATE_TRANSMIT_DATA, /* Transmit data */ + I2C_STATE_RESTART, /* Generate restart condition */ + I2C_STATE_RECEIVE_DATA, /* Receive data */ + I2C_STATE_STOP, /* Generate stop condition */ + I2C_STATE_ERROR, /* Error state */ + I2C_STATE_END +} i2c_state_t; + +/******************************************************************************/ + + +/* Function declarations */ +/*! + \brief configure the I2C interface + \param[in] none + \param[out] none + \retval i2c_result_t +*/ +i2c_result_t i2c_config(void); + +/*! + \brief reset I2C bus with proper recovery + \param[in] none + \param[out] none + \retval i2c_result_t +*/ +i2c_result_t i2c_bus_reset(void); + +/*! + \brief scan I2C bus for devices + \param[in] none + \param[out] none + \retval none +*/ +void i2c_scan(void); + +/*! + \brief write 16-bit data to I2C device + \param[in] slave_addr: 7-bit slave address + \param[in] reg_addr: register address + \param[in] data: pointer to 2-byte data array + \param[out] none + \retval i2c_result_t +*/ +i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]); + +/*! + \brief read 16-bit data from I2C device + \param[in] slave_addr: 7-bit slave address + \param[in] reg_addr: register address + \param[out] data: pointer to 2-byte data buffer + \retval i2c_result_t +*/ +i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); + +/*! + \brief read 16-bit data from I2C device + \param[in] slave_addr: 7-bit slave address + \param[in] reg_addr: register address + \param[out] data: pointer to 2-byte data buffer + \retval i2c_result_t +*/ +i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); + +/*! + \brief get status string for debugging + \param[in] status: i2c_result_t value + \param[out] none + \retval const char* status string +*/ +const char* i2c_get_status_string(i2c_result_t status); + +#endif //I2C_H diff --git a/Inc/ldc1612.h b/Inc/ldc1612.h index f2b21a2..f4e27ac 100644 --- a/Inc/ldc1612.h +++ b/Inc/ldc1612.h @@ -1,488 +1,213 @@ -// -// Created by dell on 24-12-3. -// - -#ifndef LDC1612_H -#define LDC1612_H - -#include "gd32e23x_it.h" -#include "gd32e23x.h" -#include "systick.h" -#include -#include -#include -#include -#include "board_config.h" -#include "i2c.h" - -/***************************************************************************/ - -/* IIC Interface Selection */ -#ifdef SOFTWARE_IIC - #define LDC1612_IIC_WRITE_16BITS(addr, reg, data) soft_i2c_write_16bits(addr, reg, data) - #define LDC1612_IIC_READ_16BITS(addr, reg, data) soft_i2c_read_16bits(addr, reg, data) - #define LDC1612_IIC_TYPE_STR "Software IIC" -#else - #define LDC1612_IIC_WRITE_16BITS(addr, reg, data) i2c_write_16bits(addr, reg, data) - #define LDC1612_IIC_READ_16BITS(addr, reg, data) i2c_read_16bits(addr, reg, data) - #define LDC1612_IIC_TYPE_STR "Hardware IIC" -#endif - -/* >>>>>>>>>>>>>>>>>>>>>>>>>>>>[EXT CLK(MHz)]<<<<<<<<<<<<<<<<<<<< */ - -#define LDC1612_EXT_CLK_MHZ 40 - -/***************************************************************************/ - -#define LDC1612_ADDR (0x2B) - -/******************************************************************************/ - -#define COIL_L_UH 40.9 -#define COIL_C_PF 180 - -/************************Register Addr***************************************/ - -#define CONVERSION_RESULT_REG_START 0X00 -#define SET_CONVERSION_TIME_REG_START 0X08 -#define SET_CONVERSION_OFFSET_REG_START 0X0C -#define SET_SETTLECOUNT_REG_START 0X10 -#define SET_FREQ_REG_START 0X14 -#define SENSOR_STATUS_REG 0X18 -#define ERROR_CONFIG_REG 0X19 -#define SENSOR_CONFIG_REG 0X1A -#define MUX_CONFIG_REG 0X1B -#define SENSOR_RESET_REG 0X1C -#define SET_DRIVER_CURRENT_REG 0X1E -#define READ_MANUFACTURER_ID 0X7E -#define READ_DEVICE_ID 0X7F - -/**********************Sensor Channel****************************************/ - -#define CHANNEL_0 0 -#define CHANNEL_1 1 - -/**************************DATA (0x00-0x03)*******************************************/ -/* - * 作用: 存储28位的传感器转换结果。结果分为高字节(MSB)和低字节(LSB)两个寄存器。 - * - * 结构说明: - * - DATA_CHx_MSB: 包含错误标志和数据的高12位 [27:16]。 - * - DATA_CHx_LSB: 包含数据的低16位 [15:0]。 - * - * MSB寄存器位域: - * [15] ERR_UR: 转换下溢错误标志 (1 = 发生错误) - * [14] ERR_OR: 转换上溢错误标志 (1 = 发生错误) - * [13] ERR_WD: 看门狗超时错误标志 (1 = 发生错误) - * [12] ERR_AE: 振幅错误标志 (高或低) (1 = 发生错误) - * [11:0] DATA[27:16]: 数据的高12位 - * - * 注意: - * - 仅当ERROR_CONFIG寄存器中对应的ERR2OUT位置1时，这些错误标志才会在MSB寄存器中被设置。 - * - 读取数据时，应先读取LSB，再读取MSB，以确保数据的一致性。 -*/ - -/* --- 数据寄存器错误标志位掩码 --- */ -#define LDC1612_DATA_ERR_UR (1 << 15) -#define LDC1612_DATA_ERR_OR (1 << 14) -#define LDC1612_DATA_ERR_WD (1 << 13) -#define LDC1612_DATA_ERR_AE (1 << 12) -#define LDC1612_DATA_ERR_MASK (0xF000) -#define LDC1612_DATA_MSB_MASK (0x0FFF) - -/**************************RCOUNT (0x08, 0x09)****************************************/ -/* - * 作用: 设置参考计数器值，决定了传感器的转换时间，从而影响测量分辨率。 - * - * 位域说明: - * [15:0] RCOUNT: 参考计数值。 - * - * 计算公式: - * t_CONVERSION = (RCOUNT * 16) / f_REF - * - * 注意: - * - RCOUNT值必须 ≥ 0x0004。 - * - 该寄存器在复位后值为 0x0080。 - * - * 配置建议: - * - 需要高采样率: 使用较小的RCOUNT值。 - * - 需要高分辨率: 使用较大的RCOUNT值。 -*/ - -/* --- 预设配置示例 --- */ -// 高速采样配置 (分辨率较低) -#define LDC1612_RCOUNT_HIGH_SPEED (0x04D6) // 1238, 约 1kSPS @ 40MHz/2 - -// 平衡配置 (常用) -#define LDC1612_RCOUNT_BALANCED (0x1000) // 4096, 约 380SPS @ 40MHz/2 - -// 高分辨率配置 (采样率较低) -#define LDC1612_RCOUNT_HIGH_RESOLUTION (0xFFFF) // 65535, 约 24SPS @ 40MHz/2 - -// 默认配置 -#define LDC1612_RCOUNT_TIME_CH0 LDC1612_RCOUNT_BALANCED // 0x1000=4096个时钟周期 - -/**************************OFFSET (0x0C, 0x0D)****************************************/ -/* - * 作用: 设置一个16位的数字偏移量，该值会从原始转换结果中减去。 - * - * 位域说明: - * [15:0] OFFSET: 数据偏移值。 - * - * 计算公式: - * 最终数据 = 原始转换数据 - OFFSET - * - * 注意: - * - 如果减法结果为负，将触发下溢错误 (ERR_UR)。 - * - 该寄存器在复位后值为 0x0000。 - * - * 应用场景: - * - 消除传感器或环境的固有基线偏移。 - * - 实现“去皮”(Tare)功能，将当前读数设为新的零点。 -*/ - -// 默认配置: 不设置偏移 -#define SET_CONVERSION_OFFSET_CH0 0x0000 - -/**************************SETTLECOUNT (0x10, 0x11)***********************************/ -/* - * 作用: 设置传感器振荡器在开始转换前所需的建立时间。 - * - * 位域说明: - * [15:0] SETTLECOUNT: 建立时间计数值。 - * - * 计算公式: - * t_SETTLE 的计算方式取决于SETTLECOUNT的值： - * - 当 SETTLECOUNT = 0x0000 或 0x0001 时, t_SETTLE = 32 / f_REF - * - 当 SETTLECOUNT ≥ 0x0002 时, t_SETTLE = (SETTLECOUNT * 16) / f_REF - * - * 配置建议: - * - 传感器的Q值越高，所需的建立时间越短 (SETTLECOUNT值可以越小)。 - * - 值过小可能导致传感器未充分稳定，数据不准确。 - * - 值过大则会不必要地增加总转换时间，降低采样率。 - * - 对于大多数应用，0x0100 (256) 是一个很好的起始值。 -*/ - -/* --- 预设配置示例 --- */ -// 适用于高Q值传感器 (建立时间短) -#define LDC1612_SETTLECOUNT_HIGH_Q (0x000A) // 约 4µs @ 40MHz/2 - -// 适用于中等Q值传感器 (通用) -#define LDC1612_SETTLECOUNT_MEDIUM_Q (0x0100) // 约 102µs @ 40MHz/2 - -// 适用于低Q值传感器 (建立时间长) -#define LDC1612_SETTLECOUNT_LOW_Q (0x0400) // 约 410µs @ 40MHz/2 - -// 默认配置 -#define LDC1612_SETTLECOUNT_CH0 LDC1612_SETTLECOUNT_MEDIUM_Q - -/**************************CLOCK_DIVIDER (0x14, 0x15)***********************************/ -/* - * 作用: 配置传感器输入频率(f_sensor)和参考时钟(f_ref)的分频器。 - * - * 位域说明: - * [15:12] FIN_DIVIDER: 传感器输入分频器。 - * [11:10] RESERVED: 必须为00。 - * [9:0] FREF_DIVIDER: 参考时钟分频器。 - * - * 配置逻辑: - * 1. FIN_DIVIDER: 根据传感器的谐振频率 f_sensor 选择。 - * - 目标是使 f_sensor / FIN_DIVIDER <= 8.75MHz。 - * - 例如: 如果 f_sensor = 15MHz, 则 FIN_DIVIDER 必须 >= 2。 - * - * 2. FREF_DIVIDER: 根据外部时钟 f_clk 和工作模式选择。 - * - 目标是使 f_ref = f_clk / FREF_DIVIDER。 - * - 单通道模式且 f_clk <= 35MHz: FREF_DIVIDER = 1。 - * - 双通道模式或 f_clk > 35MHz: FREF_DIVIDER = 2。 - * - * 最终寄存器值 = (FIN_DIVIDER << 12) | FREF_DIVIDER; -*/ - -/* --- 位域选项宏 --- */ -// [15:12] Sensor Input Divider (FIN_DIVIDER) -#define LDC1612_FIN_DIV_1 (0x1 << 12) // for f_sensor <= 8.75MHz -#define LDC1612_FIN_DIV_2 (0x2 << 12) // for 8.75MHz < f_sensor <= 17.5MHz -#define LDC1612_FIN_DIV_4 (0x3 << 12) // for 17.5MHz < f_sensor <= 35MHz - -// [9:0] Reference Clock Divider (FREF_DIVIDER) -#define LDC1612_FREF_DIV_1 (0x001) -#define LDC1612_FREF_DIV_2 (0x002) - -/* --- 组合宏 --- */ -#define LDC1612_CLOCK_DIVIDER_GEN(fin_div, fref_div) ((fin_div) | (fref_div)) - -/* --- 预设配置示例 (基于40MHz外部时钟) --- */ -// 适用于 f_sensor <= 8.75MHz -#define LDC1612_CLOCK_DIVIDER_DEFAULT LDC1612_CLOCK_DIVIDER_GEN(LDC1612_FIN_DIV_1, LDC1612_FREF_DIV_2) // 0x1002 - - -/**************************STATUS (0x18) MACROS**************************************** - * - * 作用: 定义STATUS寄存器的位掩码，用于解析设备状态。 - * -*/ -#define LDC1612_STATUS_DRDY (1 << 6) // 数据就绪 -#define LDC1612_STATUS_UNREAD_CH0 (1 << 3) // 通道0有未读数据 -#define LDC1612_STATUS_UNREAD_CH1 (1 << 2) // 通道1有未读数据 - -#define LDC1612_STATUS_ERR_ZC (1 << 8) // 零计数错误 -#define LDC1612_STATUS_ERR_ALE (1 << 9) // 振幅过低 -#define LDC1612_STATUS_ERR_AHE (1 << 10) // 振幅过高 -#define LDC1612_STATUS_ERR_WD (1 << 11) // 看门狗超时 -#define LDC1612_STATUS_ERR_OR (1 << 12) // 转换上溢 -#define LDC1612_STATUS_ERR_UR (1 << 13) // 转换下溢 -#define LDC1612_STATUS_ERR_CHAN_MASK (3 << 14) // 错误通道掩码 - -/**************************ERROR_CONFIG (0x19)****************************************/ -/* - * 作用: 配置状态或错误输出或者触发INTB引脚中断。 - * - * 位域说明: - * [15] UR_ERR2OUT: 1 = 转换下溢错误输出到DATA_CHx寄存器 - * [14] OR_ERR2OUT: 1 = 转换上溢错误输出到DATA_CHx寄存器 - * [13] WD_ERR2OUT: 1 = 看门狗超时错误输出到DATA_CHx寄存器 - * [12] AH_ERR2OUT: 1 = 振幅过高错误输出到DATA_CHx寄存器 - * [11] AL_ERR2OUT: 1 = 振幅过低错误输出到DATA_CHx寄存器 - * [10:8] RESERVED - * [7] UR_ERR2INT: 1 = 转换下溢错误触发INTB - * [6] OR_ERR2INT: 1 = 转换上溢错误触发INTB - * [5] WD_ERR2INT: 1 = 看门狗超时错误触发INTB - * [4] AH_ERR2INT: 1 = 振幅过高错误触发INTB - * [3] AL_ERR2INT: 1 = 振幅过低错误触发INTB - * [2] ZC_ERR2INT: 1 = 零计数错误触发INTB - * [1] RESERVED - * [0] DRDY_2INT: 1 = 数据就绪标志触发INTB -*/ - -/* --- 位域选项宏 --- */ - -// --- 中断触发 (ERR2INT) --- -#define LDC1612_ERR_CFG_DRDY_INT_EN (1 << 0) // 数据就绪中断使能 -#define LDC1612_ERR_CFG_ZC_INT_EN (1 << 2) // 零计数错误中断使能 -#define LDC1612_ERR_CFG_AL_INT_EN (1 << 3) // 振幅过低错误中断使能 -#define LDC1612_ERR_CFG_AH_INT_EN (1 << 4) // 振幅过高错误中断使能 -#define LDC1612_ERR_CFG_WD_INT_EN (1 << 5) // 看门狗超时中断使能 -#define LDC1612_ERR_CFG_OR_INT_EN (1 << 6) // 转换上溢中断使能 -#define LDC1612_ERR_CFG_UR_INT_EN (1 << 7) // 转换下溢中断使能 - -// --- 错误报告至数据寄存器 (ERR2OUT) --- -#define LDC1612_ERR_CFG_AL_OUT_EN (1 << 11) // 振幅过低错误报告使能 -#define LDC1612_ERR_CFG_AH_OUT_EN (1 << 12) // 振幅过高错误报告使能 -#define LDC1612_ERR_CFG_WD_OUT_EN (1 << 13) // 看门狗超时错误报告使能 -#define LDC1612_ERR_CFG_OR_OUT_EN (1 << 14) // 转换上溢错误报告使能 -#define LDC1612_ERR_CFG_UR_OUT_EN (1 << 15) // 转换下溢错误报告使能 - -// 常用配置: 仅使能 "数据就绪" 中断 -#define LDC1612_ERROR_CONFIG_DRDY_ONLY (LDC1612_ERR_CFG_DRDY_INT_EN) // 结果: 0x0001 - -// 常用配置: 使能所有错误报告 -#define LDC1612_ERROR_CONFIG_OUT_ONLY (LDC1612_ERR_CFG_AL_OUT_EN | \ - LDC1612_ERR_CFG_AH_OUT_EN | \ - LDC1612_ERR_CFG_WD_OUT_EN | \ - LDC1612_ERR_CFG_OR_OUT_EN | \ - LDC1612_ERR_CFG_UR_OUT_EN) // 结果: 0xF800 - -// 调试配置: 使能所有错误中断和错误报告 -#define LDC1612_ERROR_CONFIG_DEBUG_ALL (LDC1612_ERR_CFG_DRDY_INT_EN | \ - LDC1612_ERR_CFG_ZC_INT_EN | \ - LDC1612_ERR_CFG_AL_INT_EN | \ - LDC1612_ERR_CFG_AH_INT_EN | \ - LDC1612_ERR_CFG_WD_INT_EN | \ - LDC1612_ERR_CFG_OR_INT_EN | \ - LDC1612_ERR_CFG_UR_INT_EN | \ - LDC1612_ERR_CFG_AL_OUT_EN | \ - LDC1612_ERR_CFG_AH_OUT_EN | \ - LDC1612_ERR_CFG_WD_OUT_EN | \ - LDC1612_ERR_CFG_OR_OUT_EN | \ - LDC1612_ERR_CFG_UR_OUT_EN) // 结果: 0xF8FD - -// 默认配置: 所有功能都禁用 -#define LDC1612_ERROR_CONFIG_DEFAULT (0x0000) - -/**************************SENSOR_CONFIG (0x1A) MACROS***************************************/ -/* - * CONFIG寄存器位域宏定义，用于灵活组合生成配置值。 - * 使用方法: LDC1612_CONFIG_GEN(ACTIVE_CHAN, SLEEP_MODE, RP_OVERRIDE, AUTO_AMP, CLK_SRC, INTB, CURRENT_DRV) - * - * 位域说明 (根据 LDC1612_REG_LIST.md): - * [15:14] ACTIVE_CHAN: 激活通道选择 (仅在 AUTOSCAN_EN=0 时有效) - * [13] SLEEP_MODE_EN: 1 = 睡眠模式使能 - * [12] RP_OVERRIDE_EN: 1 = 禁用自动校准 (使用手动的IDRIVE设置) - * [11] SENSOR_ACTIVATE_SEL: 传感器激活电流选择 (0:低电流, 1:高电流) - * [10] AUTO_AMP_DIS: 1 = 禁用自动幅度校正 - * [9] REF_CLK_SRC: 1 = 使用外部CLKIN时钟 - * [8] RESERVED: 必须为0 - * [7] INTB_DIS: 1 = 禁用INTB中断引脚 - * [6] HIGH_CURRENT_DRV: 1 = 通道0高电流驱动模式 - * [5:0] RESERVED: 必须写入 0x01 -*/ - -/* --- 位域选项宏 --- */ -// [15:14] Active Channel Selection -#define LDC1612_CONFIG_ACTIVE_CHAN_CH0 (0x00 << 14) -#define LDC1612_CONFIG_ACTIVE_CHAN_CH1 (0x01 << 14) - -// [13] Sleep Mode Enable -#define LDC1612_CONFIG_SLEEP_MODE_DISABLE (0x00 << 13) -#define LDC1612_CONFIG_SLEEP_MODE_ENABLE (0x01 << 13) - -// [12] RP Override Enable (Auto-Calibration Disable) -#define LDC1612_CONFIG_RP_OVERRIDE_DISABLE (0x00 << 12) // 启用自动校准 -#define LDC1612_CONFIG_RP_OVERRIDE_ENABLE (0x01 << 12) // 禁用自动校准 - -// [11] Sensor Activation Current Selection -#define LDC1612_CONFIG_SENSOR_ACT_LOW_I (0x00 << 11) // 低电流激活 -#define LDC1612_CONFIG_SENSOR_ACT_HIGH_I (0x01 << 11) // 高电流激活 - -// [10] Auto Amplitude Correction Disable -#define LDC1612_CONFIG_AUTO_AMP_ENABLE (0x00 << 10) // 启用自动幅度校正 -#define LDC1612_CONFIG_AUTO_AMP_DISABLE (0x01 << 10) // 禁用自动幅度校正 - -// [9] Reference Clock Source -#define LDC1612_CONFIG_CLK_SRC_INTERNAL (0x00 << 9) -#define LDC1612_CONFIG_CLK_SRC_EXTERNAL (0x01 << 9) - -// [7] INTB Pin Disable -#define LDC1612_CONFIG_INTB_ENABLE (0x00 << 7) -#define LDC1612_CONFIG_INTB_DISABLE (0x01 << 7) - -// [6] High Current Drive (Channel 0) -#define LDC1612_CONFIG_HIGH_CURRENT_DISABLE (0x00 << 6) -#define LDC1612_CONFIG_HIGH_CURRENT_ENABLE (0x01 << 6) - -/* --- 组合宏 --- */ -// 将所有位域组合成一个16位值。注意，保留位0x01被固定添加。 -#define LDC1612_CONFIG_GEN(active_chan, sleep, rp_override, sensor_act, auto_amp, clk_src, intb, high_current) \ - ( (active_chan) | (sleep) | (rp_override) | (sensor_act) | (auto_amp) | (clk_src) | (intb) | (high_current) | 0x0001 ) - -/* --- 预设配置示例 --- */ -// CH0连续转换, 外部时钟, 高驱动电流, 禁用自动幅度修正(适用于电流检测) -#define LDC1612_SENSOR_CONFIG_CH0 LDC1612_CONFIG_GEN( \ - LDC1612_CONFIG_ACTIVE_CHAN_CH0, \ - LDC1612_CONFIG_SLEEP_MODE_DISABLE, \ - LDC1612_CONFIG_RP_OVERRIDE_ENABLE, /* Rp覆盖开启 */ \ - LDC1612_CONFIG_SENSOR_ACT_LOW_I, /* 低功耗启动 */ \ - LDC1612_CONFIG_AUTO_AMP_DISABLE, /* 禁用自动幅度校正 */ \ - LDC1612_CONFIG_CLK_SRC_EXTERNAL, /* 外部时钟 */ \ - LDC1612_CONFIG_INTB_ENABLE, /* 启用INTB引脚 */ \ - LDC1612_CONFIG_HIGH_CURRENT_ENABLE /* 大电流模式 */ ) // 结果: 0x1641 - // TODO 对比1601的不同(大电流与标准电流) - -// 睡眠模式, 外部时钟 -#define LDC1612_SLEEP_MODE LDC1612_CONFIG_GEN( \ - LDC1612_CONFIG_ACTIVE_CHAN_CH0, \ - LDC1612_CONFIG_SLEEP_MODE_ENABLE, \ - LDC1612_CONFIG_RP_OVERRIDE_DISABLE, \ - LDC1612_CONFIG_SENSOR_ACT_HIGH_I, \ - LDC1612_CONFIG_AUTO_AMP_ENABLE, \ - LDC1612_CONFIG_CLK_SRC_INTERNAL, \ - LDC1612_CONFIG_INTB_ENABLE, \ - LDC1612_CONFIG_HIGH_CURRENT_DISABLE ) // 结果: 0x2801 - -/*************************MUX_CONFIG (0x1B) MACROS***************************************/ -/* - * MUX_CONFIG寄存器位域宏定义，用于灵活组合生成配置值。 - * - * 位域说明: - * [15] AUTOSCAN_EN: 1 = 自动顺序扫描模式使能 - * [14:13] RR_SEQUENCE: 扫描序列 (00: CH0, CH1) - * [12:3] RESERVED: 必须写入 0x041 - * [2:0] DEGLITCH: 输入消抖滤波器带宽 -*/ -/* --- 位域选项宏 --- */ -// [15] Auto Scan Mode -#define LDC1612_MUX_AUTOSCAN_DISABLE (0x00 << 15) // 单通道连续模式 -#define LDC1612_MUX_AUTOSCAN_ENABLE (0x01 << 15) // 自动扫描模式 - -// [14:13] Round Robin Sequence -#define LDC1612_MUX_RR_SEQ_CH0_CH1 (0x00 << 13) // 扫描 CH0, CH1 - -// [2:0] Deglitch Filter Bandwidth -#define LDC1612_MUX_DEGLITCH_1MHZ (0x01) -#define LDC1612_MUX_DEGLITCH_3_3MHZ (0x04) -#define LDC1612_MUX_DEGLITCH_10MHZ (0x05) -#define LDC1612_MUX_DEGLITCH_33MHZ (0x07) - -/* --- 组合宏 --- */ -// 将所有位域组合成一个16位值。注意，保留位0x0208 (0x041 << 3)被固定添加。 -#define LDC1612_MUX_CONFIG_GEN(autoscan, sequence, deglitch) \ - ( (autoscan) | (sequence) | (deglitch) | 0x0208 ) - -/* --- 预设配置示例 --- */ -// 单通道模式, 3.3MHz 滤波 -#define LDC1612_MUX_CONFIG LDC1612_MUX_CONFIG_GEN( \ - LDC1612_MUX_AUTOSCAN_DISABLE, \ - LDC1612_MUX_RR_SEQ_CH0_CH1, /* 此模式下无效，但保持定义 */ \ - LDC1612_MUX_DEGLITCH_3_3MHZ ) // 0x020C - -/***********************RESET DEVICE (0x1C)***********************************/ -/* - * 向RESET_DEV寄存器写入 LDC1612_RESET_CMD 会触发软件复位。 - * 复位后，所有寄存器将恢复为默认值，设备进入睡眠模式。 - * 需要大约10ms的稳定时间后才能重新配置。 -*/ -#define LDC1612_RESET_DEV 0x8000 - -/**************************DRIVE_CURRENT (0x1E, 0x1F)****************************************/ -/* - * 作用: 设置传感器的驱动电流，以确保振荡幅度(Vosc)在1.2V到1.8V之间。 - * - * 位域说明: - * [15:11] IDRIVE: 当前驱动电流设置值 (0-31)。 - * [10:6] INIT_IDRIVE: 初始驱动电流设置值 (0-31)。 - * [5:0] RESERVED: 必须为0。 - * - * 配置建议: - * 1. 初始阶段可启用自动校准 (CONFIG.RP_OVERRIDE_EN = 0)，让芯片自动寻找合适的IDRIVE值。 - * 2. 读取DRIVE_CURRENT寄存器，获得自动校准后的IDRIVE值。 - * 3. 在最终代码中，禁用自动校准 (CONFIG.RP_OVERRIDE_EN = 1)，并手动写入这个调试好的IDRIVE值。 - * - * CH_INIT_IDRIVE will update when every conversion systick ==>AutoAmpDis is 0 - * CH_INIT_IDRIVE will store init drive current calculated ==> AutoAmpDis is 1 -*/ - -/* --- 驱动电流值生成宏 --- */ -// 参数 idrive: 0-31之间的整数 -#define LDC1612_DRIVE_CURRENT_GEN(idrive) ( (uint16_t)(idrive) << 11 ) - -#define LDC1612_DRIVE_CURRENT LDC1612_DRIVE_CURRENT_GEN(18) // 0x9000 - -/**************************IDs (Read Only 0x7E 0x7F)***********************************/ - -#define LDC1612_MANUFACTURER_ID 0x5449 -#define LDC1612_DEVICE_ID 0x3055 - -/******************************************************************************/ - -typedef enum { - LDC1612_STATUS_SUCCESS = 0, - LDC1612_STATUS_ERROR, - LDC1612_STATUS_TIMEOUT, - LDC1612_STATUS_INVALID_PARAM, - LDC1612_STATUS_NO_COIL, - LDC1612_STATUS_UNDER_RANGE, - LDC1612_STATUS_OVER_RANGE -} ldc1612_status_t; - -/******************************************************************************/ -ldc1612_status_t ldc1612_init(void); - -ldc1612_status_t ldc1612_reset_sensor(void); - -ldc1612_status_t ldc1612_config_single_channel(uint8_t channel); - -uint16_t ldc1612_get_manufacturer_id(void); - -uint16_t ldc1612_get_deveice_id(void); - -uint32_t ldc1612_get_raw_channel_result(uint8_t channel); - -void ldc1612_drvie_current_detect(uint8_t channel); - -uint16_t ldc1612_get_sensor_status(void); - -bool ldc1612_is_data_ready(uint8_t channel); - -uint16_t ldc1612_check_status_and_log_errors(void); - -#endif //LDC1612_H +// +// Created by dell on 24-12-3. +// + +#ifndef LDC1612_H +#define LDC1612_H + +#include "gd32e23x_it.h" +#include "gd32e23x.h" +#include "systick.h" +#include +#include +#include +#include +#include +#include "board_config.h" +#include "i2c.h" + +/***************************************************************************/ + +/* IIC Interface Selection */ +#ifdef SOFTWARE_IIC + #define LDC1612_IIC_WRITE_16BITS(addr, reg, data) soft_i2c_write_16bits(addr, reg, data) + #define LDC1612_IIC_READ_16BITS(addr, reg, data) soft_i2c_read_16bits(addr, reg, data) + #define LDC1612_IIC_TYPE_STR "Software IIC" +#else + #define LDC1612_IIC_WRITE_16BITS(addr, reg, data) i2c_write_16bits(addr, reg, data) + #define LDC1612_IIC_READ_16BITS(addr, reg, data) i2c_read_16bits(addr, reg, data) + #define LDC1612_IIC_TYPE_STR "Hardware IIC" +#endif + +/***************************************************************************/ + +#define LDC1612_ADDR (0x2B) + +/************************Register Addr***************************************/ + +#define CONVERTION_RESULT_REG_START 0X00 +#define SET_CONVERSION_TIME_REG_START 0X08 +#define SET_CONVERSION_OFFSET_REG_START 0X0C +#define SET_SETTLECOUNT_REG_START 0X10 +#define SET_FREQ_REG_START 0X14 + +#define SENSOR_STATUS_REG 0X18 +#define ERROR_CONFIG_REG 0X19 +#define SENSOR_CONFIG_REG 0X1A +#define MUX_CONFIG_REG 0X1B +#define SENSOR_RESET_REG 0X1C +#define SET_DRIVER_CURRENT_REG 0X1E + +#define READ_MANUFACTURER_ID 0X7E +#define READ_DEVICE_ID 0X7F + +/**********************Sensor Channel****************************************/ + +#define CHANNEL_0 0 +#define CHANNEL_1 1 + +/*************************MUX_CONFIG******************************************** + * 0x0209 AutoScanEN: 0 / RR_SEQ: 00 / RESERVED: 0 0010 0000 1 / Deglitch: 001( 1MHz) + * 0x020C AutoScanEN: 0 / RR_SEQ: 00 / RESERVED: 0 0010 0000 1 / Deglitch: 100(3.3MHz) + * 0x020D AutoScanEN: 0 / RR_SEQ: 00 / RESERVED: 0 0010 0000 1 / Deglitch: 100( 10MHz) + * 0x020F AutoScanEN: 0 / RR_SEQ: 00 / RESERVED: 0 0010 0000 1 / Deglitch: 100( 33MHz) +*/ +#define LDC1612_MUX_CONFIG 0x020C + +/***********************SENSOR_CONFIG******************************************** + * 0x1601 Active CH0: 00 / SLEEP: 0 / OVERDRIVE: 1 / LowPowerMode: 0 / AutoAmpDis 1 / CLK(ext): 1 / RESERVED: 0 / INTB_Dis : 0 / HighCurrent: 0 / RESERVED: 00 0001 + * 0x1201 Active CH0: 00 / SLEEP: 0 / OVERDRIVE: 1 / LowPowerMode: 0 / AutoAmpDis 0 / CLK(ext): 1 / RESERVED: 0 / INTB_Dis : 0 / HighCurrent: 0 / RESERVED: 00 0001 + * 0x1641 Active CH0: 00 / SLEEP: 0 / OVERDRIVE: 1 / LowPowerMode: 0 / AutoAmpDis 1 / CLK(ext): 1 / RESERVED: 0 / INTB_Dis : 0 / HighCurrent: 1 / RESERVED: 00 0001 + * 0x1241 Active CH0: 00 / SLEEP: 0 / OVERDRIVE: 1 / LowPowerMode: 0 / AutoAmpDis 0 / CLK(ext): 1 / RESERVED: 0 / INTB_Dis : 0 / HighCurrent: 1 / RESERVED: 00 0001 +*/ + +#ifdef EDDY_DRIVE_CURRENT_DETECTION + #define LDC1612_SENSOR_CONFIG_CH0 0x1241 +#else + #define LDC1612_SENSOR_CONFIG_CH0 0x1641 +#endif +#define LDC1612_SLEEP_MODE 0x2801 + +/****************************CONVERSION_TIME************************************ + * Freq_ref = 40MHz / CHx_FREF_DIVIDER + * ******RCOUNT_CHx******* + * Reference Count Conversion Interval Time + * 0x0005 ~ 0xFFFF + * default: 0x0080 + * RCOUNT_CHx * 16 / Freq_ref = Conversion Interval Time + * + * ******SETTLECOUNT_CHx******* + * Conversion Settling Time + * 0x0000 ~ 0xFFFF + * default: 0x0000 + * SETTLECOUNT_CHx * 16 / Freq_ref = Conversion Settling Time + * 0x1000 4096*16个时钟周期 + * 0x0100 256*16个时钟周期 + * 0x0000/0x0001 32*16个时钟周期 + * + * ******RCOUNT_CHx******* +*/ +#define LDC1612_RCOUNT_TIME_CH0 0x1000 // 0x1000=4096个时钟周期 +#define LDC1612_SETTLECOUNT_CH0 0x0100 + +/**************************DRIVE_CURRENT**************************************** + * 0xA000 CH_IDRIVE: 1010 0 / CH_INIT_IDRIVE: 000 00 / RESERVED: 00 0000 + * 0x9000 CH_IDRIVE: 1001 0 / CH_INIT_IDRIVE: 000 00 / RESERVED: 00 0000 + * CH_INIT_IDRIVE will update when every conversion systick ==>AutoAmpDis is 0 + * CH_INIT_IDRIVE will store init drive current calculated ==> AutoAmpDis is 1 +*/ +#define LDC1612_DRIVE_CURRENT 0x9000 + +/**************************SENSOR_CONFIG***************************************/ + + + +/**************************ERROR_CONFIG**************************************** + * [15] Under-Range ERR to OUT (DATA_CHx.CHx_ERR_UR) + * [14] Over-Range ERR to OUT (DATA_CHx.CHx_ERR_OR) + * [13] Watchdog-Timeout ERR to OUT (DATA_CHx.CHx_ERR_WD) + * [12] Amplitude-High-Error ERR to OUT (DATA_CHx.CHx_ERR_AE) + * [11] Amplitude-Low-Error ERR to OUT (DATA_CHx.CHx_ERR_AE) + * [10] RESERVED + * [ 9] RESERVED + * [ 8] RESERVED + * [ 7] Under-Range ERR to INTB (STATUS.ERR_UR) + * [ 6] Over-Range ERR to INTB (STATUS.ERR_OR) + * [ 5] Watchdog-Timeout ERR to INTB (STATUS.ERR_WD) + * [ 4] Amplitude-High-Error ERR to INTB (STATUS.ERR_AHE) + * [ 3] Amplitude-Low-Error ERR to INTB (STATUS.ERR_ALE) + * [ 2] Zero_Count_Error ERR to INTB (STATUS.ERR_ZC) + * [ 1] RESERVED + * [ 0] Data_Ready_Flag to INTB (STATUS.DRDY) + * + * 0x0000 No ERR to OUT or INTB +*/ + +#define LDC1612_ERROR_CONFIG 0x0000 + +/**************************STATUS**************************************** + * [15] + * [14] Error Channel 0b00: CH0 / 0b01: CH1 / 0b10: CH2 / 0b11: CH3 + * [13] Conversion Under-Range Error 0b0: No / 0b1: Yes + * [12] Conversion Over-Range Error 0b0: No / 0b1: Yes + * [11] Watchdog Timeout Error 0b0: No / 0b1: Yes + * [10] Amplitude High Error 0b0: No / 0b1: Yes + * [ 9] Amplitude Low Error 0b0: No / 0b1: Yes + * [ 8] Zero Count Error 0b0: No / 0b1: Yes + * [ 7] RESERVED + * [ 6] Ddata Ready Flag 0b0: No new results / 0b1: New results available + * [ 5] RESERVED + * [ 4] RESERVED + * [ 3] CH0 Unread Conversion Result 0b0: No / 0b1: Yes(DATA_CH0) + * [ 2] CH1 Unread Conversion Result 0b0: No / 0b1: Yes(DATA_CH1) + * [ 1] CH2 Unread Conversion Result 0b0: No / 0b1: Yes(DATA_CH2) + * [ 0] CH3 Unread Conversion Result 0b0: No / 0b1: Yes(DATA_CH3) + * + * 0x0000 No ERR to OUT or INTB +*/ + +/*****************CONVERSION_OFFSET_CONFIG****************************************/ + +#define SET_CONVERSION_OFFSET_CH0 0x0000 + +/***********************RESET DEVICE******************************************** +0x8000 RESET_DEV: 1 / RESERVED: 000 0000 0000 0000 +*/ + +#define LDC1612_RESET_DEV 0x8000 //[15:0] 0b1000 0000 0000 0000 + +/***********************IDs****************************************************/ + +#define LDC1612_MANUFACTURER_ID 0x5449 +#define LDC1612_DEVICE_ID 0x3055 + +/******************************************************************************/ + +#define COIL_RP_KOM 7.2 +#define COIL_L_UH 11.22 +#define COIL_C_PF 150 +#define COIL_Q_FACTOR 31.09 +#define COIL_FREQ_HZ 5323770 + +/******************************************************************************/ + +typedef enum { + LDC1612_STATUS_SUCCESS = 0, + LDC1612_STATUS_ERROR, + LDC1612_STATUS_TIMEOUT, + LDC1612_STATUS_INVALID_PARAM, + LDC1612_STATUS_NO_COIL, + LDC1612_STATUS_UNDER_RANGE, + LDC1612_STATUS_OVER_RANGE +} ldc1612_status_t; + +/******************************************************************************/ +ldc1612_status_t ldc1612_init(void); + +ldc1612_status_t ldc1612_reset_sensor(void); + +ldc1612_status_t ldc1612_config_single_channel(uint8_t channel); + +uint16_t ldc1612_get_manufacturer_id(void); + +uint16_t ldc1612_get_deveice_id(void); + +uint32_t ldc1612_get_raw_channel_result(uint8_t channel); + +void ldc1612_drvie_current_detect(uint8_t channel); + +uint16_t ldc1612_get_sensor_status(void); + +bool ldc1612_is_data_ready(uint8_t channel); + +#endif //LDC1612_H diff --git a/Inc/led.h b/Inc/led.h index 7376a5e..e3bc7ce 100644 --- a/Inc/led.h +++ b/Inc/led.h @@ -1,13 +1,13 @@ -#ifndef LED_H -#define LED_H - -#include "gd32e23x.h" -#include "board_config.h" - -void led_init(void); -void led_on(void); -void led_off(void); -void led_toggle(void); -void led_heart_beat(void); - -#endif // LED_H +#ifndef LED_H +#define LED_H + +#include "gd32e23x.h" +#include "board_config.h" + +void led_init(void); +void led_on(void); +void led_off(void); +void led_toggle(void); +void led_heart_beat(void); + +#endif // LED_H diff --git a/Inc/soft_i2c.h b/Inc/soft_i2c.h index aab2bda..4e60b12 100644 --- a/Inc/soft_i2c.h +++ b/Inc/soft_i2c.h @@ -1,52 +1,52 @@ -// -// Created by dell on 24-12-28. -// - -#ifndef SOFT_I2C_H -#define SOFT_I2C_H - -#include "gd32e23x_it.h" -#include "gd32e23x.h" -#include "systick.h" - -#include "board_config.h" - -/******************************************************************************/ - -#define I2C_SCL_HIGH() gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN) -#define I2C_SCL_LOW() gpio_bit_reset(I2C_SCL_PORT, I2C_SCL_PIN) -#define I2C_SDA_HIGH() gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN) -#define I2C_SDA_LOW() gpio_bit_reset(I2C_SDA_PORT, I2C_SDA_PIN) -#define I2C_SDA_READ() gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN) - -/******************************************************************************/ - -#define SOFT_I2C_OK 1 -#define SOFT_I2C_FAIL 0 -#define SOFT_I2C_END 1 - -/******************************************************************************/ - -void soft_i2c_delay(void); - -void soft_i2c_config(void); - -void soft_i2c_start(void); - -void soft_i2c_stop(void); - -void soft_i2c_send_ack(void); - -void soft_i2c_send_nack(void); - -uint8_t soft_i2c_wait_ack(void); - -void soft_i2c_send_byte(uint8_t data); - -uint8_t soft_i2c_receive_byte(uint8_t ack); - -uint8_t soft_i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]); - -uint8_t soft_i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); - -#endif //SOFT_I2C_H +// +// Created by dell on 24-12-28. +// + +#ifndef SOFT_I2C_H +#define SOFT_I2C_H + +#include "gd32e23x_it.h" +#include "gd32e23x.h" +#include "systick.h" + +#include "board_config.h" + +/******************************************************************************/ + +#define I2C_SCL_HIGH() gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN) +#define I2C_SCL_LOW() gpio_bit_reset(I2C_SCL_PORT, I2C_SCL_PIN) +#define I2C_SDA_HIGH() gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN) +#define I2C_SDA_LOW() gpio_bit_reset(I2C_SDA_PORT, I2C_SDA_PIN) +#define I2C_SDA_READ() gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN) + +/******************************************************************************/ + +#define SOFT_I2C_OK 1 +#define SOFT_I2C_FAIL 0 +#define SOFT_I2C_END 1 + +/******************************************************************************/ + +void soft_i2c_delay(void); + +void soft_i2c_config(void); + +void soft_i2c_start(void); + +void soft_i2c_stop(void); + +void soft_i2c_send_ack(void); + +void soft_i2c_send_nack(void); + +uint8_t soft_i2c_wait_ack(void); + +void soft_i2c_send_byte(uint8_t data); + +uint8_t soft_i2c_receive_byte(uint8_t ack); + +uint8_t soft_i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]); + +uint8_t soft_i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data); + +#endif //SOFT_I2C_H diff --git a/Inc/systick.h b/Inc/systick.h index 202ecf6..cb73c84 100644 --- a/Inc/systick.h +++ b/Inc/systick.h @@ -1,36 +1,36 @@ -/** -* ************************************************************************ - * - * @file systick.h - * @author GD32 - * @brief - * - * ************************************************************************ - * @copyright Copyright (c) 2024 GD32 - * ************************************************************************ - */ -#ifndef SYS_TICK_H -#define SYS_TICK_H - -#include - -/* function declarations */ -/* configure systick */ -void systick_config(void); - -/* delay a time in 10 microseconds */ -void delay_10us(uint32_t count); - -/* delay a time in milliseconds */ -void delay_ms(uint32_t count); - -/* decrement delay counters */ -void delay_decrement(void); - -// /* delay function that doesn't interfere with SysTick interrupt */ -// void delay_ms_safe(uint32_t count); - -// /* delay a time in microseconds (safe version) */ -// void delay_us_safe(uint32_t count); - +/** +* ************************************************************************ + * + * @file systick.h + * @author GD32 + * @brief + * + * ************************************************************************ + * @copyright Copyright (c) 2024 GD32 + * ************************************************************************ + */ +#ifndef SYS_TICK_H +#define SYS_TICK_H + +#include + +/* function declarations */ +/* configure systick */ +void systick_config(void); + +/* delay a time in 10 microseconds */ +void delay_10us(uint32_t count); + +/* delay a time in milliseconds */ +void delay_ms(uint32_t count); + +/* decrement delay counters */ +void delay_decrement(void); + +// /* delay function that doesn't interfere with SysTick interrupt */ +// void delay_ms_safe(uint32_t count); + +// /* delay a time in microseconds (safe version) */ +// void delay_us_safe(uint32_t count); + #endif /* SYS_TICK_H */ \ No newline at end of file diff --git a/Inc/tmp112.h b/Inc/tmp112.h index c473a83..270747d 100644 --- a/Inc/tmp112.h +++ b/Inc/tmp112.h @@ -1,157 +1,157 @@ -// -// Created by dell on 24-12-20. -// TMP112A Temperature Sensor Driver Header -// - -#ifndef TMP112_H -#define TMP112_H - -#include "gd32e23x_it.h" -#include "gd32e23x.h" -#include "systick.h" -#include -#include -#include -#include -#include -#include "board_config.h" -#include "i2c.h" - -/******************************************************************************/ -/* TMP112A I2C Address */ -#define TMP112A_ADDR (0x49) // 7-bit address (ADD0=GND) - -/* Register Addresses */ -/******************************************************************************/ -#define TMP112A_TEMP_REG 0x00 // 温度寄存器 -#define TMP112A_CONFIG_REG 0x01 // 配置寄存器 -#define TMP112A_TLOW_REG 0x02 // 低温阈值寄存器 -#define TMP112A_THIGH_REG 0x03 // 高温阈值寄存器 - -/* Configuration Register Bits */ -/******************************************************************************/ -#define TMP112A_CONFIG_OS (1 << 15) // One-shot -#define TMP112A_CONFIG_R1 (1 << 14) // Converter resolution bit 1 -#define TMP112A_CONFIG_R0 (1 << 13) // Converter resolution bit 0 -#define TMP112A_CONFIG_F1 (1 << 12) // Fault queue bit 1 -#define TMP112A_CONFIG_F0 (1 << 11) // Fault queue bit 0 -#define TMP112A_CONFIG_POL (1 << 10) // Polarity -#define TMP112A_CONFIG_TM (1 << 9) // Thermostat mode -#define TMP112A_CONFIG_SD (1 << 8) // Shutdown -#define TMP112A_CONFIG_CR1 (1 << 7) // Conversion rate bit 1 -#define TMP112A_CONFIG_CR0 (1 << 6) // Conversion rate bit 0 -#define TMP112A_CONFIG_AL (1 << 5) // Alert -#define TMP112A_CONFIG_EM (1 << 4) // Extended mode - -/* Resolution Settings */ -/******************************************************************************/ -#define TMP112A_RESOLUTION_9BIT 0x0000 // 9-bit (0.5°C) -#define TMP112A_RESOLUTION_10BIT 0x2000 // 10-bit (0.25°C) -#define TMP112A_RESOLUTION_11BIT 0x4000 // 11-bit (0.125°C) -#define TMP112A_RESOLUTION_12BIT 0x6000 // 12-bit (0.0625°C) - -/* Conversion Rate Settings */ -/******************************************************************************/ -#define TMP112A_RATE_0_25HZ 0x0000 // 0.25 Hz (4s) -#define TMP112A_RATE_1HZ 0x0040 // 1 Hz (1s) -#define TMP112A_RATE_4HZ 0x0080 // 4 Hz (250ms) -#define TMP112A_RATE_8HZ 0x00C0 // 8 Hz (125ms) - -/* Default Configuration */ -/******************************************************************************/ -#define TMP112A_CONFIG_DEFAULT (TMP112A_RESOLUTION_12BIT | TMP112A_RATE_8HZ) - -/* Temperature Conversion Constants */ -/******************************************************************************/ -#define TMP112A_TEMP_RESOLUTION 0.0625f // 12-bit resolution (°C/LSB) -#define TMP112A_TEMP_MIN -55.0f // 最低温度 (°C) -#define TMP112A_TEMP_MAX 125.0f // 最高温度 (°C) - -/* Status Definitions */ -/******************************************************************************/ -typedef enum { - TMP112A_STATUS_SUCCESS = 0, - TMP112A_STATUS_ERROR, - TMP112A_STATUS_TIMEOUT, - TMP112A_STATUS_INVALID_PARAM, - TMP112A_STATUS_OUT_OF_RANGE -} tmp112a_status_t; - -typedef struct { - uint16_t raw_data; - float temperature_c; - float temperature_f; - bool alert_flag; -} tmp112a_result_t; - -/******************************************************************************/ -/* Function Declarations */ - -/*! - \brief 初始化TMP112A传感器 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_init(void); - -/*! - \brief 配置TMP112A传感器 - \param[in] config: 配置值 - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_config(uint16_t config); - -/*! - \brief 读取温度 - \param[in] none - \param[out] result: 结果结构体指针 - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_read_temperature(tmp112a_result_t *result); - -void tmp112a_get_raw_temperature_value(uint8_t *value); - -/*! - \brief 设置温度阈值 - \param[in] low_temp: 低温阈值 (°C) - \param[in] high_temp: 高温阈值 (°C) - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_set_thresholds(float low_temp, float high_temp); - -/*! - \brief 进入关机模式 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_shutdown(void); - -/*! - \brief 退出关机模式 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_wakeup(void); - -/*! - \brief 单次转换 - \param[in] none - \param[out] result: 结果结构体指针 - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_one_shot(tmp112a_result_t *result); - -/*! - \brief 获取状态字符串 - \param[in] status: 状态码 - \param[out] none - \retval const char* 状态字符串 -*/ -const char* tmp112a_get_status_string(tmp112a_status_t status); - -#endif //TMP112_H +// +// Created by dell on 24-12-20. +// TMP112A Temperature Sensor Driver Header +// + +#ifndef TMP112_H +#define TMP112_H + +#include "gd32e23x_it.h" +#include "gd32e23x.h" +#include "systick.h" +#include +#include +#include +#include +#include +#include "board_config.h" +#include "i2c.h" + +/******************************************************************************/ +/* TMP112A I2C Address */ +#define TMP112A_ADDR (0x49) // 7-bit address (ADD0=GND) + +/* Register Addresses */ +/******************************************************************************/ +#define TMP112A_TEMP_REG 0x00 // 温度寄存器 +#define TMP112A_CONFIG_REG 0x01 // 配置寄存器 +#define TMP112A_TLOW_REG 0x02 // 低温阈值寄存器 +#define TMP112A_THIGH_REG 0x03 // 高温阈值寄存器 + +/* Configuration Register Bits */ +/******************************************************************************/ +#define TMP112A_CONFIG_OS (1 << 15) // One-shot +#define TMP112A_CONFIG_R1 (1 << 14) // Converter resolution bit 1 +#define TMP112A_CONFIG_R0 (1 << 13) // Converter resolution bit 0 +#define TMP112A_CONFIG_F1 (1 << 12) // Fault queue bit 1 +#define TMP112A_CONFIG_F0 (1 << 11) // Fault queue bit 0 +#define TMP112A_CONFIG_POL (1 << 10) // Polarity +#define TMP112A_CONFIG_TM (1 << 9) // Thermostat mode +#define TMP112A_CONFIG_SD (1 << 8) // Shutdown +#define TMP112A_CONFIG_CR1 (1 << 7) // Conversion rate bit 1 +#define TMP112A_CONFIG_CR0 (1 << 6) // Conversion rate bit 0 +#define TMP112A_CONFIG_AL (1 << 5) // Alert +#define TMP112A_CONFIG_EM (1 << 4) // Extended mode + +/* Resolution Settings */ +/******************************************************************************/ +#define TMP112A_RESOLUTION_9BIT 0x0000 // 9-bit (0.5°C) +#define TMP112A_RESOLUTION_10BIT 0x2000 // 10-bit (0.25°C) +#define TMP112A_RESOLUTION_11BIT 0x4000 // 11-bit (0.125°C) +#define TMP112A_RESOLUTION_12BIT 0x6000 // 12-bit (0.0625°C) + +/* Conversion Rate Settings */ +/******************************************************************************/ +#define TMP112A_RATE_0_25HZ 0x0000 // 0.25 Hz (4s) +#define TMP112A_RATE_1HZ 0x0040 // 1 Hz (1s) +#define TMP112A_RATE_4HZ 0x0080 // 4 Hz (250ms) +#define TMP112A_RATE_8HZ 0x00C0 // 8 Hz (125ms) + +/* Default Configuration */ +/******************************************************************************/ +#define TMP112A_CONFIG_DEFAULT (TMP112A_RESOLUTION_12BIT | TMP112A_RATE_8HZ) + +/* Temperature Conversion Constants */ +/******************************************************************************/ +#define TMP112A_TEMP_RESOLUTION 0.0625f // 12-bit resolution (°C/LSB) +#define TMP112A_TEMP_MIN -55.0f // 最低温度 (°C) +#define TMP112A_TEMP_MAX 125.0f // 最高温度 (°C) + +/* Status Definitions */ +/******************************************************************************/ +typedef enum { + TMP112A_STATUS_SUCCESS = 0, + TMP112A_STATUS_ERROR, + TMP112A_STATUS_TIMEOUT, + TMP112A_STATUS_INVALID_PARAM, + TMP112A_STATUS_OUT_OF_RANGE +} tmp112a_status_t; + +typedef struct { + uint16_t raw_data; + float temperature_c; + float temperature_f; + bool alert_flag; +} tmp112a_result_t; + +/******************************************************************************/ +/* Function Declarations */ + +/*! + \brief 初始化TMP112A传感器 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_init(void); + +/*! + \brief 配置TMP112A传感器 + \param[in] config: 配置值 + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_config(uint16_t config); + +/*! + \brief 读取温度 + \param[in] none + \param[out] result: 结果结构体指针 + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_read_temperature(tmp112a_result_t *result); + +void tmp112a_get_raw_temperature_value(uint8_t *value); + +/*! + \brief 设置温度阈值 + \param[in] low_temp: 低温阈值 (°C) + \param[in] high_temp: 高温阈值 (°C) + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_set_thresholds(float low_temp, float high_temp); + +/*! + \brief 进入关机模式 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_shutdown(void); + +/*! + \brief 退出关机模式 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_wakeup(void); + +/*! + \brief 单次转换 + \param[in] none + \param[out] result: 结果结构体指针 + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_one_shot(tmp112a_result_t *result); + +/*! + \brief 获取状态字符串 + \param[in] status: 状态码 + \param[out] none + \retval const char* 状态字符串 +*/ +const char* tmp112a_get_status_string(tmp112a_status_t status); + +#endif //TMP112_H diff --git a/Inc/uart.h b/Inc/uart.h index b7edabc..f68da45 100644 --- a/Inc/uart.h +++ b/Inc/uart.h @@ -1,8 +1,8 @@ -#ifndef UART_H -#define UART_H - -#include "gd32e23x.h" - -void rs485_init(void); - -#endif // UART_H +#ifndef UART_H +#define UART_H + +#include "gd32e23x.h" + +void rs485_init(void); + +#endif // UART_H diff --git a/Inc/uart_ring_buffer.h b/Inc/uart_ring_buffer.h index effeb35..34692ba 100644 --- a/Inc/uart_ring_buffer.h +++ b/Inc/uart_ring_buffer.h @@ -1,119 +1,119 @@ -/** - * @file uart_ring_buffer.h - * @brief 简单高效的环形接收缓冲区（字节队列）接口声明。 - * @details 提供字节写入/读取、可读长度查询、清空与丢弃统计等 API， - * 适用于中断接收（写）与主循环解析（读）的典型嵌入式串口场景。 - */ -#ifndef UART_RING_BUFFER_H -#define UART_RING_BUFFER_H - -#include -#include - -/** - * @def UART_RX_BUFFER_SIZE - * @brief 接收环形缓冲区容量（单位：字节）。 - * @note 采用“预留一格”区分空/满策略，最大可用容量为 UART_RX_BUFFER_SIZE-1。 - */ -#define UART_RX_BUFFER_SIZE 64 - -/** - * @defgroup RingBuffer 环形缓冲区 - * @brief 字节环形缓冲区（接收端） - * @{ - */ - -/** - * @section RingBuffer_Usage 使用说明 - * 典型用法：中断接收（写入环形缓冲）、主循环解析（读取环形缓冲）。 - * - * 1) 初始化 - * @code{.c} - * uart_ring_buffer_init(); - * @endcode - * - * 2) 使能串口接收非空中断（RBNE）并开启中断（以 USART0 为例） - * @code{.c} - * usart_interrupt_enable(USART0, USART_INT_RBNE); - * nvic_irq_enable(USART0_IRQn, 2, 0); // 根据工程需要设置优先级 - * @endcode - * - * 3) 在中断服务函数中写入环形缓冲（参考你当前工程的写法） - * @code{.c} - * void USART0_IRQHandler(void) { - * if (RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) { - * uint8_t data = usart_data_receive(USART0); - * (void)uart_ring_buffer_put(data); // 缓冲满时丢弃并计数 - * } - * } - * @endcode - * - * 4) 在主循环中读取处理 - * @code{.c} - * while (uart_ring_buffer_available() > 0) { - * int b = uart_ring_buffer_get(); - * if (b >= 0) { - * // 处理字节 b - * } - * } - * @endcode - * - * @note 缓冲区满时新字节会被丢弃，可用 uart_ring_buffer_drop_count() 查看累计丢弃数。 - * @note 采用“预留一格”区分空/满，最大可用容量为 UART_RX_BUFFER_SIZE-1。 - */ - -/** - * @brief 初始化环形缓冲区。 - * @details 复位读/写索引与丢弃计数，准备接收数据。 - * @note 若在中断环境使用，初始化前建议关闭相关接收中断以避免并发竞争。 - * @ingroup RingBuffer - */ -void uart_ring_buffer_init(void); - -/** - * @brief 获取当前可读的字节数。 - * @details 返回范围为 [0, UART_RX_BUFFER_SIZE-1]。 - * @return 可读字节数（uint8_t）。 - * @note 预留一个空槽区分“空/满”，因此满时返回 UART_RX_BUFFER_SIZE-1。 - * @ingroup RingBuffer - */ -uint8_t uart_ring_buffer_available(void); - -/** - * @brief 从环形缓冲区读取一个字节。 - * @details 若缓冲区非空，返回队头字节并推进读指针；若为空，返回 -1。 - * @return 读取到的字节（0..255），或 -1 表示缓冲区为空。 - * @retval -1 缓冲区为空，无数据可读。 - * @ingroup RingBuffer - */ -int uart_ring_buffer_get(void); - -/** - * @brief 向环形缓冲区写入一个字节。 - * @param data 待写入的字节。 - * @return 是否写入成功。 - * @retval true 写入成功。 - * @retval false 写入失败（缓冲区已满，数据被丢弃并计数）。 - * @note 如需改为“覆盖写入”策略，可在满时先推进读指针再写入。 - * @ingroup RingBuffer - */ -bool uart_ring_buffer_put(uint8_t data); - -/** - * @brief 清空环形缓冲区。 - * @details 复位读/写索引与丢弃计数，相当于逻辑上丢弃所有已接收数据，不擦除数据区内容。 - * @ingroup RingBuffer - */ -void uart_ring_buffer_clear(void); - -/** - * @brief 获取因缓冲区满而被丢弃的字节累计数量。 - * @details 该计数在 init/clear 时清零。 - * @return 丢弃的累计字节数。 - * @ingroup RingBuffer - */ -uint32_t uart_ring_buffer_drop_count(void); - -/** @} */ - -#endif // UART_RING_BUFFER_H +/** + * @file uart_ring_buffer.h + * @brief 简单高效的环形接收缓冲区（字节队列）接口声明。 + * @details 提供字节写入/读取、可读长度查询、清空与丢弃统计等 API， + * 适用于中断接收（写）与主循环解析（读）的典型嵌入式串口场景。 + */ +#ifndef UART_RING_BUFFER_H +#define UART_RING_BUFFER_H + +#include +#include + +/** + * @def UART_RX_BUFFER_SIZE + * @brief 接收环形缓冲区容量（单位：字节）。 + * @note 采用“预留一格”区分空/满策略，最大可用容量为 UART_RX_BUFFER_SIZE-1。 + */ +#define UART_RX_BUFFER_SIZE 64 + +/** + * @defgroup RingBuffer 环形缓冲区 + * @brief 字节环形缓冲区（接收端） + * @{ + */ + +/** + * @section RingBuffer_Usage 使用说明 + * 典型用法：中断接收（写入环形缓冲）、主循环解析（读取环形缓冲）。 + * + * 1) 初始化 + * @code{.c} + * uart_ring_buffer_init(); + * @endcode + * + * 2) 使能串口接收非空中断（RBNE）并开启中断（以 USART0 为例） + * @code{.c} + * usart_interrupt_enable(USART0, USART_INT_RBNE); + * nvic_irq_enable(USART0_IRQn, 2, 0); // 根据工程需要设置优先级 + * @endcode + * + * 3) 在中断服务函数中写入环形缓冲（参考你当前工程的写法） + * @code{.c} + * void USART0_IRQHandler(void) { + * if (RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) { + * uint8_t data = usart_data_receive(USART0); + * (void)uart_ring_buffer_put(data); // 缓冲满时丢弃并计数 + * } + * } + * @endcode + * + * 4) 在主循环中读取处理 + * @code{.c} + * while (uart_ring_buffer_available() > 0) { + * int b = uart_ring_buffer_get(); + * if (b >= 0) { + * // 处理字节 b + * } + * } + * @endcode + * + * @note 缓冲区满时新字节会被丢弃，可用 uart_ring_buffer_drop_count() 查看累计丢弃数。 + * @note 采用“预留一格”区分空/满，最大可用容量为 UART_RX_BUFFER_SIZE-1。 + */ + +/** + * @brief 初始化环形缓冲区。 + * @details 复位读/写索引与丢弃计数，准备接收数据。 + * @note 若在中断环境使用，初始化前建议关闭相关接收中断以避免并发竞争。 + * @ingroup RingBuffer + */ +void uart_ring_buffer_init(void); + +/** + * @brief 获取当前可读的字节数。 + * @details 返回范围为 [0, UART_RX_BUFFER_SIZE-1]。 + * @return 可读字节数（uint8_t）。 + * @note 预留一个空槽区分“空/满”，因此满时返回 UART_RX_BUFFER_SIZE-1。 + * @ingroup RingBuffer + */ +uint8_t uart_ring_buffer_available(void); + +/** + * @brief 从环形缓冲区读取一个字节。 + * @details 若缓冲区非空，返回队头字节并推进读指针；若为空，返回 -1。 + * @return 读取到的字节（0..255），或 -1 表示缓冲区为空。 + * @retval -1 缓冲区为空，无数据可读。 + * @ingroup RingBuffer + */ +int uart_ring_buffer_get(void); + +/** + * @brief 向环形缓冲区写入一个字节。 + * @param data 待写入的字节。 + * @return 是否写入成功。 + * @retval true 写入成功。 + * @retval false 写入失败（缓冲区已满，数据被丢弃并计数）。 + * @note 如需改为“覆盖写入”策略，可在满时先推进读指针再写入。 + * @ingroup RingBuffer + */ +bool uart_ring_buffer_put(uint8_t data); + +/** + * @brief 清空环形缓冲区。 + * @details 复位读/写索引与丢弃计数，相当于逻辑上丢弃所有已接收数据，不擦除数据区内容。 + * @ingroup RingBuffer + */ +void uart_ring_buffer_clear(void); + +/** + * @brief 获取因缓冲区满而被丢弃的字节累计数量。 + * @details 该计数在 init/clear 时清零。 + * @return 丢弃的累计字节数。 + * @ingroup RingBuffer + */ +uint32_t uart_ring_buffer_drop_count(void); + +/** @} */ + +#endif // UART_RING_BUFFER_H diff --git a/LD/gd32e23x_flash.ld b/LD/gd32e23x_flash.ld index de91ddc..eebf864 100644 --- a/LD/gd32e23x_flash.ld +++ b/LD/gd32e23x_flash.ld @@ -1,155 +1,155 @@ -/* Memory Map */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_sp = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .vectors : - { - . = ALIGN(4); - KEEP(*(.vectors)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} +/* Memory Map */ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_sp = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08002000, LENGTH = 32K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The READONLY keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/README.md b/README.md index a2cadad..172f39c 100644 --- a/README.md +++ b/README.md @@ -1,139 +1,139 @@ -# GD32E23x 工程模板 - -本仓库为兆易创新 GD32E23x 系列 MCU 的 CMake + VSCode 工程模板，适合嵌入式开发快速上手和团队协作。 - ---- - -## 目录 - -- [适用范围](#适用范围) -- [默认配置](#默认配置) -- [工具链准备](#工具链准备) -- [使用说明](#使用说明) -- [时钟配置说明](#时钟配置说明) -- [vcpkg 依赖管理（可选）](#vcpkg-依赖管理可选) -- [建议补充内容](#建议补充内容) - ---- - -## 适用范围 - -- 适用于兆易创新 GD32E23x 系列 Cortex-M23 内核单片机 -- 支持标准外设库开发 -- 推荐开发环境：VSCode + CMake + ARM GCC 工具链 - ---- - -## 默认配置 - -- MCU 主频：内部 RC 振荡器，系统时钟配置为 72MHz - ---- - -## 工具链准备 - -### 1. xPack GNU Arm Embedded GCC Toolchain - -- **版本**：xpack-arm-none-eabi-gcc-11.3.1-1.1 -- **建议解压路径**：Tools/xpack-arm-none-eabi-gcc-11.3.1-1.1 -- **官方下载地址**：https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases -- **路径自定义说明**： - 如需自定义工具链路径，请同步修改以下文件： - - `Projects///cmake/arm-none-eabi-gcc.cmake`（第2行） - - `Projects///.vscode/launch.json`（第12行） - -### 2. OpenOCD - -- **版本**：xpack-openocd-0.11.0-3 -- **建议解压路径**：Tools/xpack-openocd-0.11.0-3 -- **获取地址**：https://github.com/burakenez/gd32-tools-xpack-openocd/tree/v0.11.0-3 -- **说明**： - - 本版本提取自 Embedded Builder V1.4.1.23782。 - - ⚠️ 请勿随意更换版本，因 GD32 MCU 支持有限，推荐严格使用此版本。 -- **路径自定义说明**： - 如需自定义 OpenOCD 路径，请同步修改以下文件： - - `Projects///.vscode/launch.json`（第14、17行） - - `Projects///.vscode/task.json` 中所有相关路径 - ---- - -## 使用说明 - -1. **准备工具链** - - 按上述说明下载并解压 ARM GCC 和 OpenOCD 到 Tools 目录。 - - Toolchain 目录内容不会被 git 跟踪，需自行维护。 - -2. **烧录固件** - - 可直接使用 VSCode 任务栏的 Flash MCU 任务，或命令行运行 OpenOCD。 - ---- - -## 时钟配置说明 - -本工程默认系统时钟为内部 IRC8M 振荡器经 PLL 倍频后的 72MHz。 - -如需修改主频或时钟源，请编辑 `Src/system_gd32e23x.c` 文件： - -1. 查找如下宏定义区： - ```c - // #define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) - // #define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) - // #define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) - #define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) - ``` -2. 取消你需要的时钟方案的注释，并注释掉其它方案。 -3. 保存后重新编译工程即可生效。 - -详细时钟初始化流程可参考 `system_gd32e23x.c` 文件中的 `system_clock_config` 及相关函数实现。 - ---- - -## vcpkg 依赖管理（可选） - -本工程可选支持 vcpkg 作为 C/C++ 工具链和构建工具的自动化依赖管理方案。 - -- 自动下载和管理如 CMake、Ninja 等构建工具，简化环境配置。 -- 可扩展用于第三方 C/C++ 库的统一管理。 - -**启用方法**： -1. 在项目根目录创建 `vcpkg-configuration.json` 文件，内容如下： - - ```json - { - "registries": [ - { - "name": "microsoft", - "location": "https://aka.ms/vcpkg-ce-default", - "kind": "artifact" - }, - { - "name": "arm", - "location": "https://aka.ms/vcpkg-artifacts-arm", - "kind": "artifact" - } - ], - "requires": { - "arm:tools/ninja-build/ninja": "^1.12.0", - "arm:tools/kitware/cmake": "^3.28.4" - } - } - ``` - -2. 启动 VSCode 或命令行，vcpkg 会自动检测并安装所需工具。 - -如不需要 vcpkg，可忽略本文件。 - ---- - -## 建议补充内容 - -- **快速上手示例**：如 main.c 的最小点灯/串口输出代码片段。 -- **常见问题与解答**：如构建失败、烧录失败的排查建议。 -- **调试说明**：如何用 VSCode 调试、断点、查看寄存器等。 -- **多板卡适配说明**：如有多种硬件，如何切换 BoardName。 -- **贡献指南**：如何提交 PR、代码风格约定等。 -- **License 说明**：开源协议和版权声明。 - ---- - -如需进一步完善或有其他建议，欢迎随时反馈！ +# GD32E23x 工程模板 + +本仓库为兆易创新 GD32E23x 系列 MCU 的 CMake + VSCode 工程模板，适合嵌入式开发快速上手和团队协作。 + +--- + +## 目录 + +- [适用范围](#适用范围) +- [默认配置](#默认配置) +- [工具链准备](#工具链准备) +- [使用说明](#使用说明) +- [时钟配置说明](#时钟配置说明) +- [vcpkg 依赖管理（可选）](#vcpkg-依赖管理可选) +- [建议补充内容](#建议补充内容) + +--- + +## 适用范围 + +- 适用于兆易创新 GD32E23x 系列 Cortex-M23 内核单片机 +- 支持标准外设库开发 +- 推荐开发环境：VSCode + CMake + ARM GCC 工具链 + +--- + +## 默认配置 + +- MCU 主频：内部 RC 振荡器，系统时钟配置为 72MHz + +--- + +## 工具链准备 + +### 1. xPack GNU Arm Embedded GCC Toolchain + +- **版本**：xpack-arm-none-eabi-gcc-11.3.1-1.1 +- **建议解压路径**：Tools/xpack-arm-none-eabi-gcc-11.3.1-1.1 +- **官方下载地址**：https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases +- **路径自定义说明**： + 如需自定义工具链路径，请同步修改以下文件： + - `Projects///cmake/arm-none-eabi-gcc.cmake`（第2行） + - `Projects///.vscode/launch.json`（第12行） + +### 2. OpenOCD + +- **版本**：xpack-openocd-0.11.0-3 +- **建议解压路径**：Tools/xpack-openocd-0.11.0-3 +- **获取地址**：https://github.com/burakenez/gd32-tools-xpack-openocd/tree/v0.11.0-3 +- **说明**： + - 本版本提取自 Embedded Builder V1.4.1.23782。 + - ⚠️ 请勿随意更换版本，因 GD32 MCU 支持有限，推荐严格使用此版本。 +- **路径自定义说明**： + 如需自定义 OpenOCD 路径，请同步修改以下文件： + - `Projects///.vscode/launch.json`（第14、17行） + - `Projects///.vscode/task.json` 中所有相关路径 + +--- + +## 使用说明 + +1. **准备工具链** + - 按上述说明下载并解压 ARM GCC 和 OpenOCD 到 Tools 目录。 + - Toolchain 目录内容不会被 git 跟踪，需自行维护。 + +2. **烧录固件** + - 可直接使用 VSCode 任务栏的 Flash MCU 任务，或命令行运行 OpenOCD。 + +--- + +## 时钟配置说明 + +本工程默认系统时钟为内部 IRC8M 振荡器经 PLL 倍频后的 72MHz。 + +如需修改主频或时钟源，请编辑 `Src/system_gd32e23x.c` 文件： + +1. 查找如下宏定义区： + ```c + // #define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) + // #define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) + // #define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) + #define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) + ``` +2. 取消你需要的时钟方案的注释，并注释掉其它方案。 +3. 保存后重新编译工程即可生效。 + +详细时钟初始化流程可参考 `system_gd32e23x.c` 文件中的 `system_clock_config` 及相关函数实现。 + +--- + +## vcpkg 依赖管理（可选） + +本工程可选支持 vcpkg 作为 C/C++ 工具链和构建工具的自动化依赖管理方案。 + +- 自动下载和管理如 CMake、Ninja 等构建工具，简化环境配置。 +- 可扩展用于第三方 C/C++ 库的统一管理。 + +**启用方法**： +1. 在项目根目录创建 `vcpkg-configuration.json` 文件，内容如下： + + ```json + { + "registries": [ + { + "name": "microsoft", + "location": "https://aka.ms/vcpkg-ce-default", + "kind": "artifact" + }, + { + "name": "arm", + "location": "https://aka.ms/vcpkg-artifacts-arm", + "kind": "artifact" + } + ], + "requires": { + "arm:tools/ninja-build/ninja": "^1.12.0", + "arm:tools/kitware/cmake": "^3.28.4" + } + } + ``` + +2. 启动 VSCode 或命令行，vcpkg 会自动检测并安装所需工具。 + +如不需要 vcpkg，可忽略本文件。 + +--- + +## 建议补充内容 + +- **快速上手示例**：如 main.c 的最小点灯/串口输出代码片段。 +- **常见问题与解答**：如构建失败、烧录失败的排查建议。 +- **调试说明**：如何用 VSCode 调试、断点、查看寄存器等。 +- **多板卡适配说明**：如有多种硬件，如何切换 BoardName。 +- **贡献指南**：如何提交 PR、代码风格约定等。 +- **License 说明**：开源协议和版权声明。 + +--- + +如需进一步完善或有其他建议，欢迎随时反馈！ diff --git a/SDK/CMSIS/CMakeLists.txt b/SDK/CMSIS/CMakeLists.txt index 75477bc..7f18eaf 100644 --- a/SDK/CMSIS/CMakeLists.txt +++ b/SDK/CMSIS/CMakeLists.txt @@ -1,13 +1,13 @@ -project(CMSIS LANGUAGES C CXX ASM) - -add_library(CMSIS INTERFACE) - -target_include_directories(CMSIS INTERFACE - ${CMAKE_SOURCE_DIR}/SDK/CMSIS - ${CMAKE_SOURCE_DIR}/SDK/CMSIS/GD/GD32E23x/Include - - # Added directory of "gd32e23x_libopt.h". - ${CMAKE_SOURCE_DIR}/Inc - - # 如有其它需要的头文件目录，可继续添加 +project(CMSIS LANGUAGES C CXX ASM) + +add_library(CMSIS INTERFACE) + +target_include_directories(CMSIS INTERFACE + ${CMAKE_SOURCE_DIR}/SDK/CMSIS + ${CMAKE_SOURCE_DIR}/SDK/CMSIS/GD/GD32E23x/Include + + # Added directory of "gd32e23x_libopt.h". + ${CMAKE_SOURCE_DIR}/Inc + + # 如有其它需要的头文件目录，可继续添加 ) \ No newline at end of file diff --git a/SDK/CMSIS/GD/GD32E23x/Include/gd32e23x.h b/SDK/CMSIS/GD/GD32E23x/Include/gd32e23x.h index 9e73b3f..49e9ae5 100644 --- a/SDK/CMSIS/GD/GD32E23x/Include/gd32e23x.h +++ b/SDK/CMSIS/GD/GD32E23x/Include/gd32e23x.h @@ -1,213 +1,213 @@ -/*! - \file gd32e23x.h - \brief general definitions for GD32E23x - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* Copyright (c) 2012 ARM LIMITED - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef GD32E23X_H -#define GD32E23X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* define GD32E23x */ -#if !defined (GD32E23x) - #define GD32E23x -#endif /* define GD32E23x */ -#if !defined (GD32E23x) - #error "Please select the target GD32E23x device used in your application (in gd32e23x.h file)" -#endif /* undefine GD32E23x tip */ - -/* define value of high speed crystal oscillator (HXTAL) in Hz */ -#if !defined (HXTAL_VALUE) -#define HXTAL_VALUE ((uint32_t)8000000) -#endif /* high speed crystal oscillator value */ - -/* define startup timeout value of high speed crystal oscillator (HXTAL) */ -#if !defined (HXTAL_STARTUP_TIMEOUT) -#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) -#endif /* high speed crystal oscillator startup timeout */ - -/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ -#if !defined (IRC8M_VALUE) -#define IRC8M_VALUE ((uint32_t)8000000) -#endif /* internal 8MHz RC oscillator value */ - -/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ -#if !defined (IRC8M_STARTUP_TIMEOUT) -#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) -#endif /* internal 8MHz RC oscillator startup timeout */ - -/* define value of internal RC oscillator for ADC in Hz */ -#if !defined (IRC28M_VALUE) -#define IRC28M_VALUE ((uint32_t)28000000) -#endif /* IRC28M_VALUE */ - -#if !defined (IRC48M_VALUE) -#define IRC48M_VALUE ((uint32_t)48000000) -#endif /* IRC48M_VALUE */ - -/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ -#if !defined (IRC40K_VALUE) -#define IRC40K_VALUE ((uint32_t)40000) -#endif /* internal 40KHz RC oscillator value */ - -/* define value of low speed crystal oscillator (LXTAL)in Hz */ -#if !defined (LXTAL_VALUE) -#define LXTAL_VALUE ((uint32_t)32768) -#endif /* low speed crystal oscillator value */ - -/* GD32E23x firmware library version number V1.0 */ -#define __GD32E23x_STDPERIPH_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __GD32E23x_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ -#define __GD32E23x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __GD32E23x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __GD32E23x_STDPERIPH_VERSION ((__GD32E23x_STDPERIPH_VERSION_MAIN << 24)\ - |(__GD32E23x_STDPERIPH_VERSION_SUB1 << 16)\ - |(__GD32E23x_STDPERIPH_VERSION_SUB2 << 8)\ - |(__GD32E23x_STDPERIPH_VERSION_RC)) - -/* configuration of the Cortex-M23 processor and core peripherals */ -#define __CM23_REV 0x0100U /*!< Core revision r1p0 */ -#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ -#define __MPU_PRESENT 0U /*!< MPU is present */ -#define __VTOR_PRESENT 1U /*!< VTOR is present */ -#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/* define interrupt number */ -typedef enum IRQn -{ - /* Cortex-M23 processor exceptions numbers */ - NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */ - HardFault_IRQn = -13, /*!< hardfault interrupt */ - - SVCall_IRQn = -5, /*!< sv call interrupt */ - - PendSV_IRQn = -2, /*!< pend sv interrupt */ - SysTick_IRQn = -1, /*!< system tick interrupt */ - /* interruput numbers */ - WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ - LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */ - FMC_IRQn = 3, /*!< FMC interrupt */ - RCU_IRQn = 4, /*!< RCU interrupt */ - EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ - DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ - DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ - DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ - ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */ - TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ - TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ - TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ - TIMER5_IRQn = 17, /*!< TIMER5 interrupt */ - TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ - TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ - TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ - TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ - I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ - I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ - SPI0_IRQn = 25, /*!< SPI0 interrupt */ - SPI1_IRQn = 26, /*!< SPI1 interrupt */ - USART0_IRQn = 27, /*!< USART0 interrupt */ - USART1_IRQn = 28, /*!< USART1 interrupt */ - I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ - I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ -} IRQn_Type; - -/* includes */ -#include "core_cm23.h" -#include "system_gd32e23x.h" -#include - -/* enum definitions */ -typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; -typedef enum {RESET = 0, SET = !RESET} FlagStatus; -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; - -/* bit operations */ -#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) -#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) -#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) -#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) -#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) -#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) - -/* main flash and SRAM memory map */ -#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ -#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ -/* SRAM and peripheral base bit-band region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ -/* peripheral memory map */ -#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ -#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ -#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ -#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ -/* advanced peripheral bus 1 memory map */ -#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ -#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ -#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ -#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ -#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ -#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ -#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ -#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ -/* advanced peripheral bus 2 memory map */ -#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ -#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ -#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ -#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ -/* advanced high performance bus 1 memory map */ -#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ -#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ -#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ -#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ -#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ -/* advanced high performance bus 2 memory map */ -#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ -/* option byte and debug memory map */ -#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ -#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */ - -#include "gd32e23x_libopt.h" - -#ifdef __cplusplus -} -#endif - -#endif /* GD32E23X_H */ +/*! + \file gd32e23x.h + \brief general definitions for GD32E23x + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef GD32E23X_H +#define GD32E23X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* define GD32E23x */ +#if !defined (GD32E23x) + #define GD32E23x +#endif /* define GD32E23x */ +#if !defined (GD32E23x) + #error "Please select the target GD32E23x device used in your application (in gd32e23x.h file)" +#endif /* undefine GD32E23x tip */ + +/* define value of high speed crystal oscillator (HXTAL) in Hz */ +#if !defined (HXTAL_VALUE) +#define HXTAL_VALUE ((uint32_t)8000000) +#endif /* high speed crystal oscillator value */ + +/* define startup timeout value of high speed crystal oscillator (HXTAL) */ +#if !defined (HXTAL_STARTUP_TIMEOUT) +#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) +#endif /* high speed crystal oscillator startup timeout */ + +/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ +#if !defined (IRC8M_VALUE) +#define IRC8M_VALUE ((uint32_t)8000000) +#endif /* internal 8MHz RC oscillator value */ + +/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ +#if !defined (IRC8M_STARTUP_TIMEOUT) +#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) +#endif /* internal 8MHz RC oscillator startup timeout */ + +/* define value of internal RC oscillator for ADC in Hz */ +#if !defined (IRC28M_VALUE) +#define IRC28M_VALUE ((uint32_t)28000000) +#endif /* IRC28M_VALUE */ + +#if !defined (IRC48M_VALUE) +#define IRC48M_VALUE ((uint32_t)48000000) +#endif /* IRC48M_VALUE */ + +/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ +#if !defined (IRC40K_VALUE) +#define IRC40K_VALUE ((uint32_t)40000) +#endif /* internal 40KHz RC oscillator value */ + +/* define value of low speed crystal oscillator (LXTAL)in Hz */ +#if !defined (LXTAL_VALUE) +#define LXTAL_VALUE ((uint32_t)32768) +#endif /* low speed crystal oscillator value */ + +/* GD32E23x firmware library version number V1.0 */ +#define __GD32E23x_STDPERIPH_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __GD32E23x_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ +#define __GD32E23x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __GD32E23x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __GD32E23x_STDPERIPH_VERSION ((__GD32E23x_STDPERIPH_VERSION_MAIN << 24)\ + |(__GD32E23x_STDPERIPH_VERSION_SUB1 << 16)\ + |(__GD32E23x_STDPERIPH_VERSION_SUB2 << 8)\ + |(__GD32E23x_STDPERIPH_VERSION_RC)) + +/* configuration of the Cortex-M23 processor and core peripherals */ +#define __CM23_REV 0x0100U /*!< Core revision r1p0 */ +#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ +#define __MPU_PRESENT 0U /*!< MPU is present */ +#define __VTOR_PRESENT 1U /*!< VTOR is present */ +#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ + +/* define interrupt number */ +typedef enum IRQn +{ + /* Cortex-M23 processor exceptions numbers */ + NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */ + HardFault_IRQn = -13, /*!< hardfault interrupt */ + + SVCall_IRQn = -5, /*!< sv call interrupt */ + + PendSV_IRQn = -2, /*!< pend sv interrupt */ + SysTick_IRQn = -1, /*!< system tick interrupt */ + /* interruput numbers */ + WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */ + LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */ + FMC_IRQn = 3, /*!< FMC interrupt */ + RCU_IRQn = 4, /*!< RCU interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */ + DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */ + DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */ + DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */ + ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */ + TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */ + TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */ + TIMER2_IRQn = 16, /*!< TIMER2 interrupt */ + TIMER5_IRQn = 17, /*!< TIMER5 interrupt */ + TIMER13_IRQn = 19, /*!< TIMER13 interrupt */ + TIMER14_IRQn = 20, /*!< TIMER14 interrupt */ + TIMER15_IRQn = 21, /*!< TIMER15 interrupt */ + TIMER16_IRQn = 22, /*!< TIMER16 interrupt */ + I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */ + I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */ + SPI0_IRQn = 25, /*!< SPI0 interrupt */ + SPI1_IRQn = 26, /*!< SPI1 interrupt */ + USART0_IRQn = 27, /*!< USART0 interrupt */ + USART1_IRQn = 28, /*!< USART1 interrupt */ + I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ + I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ +} IRQn_Type; + +/* includes */ +#include "core_cm23.h" +#include "system_gd32e23x.h" +#include + +/* enum definitions */ +typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; +typedef enum {RESET = 0, SET = !RESET} FlagStatus; +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; + +/* bit operations */ +#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) +#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) +#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) +#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) +#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) +#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) + +/* main flash and SRAM memory map */ +#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ +#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ +/* SRAM and peripheral base bit-band region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */ +#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */ +/* peripheral memory map */ +#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ +#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ +#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */ +#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */ +/* advanced peripheral bus 1 memory map */ +#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ +#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ +#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ +#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ +#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ +#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ +#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ +#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ +/* advanced peripheral bus 2 memory map */ +#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */ +#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */ +#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ +#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ +/* advanced high performance bus 1 memory map */ +#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */ +#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */ +#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */ +#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */ +#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */ +/* advanced high performance bus 2 memory map */ +#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */ +/* option byte and debug memory map */ +#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ +#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */ + +#include "gd32e23x_libopt.h" + +#ifdef __cplusplus +} +#endif + +#endif /* GD32E23X_H */ diff --git a/SDK/CMSIS/GD/GD32E23x/Include/system_gd32e23x.h b/SDK/CMSIS/GD/GD32E23x/Include/system_gd32e23x.h index 21d8782..c4153ca 100644 --- a/SDK/CMSIS/GD/GD32E23x/Include/system_gd32e23x.h +++ b/SDK/CMSIS/GD/GD32E23x/Include/system_gd32e23x.h @@ -1,66 +1,66 @@ -/*! - \file system_gd32e23x.h - \brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for - GD32E23x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#ifndef SYSTEM_GD32E23X_H -#define SYSTEM_GD32E23X_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/* firmware version can be acquired by uncommenting the macro */ -#define __FIRMWARE_VERSION_DEFINE - -/* system clock frequency (core clock) */ -extern uint32_t SystemCoreClock; - -/* function declarations */ -/* initialize the system and update the SystemCoreClock variable */ -extern void SystemInit (void); -/* update the SystemCoreClock with current core clock retrieved from cpu registers */ -extern void SystemCoreClockUpdate (void); - -#ifdef __FIRMWARE_VERSION_DEFINE -/* get firmware version */ -extern uint32_t gd32e23x_firmware_version_get(void); -#endif /* __FIRMWARE_VERSION_DEFINE */ -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_GD32E23X_H */ +/*! + \file system_gd32e23x.h + \brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for + GD32E23x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#ifndef SYSTEM_GD32E23X_H +#define SYSTEM_GD32E23X_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/* firmware version can be acquired by uncommenting the macro */ +#define __FIRMWARE_VERSION_DEFINE + +/* system clock frequency (core clock) */ +extern uint32_t SystemCoreClock; + +/* function declarations */ +/* initialize the system and update the SystemCoreClock variable */ +extern void SystemInit (void); +/* update the SystemCoreClock with current core clock retrieved from cpu registers */ +extern void SystemCoreClockUpdate (void); + +#ifdef __FIRMWARE_VERSION_DEFINE +/* get firmware version */ +extern uint32_t gd32e23x_firmware_version_get(void); +#endif /* __FIRMWARE_VERSION_DEFINE */ +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_GD32E23X_H */ diff --git a/SDK/CMSIS/GD/GD32E23x/Source/ARM/startup_gd32e23x.s b/SDK/CMSIS/GD/GD32E23x/Source/ARM/startup_gd32e23x.s index d97361e..4b37ab0 100644 --- a/SDK/CMSIS/GD/GD32E23x/Source/ARM/startup_gd32e23x.s +++ b/SDK/CMSIS/GD/GD32E23x/Source/ARM/startup_gd32e23x.s @@ -1,270 +1,270 @@ -;/*! -; \file startup_gd32e23x.s -; \brief start up file -; -; \version 2025-02-10, V2.3.0, firmware for GD32E23x -;*/ - -;/* Copyright (c) 2012 ARM LIMITED -; Copyright (c) 2025, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;*/ -;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; /* reset Vector Mapped to at Address 0 */ - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; /* external interrupts handler */ - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD RTC_IRQHandler ; 18:RTC through EXTI Line - DCD FMC_IRQHandler ; 19:FMC - DCD RCU_IRQHandler ; 20:RCU - DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 - DCD 0 ; Reserved - DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare - DCD 0 ; Reserved - DCD TIMER2_IRQHandler ; 32:TIMER2 - DCD TIMER5_IRQHandler ; 33:TIMER5 - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; 35:TIMER13 - DCD TIMER14_IRQHandler ; 36:TIMER14 - DCD TIMER15_IRQHandler ; 37:TIMER15 - DCD TIMER16_IRQHandler ; 38:TIMER16 - DCD I2C0_EV_IRQHandler ; 39:I2C0 Event - DCD I2C1_EV_IRQHandler ; 40:I2C1 Event - DCD SPI0_IRQHandler ; 41:SPI0 - DCD SPI1_IRQHandler ; 42:SPI1 - DCD USART0_IRQHandler ; 43:USART0 - DCD USART1_IRQHandler ; 44:USART1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -;/* reset Handler */ -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =0x1FFFF7E0 - LDR R2, [R0] - LDR R0, = 0xFFFF0000 - ANDS R2, R2, R0 - LSRS R2, R2, #16 - LSLS R2, R2, #10 - LDR R1, =0x20000000 - MOV R0, #0x00 -SRAM_INIT STM R1!, {R0} - SUBS R2, R2, #4 - CMP R2, #0x00 - BNE SRAM_INIT - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -;/* dummy Exception Handlers */ -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC -; /* external interrupts handler */ - EXPORT WWDGT_IRQHandler [WEAK] - EXPORT LVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT RCU_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA_Channel0_IRQHandler [WEAK] - EXPORT DMA_Channel1_2_IRQHandler [WEAK] - EXPORT DMA_Channel3_4_IRQHandler [WEAK] - EXPORT ADC_CMP_IRQHandler [WEAK] - EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIMER0_Channel_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER5_IRQHandler [WEAK] - EXPORT TIMER13_IRQHandler [WEAK] - EXPORT TIMER14_IRQHandler [WEAK] - EXPORT TIMER15_IRQHandler [WEAK] - EXPORT TIMER16_IRQHandler [WEAK] - EXPORT I2C0_EV_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART0_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT I2C0_ER_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - -;/* external interrupts handler */ -WWDGT_IRQHandler -LVD_IRQHandler -RTC_IRQHandler -FMC_IRQHandler -RCU_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA_Channel0_IRQHandler -DMA_Channel1_2_IRQHandler -DMA_Channel3_4_IRQHandler -ADC_CMP_IRQHandler -TIMER0_BRK_UP_TRG_COM_IRQHandler -TIMER0_Channel_IRQHandler -TIMER2_IRQHandler -TIMER5_IRQHandler -TIMER13_IRQHandler -TIMER14_IRQHandler -TIMER15_IRQHandler -TIMER16_IRQHandler -I2C0_EV_IRQHandler -I2C1_EV_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -USART0_IRQHandler -USART1_IRQHandler -I2C0_ER_IRQHandler -I2C1_ER_IRQHandler - - B . - ENDP - - ALIGN - -; user Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END +;/*! +; \file startup_gd32e23x.s +; \brief start up file +; +; \version 2025-02-10, V2.3.0, firmware for GD32E23x +;*/ + +;/* Copyright (c) 2012 ARM LIMITED +; Copyright (c) 2025, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;*/ +;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; /* reset Vector Mapped to at Address 0 */ + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; /* external interrupts handler */ + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD RTC_IRQHandler ; 18:RTC through EXTI Line + DCD FMC_IRQHandler ; 19:FMC + DCD RCU_IRQHandler ; 20:RCU + DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 + DCD 0 ; Reserved + DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare + DCD 0 ; Reserved + DCD TIMER2_IRQHandler ; 32:TIMER2 + DCD TIMER5_IRQHandler ; 33:TIMER5 + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; 35:TIMER13 + DCD TIMER14_IRQHandler ; 36:TIMER14 + DCD TIMER15_IRQHandler ; 37:TIMER15 + DCD TIMER16_IRQHandler ; 38:TIMER16 + DCD I2C0_EV_IRQHandler ; 39:I2C0 Event + DCD I2C1_EV_IRQHandler ; 40:I2C1 Event + DCD SPI0_IRQHandler ; 41:SPI0 + DCD SPI1_IRQHandler ; 42:SPI1 + DCD USART0_IRQHandler ; 43:USART0 + DCD USART1_IRQHandler ; 44:USART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +;/* reset Handler */ +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =0x1FFFF7E0 + LDR R2, [R0] + LDR R0, = 0xFFFF0000 + ANDS R2, R2, R0 + LSRS R2, R2, #16 + LSLS R2, R2, #10 + LDR R1, =0x20000000 + MOV R0, #0x00 +SRAM_INIT STM R1!, {R0} + SUBS R2, R2, #4 + CMP R2, #0x00 + BNE SRAM_INIT + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +;/* dummy Exception Handlers */ +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC +; /* external interrupts handler */ + EXPORT WWDGT_IRQHandler [WEAK] + EXPORT LVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT RCU_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA_Channel0_IRQHandler [WEAK] + EXPORT DMA_Channel1_2_IRQHandler [WEAK] + EXPORT DMA_Channel3_4_IRQHandler [WEAK] + EXPORT ADC_CMP_IRQHandler [WEAK] + EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIMER0_Channel_IRQHandler [WEAK] + EXPORT TIMER2_IRQHandler [WEAK] + EXPORT TIMER5_IRQHandler [WEAK] + EXPORT TIMER13_IRQHandler [WEAK] + EXPORT TIMER14_IRQHandler [WEAK] + EXPORT TIMER15_IRQHandler [WEAK] + EXPORT TIMER16_IRQHandler [WEAK] + EXPORT I2C0_EV_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART0_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT I2C0_ER_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + +;/* external interrupts handler */ +WWDGT_IRQHandler +LVD_IRQHandler +RTC_IRQHandler +FMC_IRQHandler +RCU_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA_Channel0_IRQHandler +DMA_Channel1_2_IRQHandler +DMA_Channel3_4_IRQHandler +ADC_CMP_IRQHandler +TIMER0_BRK_UP_TRG_COM_IRQHandler +TIMER0_Channel_IRQHandler +TIMER2_IRQHandler +TIMER5_IRQHandler +TIMER13_IRQHandler +TIMER14_IRQHandler +TIMER15_IRQHandler +TIMER16_IRQHandler +I2C0_EV_IRQHandler +I2C1_EV_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +USART0_IRQHandler +USART1_IRQHandler +I2C0_ER_IRQHandler +I2C1_ER_IRQHandler + + B . + ENDP + + ALIGN + +; user Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + END diff --git a/SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s b/SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s index f730531..44feef5 100644 --- a/SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s +++ b/SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s @@ -1,296 +1,296 @@ -;/*! -; \file startup_gd32e23x.s -; \brief start up file -; -; \version 2025-02-10, V2.3.0, firmware for GD32E23x -;*/ - -;/* Copyright (c) 2012 ARM LIMITED -; Copyright (c) 2025, GigaDevice Semiconductor Inc. -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;*/ -;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) ; top of stack - DCD Reset_Handler ; Vector Number 1,Reset Handler - - DCD NMI_Handler ; Vector Number 2,NMI Handler - DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; Vector Number 11,SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; Vector Number 14,PendSV Handler - DCD SysTick_Handler ; Vector Number 15,SysTick Handler - - ; External Interrupts - DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer - DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect - DCD RTC_IRQHandler ; 18:RTC through EXTI Line - DCD FMC_IRQHandler ; 19:FMC - DCD RCU_IRQHandler ; 20:RCU - DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 - DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 - DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 - DCD 0 ; Reserved - DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 - DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 - DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 - DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator - DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation - DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare - DCD 0 ; Reserved - DCD TIMER2_IRQHandler ; 32:TIMER2 - DCD TIMER5_IRQHandler ; 33:TIMER5 - DCD 0 ; Reserved - DCD TIMER13_IRQHandler ; 35:TIMER13 - DCD TIMER14_IRQHandler ; 36:TIMER14 - DCD TIMER15_IRQHandler ; 37:TIMER15 - DCD TIMER16_IRQHandler ; 38:TIMER16 - DCD I2C0_EV_IRQHandler ; 39:I2C0 Event - DCD I2C1_EV_IRQHandler ; 40:I2C1 Event - DCD SPI0_IRQHandler ; 41:SPI0 - DCD SPI1_IRQHandler ; 42:SPI1 - DCD USART0_IRQHandler ; 43:USART0 - DCD USART1_IRQHandler ; 44:USART1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C0_ER_IRQHandler ; 48:I2C0 Error - DCD 0 ; Reserved - DCD I2C1_ER_IRQHandler ; 50:I2C1 Error - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =0x1FFFF7E0 - LDR R2, [R0] - LDR R0, = 0xFFFF0000 - ANDS R2, R2, R0 - LSRS R2, R2, #16 - LSLS R2, R2, #10 - LDR R1, =0x20000000 - MOV R0, #0x00 -SRAM_INIT STM R1!, {R0} - SUBS R2, R2, #4 - CMP R2, #0x00 - BNE SRAM_INIT - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDGT_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDGT_IRQHandler - B WWDGT_IRQHandler - - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK RCU_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCU_IRQHandler - B RCU_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA_Channel0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel0_IRQHandler - B DMA_Channel0_IRQHandler - - PUBWEAK DMA_Channel1_2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel1_2_IRQHandler - B DMA_Channel1_2_IRQHandler - - PUBWEAK DMA_Channel3_4_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA_Channel3_4_IRQHandler - B DMA_Channel3_4_IRQHandler - - PUBWEAK ADC_CMP_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC_CMP_IRQHandler - B ADC_CMP_IRQHandler - - PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_BRK_UP_TRG_COM_IRQHandler - B TIMER0_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIMER0_Channel_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER0_Channel_IRQHandler - B TIMER0_Channel_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER5_IRQHandler - B TIMER5_IRQHandler - - PUBWEAK TIMER13_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER13_IRQHandler - B TIMER13_IRQHandler - - PUBWEAK TIMER14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER14_IRQHandler - B TIMER14_IRQHandler - - PUBWEAK TIMER15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER15_IRQHandler - B TIMER15_IRQHandler - - PUBWEAK TIMER16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIMER16_IRQHandler - B TIMER16_IRQHandler - - PUBWEAK I2C0_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_EV_IRQHandler - B I2C0_EV_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK SPI0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI0_IRQHandler - B SPI0_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART0_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART0_IRQHandler - B USART0_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK I2C0_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C0_ER_IRQHandler - B I2C0_ER_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler +;/*! +; \file startup_gd32e23x.s +; \brief start up file +; +; \version 2025-02-10, V2.3.0, firmware for GD32E23x +;*/ + +;/* Copyright (c) 2012 ARM LIMITED +; Copyright (c) 2025, GigaDevice Semiconductor Inc. +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;*/ +;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) ; top of stack + DCD Reset_Handler ; Vector Number 1,Reset Handler + + DCD NMI_Handler ; Vector Number 2,NMI Handler + DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; Vector Number 11,SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; Vector Number 14,PendSV Handler + DCD SysTick_Handler ; Vector Number 15,SysTick Handler + + ; External Interrupts + DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer + DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect + DCD RTC_IRQHandler ; 18:RTC through EXTI Line + DCD FMC_IRQHandler ; 19:FMC + DCD RCU_IRQHandler ; 20:RCU + DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1 + DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3 + DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15 + DCD 0 ; Reserved + DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0 + DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2 + DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4 + DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator + DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation + DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare + DCD 0 ; Reserved + DCD TIMER2_IRQHandler ; 32:TIMER2 + DCD TIMER5_IRQHandler ; 33:TIMER5 + DCD 0 ; Reserved + DCD TIMER13_IRQHandler ; 35:TIMER13 + DCD TIMER14_IRQHandler ; 36:TIMER14 + DCD TIMER15_IRQHandler ; 37:TIMER15 + DCD TIMER16_IRQHandler ; 38:TIMER16 + DCD I2C0_EV_IRQHandler ; 39:I2C0 Event + DCD I2C1_EV_IRQHandler ; 40:I2C1 Event + DCD SPI0_IRQHandler ; 41:SPI0 + DCD SPI1_IRQHandler ; 42:SPI1 + DCD USART0_IRQHandler ; 43:USART0 + DCD USART1_IRQHandler ; 44:USART1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C0_ER_IRQHandler ; 48:I2C0 Error + DCD 0 ; Reserved + DCD I2C1_ER_IRQHandler ; 50:I2C1 Error + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =0x1FFFF7E0 + LDR R2, [R0] + LDR R0, = 0xFFFF0000 + ANDS R2, R2, R0 + LSRS R2, R2, #16 + LSLS R2, R2, #10 + LDR R1, =0x20000000 + MOV R0, #0x00 +SRAM_INIT STM R1!, {R0} + SUBS R2, R2, #4 + CMP R2, #0x00 + BNE SRAM_INIT + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDGT_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDGT_IRQHandler + B WWDGT_IRQHandler + + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK RCU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCU_IRQHandler + B RCU_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA_Channel0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel0_IRQHandler + B DMA_Channel0_IRQHandler + + PUBWEAK DMA_Channel1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel1_2_IRQHandler + B DMA_Channel1_2_IRQHandler + + PUBWEAK DMA_Channel3_4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA_Channel3_4_IRQHandler + B DMA_Channel3_4_IRQHandler + + PUBWEAK ADC_CMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_CMP_IRQHandler + B ADC_CMP_IRQHandler + + PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_BRK_UP_TRG_COM_IRQHandler + B TIMER0_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIMER0_Channel_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER0_Channel_IRQHandler + B TIMER0_Channel_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER5_IRQHandler + B TIMER5_IRQHandler + + PUBWEAK TIMER13_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER13_IRQHandler + B TIMER13_IRQHandler + + PUBWEAK TIMER14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER14_IRQHandler + B TIMER14_IRQHandler + + PUBWEAK TIMER15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER15_IRQHandler + B TIMER15_IRQHandler + + PUBWEAK TIMER16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIMER16_IRQHandler + B TIMER16_IRQHandler + + PUBWEAK I2C0_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_EV_IRQHandler + B I2C0_EV_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK SPI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI0_IRQHandler + B SPI0_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART0_IRQHandler + B USART0_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK I2C0_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C0_ER_IRQHandler + B I2C0_ER_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler END \ No newline at end of file diff --git a/SDK/CMSIS/GD/GD32E23x/Source/system_gd32e23x.c b/SDK/CMSIS/GD/GD32E23x/Source/system_gd32e23x.c index ce5be24..5da19fa 100644 --- a/SDK/CMSIS/GD/GD32E23x/Source/system_gd32e23x.c +++ b/SDK/CMSIS/GD/GD32E23x/Source/system_gd32e23x.c @@ -1,451 +1,451 @@ -/*! - \file system_gd32e23x.c - \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for - GD32E23x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32e23x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ - -/* select a system clock by uncommenting the following line */ -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) - -/* The following is to prevent Vcore fluctuations caused by frequency switching. - It is strongly recommended to include it to avoid issues caused by self-removal. -*/ -#define RCU_MODIFY(__delay) do{ \ - volatile uint32_t i,reg; \ - if(0 != __delay){ \ - reg = RCU_CFG0; \ - reg &= ~(RCU_CFG0_AHBPSC); \ - /* CK_AHB = SYSCLK/2 */ \ - reg |= RCU_AHB_CKSYS_DIV2; \ - RCU_CFG0 = reg; \ - for(i=0; i<__delay; i++){ \ - } \ - reg = RCU_CFG0; \ - reg &= ~(RCU_CFG0_AHBPSC); \ - reg |= RCU_AHB_CKSYS_DIV4; \ - /* CK_AHB = SYSCLK/4 */ \ - RCU_CFG0 = reg; \ - for(i=0; i<__delay; i++){ \ - } \ - } \ - }while(0) - -#define SEL_IRC8M 0x00 -#define SEL_HXTAL 0x01 -#define SEL_PLL 0x02 - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_8M_HXTAL -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; -static void system_clock_8m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; -static void system_clock_72m_irc8m(void); - -#else -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; -static void system_clock_8m_irc8m(void); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/* configure the system clock */ -static void system_clock_config(void); - -/* software delay to prevent the impact of Vcore fluctuations. - It is strongly recommended to include it to avoid issues caused by self-removal. */ -static void _soft_delay_(uint32_t time) -{ - __IO uint32_t i; - for(i=0; i> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock >>= clk_exp; -} - -#ifdef __FIRMWARE_VERSION_DEFINE -/*! - \brief get firmware version - \param[in] none - \param[out] none - \retval firmware version -*/ -uint32_t gd32e23x_firmware_version_get(void) -{ - return __GD32E23x_STDPERIPH_VERSION; -} -#endif /* __FIRMWARE_VERSION_DEFINE */ +/*! + \file system_gd32e23x.c + \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for + GD32E23x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32e23x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ + +/* select a system clock by uncommenting the following line */ +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) + +/* The following is to prevent Vcore fluctuations caused by frequency switching. + It is strongly recommended to include it to avoid issues caused by self-removal. +*/ +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i,reg; \ + if(0 != __delay){ \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + /* CK_AHB = SYSCLK/2 */ \ + reg |= RCU_AHB_CKSYS_DIV2; \ + RCU_CFG0 = reg; \ + for(i=0; i<__delay; i++){ \ + } \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV4; \ + /* CK_AHB = SYSCLK/4 */ \ + RCU_CFG0 = reg; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + +#define SEL_IRC8M 0x00 +#define SEL_HXTAL 0x01 +#define SEL_PLL 0x02 + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_8M_HXTAL +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; +static void system_clock_8m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; +static void system_clock_72m_irc8m(void); + +#else +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; +static void system_clock_8m_irc8m(void); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/* configure the system clock */ +static void system_clock_config(void); + +/* software delay to prevent the impact of Vcore fluctuations. + It is strongly recommended to include it to avoid issues caused by self-removal. */ +static void _soft_delay_(uint32_t time) +{ + __IO uint32_t i; + for(i=0; i> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} + +#ifdef __FIRMWARE_VERSION_DEFINE +/*! + \brief get firmware version + \param[in] none + \param[out] none + \retval firmware version +*/ +uint32_t gd32e23x_firmware_version_get(void) +{ + return __GD32E23x_STDPERIPH_VERSION; +} +#endif /* __FIRMWARE_VERSION_DEFINE */ diff --git a/SDK/CMSIS/cmsis_armclang.h b/SDK/CMSIS/cmsis_armclang.h index 446d21a..334837c 100644 --- a/SDK/CMSIS/cmsis_armclang.h +++ b/SDK/CMSIS/cmsis_armclang.h @@ -1,707 +1,707 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".bss.noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} -#endif - - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - -/** @} end of CMSIS_Core_RegAccFunctions */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' - #include "./a-profile/cmsis_armclang_a.h" -#elif __ARM_ARCH_PROFILE == 'R' - #include "./r-profile/cmsis_armclang_r.h" -#elif __ARM_ARCH_PROFILE == 'M' - #include "./m-profile/cmsis_armclang_m.h" -#else - #error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_ARMCLANG_H */ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".bss.noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_armclang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_armclang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_armclang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/SDK/CMSIS/cmsis_clang.h b/SDK/CMSIS/cmsis_clang.h index 872e16c..46ffb3e 100644 --- a/SDK/CMSIS/cmsis_clang.h +++ b/SDK/CMSIS/cmsis_clang.h @@ -1,708 +1,708 @@ -/**************************************************************************//** - * @file cmsis_clang.h - * @brief CMSIS compiler LLVM/Clang header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_CLANG_H -#define __CMSIS_CLANG_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} -#endif - - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - -/** @} end of CMSIS_Core_RegAccFunctions */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' - #include "./a-profile/cmsis_clang_a.h" -#elif __ARM_ARCH_PROFILE == 'R' - #include "./r-profile/cmsis_clang_r.h" -#elif __ARM_ARCH_PROFILE == 'M' - #include "./m-profile/cmsis_clang_m.h" -#else - #error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_CLANG_H */ +/**************************************************************************//** + * @file cmsis_clang.h + * @brief CMSIS compiler LLVM/Clang header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_CLANG_H +#define __CMSIS_CLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/* __ARM_FEATURE_SAT is wrong for Armv8-M Baseline devices */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} +#endif + + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + +/** @} end of CMSIS_Core_RegAccFunctions */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "./a-profile/cmsis_clang_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "./r-profile/cmsis_clang_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "./m-profile/cmsis_clang_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_CLANG_H */ diff --git a/SDK/CMSIS/cmsis_compiler.h b/SDK/CMSIS/cmsis_compiler.h index cf3f5b0..6c27f2a 100644 --- a/SDK/CMSIS/cmsis_compiler.h +++ b/SDK/CMSIS/cmsis_compiler.h @@ -1,292 +1,292 @@ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Compiler Generic Header File - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler above 6.10.1 (armclang) - */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - -/* - * TI Arm Clang Compiler (tiarmclang) - */ -#elif defined (__ti__) - #include "cmsis_tiarmclang.h" - - -/* - * LLVM/Clang Compiler - */ -#elif defined ( __clang__ ) - #include "cmsis_clang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #if __ARM_ARCH_PROFILE == 'A' - #include "a-profile/cmsis_iccarm_a.h" - #elif __ARM_ARCH_PROFILE == 'R' - #include "r-profile/cmsis_iccarm_r.h" - #elif __ARM_ARCH_PROFILE == 'M' - #include "m-profile/cmsis_iccarm_m.h" - #else - #error "Unknown Arm architecture profile" - #endif - - -/* - * TI Arm Compiler (armcl) - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - #ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) - #endif - #ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) - #endif - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Compiler Generic Header File + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler above 6.10.1 (armclang) + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + +/* + * TI Arm Clang Compiler (tiarmclang) + */ +#elif defined (__ti__) + #include "cmsis_tiarmclang.h" + + +/* + * LLVM/Clang Compiler + */ +#elif defined ( __clang__ ) + #include "cmsis_clang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_iccarm_a.h" + #elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_iccarm_r.h" + #elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_iccarm_m.h" + #else + #error "Unknown Arm architecture profile" + #endif + + +/* + * TI Arm Compiler (armcl) + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + #ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) + #endif + #ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) + #endif + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/SDK/CMSIS/cmsis_gcc.h b/SDK/CMSIS/cmsis_gcc.h index 4771466..f236417 100644 --- a/SDK/CMSIS/cmsis_gcc.h +++ b/SDK/CMSIS/cmsis_gcc.h @@ -1,1006 +1,1006 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V6.0.0 - * @date 27. July 2024 - ******************************************************************************/ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -#pragma GCC system_header /* treat file as system include file */ - -#include - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef CMSIS_DEPRECATED - #define CMSIS_DEPRECATED __attribute__((deprecated)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ - return __builtin_bswap32(value); -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return (result); -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ - return (int16_t)__builtin_bswap16(value); -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__ARM_ARCH_ISA_THUMB >= 2) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return (result); -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if (__ARM_FEATURE_SAT >= 1) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return (result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return (result); -} -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return (result); -} - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - -#if (__ARM_ARCH_ISA_THUMB >= 2) - /** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ - __STATIC_FORCEINLINE void __enable_fault_irq(void) - { - __ASM volatile ("cpsie f" : : : "memory"); - } - - - /** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ - __STATIC_FORCEINLINE void __disable_fault_irq(void) - { - __ASM volatile ("cpsid f" : : : "memory"); - } -#endif - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - - -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - #define __SADD8 __sadd8 - #define __QADD8 __qadd8 - #define __SHADD8 __shadd8 - #define __UADD8 __uadd8 - #define __UQADD8 __uqadd8 - #define __UHADD8 __uhadd8 - #define __SSUB8 __ssub8 - #define __QSUB8 __qsub8 - #define __SHSUB8 __shsub8 - #define __USUB8 __usub8 - #define __UQSUB8 __uqsub8 - #define __UHSUB8 __uhsub8 - #define __SADD16 __sadd16 - #define __QADD16 __qadd16 - #define __SHADD16 __shadd16 - #define __UADD16 __uadd16 - #define __UQADD16 __uqadd16 - #define __UHADD16 __uhadd16 - #define __SSUB16 __ssub16 - #define __QSUB16 __qsub16 - #define __SHSUB16 __shsub16 - #define __USUB16 __usub16 - #define __UQSUB16 __uqsub16 - #define __UHSUB16 __uhsub16 - #define __SASX __sasx - #define __QASX __qasx - #define __SHASX __shasx - #define __UASX __uasx - #define __UQASX __uqasx - #define __UHASX __uhasx - #define __SSAX __ssax - #define __QSAX __qsax - #define __SHSAX __shsax - #define __USAX __usax - #define __UQSAX __uqsax - #define __UHSAX __uhsax - #define __USAD8 __usad8 - #define __USADA8 __usada8 - #define __SSAT16 __ssat16 - #define __USAT16 __usat16 - #define __UXTB16 __uxtb16 - #define __UXTAB16 __uxtab16 - #define __SXTB16 __sxtb16 - #define __SXTAB16 __sxtab16 - #define __SMUAD __smuad - #define __SMUADX __smuadx - #define __SMLAD __smlad - #define __SMLADX __smladx - #define __SMLALD __smlald - #define __SMLALDX __smlaldx - #define __SMUSD __smusd - #define __SMUSDX __smusdx - #define __SMLSD __smlsd - #define __SMLSDX __smlsdx - #define __SMLSLD __smlsld - #define __SMLSLDX __smlsldx - #define __SEL __sel - #define __QADD __qadd - #define __QSUB __qsub - - #define __PKHBT(ARG1,ARG2,ARG3) \ - __extension__ \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - #define __PKHTB(ARG1,ARG2,ARG3) \ - __extension__ \ - ({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) - { - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) - { - __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); - } - else - { - result = __SXTB16(__ROR(op1, rotate)); - } - return result; - } - - __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) - { - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) - { - __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); - } - else - { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; - } - - __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) - { - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); - } -#endif /* (__ARM_FEATURE_DSP == 1) */ -/** @} end of group CMSIS_SIMD_intrinsics */ - -// Include the profile specific settings: -#if __ARM_ARCH_PROFILE == 'A' - #include "a-profile/cmsis_gcc_a.h" -#elif __ARM_ARCH_PROFILE == 'R' - #include "r-profile/cmsis_gcc_r.h" -#elif __ARM_ARCH_PROFILE == 'M' - #include "m-profile/cmsis_gcc_m.h" -#else - #error "Unknown Arm architecture profile" -#endif - -#endif /* __CMSIS_GCC_H */ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V6.0.0 + * @date 27. July 2024 + ******************************************************************************/ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +#pragma GCC system_header /* treat file as system include file */ + +#include + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ + return __builtin_bswap32(value); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return (result); +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ + return (int16_t)__builtin_bswap16(value); +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__ARM_ARCH_ISA_THUMB >= 2) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return (result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if (__ARM_FEATURE_SAT >= 1) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return (result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return (result); +} +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return (result); +} + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + +#if (__ARM_ARCH_ISA_THUMB >= 2) + /** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __enable_fault_irq(void) + { + __ASM volatile ("cpsie f" : : : "memory"); + } + + + /** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ + __STATIC_FORCEINLINE void __disable_fault_irq(void) + { + __ASM volatile ("cpsid f" : : : "memory"); + } +#endif + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define __SADD8 __sadd8 + #define __QADD8 __qadd8 + #define __SHADD8 __shadd8 + #define __UADD8 __uadd8 + #define __UQADD8 __uqadd8 + #define __UHADD8 __uhadd8 + #define __SSUB8 __ssub8 + #define __QSUB8 __qsub8 + #define __SHSUB8 __shsub8 + #define __USUB8 __usub8 + #define __UQSUB8 __uqsub8 + #define __UHSUB8 __uhsub8 + #define __SADD16 __sadd16 + #define __QADD16 __qadd16 + #define __SHADD16 __shadd16 + #define __UADD16 __uadd16 + #define __UQADD16 __uqadd16 + #define __UHADD16 __uhadd16 + #define __SSUB16 __ssub16 + #define __QSUB16 __qsub16 + #define __SHSUB16 __shsub16 + #define __USUB16 __usub16 + #define __UQSUB16 __uqsub16 + #define __UHSUB16 __uhsub16 + #define __SASX __sasx + #define __QASX __qasx + #define __SHASX __shasx + #define __UASX __uasx + #define __UQASX __uqasx + #define __UHASX __uhasx + #define __SSAX __ssax + #define __QSAX __qsax + #define __SHSAX __shsax + #define __USAX __usax + #define __UQSAX __uqsax + #define __UHSAX __uhsax + #define __USAD8 __usad8 + #define __USADA8 __usada8 + #define __SSAT16 __ssat16 + #define __USAT16 __usat16 + #define __UXTB16 __uxtb16 + #define __UXTAB16 __uxtab16 + #define __SXTB16 __sxtb16 + #define __SXTAB16 __sxtab16 + #define __SMUAD __smuad + #define __SMUADX __smuadx + #define __SMLAD __smlad + #define __SMLADX __smladx + #define __SMLALD __smlald + #define __SMLALDX __smlaldx + #define __SMUSD __smusd + #define __SMUSDX __smusdx + #define __SMLSD __smlsd + #define __SMLSDX __smlsdx + #define __SMLSLD __smlsld + #define __SMLSLDX __smlsldx + #define __SEL __sel + #define __QADD __qadd + #define __QSUB __qsub + + #define __PKHBT(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + #define __PKHTB(ARG1,ARG2,ARG3) \ + __extension__ \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + __STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate)); + } + else + { + result = __SXTB16(__ROR(op1, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) + { + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) + { + __ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate)); + } + else + { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; + } + + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) + { + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); + } +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + +// Include the profile specific settings: +#if __ARM_ARCH_PROFILE == 'A' + #include "a-profile/cmsis_gcc_a.h" +#elif __ARM_ARCH_PROFILE == 'R' + #include "r-profile/cmsis_gcc_r.h" +#elif __ARM_ARCH_PROFILE == 'M' + #include "m-profile/cmsis_gcc_m.h" +#else + #error "Unknown Arm architecture profile" +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/SDK/CMSIS/cmsis_version.h b/SDK/CMSIS/cmsis_version.h index 849a8a4..8c1e06a 100644 --- a/SDK/CMSIS/cmsis_version.h +++ b/SDK/CMSIS/cmsis_version.h @@ -1,44 +1,44 @@ -/* - * Copyright (c) 2009-2023 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Core Version Definitions - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS-Core(M) Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ - -/* CMSIS-Core(A) Version definitions */ -#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ -#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ -#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ - __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ - -#endif +/* + * Copyright (c) 2009-2023 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Core Version Definitions + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS-Core(M) Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */ + +/* CMSIS-Core(A) Version definitions */ +#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA_CMSIS_VERSION_SUB ( 1U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \ + __CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#endif diff --git a/SDK/CMSIS/core_cm23.h b/SDK/CMSIS/core_cm23.h index d6337a4..d6df1de 100644 --- a/SDK/CMSIS/core_cm23.h +++ b/SDK/CMSIS/core_cm23.h @@ -1,2253 +1,2253 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS Cortex-M23 Core Peripheral Access Layer Header File - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM23 definitions */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ti__) - #if defined (__ARM_FP) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/** \brief APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/** \brief IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/** \brief xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/** \brief CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/** \brief SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/** \brief SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/** \brief SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/** \brief SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ -#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/** \brief SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/** \brief SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/** \brief SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/** \brief SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/** \brief SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/** \brief SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/** \brief SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED14[992U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ -} DWT_Type; - -/** \brief DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/** \brief DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) - \brief Type definitions for the Trace Port Interface Unit (TPIU) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Unit Register (TPIU). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPIU_Type; - -/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ -#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ -#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ - -/** \brief TPIU Selected Pin Protocol Register Definitions */ -#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ -#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ - -/** \brief TPIU Formatter and Flush Status Register Definitions */ -#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ -#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ - -#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ -#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ - -#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ -#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ - -#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ -#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ - -/** \brief TPIU Formatter and Flush Control Register Definitions */ -#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ -#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ - -#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ -#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ - -#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ -#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ - -/** \brief TPIU Periodic Synchronization Control Register Definitions */ -#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ -#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ - -/** \brief TPIU TRIGGER Register Definitions */ -#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ -#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ - -/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ -#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ -#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ -#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ -#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ - -/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ -#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ -#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ - -#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ -#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ - -#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ -#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ - -#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ -#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ - -/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ -#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ -#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ -#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ -#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ - -/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ -#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ -#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ - -#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ -#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ - -#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ -#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ - -#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ -#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ - -/** \brief TPIU Integration Mode Control Register Definitions */ -#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ -#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ - -/** \brief TPIU DEVID Register Definitions */ -#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ -#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ - -#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ -#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ - -#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ -#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ - -#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ -#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ - -#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ -#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ - -/** \brief TPIU DEVTYPE Register Definitions */ -#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ -#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ - -#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ -#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPIU */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/** \brief MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/** \brief MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/** \brief MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/** \brief MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/** \brief MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ - -/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/** \brief SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/** \brief SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/** \brief SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/** \brief SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/** \brief SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/** \brief DCB Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/** \brief DCB Debug Core Register Selector Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/** \brief DCB Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/** \brief DCB Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/** \brief DCB Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/** \brief DCB Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/** \brief DIB SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/** \brief DIB SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/** \brief DIB Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/** \brief DIB SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/** \brief DIB SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases - \brief Alias definitions present for backwards compatibility for deprecated symbols. - @{ - */ - -#ifndef CMSIS_DISABLE_DEPRECATED - -#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos -#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk - -/* deprecated, CMSIS_5 backward compatibility */ -typedef struct -{ - __IOM uint32_t DHCSR; - __OM uint32_t DCRSR; - __IOM uint32_t DCRDR; - __IOM uint32_t DEMCR; - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; - __IOM uint32_t DSCSR; -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos -#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos -#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk - -#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos -#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk - -#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos -#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk - -#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos -#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk - -#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos -#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk - -#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos -#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk - -#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos -#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk - -#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos -#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk - -#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos -#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos -#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos -#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk - -#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos -#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos -#define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk - -#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos -#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk - -#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos -#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos -#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk - -#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos -#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk - -#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos -#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk - -#define CoreDebug ((CoreDebug_Type *) DCB_BASE) -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) -#endif - -#endif // CMSIS_DISABLE_DEPRECATED - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/* NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/* NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - - #include "m-profile/armv8m_mpu.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS Cortex-M23 Core Peripheral Access Layer Header File + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM23 definitions */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ti__) + #if defined (__ARM_FP) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/** \brief CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/** \brief SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/** \brief SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/** \brief SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/** \brief SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */ +#define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/** \brief SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/** \brief SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/** \brief SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/** \brief SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/** \brief SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/** \brief SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/** \brief SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED14[992U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Architecture Register */ +} DWT_Type; + +/** \brief DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/** \brief DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU) + \brief Type definitions for the Trace Port Interface Unit (TPIU) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Unit Register (TPIU). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPIU_Type; + +/** \brief TPIU Asynchronous Clock Prescaler Register Definitions */ +#define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */ +#define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */ + +/** \brief TPIU Selected Pin Protocol Register Definitions */ +#define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */ +#define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */ + +/** \brief TPIU Formatter and Flush Status Register Definitions */ +#define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */ +#define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */ + +#define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */ +#define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */ + +#define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */ +#define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */ + +#define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */ +#define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */ + +/** \brief TPIU Formatter and Flush Control Register Definitions */ +#define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */ +#define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */ + +#define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */ +#define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */ + +#define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */ +#define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */ + +/** \brief TPIU Periodic Synchronization Control Register Definitions */ +#define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */ +#define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */ + +/** \brief TPIU TRIGGER Register Definitions */ +#define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */ +#define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */ +#define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */ +#define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */ +#define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */ +#define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */ +#define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */ + +#define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */ +#define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */ + +/** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */ +#define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */ +#define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */ + +/** \brief TPIU Integration Test ATB Control Register 0 Definitions */ +#define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */ +#define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */ + +#define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */ +#define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */ + +#define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */ +#define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */ + +#define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */ +#define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */ + +/** \brief TPIU Integration Mode Control Register Definitions */ +#define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ +#define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */ + +/** \brief TPIU DEVID Register Definitions */ +#define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */ +#define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */ + +#define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */ +#define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */ + +#define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */ +#define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */ + +#define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */ +#define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */ + +#define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */ +#define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */ + +/** \brief TPIU DEVTYPE Register Definitions */ +#define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */ +#define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */ + +#define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */ +#define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPIU */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/** \brief MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/** \brief MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/** \brief MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/** \brief MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/** \brief MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */ + +/** \brief MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/** \brief MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/** \brief SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/** \brief SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/** \brief SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/** \brief SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/** \brief SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/** \brief DIB SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/** \brief DIB SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/** \brief DIB Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/** \brief DIB SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/** \brief DIB SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases + \brief Alias definitions present for backwards compatibility for deprecated symbols. + @{ + */ + +#ifndef CMSIS_DISABLE_DEPRECATED + +#define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos +#define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk + +/* deprecated, CMSIS_5 backward compatibility */ +typedef struct +{ + __IOM uint32_t DHCSR; + __OM uint32_t DCRSR; + __IOM uint32_t DCRDR; + __IOM uint32_t DEMCR; + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; + __IOM uint32_t DSCSR; +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos DCB_DHCSR_DBGKEY_Pos +#define CoreDebug_DHCSR_DBGKEY_Msk DCB_DHCSR_DBGKEY_Msk + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos DCB_DHCSR_S_RESTART_ST_Pos +#define CoreDebug_DHCSR_S_RESTART_ST_Msk DCB_DHCSR_S_RESTART_ST_Msk + +#define CoreDebug_DHCSR_S_RESET_ST_Pos DCB_DHCSR_S_RESET_ST_Pos +#define CoreDebug_DHCSR_S_RESET_ST_Msk DCB_DHCSR_S_RESET_ST_Msk + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos DCB_DHCSR_S_RETIRE_ST_Pos +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk DCB_DHCSR_S_RETIRE_ST_Msk + +#define CoreDebug_DHCSR_S_LOCKUP_Pos DCB_DHCSR_S_LOCKUP_Pos +#define CoreDebug_DHCSR_S_LOCKUP_Msk DCB_DHCSR_S_LOCKUP_Msk + +#define CoreDebug_DHCSR_S_SLEEP_Pos DCB_DHCSR_S_SLEEP_Pos +#define CoreDebug_DHCSR_S_SLEEP_Msk DCB_DHCSR_S_SLEEP_Msk + +#define CoreDebug_DHCSR_S_HALT_Pos DCB_DHCSR_S_HALT_Pos +#define CoreDebug_DHCSR_S_HALT_Msk DCB_DHCSR_S_HALT_Msk + +#define CoreDebug_DHCSR_S_REGRDY_Pos DCB_DHCSR_S_REGRDY_Pos +#define CoreDebug_DHCSR_S_REGRDY_Msk DCB_DHCSR_S_REGRDY_Msk + +#define CoreDebug_DHCSR_C_MASKINTS_Pos DCB_DHCSR_C_MASKINTS_Pos +#define CoreDebug_DHCSR_C_MASKINTS_Msk DCB_DHCSR_C_MASKINTS_Msk + +#define CoreDebug_DHCSR_C_STEP_Pos DCB_DHCSR_C_STEP_Pos +#define CoreDebug_DHCSR_C_STEP_Msk DCB_DHCSR_C_STEP_Msk + +#define CoreDebug_DHCSR_C_HALT_Pos DCB_DHCSR_C_HALT_Pos +#define CoreDebug_DHCSR_C_HALT_Msk DCB_DHCSR_C_HALT_Msk + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos DCB_DHCSR_C_DEBUGEN_Pos +#define CoreDebug_DHCSR_C_DEBUGEN_Msk DCB_DHCSR_C_DEBUGEN_Msk + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos DCB_DCRSR_REGWnR_Pos +#define CoreDebug_DCRSR_REGWnR_Msk DCB_DCRSR_REGWnR_Msk + +#define CoreDebug_DCRSR_REGSEL_Pos DCB_DCRSR_REGSEL_Pos +#define CoreDebug_DCRSR_REGSEL_Msk DCB_DCRSR_REGSEL_Msk + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos DCB_DEMCR_TRCENA_Pos +#define CoreDebug_DEMCR_DWTENA_Msk DCB_DEMCR_TRCENA_Msk + +#define CoreDebug_DEMCR_VC_HARDERR_Pos DCB_DEMCR_VC_HARDERR_Pos +#define CoreDebug_DEMCR_VC_HARDERR_Msk DCB_DEMCR_VC_HARDERR_Msk + +#define CoreDebug_DEMCR_VC_CORERESET_Pos DCB_DEMCR_VC_CORERESET_Pos +#define CoreDebug_DEMCR_VC_CORERESET_Msk DCB_DEMCR_VC_CORERESET_Msk + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos DCB_DAUTHCTRL_INTSPNIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk DCB_DAUTHCTRL_INTSPNIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos DCB_DAUTHCTRL_SPNIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk DCB_DAUTHCTRL_SPNIDENSEL_Msk + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos DCB_DAUTHCTRL_INTSPIDEN_Pos +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk DCB_DAUTHCTRL_INTSPIDEN_Msk + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos DCB_DAUTHCTRL_SPIDENSEL_Pos +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk DCB_DAUTHCTRL_SPIDENSEL_Msk + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos DCB_DSCSR_CDS_Pos +#define CoreDebug_DSCSR_CDS_Msk DCB_DSCSR_CDS_Msk + +#define CoreDebug_DSCSR_SBRSEL_Pos DCB_DSCSR_SBRSEL_Pos +#define CoreDebug_DSCSR_SBRSEL_Msk DCB_DSCSR_SBRSEL_Msk + +#define CoreDebug_DSCSR_SBRSELEN_Pos DCB_DSCSR_SBRSELEN_Pos +#define CoreDebug_DSCSR_SBRSELEN_Msk DCB_DSCSR_SBRSELEN_Msk + +#define CoreDebug ((CoreDebug_Type *) DCB_BASE) +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define CoreDebug_NS ((CoreDebug_Type *) DCB_BASE_NS) +#endif + +#endif // CMSIS_DISABLE_DEPRECATED + +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/* NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/* NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR); +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + + #include "m-profile/armv8m_mpu.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/SDK/CMSIS/m-profile/armv7m_cachel1.h b/SDK/CMSIS/m-profile/armv7m_cachel1.h index d7338a7..52da06f 100644 --- a/SDK/CMSIS/m-profile/armv7m_cachel1.h +++ b/SDK/CMSIS/m-profile/armv7m_cachel1.h @@ -1,439 +1,439 @@ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later - */ - -#ifndef ARM_ARMV7M_CACHEL1_H -#define ARM_ARMV7M_CACHEL1_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#ifndef __SCB_DCACHE_LINE_SIZE -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -#ifndef __SCB_ICACHE_LINE_SIZE -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - struct { - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - } locals - #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) - __ALIGNED(__SCB_DCACHE_LINE_SIZE) - #endif - ; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - #if !defined(__OPTIMIZE__) - /* - * For the endless loop issue with no optimization builds. - * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 - * - * The issue only happens when local variables are in stack. If - * local variables are saved in general purpose register, then the function - * is OK. - * - * When local variables are in stack, after disabling the cache, flush the - * local variables cache line for data consistency. - */ - /* Clean and invalidate the local variable cache. */ - #if defined(__ICCARM__) - /* As we can't align the stack to the cache line size, invalidate each of the variables */ - SCB->DCCIMVAC = (uint32_t)&locals.sets; - SCB->DCCIMVAC = (uint32_t)&locals.ways; - SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; - #else - SCB->DCCIMVAC = (uint32_t)&locals; - #endif - __DSB(); - __ISB(); - #endif - - locals.ccsidr = SCB->CCSIDR; - /* clean & invalidate D-Cache */ - locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); - do { - locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); - do { - SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (locals.ways-- != 0U); - } while(locals.sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - -#endif /* ARM_ARMV7M_CACHEL1_H */ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Level 1 Cache API for Armv7-M and later + */ + +#ifndef ARM_ARMV7M_CACHEL1_H +#define ARM_ARMV7M_CACHEL1_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + struct { + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + } locals + #if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__)) + __ALIGNED(__SCB_DCACHE_LINE_SIZE) + #endif + ; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + #if !defined(__OPTIMIZE__) + /* + * For the endless loop issue with no optimization builds. + * More details, see https://github.com/ARM-software/CMSIS_5/issues/620 + * + * The issue only happens when local variables are in stack. If + * local variables are saved in general purpose register, then the function + * is OK. + * + * When local variables are in stack, after disabling the cache, flush the + * local variables cache line for data consistency. + */ + /* Clean and invalidate the local variable cache. */ + #if defined(__ICCARM__) + /* As we can't align the stack to the cache line size, invalidate each of the variables */ + SCB->DCCIMVAC = (uint32_t)&locals.sets; + SCB->DCCIMVAC = (uint32_t)&locals.ways; + SCB->DCCIMVAC = (uint32_t)&locals.ccsidr; + #else + SCB->DCCIMVAC = (uint32_t)&locals; + #endif + __DSB(); + __ISB(); + #endif + + locals.ccsidr = SCB->CCSIDR; + /* clean & invalidate D-Cache */ + locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr)); + do { + locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr)); + do { + SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (locals.ways-- != 0U); + } while(locals.sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_ARMV7M_CACHEL1_H */ diff --git a/SDK/CMSIS/m-profile/armv7m_mpu.h b/SDK/CMSIS/m-profile/armv7m_mpu.h index 5a4eba2..65b4575 100644 --- a/SDK/CMSIS/m-profile/armv7m_mpu.h +++ b/SDK/CMSIS/m-profile/armv7m_mpu.h @@ -1,273 +1,273 @@ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) MPU API for Armv7-M MPU - */ - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv7-M MPU + */ + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/SDK/CMSIS/m-profile/armv81m_pac.h b/SDK/CMSIS/m-profile/armv81m_pac.h index 648cf88..93f1c63 100644 --- a/SDK/CMSIS/m-profile/armv81m_pac.h +++ b/SDK/CMSIS/m-profile/armv81m_pac.h @@ -1,203 +1,203 @@ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension - */ - -#ifndef PAC_ARMV81_H -#define PAC_ARMV81_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/* ################### PAC Key functions ########################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions - \brief Functions that access the PAC keys. - @{ - */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) - -/** - \brief read the PAC key used for privileged mode - \details Reads the PAC key stored in the PAC_KEY_P registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode - \details writes the given PAC key to the PAC_KEY_P registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode - \details Reads the PAC key stored in the PAC_KEY_U registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode - \details writes the given PAC key to the PAC_KEY_U registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) - -/** - \brief read the PAC key used for privileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ - -#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ - -/*@} end of CMSIS_Core_PacKeyFunctions */ - - -#endif /* PAC_ARMV81_H */ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension + */ + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/SDK/CMSIS/m-profile/armv8m_mpu.h b/SDK/CMSIS/m-profile/armv8m_mpu.h index d743af1..0089068 100644 --- a/SDK/CMSIS/m-profile/armv8m_mpu.h +++ b/SDK/CMSIS/m-profile/armv8m_mpu.h @@ -1,421 +1,421 @@ -/* - * Copyright (c) 2017-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU - */ - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for Normal memory, Outer and Inner cacheability. -* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. -* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. -* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Normal memory outer-cacheable and inner-cacheable attributes -* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate -*/ -#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) -#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) -#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) -#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) -#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) -#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) -#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) -#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) -#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) -#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) -#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) -#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) -#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) -#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) -#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) -#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) -#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) -#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) -#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) -#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) -#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) -#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/* \brief Specifies MAIR_ATTR number */ -#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) - -/** - * Shareability - */ -/** \brief Normal memory, non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory, outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory, inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** - * Access permissions - * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only - */ -/** \brief Normal memory, read/write */ -#define ARM_MPU_AP_RW (0U) - -/** \brief Normal memory, read-only */ -#define ARM_MPU_AP_RO (1U) - -/** \brief Normal memory, any privilege level */ -#define ARM_MPU_AP_NP (1U) - -/** \brief Normal memory, privileged access only */ -#define ARM_MPU_AP_PO (0U) - -/* - * Execute-never - * XN = Execute-never, EX = Executable - */ -/** \brief Normal memory, Execution only permitted if read permitted */ -#define ARM_MPU_XN (1U) - -/** \brief Normal memory, Execution only permitted if read permitted */ -#define ARM_MPU_EX (0U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. -* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** - \brief Read MPU Type Register - \return Number of MPU regions -*/ -__STATIC_INLINE uint32_t ARM_MPU_TYPE() -{ - return ((MPU->TYPE) >> 8); -} - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - +/* + * Copyright (c) 2017-2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU + */ + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for Normal memory, Outer and Inner cacheability. +* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data. +* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy. +* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Normal memory outer-cacheable and inner-cacheable attributes +* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate +*/ +#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_OUTER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_OUTER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_OUTER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_OUTER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA (0b1111) +#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA (0b0010) +#define MPU_ATTR_NORMAL_INNER_WT_TR_WA (0b0001) +#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA (0b0011) +#define MPU_ATTR_NORMAL_INNER_WT_RA (0b1010) +#define MPU_ATTR_NORMAL_INNER_WT_WA (0b1001) +#define MPU_ATTR_NORMAL_INNER_WT_RA_WA (0b1011) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA (0b0101) +#define MPU_ATTR_NORMAL_INNER_WB_TR_WA (0b0110) +#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA (0b0111) +#define MPU_ATTR_NORMAL_INNER_WB_RA (0b1101) +#define MPU_ATTR_NORMAL_INNER_WB_WA (0b1110) +#define MPU_ATTR_NORMAL_INNER_WB_RA_WA (0b1111) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/* \brief Specifies MAIR_ATTR number */ +#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x) + +/** + * Shareability + */ +/** \brief Normal memory, non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory, outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory, inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** + * Access permissions + * AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only + */ +/** \brief Normal memory, read/write */ +#define ARM_MPU_AP_RW (0U) + +/** \brief Normal memory, read-only */ +#define ARM_MPU_AP_RO (1U) + +/** \brief Normal memory, any privilege level */ +#define ARM_MPU_AP_NP (1U) + +/** \brief Normal memory, privileged access only */ +#define ARM_MPU_AP_PO (0U) + +/* + * Execute-never + * XN = Execute-never, EX = Executable + */ +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_XN (1U) + +/** \brief Normal memory, Execution only permitted if read permitted */ +#define ARM_MPU_EX (0U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. Set to 0 for a read/write memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. Set to 0 for privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region. +* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** + \brief Read MPU Type Register + \return Number of MPU regions +*/ +__STATIC_INLINE uint32_t ARM_MPU_TYPE() +{ + return ((MPU->TYPE) >> 8); +} + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/SDK/CMSIS/m-profile/armv8m_pmu.h b/SDK/CMSIS/m-profile/armv8m_pmu.h index fb16533..01f844b 100644 --- a/SDK/CMSIS/m-profile/armv8m_pmu.h +++ b/SDK/CMSIS/m-profile/armv8m_pmu.h @@ -1,335 +1,335 @@ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) PMU API for Armv8.1-M PMU - */ - -#ifndef ARM_PMU_ARMV8_H -#define ARM_PMU_ARMV8_H - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -/** - * \brief PMU Events - * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. - * */ - -#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ -#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ -#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ -#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ -#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ -#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ -#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ -#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ -#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ -#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ -#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ -#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ -#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ -#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ -#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ -#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ -#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ -#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ -#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ -#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ -#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ -#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ -#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ -#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ -#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ -#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ -#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ -#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ -#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ -#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ -#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ -#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ -#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ -#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ -#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ -#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ -#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ -#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ -#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ -#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ -#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ -#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ -#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ -#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ -#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ -#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ -#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ -#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ -#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ -#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ -#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ -#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ -#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ -#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ -#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ -#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ -#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ -#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ -#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ -#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ -#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ -#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ -#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ -#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ -#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ -#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ -#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ -#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ -#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ -#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ -#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ -#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ -#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ -#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ -#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ - -/** \brief PMU Functions */ - -__STATIC_INLINE void ARM_PMU_Enable(void); -__STATIC_INLINE void ARM_PMU_Disable(void); - -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); - -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); - -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); - -/** - \brief Enable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Enable(void) -{ - PMU->CTRL |= PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Disable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Disable(void) -{ - PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Set event to count for PMU eventer counter - \param [in] num Event counter (0-30) to configure - \param [in] type Event to count -*/ -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) -{ - PMU->EVTYPER[num] = type; -} - -/** - \brief Reset cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; -} - -/** - \brief Reset all event counters -*/ -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; -} - -/** - \brief Enable counters - \param [in] mask Counters to enable - \note Enables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) -{ - PMU->CNTENSET = mask; -} - -/** - \brief Disable counters - \param [in] mask Counters to enable - \note Disables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) -{ - PMU->CNTENCLR = mask; -} - -/** - \brief Read cycle counter - \return Cycle count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) -{ - return PMU->CCNTR; -} - -/** - \brief Read event counter - \param [in] num Event counter (0-30) to read - \return Event count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) -{ - return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; -} - -/** - \brief Read counter overflow status - \return Counter overflow status bits for the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) -{ - return PMU->OVSSET; -} - -/** - \brief Clear counter overflow status - \param [in] mask Counter overflow status bits to clear - \note Clears overflow status bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) -{ - PMU->OVSCLR = mask; -} - -/** - \brief Enable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to set - \note Sets overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) -{ - PMU->INTENSET = mask; -} - -/** - \brief Disable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to clear - \note Clears overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) -{ - PMU->INTENCLR = mask; -} - -/** - \brief Software increment event counter - \param [in] mask Counters to increment - \note Software increment bits for one or more event counters (0-30) -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) -{ - PMU->SWINC = mask; -} - -#endif +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) PMU API for Armv8.1-M PMU + */ + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/SDK/CMSIS/m-profile/cmsis_armclang_m.h b/SDK/CMSIS/m-profile/cmsis_armclang_m.h index 82fb6d4..537b366 100644 --- a/SDK/CMSIS/m-profile/cmsis_armclang_m.h +++ b/SDK/CMSIS/m-profile/cmsis_armclang_m.h @@ -1,818 +1,818 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File - */ - -#ifndef __CMSIS_ARMCLANG_M_H -#define __CMSIS_ARMCLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __CMSIS_ARMCLANG_H - #error "This file must not be included directly" -#endif - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; - } -#endif - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif -#endif /* (__ARM_ARCH >= 8) */ -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} -#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ - /** @} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_M_H */ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File + */ + +#ifndef __CMSIS_ARMCLANG_M_H +#define __CMSIS_ARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_ARMCLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif +#endif /* (__ARM_ARCH >= 8) */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_M_H */ diff --git a/SDK/CMSIS/m-profile/cmsis_clang_m.h b/SDK/CMSIS/m-profile/cmsis_clang_m.h index a594442..7ea89e2 100644 --- a/SDK/CMSIS/m-profile/cmsis_clang_m.h +++ b/SDK/CMSIS/m-profile/cmsis_clang_m.h @@ -1,824 +1,824 @@ -/* - * Copyright (c) 2009-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler LLVM/Clang Header File - */ - -#ifndef __CMSIS_CLANG_M_H -#define __CMSIS_CLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#ifndef __CMSIS_CLANG_H - #error "This file must not be included directly" -#endif - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START _start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __stack -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __stack_limit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL __stack_seal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; - } -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} - -#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ - /** @} end of group CMSIS_SIMD_intrinsics */ -/** @} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CMSIS_CLANG_M_H */ +/* + * Copyright (c) 2009-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler LLVM/Clang Header File + */ + +#ifndef __CMSIS_CLANG_M_H +#define __CMSIS_CLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __CMSIS_CLANG_H + #error "This file must not be included directly" +#endif + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __stack +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __stack_limit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __stack_seal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; + } +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */ + /** @} end of group CMSIS_SIMD_intrinsics */ +/** @} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CMSIS_CLANG_M_H */ diff --git a/SDK/CMSIS/m-profile/cmsis_gcc_m.h b/SDK/CMSIS/m-profile/cmsis_gcc_m.h index 54d1f54..a096a40 100644 --- a/SDK/CMSIS/m-profile/cmsis_gcc_m.h +++ b/SDK/CMSIS/m-profile/cmsis_gcc_m.h @@ -1,717 +1,717 @@ -/* - * Copyright (c) 2009-2023 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler GCC Header File - */ - -#ifndef __CMSIS_GCC_M_H -#define __CMSIS_GCC_M_H - -#ifndef __CMSIS_GCC_H - #error "This file must not be included directly" -#endif - -#include - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct __copy_table { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct __zero_table { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CMSIS_GCC_M_H */ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler GCC Header File + */ + +#ifndef __CMSIS_GCC_M_H +#define __CMSIS_GCC_M_H + +#ifndef __CMSIS_GCC_H + #error "This file must not be included directly" +#endif + +#include + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct __copy_table { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct __zero_table { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1))) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CMSIS_GCC_M_H */ diff --git a/SDK/CMSIS/m-profile/cmsis_iccarm_m.h b/SDK/CMSIS/m-profile/cmsis_iccarm_m.h index cfc6f80..e888fae 100644 --- a/SDK/CMSIS/m-profile/cmsis_iccarm_m.h +++ b/SDK/CMSIS/m-profile/cmsis_iccarm_m.h @@ -1,1043 +1,1043 @@ -/* - * Copyright (c) 2017-2021 IAR Systems - * Copyright (c) 2017-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File - */ - -#ifndef __CMSIS_ICCARM_M_H__ -#define __CMSIS_ICCARM_M_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #elif __ARM_ARCH == 801 - #define __ARM_ARCH_8_1M_MAIN__ 1 - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 - #define __ARM_ARCH_8_1M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if defined(__cplusplus) && __cplusplus >= 201103L - #define __NO_RETURN [[noreturn]] - #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L - #define __NO_RETURN _Noreturn - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) - __IAR_FT void __disable_fault_irq() - { - __ASM volatile ("CPSID F" ::: "memory"); - } - - __IAR_FT void __enable_fault_irq() - { - __ASM volatile ("CPSIE F" ::: "memory"); - } - #endif - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if (defined (__ARM_FP) && (__ARM_FP >= 1)) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - - /* - * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. - * As a workaround we use inline assembly and a memory barrier. - * (IAR issue EWARM-11901) - */ - #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - __IAR_FT void __disable_fault_irq() - { - __ASM volatile ("CPSID F" ::: "memory"); - } - - __IAR_FT void __enable_fault_irq() - { - __ASM volatile ("CPSIE F" ::: "memory"); - } - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extension and secure, there is no stack limit check. - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions and secure, there is no stack limit check. - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_M_H__ */ +/* + * Copyright (c) 2017-2021 IAR Systems + * Copyright (c) 2017-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File + */ + +#ifndef __CMSIS_ICCARM_M_H__ +#define __CMSIS_ICCARM_M_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #elif __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' && __ARM_ARCH == 801 + #define __ARM_ARCH_8_1M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if defined(__cplusplus) && __cplusplus >= 201103L + #define __NO_RETURN [[noreturn]] + #elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L + #define __NO_RETURN _Noreturn + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2) + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + #endif + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if (defined (__ARM_FP) && (__ARM_FP >= 1)) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + + /* + * __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations. + * As a workaround we use inline assembly and a memory barrier. + * (IAR issue EWARM-11901) + */ + #define __CLREX() (__ASM volatile ("CLREX" ::: "memory")) + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!(defined (__ARM_FP) && (__ARM_FP >= 1))) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + __IAR_FT void __disable_fault_irq() + { + __ASM volatile ("CPSID F" ::: "memory"); + } + + __IAR_FT void __enable_fault_irq() + { + __ASM volatile ("CPSIE F" ::: "memory"); + } + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extension and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions and secure, there is no stack limit check. + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + !(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_M_H__ */ diff --git a/SDK/CMSIS/m-profile/cmsis_tiarmclang_m.h b/SDK/CMSIS/m-profile/cmsis_tiarmclang_m.h index 5b193a1..337fd82 100644 --- a/SDK/CMSIS/m-profile/cmsis_tiarmclang_m.h +++ b/SDK/CMSIS/m-profile/cmsis_tiarmclang_m.h @@ -1,1451 +1,1451 @@ -/* - * Copyright (c) 2023-2024 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * CMSIS-Core(M) Compiler TIARMClang Header File - */ - -#ifndef __CMSIS_TIARMCLANG_M_H -#define __CMSIS_TIARMCLANG_M_H - -#pragma clang system_header /* treat file as system include file */ - -#if (__ARM_ACLE >= 200) - #include -#else - #error Compiler must support ACLE V2.0 -#endif /* (__ARM_ACLE >= 200) */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif -#ifndef __NO_INIT - #define __NO_INIT __attribute__ ((section (".noinit"))) -#endif -#ifndef __ALIAS - #define __ALIAS(x) __attribute__ ((alias(x))) -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ -#ifndef __PROGRAM_START -#define __PROGRAM_START _c_int00 -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __STACK_END -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __STACK_SIZE -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) -#endif - -#if (__ARM_FEATURE_CMSE == 3) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __nop() - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __wfi() - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __wfe() - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __sev() - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __rev(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __rev16(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) __revsh(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR(op1, op2) __ror(op1, op2) - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT(value) __rbit(value) - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ(value) __clz(value) - - -/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ -#if ((__ARM_FEATURE_SAT >= 1) && \ - (__ARM_ARCH_ISA_THUMB >= 2) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(value, sat) __ssat(value, sat) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(value, sat) __usat(value, sat) - -#else /* (__ARM_FEATURE_SAT >= 1) */ -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return (max); - } - else if (val < min) - { - return (min); - } - } - return (val); -} - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return (max); - } - else if (val < 0) - { - return (0U); - } - } - return ((uint32_t)val); -} -#endif /* (__ARM_FEATURE_SAT >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 1) -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 1) */ - - -#if (__ARM_FEATURE_LDREX >= 2) -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 2) */ - - -#if (__ARM_FEATURE_LDREX >= 4) -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex -#endif /* (__ARM_FEATURE_LDREX >= 4) */ - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); - return (result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return (result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t)result); /* Add explicit type cast here */ -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return (result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* (__ARM_ARCH >= 8) */ - -/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return (result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return (result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if (__ARM_ARCH_ISA_THUMB >= 2) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return (result); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return (result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ - - -#if (__ARM_ARCH >= 8) -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return (result); -#endif -} - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure PSPLIM is RAZ/WI */ - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return (result); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - return (0U); -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return (result); -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ - (__ARM_FEATURE_CMSE < 3) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (__ARM_FEATURE_CMSE == 3) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ - (__ARM_ARCH_8_1M_MAIN__ < 1) ) - /* without main extensions, the non-secure MSPLIM is RAZ/WI */ - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* (__ARM_ARCH >= 8) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - return (__builtin_arm_get_fpscr()); -#else - return (0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (defined(__ARM_FP) && (__ARM_FP >= 1)) - __builtin_arm_set_fpscr(fpscr); -#else - (void)fpscr; -#endif -} - - -/** @} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (__ARM_FEATURE_DSP == 1) -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return (result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/** @} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_TIARMCLANG_M_H */ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * CMSIS-Core(M) Compiler TIARMClang Header File + */ + +#ifndef __CMSIS_TIARMCLANG_M_H +#define __CMSIS_TIARMCLANG_M_H + +#pragma clang system_header /* treat file as system include file */ + +#if (__ARM_ACLE >= 200) + #include +#else + #error Compiler must support ACLE V2.0 +#endif /* (__ARM_ACLE >= 200) */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +#ifndef __NO_INIT + #define __NO_INIT __attribute__ ((section (".noinit"))) +#endif +#ifndef __ALIAS + #define __ALIAS(x) __attribute__ ((alias(x))) +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ +#ifndef __PROGRAM_START +#define __PROGRAM_START _c_int00 +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __STACK_END +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __STACK_SIZE +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".intvecs"))) +#endif + +#if (__ARM_FEATURE_CMSE == 3) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __nop() + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __wfi() + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __wfe() + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __sev() + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __rev(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __rev16(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) __revsh(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR(op1, op2) __ror(op1, op2) + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT(value) __rbit(value) + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ(value) __clz(value) + + +/* __ARM_FEATURE_SAT is wrong for for Armv8-M Baseline devices */ +#if ((__ARM_FEATURE_SAT >= 1) && \ + (__ARM_ARCH_ISA_THUMB >= 2) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(value, sat) __ssat(value, sat) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(value, sat) __usat(value, sat) + +#else /* (__ARM_FEATURE_SAT >= 1) */ +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return (max); + } + else if (val < min) + { + return (min); + } + } + return (val); +} + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return (max); + } + else if (val < 0) + { + return (0U); + } + } + return ((uint32_t)val); +} +#endif /* (__ARM_FEATURE_SAT >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 1) +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 1) */ + + +#if (__ARM_FEATURE_LDREX >= 2) +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 2) */ + + +#if (__ARM_FEATURE_LDREX >= 4) +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex +#endif /* (__ARM_FEATURE_LDREX >= 4) */ + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value)); + return (result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return (result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t)result); /* Add explicit type cast here */ +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return (result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* (__ARM_ARCH >= 8) */ + +/** @}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return (result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return (result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if (__ARM_ARCH_ISA_THUMB >= 2) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return (result); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return (result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */ + + +#if (__ARM_ARCH >= 8) +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return (result); +#endif +} + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure PSPLIM is RAZ/WI */ + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return (result); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + return (0U); +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return (result); +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) && \ + (__ARM_FEATURE_CMSE < 3) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (__ARM_FEATURE_CMSE == 3) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if ((__ARM_ARCH_8M_MAIN__ < 1) && \ + (__ARM_ARCH_8_1M_MAIN__ < 1) ) + /* without main extensions, the non-secure MSPLIM is RAZ/WI */ + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* (__ARM_ARCH >= 8) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + return (__builtin_arm_get_fpscr()); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (defined(__ARM_FP) && (__ARM_FP >= 1)) + __builtin_arm_set_fpscr(fpscr); +#else + (void)fpscr; +#endif +} + + +/** @} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__ARM_FEATURE_DSP == 1) +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return (result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/** @} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_TIARMCLANG_M_H */ diff --git a/SDK/CMSIS/startup/startup_gd32e23x.S b/SDK/CMSIS/startup/startup_gd32e23x.S index 8d20030..d11a907 100644 --- a/SDK/CMSIS/startup/startup_gd32e23x.S +++ b/SDK/CMSIS/startup/startup_gd32e23x.S @@ -1,232 +1,232 @@ - .syntax unified - .cpu cortex-m23 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* necessary symbols defined in linker script to initialize data */ -.word _sidata -.word _sdata -.word _edata -.word _sbss -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function - -/* reset Handler */ -Reset_Handler: - ldr r0, =_sp - mov sp, r0 -/* copy the data segment into ram */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss - -FillZerobss: - movs r3, #0 - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call SystemInit function */ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/*Call the main function */ - bl main - -LoopForever: - b LoopForever - -.size Reset_Handler, .-Reset_Handler - -.section .text.Default_Handler,"ax",%progbits - -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler - - .section .vectors,"a",%progbits - .global __gVectors - -__gVectors: - .word _sp /* Top of Stack */ - .word Reset_Handler /* 1:Reset Handler */ - .word NMI_Handler /* 2:NMI Handler */ - .word HardFault_Handler /* 3:Hard Fault Handler */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SVC_Handler /* 11:SVCall Handler */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word PendSV_Handler /* 14:PendSV Handler */ - .word SysTick_Handler /* 15:SysTick Handler */ - - /* external interrupts handler */ - .word WWDGT_IRQHandler /* 16:Window Watchdog Timer */ - .word LVD_IRQHandler /* 17:LVD through EXTI Line detect */ - .word RTC_IRQHandler /* 18:RTC through EXTI Line */ - .word FMC_IRQHandler /* 19:FMC */ - .word RCU_IRQHandler /* 20:RCU */ - .word EXTI0_1_IRQHandler /* 21:EXTI Line 0 and EXTI Line 1 */ - .word EXTI2_3_IRQHandler /* 22:EXTI Line 2 and EXTI Line 3 */ - .word EXTI4_15_IRQHandler /* 23:EXTI Line 4 to EXTI Line 15 */ - .word 0 /* Reserved */ - .word DMA_Channel0_IRQHandler /* 25:DMA Channel 0 */ - .word DMA_Channel1_2_IRQHandler /* 26:DMA Channel 1 and DMA Channel 2 */ - .word DMA_Channel3_4_IRQHandler /* 27:DMA Channel 3 and DMA Channel 4 */ - .word ADC_CMP_IRQHandler /* 28:ADC and Comparator */ - .word TIMER0_BRK_UP_TRG_COM_IRQHandler /* 29:TIMER0 Break,Update,Trigger and Commutation */ - .word TIMER0_Channel_IRQHandler /* 30:TIMER0 Channel Capture Compare */ - .word 0 /* Reserved */ - .word TIMER2_IRQHandler /* 32:TIMER2 */ - .word TIMER5_IRQHandler /* 33:TIMER5 */ - .word 0 /* Reserved */ - .word TIMER13_IRQHandler /* 35:TIMER13 */ - .word TIMER14_IRQHandler /* 36:TIMER14 */ - .word TIMER15_IRQHandler /* 37:TIMER15 */ - .word TIMER16_IRQHandler /* 38:TIMER16 */ - .word I2C0_EV_IRQHandler /* 39:I2C0 Event */ - .word I2C1_EV_IRQHandler /* 40:I2C1 Event */ - .word SPI0_IRQHandler /* 41:SPI0 */ - .word SPI1_IRQHandler /* 42:SPI1 */ - .word USART0_IRQHandler /* 43:USART0 */ - .word USART1_IRQHandler /* 44:USART1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word I2C0_ER_IRQHandler /* 48:I2C0 Error */ - .word 0 /* Reserved */ - .word I2C1_ER_IRQHandler /* 50:I2C1 Error */ - - .size __gVectors, . - __gVectors - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDGT_IRQHandler - .thumb_set WWDGT_IRQHandler,Default_Handler - - .weak LVD_IRQHandler - .thumb_set LVD_IRQHandler,Default_Handler - - .weak TAMPER_IRQHandler - .thumb_set TAMPER_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak RCU_IRQHandler - .thumb_set RCU_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA_Channel0_IRQHandler - .thumb_set DMA_Channel0_IRQHandler,Default_Handler - - .weak DMA_Channel1_2_IRQHandler - .thumb_set DMA_Channel1_2_IRQHandler,Default_Handler - - .weak DMA_Channel3_4_IRQHandler - .thumb_set DMA_Channel3_4_IRQHandler,Default_Handler - - .weak ADC_CMP_IRQHandler - .thumb_set ADC_CMP_IRQHandler,Default_Handler - - .weak TIMER0_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIMER0_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIMER0_Channel_IRQHandler - .thumb_set TIMER0_Channel_IRQHandler,Default_Handler - - .weak TIMER2_IRQHandler - .thumb_set TIMER2_IRQHandler,Default_Handler - - .weak TIMER5_IRQHandler - .thumb_set TIMER5_IRQHandler,Default_Handler - - .weak TIMER13_IRQHandler - .thumb_set TIMER13_IRQHandler,Default_Handler - - .weak TIMER14_IRQHandler - .thumb_set TIMER14_IRQHandler,Default_Handler - - .weak TIMER15_IRQHandler - .thumb_set TIMER15_IRQHandler,Default_Handler - - .weak TIMER16_IRQHandler - .thumb_set TIMER16_IRQHandler,Default_Handler - - .weak I2C0_EV_IRQHandler - .thumb_set I2C0_EV_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak SPI0_IRQHandler - .thumb_set SPI0_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART0_IRQHandler - .thumb_set USART0_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak I2C0_ER_IRQHandler - .thumb_set I2C0_ER_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler + .syntax unified + .cpu cortex-m23 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* necessary symbols defined in linker script to initialize data */ +.word _sidata +.word _sdata +.word _edata +.word _sbss +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +/* reset Handler */ +Reset_Handler: + ldr r0, =_sp + mov sp, r0 +/* copy the data segment into ram */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss + +FillZerobss: + movs r3, #0 + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call SystemInit function */ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/*Call the main function */ + bl main + +LoopForever: + b LoopForever + +.size Reset_Handler, .-Reset_Handler + +.section .text.Default_Handler,"ax",%progbits + +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler + + .section .vectors,"a",%progbits + .global __gVectors + +__gVectors: + .word _sp /* Top of Stack */ + .word Reset_Handler /* 1:Reset Handler */ + .word NMI_Handler /* 2:NMI Handler */ + .word HardFault_Handler /* 3:Hard Fault Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SVC_Handler /* 11:SVCall Handler */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word PendSV_Handler /* 14:PendSV Handler */ + .word SysTick_Handler /* 15:SysTick Handler */ + + /* external interrupts handler */ + .word WWDGT_IRQHandler /* 16:Window Watchdog Timer */ + .word LVD_IRQHandler /* 17:LVD through EXTI Line detect */ + .word RTC_IRQHandler /* 18:RTC through EXTI Line */ + .word FMC_IRQHandler /* 19:FMC */ + .word RCU_IRQHandler /* 20:RCU */ + .word EXTI0_1_IRQHandler /* 21:EXTI Line 0 and EXTI Line 1 */ + .word EXTI2_3_IRQHandler /* 22:EXTI Line 2 and EXTI Line 3 */ + .word EXTI4_15_IRQHandler /* 23:EXTI Line 4 to EXTI Line 15 */ + .word 0 /* Reserved */ + .word DMA_Channel0_IRQHandler /* 25:DMA Channel 0 */ + .word DMA_Channel1_2_IRQHandler /* 26:DMA Channel 1 and DMA Channel 2 */ + .word DMA_Channel3_4_IRQHandler /* 27:DMA Channel 3 and DMA Channel 4 */ + .word ADC_CMP_IRQHandler /* 28:ADC and Comparator */ + .word TIMER0_BRK_UP_TRG_COM_IRQHandler /* 29:TIMER0 Break,Update,Trigger and Commutation */ + .word TIMER0_Channel_IRQHandler /* 30:TIMER0 Channel Capture Compare */ + .word 0 /* Reserved */ + .word TIMER2_IRQHandler /* 32:TIMER2 */ + .word TIMER5_IRQHandler /* 33:TIMER5 */ + .word 0 /* Reserved */ + .word TIMER13_IRQHandler /* 35:TIMER13 */ + .word TIMER14_IRQHandler /* 36:TIMER14 */ + .word TIMER15_IRQHandler /* 37:TIMER15 */ + .word TIMER16_IRQHandler /* 38:TIMER16 */ + .word I2C0_EV_IRQHandler /* 39:I2C0 Event */ + .word I2C1_EV_IRQHandler /* 40:I2C1 Event */ + .word SPI0_IRQHandler /* 41:SPI0 */ + .word SPI1_IRQHandler /* 42:SPI1 */ + .word USART0_IRQHandler /* 43:USART0 */ + .word USART1_IRQHandler /* 44:USART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word I2C0_ER_IRQHandler /* 48:I2C0 Error */ + .word 0 /* Reserved */ + .word I2C1_ER_IRQHandler /* 50:I2C1 Error */ + + .size __gVectors, . - __gVectors + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDGT_IRQHandler + .thumb_set WWDGT_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak TAMPER_IRQHandler + .thumb_set TAMPER_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak RCU_IRQHandler + .thumb_set RCU_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA_Channel0_IRQHandler + .thumb_set DMA_Channel0_IRQHandler,Default_Handler + + .weak DMA_Channel1_2_IRQHandler + .thumb_set DMA_Channel1_2_IRQHandler,Default_Handler + + .weak DMA_Channel3_4_IRQHandler + .thumb_set DMA_Channel3_4_IRQHandler,Default_Handler + + .weak ADC_CMP_IRQHandler + .thumb_set ADC_CMP_IRQHandler,Default_Handler + + .weak TIMER0_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIMER0_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIMER0_Channel_IRQHandler + .thumb_set TIMER0_Channel_IRQHandler,Default_Handler + + .weak TIMER2_IRQHandler + .thumb_set TIMER2_IRQHandler,Default_Handler + + .weak TIMER5_IRQHandler + .thumb_set TIMER5_IRQHandler,Default_Handler + + .weak TIMER13_IRQHandler + .thumb_set TIMER13_IRQHandler,Default_Handler + + .weak TIMER14_IRQHandler + .thumb_set TIMER14_IRQHandler,Default_Handler + + .weak TIMER15_IRQHandler + .thumb_set TIMER15_IRQHandler,Default_Handler + + .weak TIMER16_IRQHandler + .thumb_set TIMER16_IRQHandler,Default_Handler + + .weak I2C0_EV_IRQHandler + .thumb_set I2C0_EV_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak SPI0_IRQHandler + .thumb_set SPI0_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART0_IRQHandler + .thumb_set USART0_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak I2C0_ER_IRQHandler + .thumb_set I2C0_ER_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler diff --git a/SDK/GD32E23x_standard_peripheral/CMakeLists.txt b/SDK/GD32E23x_standard_peripheral/CMakeLists.txt index 4db994c..a01a0ba 100644 --- a/SDK/GD32E23x_standard_peripheral/CMakeLists.txt +++ b/SDK/GD32E23x_standard_peripheral/CMakeLists.txt @@ -1,30 +1,30 @@ -project(GD32E23x_standard_peripheral LANGUAGES C CXX ASM) - -add_library(GD32E23x_standard_peripheral OBJECT - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c -) - -target_include_directories(GD32E23x_standard_peripheral PUBLIC - ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Include -) - -# CMSIS header only library is linked. +project(GD32E23x_standard_peripheral LANGUAGES C CXX ASM) + +add_library(GD32E23x_standard_peripheral OBJECT + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c +) + +target_include_directories(GD32E23x_standard_peripheral PUBLIC + ${CMAKE_SOURCE_DIR}/SDK/GD32E23x_standard_peripheral/Include +) + +# CMSIS header only library is linked. target_link_libraries(GD32E23x_standard_peripheral PUBLIC CMSIS) \ No newline at end of file diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_adc.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_adc.h index 0238c92..b1aa01c 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_adc.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_adc.h @@ -1,349 +1,349 @@ -/*! - \file gd32e23x_adc.h - \brief definitions for the ADC - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_ADC_H -#define GD32E23X_ADC_H - -#include "gd32e23x.h" - -/* ADC definitions */ -#define ADC ADC_BASE - -/* registers definitions */ -#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */ -#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */ -#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */ -#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */ -#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */ -#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */ -#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */ -#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */ -#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */ -#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */ -#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */ -#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */ -#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */ -#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */ -#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */ -#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */ -#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */ -#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */ -#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */ -#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */ -#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */ - -/* bits definitions */ -/* ADC_STAT */ -#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ -#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ -#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ -#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ -#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ - -/* ADC_CTL0 */ -#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ -#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ -#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ -#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ -#define ADC_CTL0_SM BIT(8) /*!< scan mode */ -#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ -#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ -#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ -#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ -#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ -#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ -#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ -#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ - -/* ADC_CTL1 */ -#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ -#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ -#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ -#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ -#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ -#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ -#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ -#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ -#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ -#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ -#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ -#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ -#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ - -/* ADC_SAMPTx x=0,1 */ -#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */ - -/* ADC_IOFFx x=0..3 */ -#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ - -/* ADC_WDHT */ -#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ - -/* ADC_WDLT */ -#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ - -/* ADC_RSQx x=0..2 */ -#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ - -/* ADC_ISQ */ -#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ -#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ - -/* ADC_IDATAx x=0..3*/ -#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ - -/* ADC_RDATA */ -#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ - -/* ADC_OVSAMPCTL */ -#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ -#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ -#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ -#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ - -/* constants definitions */ -/* ADC flag definitions */ -#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ -#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ -#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ -#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ -#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ - -/* adc_ctl0 register value */ -#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ - -/* ADC special function */ -#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ -#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ -#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ - -/* ADC data alignment */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ -#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ - -/* external trigger select for regular channel */ -#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) -#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ -#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ -#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ -#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ -#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ -#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ - -/* external trigger select for inserted channel */ -#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) -#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ -#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ -#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ -#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ - -/* adc_samptx register value */ -#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) -#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ -#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ -#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ -#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ -#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ -#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ -#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ -#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ - -/* ADC data offset for inserted channel x */ -#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog high threshold */ -#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC analog watchdog low threshold */ -#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) - -/* ADC regular channel group length */ -#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) - -/* ADC inserted channel group length */ -#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) - -/* ADC resolution definitions */ -#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */ -#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ -#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ -#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ -#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ - -/* ADC oversampling shift */ -#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) -#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ -#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ - -/* ADC oversampling ratio */ -#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) -#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ -#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ -#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ -#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ -#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ -#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ -#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ -#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ - -/* ADC triggered oversampling */ -#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ -#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ - -/* ADC channel group definitions */ -#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ -#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ -#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ -#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ - -/* ADC inserted channel definitions */ -#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ -#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ -#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ -#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ - -/* ADC channel definitions */ -#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ -#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ -#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ -#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ -#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ -#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ -#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ -#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ -#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ -#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ -#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ -#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ - -/* ADC interrupt definitions */ -#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ -#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ -#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ - -/* ADC interrupt flag */ -#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ -#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ -#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ - -/* function declarations */ -/* reset ADC */ -void adc_deinit(void); -/* enable ADC interface */ -void adc_enable(void); -/* disable ADC interface */ -void adc_disable(void); - -/* ADC calibration and reset calibration */ -void adc_calibration_enable(void); -/* enable DMA request */ -void adc_dma_mode_enable(void); -/* disable DMA request */ -void adc_dma_mode_disable(void); - -/* enable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_enable(void); -/* disable the temperature sensor and Vrefint channel */ -void adc_tempsensor_vrefint_disable(void); - -/* configure ADC discontinuous mode */ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); -/* configure ADC special function */ -void adc_special_function_config(uint32_t function, ControlStatus newvalue); - -/* configure ADC data alignment */ -void adc_data_alignment_config(uint32_t data_alignment); -/* configure the length of regular channel group or inserted channel group */ -void adc_channel_length_config(uint8_t channel_group, uint32_t length); -/* configure ADC regular channel */ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel */ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); -/* configure ADC inserted channel offset */ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); -/* enable ADC external trigger */ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); -/* configure ADC external trigger source */ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); -/* enable ADC software trigger */ -void adc_software_trigger_enable(uint8_t channel_group); - -/* read ADC regular group data register */ -uint16_t adc_regular_data_read(void); -/* read ADC inserted group data register */ -uint16_t adc_inserted_data_read(uint8_t inserted_channel); - -/* get the ADC flag bits */ -FlagStatus adc_flag_get(uint32_t flag); -/* clear the ADC flag bits */ -void adc_flag_clear(uint32_t flag); -/* get the ADC interrupt bits */ -FlagStatus adc_interrupt_flag_get(uint32_t flag); -/* clear the ADC flag */ -void adc_interrupt_flag_clear(uint32_t flag); -/* enable ADC interrupt */ -void adc_interrupt_enable(uint32_t interrupt); -/* disable ADC interrupt */ -void adc_interrupt_disable(uint32_t interrupt); - -/* configure ADC analog watchdog single channel */ -void adc_watchdog_single_channel_enable(uint8_t channel); -/* configure ADC analog watchdog group channel */ -void adc_watchdog_group_channel_enable(uint8_t channel_group); -/* disable ADC analog watchdog */ -void adc_watchdog_disable(void); -/* configure ADC analog watchdog threshold */ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); - -/* configure ADC resolution */ -void adc_resolution_config(uint32_t resolution); -/* configure ADC oversample mode */ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); -/* enable ADC oversample mode */ -void adc_oversample_mode_enable(void); -/* disable ADC oversample mode */ -void adc_oversample_mode_disable(void); - -#endif /* GD32E23X_ADC_H */ +/*! + \file gd32e23x_adc.h + \brief definitions for the ADC + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_ADC_H +#define GD32E23X_ADC_H + +#include "gd32e23x.h" + +/* ADC definitions */ +#define ADC ADC_BASE + +/* registers definitions */ +#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */ +#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */ +#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */ +#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */ +#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */ +#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */ +#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */ +#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */ +#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */ +#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */ +#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */ +#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */ +#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */ +#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */ +#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */ +#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */ +#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */ +#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */ +#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */ +#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */ +#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */ + +/* bits definitions */ +/* ADC_STAT */ +#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ +#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */ +#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */ +#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ +#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ + +/* ADC_CTL0 */ +#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */ +#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ +#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ +#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ +#define ADC_CTL0_SM BIT(8) /*!< scan mode */ +#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ +#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ +#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ +#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ +#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */ +#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ +#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ +#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */ + +/* ADC_CTL1 */ +#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ +#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ +#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ +#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ +#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */ +#define ADC_CTL1_DAL BIT(11) /*!< data alignment */ +#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */ +#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ +#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */ +#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ +#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ +#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ +#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */ + +/* ADC_SAMPTx x=0,1 */ +#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */ + +/* ADC_IOFFx x=0..3 */ +#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */ + +/* ADC_WDHT */ +#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */ + +/* ADC_WDLT */ +#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */ + +/* ADC_RSQx x=0..2 */ +#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */ + +/* ADC_ISQ */ +#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */ +#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */ + +/* ADC_IDATAx x=0..3*/ +#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */ + +/* ADC_RDATA */ +#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */ + +/* ADC_OVSAMPCTL */ +#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ +#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */ +#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */ +#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ + +/* constants definitions */ +/* ADC flag definitions */ +#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ +#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */ +#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */ +#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */ +#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */ + +/* adc_ctl0 register value */ +#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */ + +/* ADC special function */ +#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ +#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ +#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ + +/* ADC data alignment */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */ +#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */ + +/* external trigger select for regular channel */ +#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) +#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ +#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ +#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ +#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */ +#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ +#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ + +/* external trigger select for inserted channel */ +#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) +#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ +#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */ +#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ +#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ + +/* adc_samptx register value */ +#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) +#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ +#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ +#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ +#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ +#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ +#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ +#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ +#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ + +/* ADC data offset for inserted channel x */ +#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog high threshold */ +#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC analog watchdog low threshold */ +#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) + +/* ADC regular channel group length */ +#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) + +/* ADC inserted channel group length */ +#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) + +/* ADC resolution definitions */ +#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */ +#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ +#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ +#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ +#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ + +/* ADC oversampling shift */ +#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) +#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ +#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ + +/* ADC oversampling ratio */ +#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) +#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ +#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ +#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ +#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ +#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ +#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ +#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ +#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ + +/* ADC triggered oversampling */ +#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */ +#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */ + +/* ADC channel group definitions */ +#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ +#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ +#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ +#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ + +/* ADC inserted channel definitions */ +#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ +#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ +#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ +#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ + +/* ADC channel definitions */ +#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ +#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ +#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ +#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ +#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ +#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ +#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ +#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ +#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ +#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ +#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ +#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ + +/* ADC interrupt definitions */ +#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ +#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ +#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ + +/* ADC interrupt flag */ +#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */ +#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ +#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ + +/* function declarations */ +/* reset ADC */ +void adc_deinit(void); +/* enable ADC interface */ +void adc_enable(void); +/* disable ADC interface */ +void adc_disable(void); + +/* ADC calibration and reset calibration */ +void adc_calibration_enable(void); +/* enable DMA request */ +void adc_dma_mode_enable(void); +/* disable DMA request */ +void adc_dma_mode_disable(void); + +/* enable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_enable(void); +/* disable the temperature sensor and Vrefint channel */ +void adc_tempsensor_vrefint_disable(void); + +/* configure ADC discontinuous mode */ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length); +/* configure ADC special function */ +void adc_special_function_config(uint32_t function, ControlStatus newvalue); + +/* configure ADC data alignment */ +void adc_data_alignment_config(uint32_t data_alignment); +/* configure the length of regular channel group or inserted channel group */ +void adc_channel_length_config(uint8_t channel_group, uint32_t length); +/* configure ADC regular channel */ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel */ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time); +/* configure ADC inserted channel offset */ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); +/* enable ADC external trigger */ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue); +/* configure ADC external trigger source */ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source); +/* enable ADC software trigger */ +void adc_software_trigger_enable(uint8_t channel_group); + +/* read ADC regular group data register */ +uint16_t adc_regular_data_read(void); +/* read ADC inserted group data register */ +uint16_t adc_inserted_data_read(uint8_t inserted_channel); + +/* get the ADC flag bits */ +FlagStatus adc_flag_get(uint32_t flag); +/* clear the ADC flag bits */ +void adc_flag_clear(uint32_t flag); +/* get the ADC interrupt bits */ +FlagStatus adc_interrupt_flag_get(uint32_t flag); +/* clear the ADC flag */ +void adc_interrupt_flag_clear(uint32_t flag); +/* enable ADC interrupt */ +void adc_interrupt_enable(uint32_t interrupt); +/* disable ADC interrupt */ +void adc_interrupt_disable(uint32_t interrupt); + +/* configure ADC analog watchdog single channel */ +void adc_watchdog_single_channel_enable(uint8_t channel); +/* configure ADC analog watchdog group channel */ +void adc_watchdog_group_channel_enable(uint8_t channel_group); +/* disable ADC analog watchdog */ +void adc_watchdog_disable(void); +/* configure ADC analog watchdog threshold */ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); + +/* configure ADC resolution */ +void adc_resolution_config(uint32_t resolution); +/* configure ADC oversample mode */ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio); +/* enable ADC oversample mode */ +void adc_oversample_mode_enable(void); +/* disable ADC oversample mode */ +void adc_oversample_mode_disable(void); + +#endif /* GD32E23X_ADC_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_cmp.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_cmp.h index 345a686..22769eb 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_cmp.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_cmp.h @@ -1,132 +1,132 @@ -/*! - \file gd32e23x_cmp.h - \brief definitions for the CMP - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_CMP_H -#define GD32E23X_CMP_H - -#include "gd32e23x.h" - -/* CMP definitions */ -#define CMP CMP_BASE /*!< CMP base address */ - -/* registers definitions */ -#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ - -/* bits definitions */ -/* CMP_CS */ -#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ -#define CMP_CS_CMP0SW BIT(1) /*!< CMP switch mode enable */ -#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ -#define CMP_CS_CMP0MSEL BITS(4,6) /*!< CMP_IM input selection */ -#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ -#define CMP_CS_CMP0PL BIT(11) /*!< CMP0 output polarity */ -#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ -#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output state bit */ -#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ - -/* constants definitions */ -/* CMP units */ -typedef enum{ - CMP0, /*!< comparator 0 */ -}cmp_enum; - -/* CMP operating mode */ -#define CS_CMPXM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) -#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */ -#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */ -#define CMP_MODE_LOWSPEED CS_CMPXM(2) /*!< CMP mode low speed */ -#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */ - -/* CMP hysteresis */ -#define CS_CMPXHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U)) -#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */ -#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */ -#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */ -#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */ - -/* CMP inverting input */ -#define CS_CMPXMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) -#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */ -#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */ -#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */ -#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */ -#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input PA4 */ -#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input PA5 */ -#define CMP_INVERTING_INPUT_PA0 CS_CMPXMSEL(6) /*!< CMP inverting input PA0 */ -#define CMP_INVERTING_INPUT_PA2 CS_CMPXMSEL(7) /*!< CMP inverting input PA2 */ - -/* CMP output */ -#define CS_CMPXOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) -#define CMP_OUTPUT_NONE CS_CMPXOSEL(0) /*!< CMP output none */ -#define CMP_OUTPUT_TIMER0_BKIN CS_CMPXOSEL(1) /*!< CMP output TIMER0 break input */ -#define CMP_OUTPUT_TIMER0_IC0 CS_CMPXOSEL(2) /*!< CMP output TIMER0_CH0 input capture */ -#define CMP_OUTPUT_TIMER0_OCPRECLR CS_CMPXOSEL(3) /*!< CMP output TIMER0 OCPRE_CLR input */ -#define CMP_OUTPUT_TIMER2_IC0 CS_CMPXOSEL(6) /*!< CMP output TIMER2_CH0 input capture */ -#define CMP_OUTPUT_TIMER2_OCPRECLR CS_CMPXOSEL(7) /*!< CMP output TIMER2 OCPRE_CLR input */ - -/* CMP output polarity*/ -#define CS_CMPXPL(regval) (BIT(11) & ((uint32_t)(regval) << 11U)) -#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */ -#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */ - -/* CMP output level */ -#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< CMP output high */ -#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< CMP output low */ - -/* function declarations */ -/* initialization functions */ -/* CMP deinit */ -void cmp_deinit(cmp_enum cmp_periph); -/* CMP mode init */ -void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis); -/* CMP output init */ -void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity); - -/* enable functions */ -/* enable CMP */ -void cmp_enable(cmp_enum cmp_periph); -/* disable CMP */ -void cmp_disable(cmp_enum cmp_periph); -/* enable CMP switch */ -void cmp_switch_enable(void); -/* disable CMP switch */ -void cmp_switch_disable(void); -/* lock the CMP */ -void cmp_lock_enable(cmp_enum cmp_periph); - -/* get state related functions */ -/* get output level */ -uint32_t cmp_output_level_get(cmp_enum cmp_periph); - -#endif /* GD32E23X_CMP_H */ +/*! + \file gd32e23x_cmp.h + \brief definitions for the CMP + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_CMP_H +#define GD32E23X_CMP_H + +#include "gd32e23x.h" + +/* CMP definitions */ +#define CMP CMP_BASE /*!< CMP base address */ + +/* registers definitions */ +#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */ + +/* bits definitions */ +/* CMP_CS */ +#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */ +#define CMP_CS_CMP0SW BIT(1) /*!< CMP switch mode enable */ +#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */ +#define CMP_CS_CMP0MSEL BITS(4,6) /*!< CMP_IM input selection */ +#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */ +#define CMP_CS_CMP0PL BIT(11) /*!< CMP0 output polarity */ +#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */ +#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output state bit */ +#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */ + +/* constants definitions */ +/* CMP units */ +typedef enum{ + CMP0, /*!< comparator 0 */ +}cmp_enum; + +/* CMP operating mode */ +#define CS_CMPXM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U)) +#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */ +#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */ +#define CMP_MODE_LOWSPEED CS_CMPXM(2) /*!< CMP mode low speed */ +#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */ + +/* CMP hysteresis */ +#define CS_CMPXHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U)) +#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */ +#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */ +#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */ +#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */ + +/* CMP inverting input */ +#define CS_CMPXMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U)) +#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */ +#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */ +#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */ +#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */ +#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input PA4 */ +#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input PA5 */ +#define CMP_INVERTING_INPUT_PA0 CS_CMPXMSEL(6) /*!< CMP inverting input PA0 */ +#define CMP_INVERTING_INPUT_PA2 CS_CMPXMSEL(7) /*!< CMP inverting input PA2 */ + +/* CMP output */ +#define CS_CMPXOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) +#define CMP_OUTPUT_NONE CS_CMPXOSEL(0) /*!< CMP output none */ +#define CMP_OUTPUT_TIMER0_BKIN CS_CMPXOSEL(1) /*!< CMP output TIMER0 break input */ +#define CMP_OUTPUT_TIMER0_IC0 CS_CMPXOSEL(2) /*!< CMP output TIMER0_CH0 input capture */ +#define CMP_OUTPUT_TIMER0_OCPRECLR CS_CMPXOSEL(3) /*!< CMP output TIMER0 OCPRE_CLR input */ +#define CMP_OUTPUT_TIMER2_IC0 CS_CMPXOSEL(6) /*!< CMP output TIMER2_CH0 input capture */ +#define CMP_OUTPUT_TIMER2_OCPRECLR CS_CMPXOSEL(7) /*!< CMP output TIMER2 OCPRE_CLR input */ + +/* CMP output polarity*/ +#define CS_CMPXPL(regval) (BIT(11) & ((uint32_t)(regval) << 11U)) +#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */ +#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */ + +/* CMP output level */ +#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< CMP output high */ +#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< CMP output low */ + +/* function declarations */ +/* initialization functions */ +/* CMP deinit */ +void cmp_deinit(cmp_enum cmp_periph); +/* CMP mode init */ +void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis); +/* CMP output init */ +void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity); + +/* enable functions */ +/* enable CMP */ +void cmp_enable(cmp_enum cmp_periph); +/* disable CMP */ +void cmp_disable(cmp_enum cmp_periph); +/* enable CMP switch */ +void cmp_switch_enable(void); +/* disable CMP switch */ +void cmp_switch_disable(void); +/* lock the CMP */ +void cmp_lock_enable(cmp_enum cmp_periph); + +/* get state related functions */ +/* get output level */ +uint32_t cmp_output_level_get(cmp_enum cmp_periph); + +#endif /* GD32E23X_CMP_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_crc.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_crc.h index 2255864..fa41691 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_crc.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_crc.h @@ -1,123 +1,123 @@ -/*! - \file gd32e23x_crc.h - \brief definitions for the CRC - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_CRC_H -#define GD32E23X_CRC_H - -#include "gd32e23x.h" - -/* CRC definitions */ -#define CRC CRC_BASE /*!< CRC bsae address */ - -/* registers definitions */ -#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */ -#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */ -#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */ -#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */ -#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */ - -/* bits definitions */ -/* CRC_DATA */ -#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ - -/* CRC_FDATA */ -#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ - -/* CRC_CTL */ -#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ -#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ -#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ -#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ - -/* CRC_INIT */ -#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ - -/* CRC_POLY */ -#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ - -/* constants definitions */ -/* size of polynomial function */ -#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) -#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ -#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ - -/* input data reverse function */ -#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) -#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ -#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ -#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ -#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ - -/* input data format */ -#define INPUT_FORMAT_WORD 0U /*!< input data in word format */ -#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */ -#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */ - -/* function declarations */ -/* deinit CRC calculation unit */ -void crc_deinit(void); - -/* enable the reverse operation of output data */ -void crc_reverse_output_data_enable(void); -/* disable the reverse operation of output data */ -void crc_reverse_output_data_disable(void); - -/* reset data register to the value of initialization data register */ -void crc_data_register_reset(void); -/* read the data register */ -uint32_t crc_data_register_read(void); - -/* read the free data register */ -uint8_t crc_free_data_register_read(void); -/* write the free data register */ -void crc_free_data_register_write(uint8_t free_data); - -/* write the initial value register */ -void crc_init_data_register_write(uint32_t init_data); -/* configure the CRC input data function */ -void crc_input_data_reverse_config(uint32_t data_reverse); - -/* configure the CRC size of polynomial function */ -void crc_polynomial_size_set(uint32_t poly_size); -/* configure the CRC polynomial value function */ -void crc_polynomial_set(uint32_t poly); - -/* CRC calculate single data */ -uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format); -/* CRC calculate a data array */ -uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format); - -#endif /* GD32E23X_CRC_H */ +/*! + \file gd32e23x_crc.h + \brief definitions for the CRC + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_CRC_H +#define GD32E23X_CRC_H + +#include "gd32e23x.h" + +/* CRC definitions */ +#define CRC CRC_BASE /*!< CRC bsae address */ + +/* registers definitions */ +#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */ +#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */ +#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */ +#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */ +#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */ + +/* bits definitions */ +/* CRC_DATA */ +#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */ + +/* CRC_FDATA */ +#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */ + +/* CRC_CTL */ +#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */ +#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */ +#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */ +#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */ + +/* CRC_INIT */ +#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */ + +/* CRC_POLY */ +#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */ + +/* constants definitions */ +/* size of polynomial function */ +#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3)) +#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */ +#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */ + +/* input data reverse function */ +#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5)) +#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */ +#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */ +#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */ +#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */ + +/* input data format */ +#define INPUT_FORMAT_WORD 0U /*!< input data in word format */ +#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */ +#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */ + +/* function declarations */ +/* deinit CRC calculation unit */ +void crc_deinit(void); + +/* enable the reverse operation of output data */ +void crc_reverse_output_data_enable(void); +/* disable the reverse operation of output data */ +void crc_reverse_output_data_disable(void); + +/* reset data register to the value of initialization data register */ +void crc_data_register_reset(void); +/* read the data register */ +uint32_t crc_data_register_read(void); + +/* read the free data register */ +uint8_t crc_free_data_register_read(void); +/* write the free data register */ +void crc_free_data_register_write(uint8_t free_data); + +/* write the initial value register */ +void crc_init_data_register_write(uint32_t init_data); +/* configure the CRC input data function */ +void crc_input_data_reverse_config(uint32_t data_reverse); + +/* configure the CRC size of polynomial function */ +void crc_polynomial_size_set(uint32_t poly_size); +/* configure the CRC polynomial value function */ +void crc_polynomial_set(uint32_t poly); + +/* CRC calculate single data */ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format); +/* CRC calculate a data array */ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format); + +#endif /* GD32E23X_CRC_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dbg.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dbg.h index cc638e0..eab6b77 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dbg.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dbg.h @@ -1,121 +1,121 @@ -/*! - \file gd32e23x_dbg.h - \brief definitions for the DBG - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_DBG_H -#define GD32E23X_DBG_H - -#include "gd32e23x.h" - -/* DBG definitions */ -#define DBG DBG_BASE - -/* registers definitions */ -#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ -#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ -#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ - -/* bits definitions */ -/* DBG_ID */ -#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ - -/* DBG_CTL0 */ -#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ -#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ -#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ -#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ -#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ -#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */ -#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */ -#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ -#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ -#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ -#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ - -/* DBG_CTL1 */ -#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ -#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ -#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ -#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ - -/* constants definitions */ -#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ -#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ -#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ - -/* define the peripheral debug hold bit position and its register index offset */ -#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) -#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) -#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) - -/* register index */ -enum dbg_reg_idx -{ - DBG_IDX_CTL0 = 0x04U, - DBG_IDX_CTL1 = 0x08U, -}; - -/* peripherals hold bit */ -typedef enum -{ - DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */ - DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */ - DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */ - DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */ - DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */ - DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */ - DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */ - DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */ - DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */ - DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */ - DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */ - DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */ -}dbg_periph_enum; - -/* function declarations */ -/* deinitialize the DBG */ -void dbg_deinit(void); -/* read DBG_ID code register */ -uint32_t dbg_id_get(void); - -/* enable low power behavior when the MCU is in debug mode */ -void dbg_low_power_enable(uint32_t dbg_low_power); -/* disable low power behavior when the MCU is in debug mode */ -void dbg_low_power_disable(uint32_t dbg_low_power); - -/* enable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_enable(dbg_periph_enum dbg_periph); -/* disable peripheral behavior when the MCU is in debug mode */ -void dbg_periph_disable(dbg_periph_enum dbg_periph); - -#endif /* GD32E23X_DBG_H */ +/*! + \file gd32e23x_dbg.h + \brief definitions for the DBG + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_DBG_H +#define GD32E23X_DBG_H + +#include "gd32e23x.h" + +/* DBG definitions */ +#define DBG DBG_BASE + +/* registers definitions */ +#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ +#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ +#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */ + +/* bits definitions */ +/* DBG_ID */ +#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ + +/* DBG_CTL0 */ +#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ +#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ +#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ +#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ +#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ +#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */ +#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */ +#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ +#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ +#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ +#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ + +/* DBG_CTL1 */ +#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */ +#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */ +#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */ +#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */ + +/* constants definitions */ +#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ +#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ +#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ + +/* define the peripheral debug hold bit position and its register index offset */ +#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) +#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) +#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) + +/* register index */ +enum dbg_reg_idx +{ + DBG_IDX_CTL0 = 0x04U, + DBG_IDX_CTL1 = 0x08U, +}; + +/* peripherals hold bit */ +typedef enum +{ + DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */ + DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */ + DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */ + DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */ + DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */ + DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */ + DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */ + DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */ + DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */ + DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */ + DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */ + DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */ +}dbg_periph_enum; + +/* function declarations */ +/* deinitialize the DBG */ +void dbg_deinit(void); +/* read DBG_ID code register */ +uint32_t dbg_id_get(void); + +/* enable low power behavior when the MCU is in debug mode */ +void dbg_low_power_enable(uint32_t dbg_low_power); +/* disable low power behavior when the MCU is in debug mode */ +void dbg_low_power_disable(uint32_t dbg_low_power); + +/* enable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_enable(dbg_periph_enum dbg_periph); +/* disable peripheral behavior when the MCU is in debug mode */ +void dbg_periph_disable(dbg_periph_enum dbg_periph); + +#endif /* GD32E23X_DBG_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dma.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dma.h index 56fa333..af2f3d5 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dma.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_dma.h @@ -1,262 +1,262 @@ -/*! - \file gd32e23x_dma.h - \brief definitions for the DMA - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_DMA_H -#define GD32E23X_DMA_H - -#include "gd32e23x.h" - -/* DMA definitions */ -#define DMA DMA_BASE /*!< DMA base address */ - -/* registers definitions */ -#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */ -#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */ -#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */ -#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */ -#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */ -#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */ -#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */ -#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */ -#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */ -#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */ -#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */ -#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */ -#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */ -#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */ -#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */ -#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */ -#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */ -#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */ -#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */ -#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */ -#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */ -#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */ - -/* bits definitions */ -/* DMA_INTF */ -#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ -#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ -#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ -#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ - -/* DMA_INTC */ -#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ -#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ -#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ -#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ - -/* DMA_CHxCTL,x=0..4 */ -#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ -#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ -#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ -#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ -#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ -#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ -#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ -#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ -#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ -#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ -#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ -#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ - -/* DMA_CHxCNT,x=0..4 */ -#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ - -/* DMA_CHxPADDR,x=0..4 */ -#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ - -/* DMA_CHxMADDR,x=0..4 */ -#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ - -/* constants definitions */ -/* DMA channel select */ -typedef enum -{ - DMA_CH0 = 0, /*!< DMA Channel0 */ - DMA_CH1, /*!< DMA Channel1 */ - DMA_CH2, /*!< DMA Channel2 */ - DMA_CH3, /*!< DMA Channel3 */ - DMA_CH4, /*!< DMA Channel4 */ -} dma_channel_enum; - -/* DMA initialize struct */ -typedef struct -{ - uint32_t periph_addr; /*!< peripheral base address */ - uint32_t periph_width; /*!< transfer data size of peripheral */ - uint32_t memory_addr; /*!< memory base address */ - uint32_t memory_width; /*!< transfer data size of memory */ - uint32_t number; /*!< channel transfer number */ - uint32_t priority; /*!< channel priority level */ - uint8_t periph_inc; /*!< peripheral increasing mode */ - uint8_t memory_inc; /*!< memory increasing mode */ - uint8_t direction; /*!< channel data transfer direction */ -} dma_parameter_struct; - -/* DMA reset value */ -#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ -#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ -#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ -#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ -#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ - DMA_INTF_HTFIF | DMA_INTF_ERRIF) - -#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ - -/* DMA_CHCTL base address */ -#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */ -#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */ -#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */ -#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */ - -/* DMA channel shift bit */ -#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ -#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ -#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ -#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ - -/* DMA_INTF register */ -/* interrupt flag bits */ -#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ -#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ - -/* flag bits */ -#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ -#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ -#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ -#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ - -/* DMA_CHxCTL register */ -/* interrupt enable bits */ -#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ -#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ -#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ - -/* transfer direction */ -#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ -#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ - -/* peripheral increasing mode */ -#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */ -#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */ - -/* memory increasing mode */ -#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */ -#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ - -/* transfer data size of peripheral */ -#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ -#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ -#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ -#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ - -/* transfer data size of memory */ -#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ -#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ -#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ -#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ - -/* channel priority level */ -#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ -#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ -#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ -#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ -#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ - -/* DMA_CHxCNT register */ -/* transfer counter */ -#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT - -/* function declarations */ -/* deinitialize DMA a channel registers */ -void dma_deinit(dma_channel_enum channelx); -/* initialize the parameters of DMA struct with the default values */ -void dma_struct_para_init(dma_parameter_struct* init_struct); -/* initialize DMA channel */ -void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); -/* enable DMA circulation mode */ -void dma_circulation_enable(dma_channel_enum channelx); -/* disable DMA circulation mode */ -void dma_circulation_disable(dma_channel_enum channelx); -/* enable memory to memory mode */ -void dma_memory_to_memory_enable(dma_channel_enum channelx); -/* disable memory to memory mode */ -void dma_memory_to_memory_disable(dma_channel_enum channelx); -/* enable DMA channel */ -void dma_channel_enable(dma_channel_enum channelx); -/* disable DMA channel */ -void dma_channel_disable(dma_channel_enum channelx); - -/* set DMA peripheral base address */ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); -/* set DMA memory base address */ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); -/* set the number of remaining data to be transferred by the DMA */ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); -/* get the number of remaining data to be transferred by the DMA */ -uint32_t dma_transfer_number_get(dma_channel_enum channelx); -/* configure priority level of DMA channel */ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority); -/* configure transfer data size of memory */ -void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); -/* configure transfer data size of peripheral */ -void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); -/* enable next address increasement algorithm of memory */ -void dma_memory_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of memory */ -void dma_memory_increase_disable(dma_channel_enum channelx); -/* enable next address increasement algorithm of peripheral */ -void dma_periph_increase_enable(dma_channel_enum channelx); -/* disable next address increasement algorithm of peripheral */ -void dma_periph_increase_disable(dma_channel_enum channelx); -/* configure the direction of data transfer on the channel */ -void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction); - -/* check DMA flag is set or not */ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* check DMA flag and interrupt enable bit is set or not */ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); -/* clear DMA a channel flag */ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); -/* enable DMA interrupt */ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); -/* disable DMA interrupt */ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); - -#endif /* GD32E23X_DMA_H */ +/*! + \file gd32e23x_dma.h + \brief definitions for the DMA + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_DMA_H +#define GD32E23X_DMA_H + +#include "gd32e23x.h" + +/* DMA definitions */ +#define DMA DMA_BASE /*!< DMA base address */ + +/* registers definitions */ +#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */ +#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */ +#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */ +#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */ +#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */ +#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */ +#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */ +#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */ +#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */ +#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */ +#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */ +#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */ +#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */ +#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */ +#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */ +#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */ +#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */ +#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */ +#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */ +#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */ +#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */ +#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */ + +/* bits definitions */ +/* DMA_INTF */ +#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ +#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ +#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ +#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ + +/* DMA_INTC */ +#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ +#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ +#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ +#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ + +/* DMA_CHxCTL,x=0..4 */ +#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ +#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ +#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ +#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ +#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ +#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ +#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ +#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ +#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ +#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ +#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ +#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ + +/* DMA_CHxCNT,x=0..4 */ +#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ + +/* DMA_CHxPADDR,x=0..4 */ +#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ + +/* DMA_CHxMADDR,x=0..4 */ +#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ + +/* constants definitions */ +/* DMA channel select */ +typedef enum +{ + DMA_CH0 = 0, /*!< DMA Channel0 */ + DMA_CH1, /*!< DMA Channel1 */ + DMA_CH2, /*!< DMA Channel2 */ + DMA_CH3, /*!< DMA Channel3 */ + DMA_CH4, /*!< DMA Channel4 */ +} dma_channel_enum; + +/* DMA initialize struct */ +typedef struct +{ + uint32_t periph_addr; /*!< peripheral base address */ + uint32_t periph_width; /*!< transfer data size of peripheral */ + uint32_t memory_addr; /*!< memory base address */ + uint32_t memory_width; /*!< transfer data size of memory */ + uint32_t number; /*!< channel transfer number */ + uint32_t priority; /*!< channel priority level */ + uint8_t periph_inc; /*!< peripheral increasing mode */ + uint8_t memory_inc; /*!< memory increasing mode */ + uint8_t direction; /*!< channel data transfer direction */ +} dma_parameter_struct; + +/* DMA reset value */ +#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ +#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ +#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ +#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ +#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ + DMA_INTF_HTFIF | DMA_INTF_ERRIF) + +#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ + +/* DMA_CHCTL base address */ +#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */ +#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */ +#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */ +#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */ + +/* DMA channel shift bit */ +#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ +#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ +#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ +#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ + +/* DMA_INTF register */ +/* interrupt flag bits */ +#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ +#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ + +/* flag bits */ +#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ +#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ +#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ +#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ + +/* DMA_CHxCTL register */ +/* interrupt enable bits */ +#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ +#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ +#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ + +/* transfer direction */ +#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ +#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ + +/* peripheral increasing mode */ +#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */ +#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */ + +/* memory increasing mode */ +#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */ +#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ + +/* transfer data size of peripheral */ +#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ +#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ +#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ +#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ + +/* transfer data size of memory */ +#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ +#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ +#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ +#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ + +/* channel priority level */ +#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ +#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ +#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ +#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ +#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ + +/* DMA_CHxCNT register */ +/* transfer counter */ +#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT + +/* function declarations */ +/* deinitialize DMA a channel registers */ +void dma_deinit(dma_channel_enum channelx); +/* initialize the parameters of DMA struct with the default values */ +void dma_struct_para_init(dma_parameter_struct* init_struct); +/* initialize DMA channel */ +void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct); +/* enable DMA circulation mode */ +void dma_circulation_enable(dma_channel_enum channelx); +/* disable DMA circulation mode */ +void dma_circulation_disable(dma_channel_enum channelx); +/* enable memory to memory mode */ +void dma_memory_to_memory_enable(dma_channel_enum channelx); +/* disable memory to memory mode */ +void dma_memory_to_memory_disable(dma_channel_enum channelx); +/* enable DMA channel */ +void dma_channel_enable(dma_channel_enum channelx); +/* disable DMA channel */ +void dma_channel_disable(dma_channel_enum channelx); + +/* set DMA peripheral base address */ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); +/* set DMA memory base address */ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); +/* set the number of remaining data to be transferred by the DMA */ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); +/* get the number of remaining data to be transferred by the DMA */ +uint32_t dma_transfer_number_get(dma_channel_enum channelx); +/* configure priority level of DMA channel */ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority); +/* configure transfer data size of memory */ +void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth); +/* configure transfer data size of peripheral */ +void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth); +/* enable next address increasement algorithm of memory */ +void dma_memory_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of memory */ +void dma_memory_increase_disable(dma_channel_enum channelx); +/* enable next address increasement algorithm of peripheral */ +void dma_periph_increase_enable(dma_channel_enum channelx); +/* disable next address increasement algorithm of peripheral */ +void dma_periph_increase_disable(dma_channel_enum channelx); +/* configure the direction of data transfer on the channel */ +void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction); + +/* check DMA flag is set or not */ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); +/* check DMA flag and interrupt enable bit is set or not */ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag); +/* clear DMA a channel flag */ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag); +/* enable DMA interrupt */ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); +/* disable DMA interrupt */ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); + +#endif /* GD32E23X_DMA_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_exti.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_exti.h index 385a631..57d2f58 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_exti.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_exti.h @@ -1,280 +1,280 @@ -/*! - \file gd32e23x_exti.h - \brief definitions for the EXTI - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_EXTI_H -#define GD32E23X_EXTI_H - -#include "gd32e23x.h" - -/* EXTI definitions */ -#define EXTI EXTI_BASE - -/* registers definitions */ -#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */ -#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */ -#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */ -#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */ -#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */ -#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */ - -/* bits definitions */ -/* EXTI_INTEN */ -#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ -#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ -#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ -#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ -#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ -#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ -#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ -#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ -#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ -#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ -#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ -#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ -#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ -#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ -#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ -#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ -#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ -#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ -#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ -#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ -#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ -#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ -#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ -#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ -#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ -#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ -#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ -#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ - -/* EXTI_EVEN */ -#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ -#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ -#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ -#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ -#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ -#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ -#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ -#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ -#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ -#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ -#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ -#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ -#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ -#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ -#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ -#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ -#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ -#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ -#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ -#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ -#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ -#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ -#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ -#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ -#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ -#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ -#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ -#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ - -/* EXTI_RTEN */ -#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ -#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ -#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ -#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ -#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ -#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ -#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ -#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ -#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ -#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ -#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ -#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ -#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ -#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ -#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ -#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ -#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ -#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ -#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ -#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ - -/* EXTI_FTEN */ -#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ -#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ -#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ -#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ -#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ -#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ -#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ -#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ -#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ -#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ -#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ -#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ -#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ -#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ -#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ -#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ -#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ -#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ -#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ -#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ - -/* EXTI_SWIEV */ -#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ -#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ -#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ -#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ -#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ -#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ -#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ -#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ -#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ -#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ -#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ -#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ -#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ -#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ -#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ -#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ -#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ -#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ -#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ -#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ - -/* EXTI_PD */ -#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ -#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ -#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ -#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ -#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ -#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ -#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ -#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ -#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ -#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ -#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ -#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ -#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ -#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ -#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ -#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ -#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ -#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ -#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ -#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */ - -/* constants definitions */ -/* EXTI line number */ -typedef enum { - EXTI_0 = BIT(0), /*!< EXTI line 0 */ - EXTI_1 = BIT(1), /*!< EXTI line 1 */ - EXTI_2 = BIT(2), /*!< EXTI line 2 */ - EXTI_3 = BIT(3), /*!< EXTI line 3 */ - EXTI_4 = BIT(4), /*!< EXTI line 4 */ - EXTI_5 = BIT(5), /*!< EXTI line 5 */ - EXTI_6 = BIT(6), /*!< EXTI line 6 */ - EXTI_7 = BIT(7), /*!< EXTI line 7 */ - EXTI_8 = BIT(8), /*!< EXTI line 8 */ - EXTI_9 = BIT(9), /*!< EXTI line 9 */ - EXTI_10 = BIT(10), /*!< EXTI line 10 */ - EXTI_11 = BIT(11), /*!< EXTI line 11 */ - EXTI_12 = BIT(12), /*!< EXTI line 12 */ - EXTI_13 = BIT(13), /*!< EXTI line 13 */ - EXTI_14 = BIT(14), /*!< EXTI line 14 */ - EXTI_15 = BIT(15), /*!< EXTI line 15 */ - EXTI_16 = BIT(16), /*!< EXTI line 16 */ - EXTI_17 = BIT(17), /*!< EXTI line 17 */ - EXTI_18 = BIT(18), /*!< EXTI line 18 */ - EXTI_19 = BIT(19), /*!< EXTI line 19 */ - EXTI_20 = BIT(20), /*!< EXTI line 20 */ - EXTI_21 = BIT(21), /*!< EXTI line 21 */ - EXTI_22 = BIT(22), /*!< EXTI line 22 */ - EXTI_23 = BIT(23), /*!< EXTI line 23 */ - EXTI_24 = BIT(24), /*!< EXTI line 24 */ - EXTI_25 = BIT(25), /*!< EXTI line 25 */ - EXTI_26 = BIT(26), /*!< EXTI line 26 */ - EXTI_27 = BIT(27) /*!< EXTI line 27 */ -} exti_line_enum; - -/* external interrupt and event */ -typedef enum { - EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ - EXTI_EVENT /*!< EXTI event mode */ -} exti_mode_enum; - -/* interrupt and event trigger mode */ -typedef enum { - EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ - EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ - EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ - EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ -} exti_trig_type_enum; - -/* function declarations */ -/* initialization, EXTI lines configuration functions */ - -/* deinitialize the EXTI */ -void exti_deinit(void); -/* initialize the EXTI line x */ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); - - -/* enable the interrupts from EXTI line x */ -void exti_interrupt_enable(exti_line_enum linex); -/* disable the interrupts from EXTI line x */ -void exti_interrupt_disable(exti_line_enum linex); -/* enable the events from EXTI line x */ -void exti_event_enable(exti_line_enum linex); -/* disable the events from EXTI line x */ -void exti_event_disable(exti_line_enum linex); - - -/* enable the software interrupt event from EXTI line x */ -void exti_software_interrupt_enable(exti_line_enum linex); -/* disable the software interrupt event from EXTI line x */ -void exti_software_interrupt_disable(exti_line_enum linex); -/* interrupt & flag functions */ -/* get EXTI line x interrupt pending flag */ -FlagStatus exti_flag_get(exti_line_enum linex); -/* clear EXTI line x interrupt pending flag */ -void exti_flag_clear(exti_line_enum linex); -/* get EXTI line x interrupt pending flag */ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex); -/* clear EXTI line x interrupt pending flag */ -void exti_interrupt_flag_clear(exti_line_enum linex); - -#endif /* GD32E23X_EXTI_H */ +/*! + \file gd32e23x_exti.h + \brief definitions for the EXTI + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_EXTI_H +#define GD32E23X_EXTI_H + +#include "gd32e23x.h" + +/* EXTI definitions */ +#define EXTI EXTI_BASE + +/* registers definitions */ +#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */ +#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */ +#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */ +#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling edge trigger enable register */ +#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */ +#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */ + +/* bits definitions */ +/* EXTI_INTEN */ +#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */ +#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */ +#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */ +#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */ +#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */ +#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */ +#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */ +#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */ +#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */ +#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */ +#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */ +#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */ +#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */ +#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */ +#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */ +#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */ +#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */ +#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */ +#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */ +#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */ +#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */ +#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */ +#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */ +#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */ +#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */ +#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */ +#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */ +#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */ + +/* EXTI_EVEN */ +#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */ +#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */ +#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */ +#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */ +#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */ +#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */ +#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */ +#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */ +#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */ +#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */ +#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */ +#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */ +#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */ +#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */ +#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */ +#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */ +#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */ +#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */ +#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */ +#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */ +#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */ +#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */ +#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */ +#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */ +#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */ +#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */ +#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */ +#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */ + +/* EXTI_RTEN */ +#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */ +#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */ +#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */ +#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */ +#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */ +#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */ +#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */ +#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */ +#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */ +#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */ +#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */ +#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */ +#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */ +#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */ +#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */ +#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */ +#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */ +#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */ +#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */ +#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */ + +/* EXTI_FTEN */ +#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */ +#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */ +#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */ +#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */ +#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */ +#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */ +#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */ +#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */ +#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */ +#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */ +#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */ +#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */ +#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */ +#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */ +#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */ +#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */ +#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */ +#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */ +#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */ +#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */ + +/* EXTI_SWIEV */ +#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */ +#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */ +#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */ +#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */ +#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */ +#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */ +#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */ +#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */ +#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */ +#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */ +#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */ +#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */ +#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */ +#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */ +#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */ +#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */ +#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */ +#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */ +#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */ +#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */ + +/* EXTI_PD */ +#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */ +#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */ +#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */ +#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */ +#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */ +#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */ +#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */ +#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */ +#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */ +#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */ +#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */ +#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */ +#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */ +#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */ +#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */ +#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */ +#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */ +#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */ +#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */ +#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */ + +/* constants definitions */ +/* EXTI line number */ +typedef enum { + EXTI_0 = BIT(0), /*!< EXTI line 0 */ + EXTI_1 = BIT(1), /*!< EXTI line 1 */ + EXTI_2 = BIT(2), /*!< EXTI line 2 */ + EXTI_3 = BIT(3), /*!< EXTI line 3 */ + EXTI_4 = BIT(4), /*!< EXTI line 4 */ + EXTI_5 = BIT(5), /*!< EXTI line 5 */ + EXTI_6 = BIT(6), /*!< EXTI line 6 */ + EXTI_7 = BIT(7), /*!< EXTI line 7 */ + EXTI_8 = BIT(8), /*!< EXTI line 8 */ + EXTI_9 = BIT(9), /*!< EXTI line 9 */ + EXTI_10 = BIT(10), /*!< EXTI line 10 */ + EXTI_11 = BIT(11), /*!< EXTI line 11 */ + EXTI_12 = BIT(12), /*!< EXTI line 12 */ + EXTI_13 = BIT(13), /*!< EXTI line 13 */ + EXTI_14 = BIT(14), /*!< EXTI line 14 */ + EXTI_15 = BIT(15), /*!< EXTI line 15 */ + EXTI_16 = BIT(16), /*!< EXTI line 16 */ + EXTI_17 = BIT(17), /*!< EXTI line 17 */ + EXTI_18 = BIT(18), /*!< EXTI line 18 */ + EXTI_19 = BIT(19), /*!< EXTI line 19 */ + EXTI_20 = BIT(20), /*!< EXTI line 20 */ + EXTI_21 = BIT(21), /*!< EXTI line 21 */ + EXTI_22 = BIT(22), /*!< EXTI line 22 */ + EXTI_23 = BIT(23), /*!< EXTI line 23 */ + EXTI_24 = BIT(24), /*!< EXTI line 24 */ + EXTI_25 = BIT(25), /*!< EXTI line 25 */ + EXTI_26 = BIT(26), /*!< EXTI line 26 */ + EXTI_27 = BIT(27) /*!< EXTI line 27 */ +} exti_line_enum; + +/* external interrupt and event */ +typedef enum { + EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */ + EXTI_EVENT /*!< EXTI event mode */ +} exti_mode_enum; + +/* interrupt and event trigger mode */ +typedef enum { + EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */ + EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */ + EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */ + EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */ +} exti_trig_type_enum; + +/* function declarations */ +/* initialization, EXTI lines configuration functions */ + +/* deinitialize the EXTI */ +void exti_deinit(void); +/* initialize the EXTI line x */ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type); + + +/* enable the interrupts from EXTI line x */ +void exti_interrupt_enable(exti_line_enum linex); +/* disable the interrupts from EXTI line x */ +void exti_interrupt_disable(exti_line_enum linex); +/* enable the events from EXTI line x */ +void exti_event_enable(exti_line_enum linex); +/* disable the events from EXTI line x */ +void exti_event_disable(exti_line_enum linex); + + +/* enable the software interrupt event from EXTI line x */ +void exti_software_interrupt_enable(exti_line_enum linex); +/* disable the software interrupt event from EXTI line x */ +void exti_software_interrupt_disable(exti_line_enum linex); +/* interrupt & flag functions */ +/* get EXTI line x interrupt pending flag */ +FlagStatus exti_flag_get(exti_line_enum linex); +/* clear EXTI line x interrupt pending flag */ +void exti_flag_clear(exti_line_enum linex); +/* get EXTI line x interrupt pending flag */ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex); +/* clear EXTI line x interrupt pending flag */ +void exti_interrupt_flag_clear(exti_line_enum linex); + +#endif /* GD32E23X_EXTI_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fmc.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fmc.h index cc6863b..32db4cf 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fmc.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fmc.h @@ -1,270 +1,270 @@ -/*! - \file gd32e23x_fmc.h - \brief definitions for the FMC - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_FMC_H -#define GD32E23X_FMC_H - -#include "gd32e23x.h" - -/* FMC and option byte definition */ -#define FMC FMC_BASE /*!< FMC register base address */ -#define OB OB_BASE /*!< option byte base address */ - -/* registers definitions */ -#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ -#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ -#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ -#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ -#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ -#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ -#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ -#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */ -#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ - -#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */ -#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/ -#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */ - -/* bits definitions */ -/* FMC_WS */ -#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ -#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ -#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ - -/* FMC_KEY */ -#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ - -/* FMC_OBKEY */ -#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ - -/* FMC_STAT */ -#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ -#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ -#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */ -#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ -#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ - -/* FMC_CTL */ -#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ -#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ -#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ -#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ -#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ -#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ -#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ -#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ -#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ -#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ -#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ - -/* FMC_ADDR */ -#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ - -/* FMC_OBSTAT */ -#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ -#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ -#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ -#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ -#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ - -/* FMC_WP */ -#define FMC_WP_WP BITS(0,31) /*!< store WP[15:0] of option byte block after system reset */ - -/* FMC_PID */ -#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ - -/* constants definitions */ -/* fmc state */ -typedef enum -{ - FMC_READY, /*!< the operation has been completed */ - FMC_BUSY, /*!< the operation is in progress */ - FMC_PGERR, /*!< program error */ - FMC_PGAERR, /*!< program alignment error */ - FMC_WPERR, /*!< erase/program protection error */ - FMC_TOERR, /*!< timeout error */ - FMC_OB_HSPC /*!< option byte security protection code high */ -}fmc_state_enum; - -/* unlock key */ -#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ -#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ - -/* wait state counter value */ -#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ -#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ -#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ - -/* read protect configure */ -#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */ -#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */ -#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */ - -#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */ -#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */ - -/* option byte address */ -#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */ -#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */ -#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */ - -/* option byte write protection */ -#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ -#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ - -/* option byte software/hardware free watchdog timer */ -#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ -#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */ - -/* option byte reset or not entering deep sleep mode */ -#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ -#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */ - -/* option byte reset or not entering standby mode */ -#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ -#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */ - -/* option byte OB_BOOT1_n set */ -#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ -#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */ - -/* option byte VDDA monitor enable/disable */ -#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ -#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */ - -/* option byte SRAM parity enable/disable */ -#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ -#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */ - -/* option byte security protection level in FMC_OBSTAT register */ -#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */ -#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x02U) /*!< low security protection */ -#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x06U) /*!< high security protection */ - -/* option byte user mask */ -#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */ - -/* option byte data address */ -#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */ -#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */ - -/* FMC flags */ -#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ -#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ -#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ -#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ -#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ - -/* FMC interrupt flags */ -#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ -#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ -#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ -#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ - -/* FMC interrupt enable */ -#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ -#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ - -/* FMC time out */ -#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ - -/* function declarations */ -/* FMC main memory programming functions */ -/* unlock the main FMC operation */ -void fmc_unlock(void); -/* lock the main FMC operation */ -void fmc_lock(void); -/* set the wait state counter value */ -void fmc_wscnt_set(uint8_t wscnt); - -/* pre-fetch enable */ -void fmc_prefetch_enable(void); -/* pre-fetch disable */ -void fmc_prefetch_disable(void); -/* FMC erase page */ -fmc_state_enum fmc_page_erase(uint32_t page_address); -/* FMC erase whole chip */ -fmc_state_enum fmc_mass_erase(void); -/* FMC program a double word at the corresponding address */ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data); -/* FMC program a word at the corresponding address */ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); - -/* FMC option bytes programming functions */ -/* unlock the option byte operation */ -void ob_unlock(void); -/* lock the option byte operation */ -void ob_lock(void); -/* reload the option byte and generate a system reset */ -void ob_reset(void); -/* get option byte value */ -uint32_t option_byte_value_get(uint32_t addr); -/* erase option byte */ -fmc_state_enum ob_erase(void); -/* enable option byte write protection (OB_WP) */ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); -/* configure read out protect */ -fmc_state_enum ob_security_protection_config(uint16_t ob_spc); -/* write the FMC option byte user */ -fmc_state_enum ob_user_write(uint8_t ob_user); -/* write the FMC option byte data */ -fmc_state_enum ob_data_program(uint16_t data); -/* get the FMC option byte OB_USER */ -uint8_t ob_user_get(void); -/* get the FMC option byte OB_DATA */ -uint16_t ob_data_get(void); -/* get the FMC option byte write protection */ -uint32_t ob_write_protection_get(void); -/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ -uint32_t ob_obstat_plevel_get(void); - -/* FMC interrupts and flags management functions */ -/* enable FMC interrupt */ -void fmc_interrupt_enable(uint32_t interrupt); -/* disable FMC interrupt */ -void fmc_interrupt_disable(uint32_t interrupt); -/* get flag set or reset */ -FlagStatus fmc_flag_get(uint32_t flag); -/* clear the FMC pending flag */ -void fmc_flag_clear(uint32_t flag); -/* get intrrupt flag set or reset */ -FlagStatus fmc_interrupt_flag_get(uint32_t int_flag); -/* clear the FMC interrupt pending flag by writing 1 */ -void fmc_interrupt_flag_clear(uint32_t int_flag); -/* return the FMC state */ -fmc_state_enum fmc_state_get(void); -/* check FMC ready or not */ -fmc_state_enum fmc_ready_wait(uint32_t timeout); - -#endif /* GD32E23X_FMC_H */ +/*! + \file gd32e23x_fmc.h + \brief definitions for the FMC + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_FMC_H +#define GD32E23X_FMC_H + +#include "gd32e23x.h" + +/* FMC and option byte definition */ +#define FMC FMC_BASE /*!< FMC register base address */ +#define OB OB_BASE /*!< option byte base address */ + +/* registers definitions */ +#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ +#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ +#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ +#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ +#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ +#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ +#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ +#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */ +#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ + +#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */ +#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/ +#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */ + +/* bits definitions */ +/* FMC_WS */ +#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ +#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */ +#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */ + +/* FMC_KEY */ +#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */ + +/* FMC_OBKEY */ +#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ + +/* FMC_STAT */ +#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ +#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ +#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */ +#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */ +#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ + +/* FMC_CTL */ +#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ +#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */ +#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */ +#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ +#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ +#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ +#define FMC_CTL_LK BIT(7) /*!< flash lock bit */ +#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ +#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ +#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ +#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */ + +/* FMC_ADDR */ +#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */ + +/* FMC_OBSTAT */ +#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */ +#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */ +#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */ +#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */ +#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */ + +/* FMC_WP */ +#define FMC_WP_WP BITS(0,31) /*!< store WP[15:0] of option byte block after system reset */ + +/* FMC_PID */ +#define FMC_PID_PID BITS(0,31) /*!< product ID bits */ + +/* constants definitions */ +/* fmc state */ +typedef enum +{ + FMC_READY, /*!< the operation has been completed */ + FMC_BUSY, /*!< the operation is in progress */ + FMC_PGERR, /*!< program error */ + FMC_PGAERR, /*!< program alignment error */ + FMC_WPERR, /*!< erase/program protection error */ + FMC_TOERR, /*!< timeout error */ + FMC_OB_HSPC /*!< option byte security protection code high */ +}fmc_state_enum; + +/* unlock key */ +#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ +#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ + +/* wait state counter value */ +#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */ +#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */ +#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */ + +/* read protect configure */ +#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */ +#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */ +#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */ + +#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */ +#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */ + +/* option byte address */ +#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */ +#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */ +#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */ + +/* option byte write protection */ +#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */ +#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */ + +/* option byte software/hardware free watchdog timer */ +#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */ +#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */ + +/* option byte reset or not entering deep sleep mode */ +#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */ +#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */ + +/* option byte reset or not entering standby mode */ +#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */ +#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */ + +/* option byte OB_BOOT1_n set */ +#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */ +#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */ + +/* option byte VDDA monitor enable/disable */ +#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */ +#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */ + +/* option byte SRAM parity enable/disable */ +#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */ +#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */ + +/* option byte security protection level in FMC_OBSTAT register */ +#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */ +#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x02U) /*!< low security protection */ +#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x06U) /*!< high security protection */ + +/* option byte user mask */ +#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */ + +/* option byte data address */ +#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */ +#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */ + +/* FMC flags */ +#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */ +#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ +#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ +#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ +#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ + +/* FMC interrupt flags */ +#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */ +#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */ +#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */ +#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */ + +/* FMC interrupt enable */ +#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */ +#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */ + +/* FMC time out */ +#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */ + +/* function declarations */ +/* FMC main memory programming functions */ +/* unlock the main FMC operation */ +void fmc_unlock(void); +/* lock the main FMC operation */ +void fmc_lock(void); +/* set the wait state counter value */ +void fmc_wscnt_set(uint8_t wscnt); + +/* pre-fetch enable */ +void fmc_prefetch_enable(void); +/* pre-fetch disable */ +void fmc_prefetch_disable(void); +/* FMC erase page */ +fmc_state_enum fmc_page_erase(uint32_t page_address); +/* FMC erase whole chip */ +fmc_state_enum fmc_mass_erase(void); +/* FMC program a double word at the corresponding address */ +fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data); +/* FMC program a word at the corresponding address */ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); + +/* FMC option bytes programming functions */ +/* unlock the option byte operation */ +void ob_unlock(void); +/* lock the option byte operation */ +void ob_lock(void); +/* reload the option byte and generate a system reset */ +void ob_reset(void); +/* get option byte value */ +uint32_t option_byte_value_get(uint32_t addr); +/* erase option byte */ +fmc_state_enum ob_erase(void); +/* enable option byte write protection (OB_WP) */ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); +/* configure read out protect */ +fmc_state_enum ob_security_protection_config(uint16_t ob_spc); +/* write the FMC option byte user */ +fmc_state_enum ob_user_write(uint8_t ob_user); +/* write the FMC option byte data */ +fmc_state_enum ob_data_program(uint16_t data); +/* get the FMC option byte OB_USER */ +uint8_t ob_user_get(void); +/* get the FMC option byte OB_DATA */ +uint16_t ob_data_get(void); +/* get the FMC option byte write protection */ +uint32_t ob_write_protection_get(void); +/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */ +uint32_t ob_obstat_plevel_get(void); + +/* FMC interrupts and flags management functions */ +/* enable FMC interrupt */ +void fmc_interrupt_enable(uint32_t interrupt); +/* disable FMC interrupt */ +void fmc_interrupt_disable(uint32_t interrupt); +/* get flag set or reset */ +FlagStatus fmc_flag_get(uint32_t flag); +/* clear the FMC pending flag */ +void fmc_flag_clear(uint32_t flag); +/* get intrrupt flag set or reset */ +FlagStatus fmc_interrupt_flag_get(uint32_t int_flag); +/* clear the FMC interrupt pending flag by writing 1 */ +void fmc_interrupt_flag_clear(uint32_t int_flag); +/* return the FMC state */ +fmc_state_enum fmc_state_get(void); +/* check FMC ready or not */ +fmc_state_enum fmc_ready_wait(uint32_t timeout); + +#endif /* GD32E23X_FMC_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fwdgt.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fwdgt.h index 304487c..51cd6ac 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fwdgt.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_fwdgt.h @@ -1,122 +1,122 @@ -/*! - \file gd32e23x_fwdgt.h - \brief definitions for the FWDGT - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_FWDGT_H -#define GD32E23X_FWDGT_H - -#include "gd32e23x.h" - -/* FWDGT definitions */ -#define FWDGT FWDGT_BASE - -/* registers definitions */ -#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ -#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ -#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ -#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ -#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */ - -/* bits definitions */ -/* FWDGT_CTL */ -#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ - -/* FWDGT_PSC */ -#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ - -/* FWDGT_RLD */ -#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ - -/* FWDGT_STAT */ -#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ -#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ -#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ - -/* FWDGT_WND */ -#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ - -/* constants definitions */ -/* FWDGT_PSC register value */ -#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) -#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ -#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ -#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ -#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ -#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ -#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ -#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ - -/* control value */ -#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */ -#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */ -#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ -#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ - -/* FWDGT timeout value */ -#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ -#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ -#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ - -/* FWDGT flag definitions */ -#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ -#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ -#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ - -/* write value to FWDGT_RLD_RLD bit field */ -#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) -/* write value to FWDGT_WND_WND bit field */ -#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) - -/* function declarations */ -/* enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND */ -void fwdgt_write_enable(void); -/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ -void fwdgt_write_disable(void); -/* start the free watchdog timer counter */ -void fwdgt_enable(void); - -/* configure the free watchdog timer counter prescaler value */ -ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); -/* configure the free watchdog timer counter reload value */ -ErrStatus fwdgt_reload_value_config(uint16_t reload_value); -/* configure the free watchdog timer counter window value */ -ErrStatus fwdgt_window_value_config(uint16_t window_value); -/* reload the counter of FWDGT */ -void fwdgt_counter_reload(void); -/* configure counter reload value, and prescaler divider value */ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); - -/* get flag state of FWDGT */ -FlagStatus fwdgt_flag_get(uint16_t flag); - -#endif /* GD32E23X_FWDGT_H */ +/*! + \file gd32e23x_fwdgt.h + \brief definitions for the FWDGT + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_FWDGT_H +#define GD32E23X_FWDGT_H + +#include "gd32e23x.h" + +/* FWDGT definitions */ +#define FWDGT FWDGT_BASE + +/* registers definitions */ +#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */ +#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */ +#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */ +#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */ +#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */ + +/* bits definitions */ +/* FWDGT_CTL */ +#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */ + +/* FWDGT_PSC */ +#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */ + +/* FWDGT_RLD */ +#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */ + +/* FWDGT_STAT */ +#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */ +#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */ +#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */ + +/* FWDGT_WND */ +#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */ + +/* constants definitions */ +/* FWDGT_PSC register value */ +#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U)) +#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */ +#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */ +#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */ +#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */ +#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */ +#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */ +#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */ + +/* control value */ +#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */ +#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */ +#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */ +#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */ + +/* FWDGT timeout value */ +#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */ +#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */ +#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */ + +/* FWDGT flag definitions */ +#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */ +#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */ +#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */ + +/* write value to FWDGT_RLD_RLD bit field */ +#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) +/* write value to FWDGT_WND_WND bit field */ +#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U)) + +/* function declarations */ +/* enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_enable(void); +/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */ +void fwdgt_write_disable(void); +/* start the free watchdog timer counter */ +void fwdgt_enable(void); + +/* configure the free watchdog timer counter prescaler value */ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value); +/* configure the free watchdog timer counter reload value */ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value); +/* configure the free watchdog timer counter window value */ +ErrStatus fwdgt_window_value_config(uint16_t window_value); +/* reload the counter of FWDGT */ +void fwdgt_counter_reload(void); +/* configure counter reload value, and prescaler divider value */ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div); + +/* get flag state of FWDGT */ +FlagStatus fwdgt_flag_get(uint16_t flag); + +#endif /* GD32E23X_FWDGT_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_gpio.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_gpio.h index f22bf14..deb0a80 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_gpio.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_gpio.h @@ -1,386 +1,386 @@ -/*! - \file gd32e23x_gpio.h - \brief definitions for the GPIO - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_GPIO_H -#define GD32E23X_GPIO_H - -#include "gd32e23x.h" - -/* GPIOx(x=A,B,C,F) definitions */ -#define GPIOA (GPIO_BASE + 0x00000000U) -#define GPIOB (GPIO_BASE + 0x00000400U) -#define GPIOC (GPIO_BASE + 0x00000800U) -#define GPIOF (GPIO_BASE + 0x00001400U) - -/* registers definitions */ -#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ -#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ -#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ -#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ -#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ -#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ -#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ -#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ -#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ -#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ -#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ -#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ - -/* bits definitions */ -/* GPIO_CTL */ -#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ -#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ -#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ -#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ -#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ -#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ -#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ -#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ -#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ -#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ -#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ -#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ -#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ -#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ -#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ -#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ - -/* GPIO_OMODE */ -#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ -#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ -#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ -#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ -#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ -#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ -#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ -#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ -#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ -#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ -#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ -#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ -#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ -#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ -#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ -#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ - -/* GPIO_OSPD */ -#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ -#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ -#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ -#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ -#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ -#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ -#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ -#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ -#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ -#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ -#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ -#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ -#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ -#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ -#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ -#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ - -/* GPIO_PUD */ -#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ -#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ -#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ -#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ -#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ -#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ -#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ -#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ -#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ -#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ -#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ -#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ -#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ -#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ -#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ -#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ - -/* GPIO_ISTAT */ -#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ -#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ -#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ -#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ -#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ -#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ -#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ -#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ -#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ -#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ -#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ -#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ -#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ -#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ -#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ -#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ - -/* GPIO_OCTL */ -#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ -#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ -#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ -#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ -#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ -#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ -#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ -#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ -#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ -#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ -#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ -#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ -#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ -#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ -#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ -#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ - -/* GPIO_BOP */ -#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ -#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ -#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ -#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ -#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ -#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ -#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ -#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ -#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ -#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ -#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ -#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ -#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ -#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ -#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ -#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ -#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ -#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ -#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ -#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ -#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ -#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ -#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ -#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ -#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ -#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ -#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ -#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ -#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ -#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ -#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ -#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ - -/* GPIO_LOCK */ -#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ -#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ -#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ -#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ -#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ -#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ -#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ -#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ -#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ -#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ -#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ -#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ -#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ -#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ -#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ -#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ -#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ - -/* GPIO_AFSEL0 */ -#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ -#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ -#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ -#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ -#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ -#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ -#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ -#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ - -/* GPIO_AFSEL1 */ -#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ -#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ -#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ -#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ -#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ -#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ -#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ -#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ - -/* GPIO_BC */ -#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ -#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ -#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ -#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ -#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ -#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ -#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ -#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ -#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ -#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ -#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ -#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ -#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ -#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ -#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ -#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ - -/* GPIO_TG */ -#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ -#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ -#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ -#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ -#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ -#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ -#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ -#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ -#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ -#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ -#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ -#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ -#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ -#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ -#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ -#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ - -/* constants definitions */ -typedef FlagStatus bit_status; - -/* output mode definitions */ -#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ -#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ -#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ -#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ - -/* pull-up/pull-down definitions */ -#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ -#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ -#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ - -/* GPIO pin definitions */ -#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ -#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ -#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ -#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ -#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ -#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ -#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ -#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ -#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ -#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ -#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ -#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ -#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ -#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ -#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ -#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ -#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ - -/* GPIO mode configuration values */ -#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) -#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) - -/* GPIO pull-up/pull-down values */ -#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) -#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output speed values */ -#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) -#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) - -/* GPIO output type */ -#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ -#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ - -/* GPIO output max speed value */ -#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ -#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ -#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ - -/* GPIO alternate function values */ -#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) -#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) - -/* GPIO alternate function */ -#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ -#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ -#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ -#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ -#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ -#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ -#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ -#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ - -/* function declarations */ -/* reset GPIO port */ -void gpio_deinit(uint32_t gpio_periph); -/* set GPIO mode */ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); -/* set GPIO output type and speed */ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); - -/* set GPIO pin bit */ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); -/* reset GPIO pin bit */ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); -/* write data to the specified GPIO pin */ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); -/* write data to the specified GPIO port */ -void gpio_port_write(uint32_t gpio_periph, uint16_t data); - -/* get GPIO pin input status */ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port input status */ -uint16_t gpio_input_port_get(uint32_t gpio_periph); -/* get GPIO pin output status */ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); -/* get GPIO port output status */ -uint16_t gpio_output_port_get(uint32_t gpio_periph); - -/* set GPIO alternate function */ -void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin); -/* lock GPIO pin bit */ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); - -/* toggle GPIO pin status */ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); -/* toggle GPIO port status */ -void gpio_port_toggle(uint32_t gpio_periph); - -#endif /* GD32E23X_GPIO_H */ +/*! + \file gd32e23x_gpio.h + \brief definitions for the GPIO + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_GPIO_H +#define GD32E23X_GPIO_H + +#include "gd32e23x.h" + +/* GPIOx(x=A,B,C,F) definitions */ +#define GPIOA (GPIO_BASE + 0x00000000U) +#define GPIOB (GPIO_BASE + 0x00000400U) +#define GPIOC (GPIO_BASE + 0x00000800U) +#define GPIOF (GPIO_BASE + 0x00001400U) + +/* registers definitions */ +#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */ +#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */ +#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */ +#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */ +#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */ +#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */ +#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */ +#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */ +#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */ +#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */ +#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */ +#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */ + +/* bits definitions */ +/* GPIO_CTL */ +#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */ +#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */ +#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */ +#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */ +#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */ +#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */ +#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */ +#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */ +#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */ +#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */ +#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */ +#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */ +#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */ +#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */ +#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */ +#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ + +/* GPIO_OMODE */ +#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */ +#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */ +#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */ +#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */ +#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */ +#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */ +#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */ +#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */ +#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */ +#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */ +#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */ +#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */ +#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */ +#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */ +#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */ +#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */ + +/* GPIO_OSPD */ +#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */ +#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */ +#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */ +#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */ +#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */ +#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */ +#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */ +#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */ +#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */ +#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */ +#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */ +#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */ +#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */ +#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */ +#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */ +#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */ + +/* GPIO_PUD */ +#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */ +#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */ +#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */ +#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */ +#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */ +#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */ +#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */ +#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */ +#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */ +#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */ +#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */ +#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */ +#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */ +#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */ +#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */ +#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */ + +/* GPIO_ISTAT */ +#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ +#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ +#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ +#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ +#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ +#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ +#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ +#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ +#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ +#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ +#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ +#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ +#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ +#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ +#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ +#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ + +/* GPIO_OCTL */ +#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ +#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ +#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ +#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ +#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ +#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ +#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ +#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ +#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ +#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ +#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ +#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ +#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ +#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ +#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ +#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ + +/* GPIO_BOP */ +#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ +#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ +#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ +#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ +#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ +#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ +#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ +#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ +#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ +#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ +#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ +#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ +#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ +#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ +#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ +#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ +#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ +#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ +#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ +#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ +#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ +#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ +#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ +#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ +#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ +#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ +#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ +#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ +#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ +#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ +#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ +#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ + +/* GPIO_LOCK */ +#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ +#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ +#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ +#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ +#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ +#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ +#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ +#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ +#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ +#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ +#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ +#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ +#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ +#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ +#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ +#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ +#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ + +/* GPIO_AFSEL0 */ +#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */ +#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */ +#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */ +#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */ +#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */ +#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */ +#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */ +#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */ + +/* GPIO_AFSEL1 */ +#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */ +#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */ +#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */ +#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */ +#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */ +#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */ +#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */ +#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */ + +/* GPIO_BC */ +#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ +#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ +#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ +#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ +#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ +#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ +#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ +#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ +#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ +#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ +#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ +#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ +#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ +#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ +#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ +#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ + +/* GPIO_TG */ +#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */ +#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */ +#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */ +#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */ +#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */ +#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */ +#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */ +#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */ +#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */ +#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */ +#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */ +#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */ +#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */ +#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */ +#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */ +#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */ + +/* constants definitions */ +typedef FlagStatus bit_status; + +/* output mode definitions */ +#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */ +#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */ +#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */ +#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */ + +/* pull-up/pull-down definitions */ +#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */ +#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */ +#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */ + +/* GPIO pin definitions */ +#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ +#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ +#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ +#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ +#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ +#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ +#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ +#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ +#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ +#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ +#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ +#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ +#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ +#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ +#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ +#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ +#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ + +/* GPIO mode configuration values */ +#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n)))) +#define GPIO_MODE_MASK(n) (0x3U << (2U * (n))) + +/* GPIO pull-up/pull-down values */ +#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n)))) +#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output speed values */ +#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n)))) +#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n))) + +/* GPIO output type */ +#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */ +#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */ + +/* GPIO output max speed value */ +#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */ +#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */ +#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */ + +/* GPIO alternate function values */ +#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n)))) +#define GPIO_AFR_MASK(n) (0xFU << (4U * (n))) + +/* GPIO alternate function */ +#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */ +#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */ +#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */ +#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */ +#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */ +#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */ +#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */ +#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */ + +/* function declarations */ +/* reset GPIO port */ +void gpio_deinit(uint32_t gpio_periph); +/* set GPIO mode */ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin); +/* set GPIO output type and speed */ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin); + +/* set GPIO pin bit */ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); +/* reset GPIO pin bit */ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); +/* write data to the specified GPIO pin */ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); +/* write data to the specified GPIO port */ +void gpio_port_write(uint32_t gpio_periph, uint16_t data); + +/* get GPIO pin input status */ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port input status */ +uint16_t gpio_input_port_get(uint32_t gpio_periph); +/* get GPIO pin output status */ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); +/* get GPIO port output status */ +uint16_t gpio_output_port_get(uint32_t gpio_periph); + +/* set GPIO alternate function */ +void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin); +/* lock GPIO pin bit */ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); + +/* toggle GPIO pin status */ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin); +/* toggle GPIO port status */ +void gpio_port_toggle(uint32_t gpio_periph); + +#endif /* GD32E23X_GPIO_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_i2c.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_i2c.h index ffc45b8..5bcf9b0 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_i2c.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_i2c.h @@ -1,388 +1,388 @@ -/*! - \file gd32e23x_i2c.h - \brief definitions for the I2C - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_I2C_H -#define GD32E23X_I2C_H - -#include "gd32e23x.h" - -/* I2Cx(x=0,1) definitions */ -#define I2C0 I2C_BASE /*!< I2C0 base address */ -#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ - -/* registers definitions */ -#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ -#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ -#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ -#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ -#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ -#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ -#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ -#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ -#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ -#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ -#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast mode plus configure register */ - -/* bits definitions */ -/* I2Cx_CTL0 */ -#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ -#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ -#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ -#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ -#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ -#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ -#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ -#define I2C_CTL0_START BIT(8) /*!< start generation */ -#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ -#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ -#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ -#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ -#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ -#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ - -/* I2Cx_CTL1 */ -#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ -#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ -#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ -#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ -#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ -#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ -#define I2C_CTL1_RBNECM BIT(15) /*!< RBNE clear mode */ - -/* I2Cx_SADDR0 */ -#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ -#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ -#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ - -/* I2Cx_SADDR1 */ -#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ -#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ - -/* I2Cx_DATA */ -#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ - -/* I2Cx_STAT0 */ -#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ -#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ -#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ -#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ -#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ -#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ -#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ -#define I2C_STAT0_BERR BIT(8) /*!< bus error */ -#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ -#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ -#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ -#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ -#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ -#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ - -/* I2Cx_STAT1 */ -#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ -#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ -#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ -#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ -#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ -#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ -#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ -#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ - -/* I2Cx_CKCFG */ -#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ -#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ -#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ - -/* I2Cx_RT */ -#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ - -/* I2Cx_SAMCS */ -#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ -#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ -#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ -#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ -#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ -#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ -#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ -#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ -#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ -#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ -#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ -#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ - -/* I2Cx_FMPCFG */ -#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ - -/* constants definitions */ -/* define the I2C bit position and its register index offset */ -#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) -#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) -#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) -#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) - -/* register offset */ -#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ -#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ -#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ -#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ - -/* I2C flags */ -typedef enum { - /* flags in STAT0 register */ - I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ - I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ - I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ - I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ - I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ - I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ - I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ - I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ - I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ - I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ - I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ - I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ - I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ - I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ - /* flags in STAT1 register */ - I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ - I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ - I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ - I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ - I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ - I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ - I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ - /* flags in SAMCS register */ - I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ - I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ - I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ - I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ -} i2c_flag_enum; - -/* I2C interrupt flags */ -typedef enum { - /* interrupt flags in CTL1 register */ - I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ - I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ - I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ - I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ - I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ - I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ - I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ - I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ - I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ - I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ - I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ - I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ - I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ - I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ - /* interrupt flags in SAMCS register */ - I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ - I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ - I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ - I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ -} i2c_interrupt_flag_enum; - -/* I2C interrupt */ -typedef enum { - /* interrupt in CTL1 register */ - I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ - I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ - I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ - /* interrupt in SAMCS register */ - I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ - I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ - I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ - I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ -} i2c_interrupt_enum; - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ -#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ - -/* SMBus/I2C mode switch and SMBus type selection */ -#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ -#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ - -/* I2C transfer direction */ -#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ -#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ - -/* whether or not to send an ACK */ -#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ -#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ - -/* I2C POAP position*/ -#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ -#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ - -/* whether or not to stretch SCL low */ -#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ -#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ - -/* whether or not to response to a general call */ -#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ -#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ - -/* software reset I2C */ -#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ -#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ - -/* I2C DMA mode configure */ -/* DMA mode switch */ -#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ -#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ - -/* flag indicating DMA last transfer */ -#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ -#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ - -/* RBNE clear mode */ -#define I2C_RBNE_CLEAR_BTC_0 ((uint32_t)0x00000000U) /*!< RBNE can be cleared when I2C_DATA is read and BTC is cleared */ -#define I2C_RBNE_CLEAR I2C_CTL1_RBNECM /*!< RBNE can be cleared when I2C_DATA is read */ - -/* I2C PEC configure */ -/* PEC enable */ -#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ -#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ - -/* PEC transfer */ -#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ -#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ - -/* I2C SMBus configure */ -/* issue or not alert through SMBA pin */ -#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ -#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ - -/* ARP protocol in SMBus switch */ -#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ -#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ - -/* transmit I2C data */ -#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) - -/* receive I2C data */ -#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) - -/* I2C duty cycle in fast mode or fast mode plus */ -#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode or fast mode plus */ -#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode or fast mode plus */ - -/* address mode for the I2C slave */ -#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ -#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ - -/* function declarations */ -/* initialization functions */ -/* reset I2C */ -void i2c_deinit(uint32_t i2c_periph); -/* configure I2C clock */ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); -/* configure I2C address */ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); - -/* application function declarations */ -/* select SMBus type */ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); -/* whether or not to send an ACK */ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); -/* configure I2C POAP position */ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); -/* master sends slave address */ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); -/* enable dual-address mode */ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); -/* disable dual-address mode */ -void i2c_dualaddr_disable(uint32_t i2c_periph); -/* enable I2C */ -void i2c_enable(uint32_t i2c_periph); -/* disable I2C */ -void i2c_disable(uint32_t i2c_periph); -/* generate a START condition on I2C bus */ -void i2c_start_on_bus(uint32_t i2c_periph); -/* generate a STOP condition on I2C bus */ -void i2c_stop_on_bus(uint32_t i2c_periph); -/* I2C transmit data function */ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); -/* I2C receive data function */ -uint8_t i2c_data_receive(uint32_t i2c_periph); -/* configure I2C DMA mode */ -void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); -/* configure whether next DMA EOT is DMA last transfer or not */ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); -/* configure RBNE clear mode */ -void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode); -/* whether to stretch SCL low when data is not ready in slave mode */ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); -/* whether or not to response to a general call */ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); -/* configure software reset of I2C */ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); -/* configure I2C PEC calculation */ -void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); -/* configure whether to transfer PEC value */ -void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); -/* get packet error checking value */ -uint8_t i2c_pec_value_get(uint32_t i2c_periph); -/* configure I2C alert through SMBA pin */ -void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); -/* configure I2C ARP protocol in SMBus */ -void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); -/* enable SAM_V interface */ -void i2c_sam_enable(uint32_t i2c_periph); -/* disable SAM_V interface */ -void i2c_sam_disable(uint32_t i2c_periph); -/* enable SAM_V interface timeout detect */ -void i2c_sam_timeout_enable(uint32_t i2c_periph); -/* disable SAM_V interface timeout detect */ -void i2c_sam_timeout_disable(uint32_t i2c_periph); - -/* interrupt & flag functions */ -/* get I2C flag status */ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); -/* clear I2C flag status */ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); -/* enable I2C interrupt */ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* disable I2C interrupt */ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); -/* get I2C interrupt flag status */ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); -/* clear I2C interrupt flag status */ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); - -#endif /* GD32E23X_I2C_H */ +/*! + \file gd32e23x_i2c.h + \brief definitions for the I2C + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_I2C_H +#define GD32E23X_I2C_H + +#include "gd32e23x.h" + +/* I2Cx(x=0,1) definitions */ +#define I2C0 I2C_BASE /*!< I2C0 base address */ +#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ + +/* registers definitions */ +#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ +#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ +#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */ +#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ +#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ +#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ +#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ +#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ +#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ +#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ +#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast mode plus configure register */ + +/* bits definitions */ +/* I2Cx_CTL0 */ +#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ +#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ +#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ +#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ +#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ +#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ +#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ +#define I2C_CTL0_START BIT(8) /*!< start generation */ +#define I2C_CTL0_STOP BIT(9) /*!< stop generation */ +#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ +#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ +#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ +#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ +#define I2C_CTL0_SRESET BIT(15) /*!< software reset */ + +/* I2Cx_CTL1 */ +#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ +#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ +#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ +#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ +#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ +#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ +#define I2C_CTL1_RBNECM BIT(15) /*!< RBNE clear mode */ + +/* I2Cx_SADDR0 */ +#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ +#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ +#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ + +/* I2Cx_SADDR1 */ +#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ +#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ + +/* I2Cx_DATA */ +#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ + +/* I2Cx_STAT0 */ +#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ +#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ +#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ +#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ +#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ +#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ +#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ +#define I2C_STAT0_BERR BIT(8) /*!< bus error */ +#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ +#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ +#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ +#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ +#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ +#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ + +/* I2Cx_STAT1 */ +#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ +#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ +#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ +#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ +#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ +#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ +#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ +#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ + +/* I2Cx_CKCFG */ +#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ +#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ +#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ + +/* I2Cx_RT */ +#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ + +/* I2Cx_SAMCS */ +#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ +#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ +#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ +#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ +#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ +#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ +#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ +#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ +#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ +#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ +#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ +#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ + +/* I2Cx_FMPCFG */ +#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ + +/* constants definitions */ +/* define the I2C bit position and its register index offset */ +#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) +#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ +#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ +#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ +#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ + +/* I2C flags */ +typedef enum { + /* flags in STAT0 register */ + I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ + I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ + I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ + I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ + I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ + I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */ + I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ + I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ + I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ + I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ + I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ + I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ + I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ + I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ + /* flags in STAT1 register */ + I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ + I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ + I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ + I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ + I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ + I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ + I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ + /* flags in SAMCS register */ + I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ + I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ + I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ + I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ +} i2c_flag_enum; + +/* I2C interrupt flags */ +typedef enum { + /* interrupt flags in CTL1 register */ + I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ + I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ + I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ + I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ + I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ + I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ + I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ + I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ + I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ + I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ + I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ + I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ + I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ + I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ + /* interrupt flags in SAMCS register */ + I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ + I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ + I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ + I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ +} i2c_interrupt_flag_enum; + +/* I2C interrupt */ +typedef enum { + /* interrupt in CTL1 register */ + I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ + I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ + I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ + /* interrupt in SAMCS register */ + I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ + I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ + I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ + I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */ +} i2c_interrupt_enum; + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ +#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ + +/* SMBus/I2C mode switch and SMBus type selection */ +#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ +#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ + +/* I2C transfer direction */ +#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ +#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ + +/* whether or not to send an ACK */ +#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ +#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ + +/* I2C POAP position*/ +#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ +#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ + +/* whether or not to stretch SCL low */ +#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */ +#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */ + +/* whether or not to response to a general call */ +#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ +#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ + +/* software reset I2C */ +#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ +#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ + +/* I2C DMA mode configure */ +/* DMA mode switch */ +#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ +#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ + +/* flag indicating DMA last transfer */ +#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ +#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ + +/* RBNE clear mode */ +#define I2C_RBNE_CLEAR_BTC_0 ((uint32_t)0x00000000U) /*!< RBNE can be cleared when I2C_DATA is read and BTC is cleared */ +#define I2C_RBNE_CLEAR I2C_CTL1_RBNECM /*!< RBNE can be cleared when I2C_DATA is read */ + +/* I2C PEC configure */ +/* PEC enable */ +#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ +#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ + +/* PEC transfer */ +#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ +#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ + +/* I2C SMBus configure */ +/* issue or not alert through SMBA pin */ +#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ +#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ + +/* ARP protocol in SMBus switch */ +#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ +#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ + +/* transmit I2C data */ +#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) + +/* receive I2C data */ +#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) + +/* I2C duty cycle in fast mode or fast mode plus */ +#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode or fast mode plus */ +#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode or fast mode plus */ + +/* address mode for the I2C slave */ +#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ +#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ + +/* function declarations */ +/* initialization functions */ +/* reset I2C */ +void i2c_deinit(uint32_t i2c_periph); +/* configure I2C clock */ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); +/* configure I2C address */ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); + +/* application function declarations */ +/* select SMBus type */ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); +/* whether or not to send an ACK */ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); +/* configure I2C POAP position */ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); +/* master sends slave address */ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); +/* enable dual-address mode */ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); +/* disable dual-address mode */ +void i2c_dualaddr_disable(uint32_t i2c_periph); +/* enable I2C */ +void i2c_enable(uint32_t i2c_periph); +/* disable I2C */ +void i2c_disable(uint32_t i2c_periph); +/* generate a START condition on I2C bus */ +void i2c_start_on_bus(uint32_t i2c_periph); +/* generate a STOP condition on I2C bus */ +void i2c_stop_on_bus(uint32_t i2c_periph); +/* I2C transmit data function */ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); +/* I2C receive data function */ +uint8_t i2c_data_receive(uint32_t i2c_periph); +/* configure I2C DMA mode */ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); +/* configure whether next DMA EOT is DMA last transfer or not */ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); +/* configure RBNE clear mode */ +void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode); +/* whether to stretch SCL low when data is not ready in slave mode */ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); +/* whether or not to response to a general call */ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); +/* configure software reset of I2C */ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); +/* configure I2C PEC calculation */ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); +/* configure whether to transfer PEC value */ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); +/* get packet error checking value */ +uint8_t i2c_pec_value_get(uint32_t i2c_periph); +/* configure I2C alert through SMBA pin */ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); +/* configure I2C ARP protocol in SMBus */ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); +/* enable SAM_V interface */ +void i2c_sam_enable(uint32_t i2c_periph); +/* disable SAM_V interface */ +void i2c_sam_disable(uint32_t i2c_periph); +/* enable SAM_V interface timeout detect */ +void i2c_sam_timeout_enable(uint32_t i2c_periph); +/* disable SAM_V interface timeout detect */ +void i2c_sam_timeout_disable(uint32_t i2c_periph); + +/* interrupt & flag functions */ +/* get I2C flag status */ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); +/* clear I2C flag status */ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); +/* enable I2C interrupt */ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* disable I2C interrupt */ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); +/* get I2C interrupt flag status */ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); +/* clear I2C interrupt flag status */ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); + +#endif /* GD32E23X_I2C_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_misc.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_misc.h index a4b6295..dbd9b08 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_misc.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_misc.h @@ -1,84 +1,84 @@ -/*! - \file gd32e23x_misc.h - \brief definitions for the MISC - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_MISC_H -#define GD32E23X_MISC_H - -#include "gd32e23x.h" - -/* constants definitions */ -/* set the RAM and FLASH base address */ -#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */ -#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */ - -/* set the NVIC vector table offset mask */ -#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U) /*!< NVIC vector table offset mask */ - -/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ -#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /*!< NVIC VECTKEY mask */ - -/* choose the method to enter or exit the lowpower mode */ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */ - -#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ -#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ -#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ - -/* choose the systick clock source */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ - -/* function declarations */ - -/* enable NVIC request */ -void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_priority); -/* disable NVIC request */ -void nvic_irq_disable(IRQn_Type nvic_irq); -/* initiates a system reset request to reset the MCU */ -void nvic_system_reset(void); - -/* set the NVIC vector table base address */ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); - -/* set the state of the low power mode */ -void system_lowpower_set(uint8_t lowpower_mode); -/* reset the state of the low power mode */ -void system_lowpower_reset(uint8_t lowpower_mode); - -/* set the systick clock source */ -void systick_clksource_set(uint32_t systick_clksource); - -#endif /* GD32E23X_MISC_H */ +/*! + \file gd32e23x_misc.h + \brief definitions for the MISC + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_MISC_H +#define GD32E23X_MISC_H + +#include "gd32e23x.h" + +/* constants definitions */ +/* set the RAM and FLASH base address */ +#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000U) /*!< RAM base address */ +#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000U) /*!< Flash base address */ + +/* set the NVIC vector table offset mask */ +#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80U) /*!< NVIC vector table offset mask */ + +/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */ +#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000U) /*!< NVIC VECTKEY mask */ + +/* choose the method to enter or exit the lowpower mode */ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02U) /*!< choose the the system whether enter low power mode by exiting from ISR */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04U) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10U) /*!< choose the interrupt source that can wake up the lowpower mode */ + +#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */ +#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */ +#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */ + +/* choose the systick clock source */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */ +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */ + +/* function declarations */ + +/* enable NVIC request */ +void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_priority); +/* disable NVIC request */ +void nvic_irq_disable(IRQn_Type nvic_irq); +/* initiates a system reset request to reset the MCU */ +void nvic_system_reset(void); + +/* set the NVIC vector table base address */ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset); + +/* set the state of the low power mode */ +void system_lowpower_set(uint8_t lowpower_mode); +/* reset the state of the low power mode */ +void system_lowpower_reset(uint8_t lowpower_mode); + +/* set the systick clock source */ +void systick_clksource_set(uint32_t systick_clksource); + +#endif /* GD32E23X_MISC_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_pmu.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_pmu.h index 2229368..56a6f3f 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_pmu.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_pmu.h @@ -1,144 +1,144 @@ -/*! - \file gd32e23x_pmu.h - \brief definitions for the PMU - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_PMU_H -#define GD32E23X_PMU_H - -#include "gd32e23x.h" - -/* PMU definitions */ -#define PMU PMU_BASE /*!< PMU base address */ - -/* registers definitions */ -#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ -#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ - -/* bits definitions */ -/* PMU_CTL */ -#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ -#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ -#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ -#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ -#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ -#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ -#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ -#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */ -#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */ -#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ - -/* PMU_CS */ -#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ -#define PMU_CS_STBF BIT(1) /*!< standby flag */ -#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ -#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ -#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ - -/* constants definitions */ -/* PMU ldo definitions */ -#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ -#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ - -/* PMU low voltage detector threshold definitions */ -#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) -#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ -#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ -#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ -#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ -#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ -#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ -#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ -#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ - -/* PMU LDO output voltage select definitions */ -#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) -#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */ -#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */ - -/* PMU WKUP pin definitions */ -#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ -#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ -#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ -#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ - -/* PMU flag definitions */ -#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ -#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ -#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ - -/* PMU flag reset definitions */ -#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ -#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ - -/* PMU command constants definitions */ -#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ -#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ - -/* function declarations */ -/* reset PMU registers */ -void pmu_deinit(void); - -/* select low voltage detector threshold */ -void pmu_lvd_select(uint32_t lvdt_n); -/* select LDO output voltage */ -void pmu_ldo_output_select(uint32_t ldo_output); -/* disable PMU lvd */ -void pmu_lvd_disable(void); - -/* set PMU mode */ -/* PMU work in sleep mode */ -void pmu_to_sleepmode(uint8_t sleepmodecmd); -/* PMU work in deepsleep mode */ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); -/* PMU work in standby mode */ -void pmu_to_standbymode(void); -/* enable PMU wakeup pin */ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin); -/* disable PMU wakeup pin */ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin); - -/* backup related functions */ -/* enable backup domain write */ -void pmu_backup_write_enable(void); -/* disable backup domain write */ -void pmu_backup_write_disable(void); - -/* flag functions */ -/* get flag state */ -FlagStatus pmu_flag_get(uint32_t flag); -/* clear flag bit */ -void pmu_flag_clear(uint32_t flag); - -#endif /* GD32E23X_PMU_H */ +/*! + \file gd32e23x_pmu.h + \brief definitions for the PMU + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_PMU_H +#define GD32E23X_PMU_H + +#include "gd32e23x.h" + +/* PMU definitions */ +#define PMU PMU_BASE /*!< PMU base address */ + +/* registers definitions */ +#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ +#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ + +/* bits definitions */ +/* PMU_CTL */ +#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ +#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ +#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ +#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ +#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ +#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ +#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ +#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */ +#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */ +#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ + +/* PMU_CS */ +#define PMU_CS_WUF BIT(0) /*!< wakeup flag */ +#define PMU_CS_STBF BIT(1) /*!< standby flag */ +#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ +#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ +#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ + +/* constants definitions */ +/* PMU ldo definitions */ +#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ +#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ + +/* PMU low voltage detector threshold definitions */ +#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) +#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ +#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ +#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ +#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ +#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ +#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ +#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ +#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ + +/* PMU LDO output voltage select definitions */ +#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) +#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */ +#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */ + +/* PMU WKUP pin definitions */ +#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ +#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ +#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ +#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ + +/* PMU flag definitions */ +#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ +#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ +#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ + +/* PMU flag reset definitions */ +#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ +#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ + +/* PMU command constants definitions */ +#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ +#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ + +/* function declarations */ +/* reset PMU registers */ +void pmu_deinit(void); + +/* select low voltage detector threshold */ +void pmu_lvd_select(uint32_t lvdt_n); +/* select LDO output voltage */ +void pmu_ldo_output_select(uint32_t ldo_output); +/* disable PMU lvd */ +void pmu_lvd_disable(void); + +/* set PMU mode */ +/* PMU work in sleep mode */ +void pmu_to_sleepmode(uint8_t sleepmodecmd); +/* PMU work in deepsleep mode */ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); +/* PMU work in standby mode */ +void pmu_to_standbymode(void); +/* enable PMU wakeup pin */ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin); +/* disable PMU wakeup pin */ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin); + +/* backup related functions */ +/* enable backup domain write */ +void pmu_backup_write_enable(void); +/* disable backup domain write */ +void pmu_backup_write_disable(void); + +/* flag functions */ +/* get flag state */ +FlagStatus pmu_flag_get(uint32_t flag); +/* clear flag bit */ +void pmu_flag_clear(uint32_t flag); + +#endif /* GD32E23X_PMU_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rcu.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rcu.h index e52e58e..1d7667f 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rcu.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rcu.h @@ -1,670 +1,670 @@ -/*! - \file gd32e23x_rcu.h - \brief definitions for the RCU - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_RCU_H -#define GD32E23X_RCU_H - -#include "gd32e23x.h" - -/* RCU definitions */ -#define RCU RCU_BASE - -/* registers definitions */ -#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ -#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ -#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ -#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ -#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ -#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ -#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ -#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ -#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ -#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ -#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ -#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ -#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ -#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ -#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ -#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ - -/* bits definitions */ -/* RCU_CTL0 */ -#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ -#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ -#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ -#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ -#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ -#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ -#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ -#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ -#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ -#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ - -/* RCU_CFG0 */ -#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ -#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ -#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ -#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ -#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ -#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ -#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ -#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ -#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ -#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ -#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ -#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ -#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ - -/* RCU_INT */ -#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ -#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ -#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ -#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ -#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ -#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ -#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ -#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ -#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ -#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ -#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ -#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ -#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ -#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ -#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ -#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ -#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ -#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ -#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ -#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ - -/* RCU_APB2RST */ -#define RCU_APB2RST_CFGCMPRST BIT(0) /*!< system configuration and comparator reset */ -#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ -#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ -#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ -#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ -#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ -#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ -#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ - -/* RCU_APB1RST */ -#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ -#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ -#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ -#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ -#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ -#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ -#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ -#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ -#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ - -/* RCU_AHBEN */ -#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ -#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ -#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ -#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ -#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ -#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ -#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ -#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ - -/* RCU_APB2EN */ -#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ -#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ -#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ -#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ -#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ -#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ -#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ -#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ -#define RCU_APB2EN_DBGMCUEN BIT(22) /*!< DBGMCU clock enable */ - -/* RCU_APB1EN */ -#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ -#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ -#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ -#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ -#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ -#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ -#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ -#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ -#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ - -/* RCU_BDCTL */ -#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ -#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ -#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ -#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ -#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ -#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ -#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ - -/* RCU_RSTSCK */ -#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ -#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ -#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ -#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ -#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ -#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ -#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ -#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ -#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ -#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ -#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ - -/* RCU_AHBRST */ -#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ -#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ -#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ -#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ - -/* RCU_CFG1 */ -#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ - -/* RCU_CFG2 */ -#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ -#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ -#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ -#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ - -/* RCU_CTL1 */ -#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ -#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ -#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ -#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ - -/* RCU_VKEY */ -#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ - -/* RCU_DSV */ -#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ - -/* constants definitions */ -/* define the peripheral clock enable bit position and its register index offset */ -#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) -#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) -#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) -/* define the voltage key unlock value */ -#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D) - -/* register index */ -typedef enum -{ - /* peripherals enable */ - IDX_AHBEN = 0x14U, - IDX_APB2EN = 0x18U, - IDX_APB1EN = 0x1CU, - /* peripherals reset */ - IDX_AHBRST = 0x28U, - IDX_APB2RST = 0x0CU, - IDX_APB1RST = 0x10U, - /* clock stabilization */ - IDX_CTL0 = 0x00U, - IDX_BDCTL = 0x20U, - IDX_CTL1 = 0x34U, - /* peripheral reset */ - IDX_RSTSCK = 0x24U, - /* clock stabilization and stuck interrupt */ - IDX_INT = 0x08U, - /* configuration register */ - IDX_CFG0 = 0x04U, - IDX_CFG2 = 0x30U -}reg_idx; - -/* peripheral clock enable */ -typedef enum -{ - /* AHB peripherals */ - RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ - RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ - RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ - RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ - RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ - RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ - - /* APB2 peripherals */ - RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ - RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ - RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ - RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ - RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ - RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ - RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ - RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ - RCU_DBGMCU = RCU_REGIDX_BIT(IDX_APB2EN, 22U), /*!< DBGMCU clock */ - - /* APB1 peripherals */ - RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ - RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ - RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ - RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ - RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ - RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ - RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ - RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ - RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ - - /* Backup domain control(BDCTL) */ - RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U) /*!< RTC clock */ -}rcu_periph_enum; - -/* peripheral clock enable when sleep mode*/ -typedef enum -{ - /* AHB peripherals */ - RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ - RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ -}rcu_periph_sleep_enum; - -/* peripherals reset */ -typedef enum -{ - /* AHB peripherals reset */ - RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ - RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ - RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ - RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ - - /* APB2 peripherals reset */ - RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ - RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ - RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ - RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ - RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ - RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ - RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ - RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ - - /* APB1 peripherals reset */ - RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ - RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ - RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ - RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ - RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ - RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ - RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ - RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ - RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ -}rcu_periph_reset_enum; - -/* clock stabilization and peripheral reset flags */ -typedef enum -{ - RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ - RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ - RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ - RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ - RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ - RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ - - RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ - RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ - RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ - RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ - RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ - RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ - RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ - RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ -}rcu_flag_enum; - -/* clock stabilization and ckm interrupt flags */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ - RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ - RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ - RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ - RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ - RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ - RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ -}rcu_int_flag_enum; - -/* clock stabilization and stuck interrupt flags clear */ -typedef enum -{ - RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ - RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ - RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ - RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ - RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ - RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ -}rcu_int_flag_clear_enum; - -/* clock stabilization interrupt enable or disable */ -typedef enum -{ - RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ - RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ - RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ - RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ - RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ - RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ -}rcu_int_enum; - -/* ADC clock source */ -typedef enum -{ - RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ - RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ - RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ - RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ - RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ - RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ - RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ - RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ - RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ - RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ -}rcu_adc_clock_enum; - -/* oscillator types */ -typedef enum -{ - RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ - RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ - RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ - RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ - RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ - RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ -}rcu_osci_type_enum; - -/* rcu clock frequency */ -typedef enum -{ - CK_SYS = 0U, /*!< system clock */ - CK_AHB, /*!< AHB clock */ - CK_APB1, /*!< APB1 clock */ - CK_APB2, /*!< APB2 clock */ - CK_ADC, /*!< ADC clock */ - CK_USART /*!< USART clock */ -}rcu_clock_freq_enum; - -/* system clock source select */ -#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ -#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ -#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ - -/* system clock source select status */ -#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) -#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ -#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ -#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ - -/* AHB prescaler selection */ -#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) -#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ -#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ -#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ -#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ -#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ -#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ -#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ -#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ -#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ - -/* APB1 prescaler selection */ -#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) -#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ -#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ -#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ -#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ -#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ - -/* APB2 prescaler selection */ -#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) -#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ -#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ -#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ -#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ -#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ - -/* ADC clock prescaler selection */ -#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) -#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ -#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ -#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ -#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ - -/* PLL clock source selection */ -#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U /*!< PLL clock source select IRC8M/2 */ -#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL */ - -/* HXTAL divider for PLL source clock selection */ -#define RCU_PLLPREDV (uint32_t)0x00000000U /*!< HXTAL clock selected */ -#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< HXTAL/2 clock selected */ - -/* PLL multiply factor */ -#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) -#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ -#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ -#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ -#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ -#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ -#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ -#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ -#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ -#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ -#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ -#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ -#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ -#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ -#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ -#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ -#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ -#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ -#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ -#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ -#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ -#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ -#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ -#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ -#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ -#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ -#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ -#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ -#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ -#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ -#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ -#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ - -/* CK_OUT clock source selection */ -#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) -#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ -#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ -#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ -#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ -#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ -#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ -#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ -#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ -#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ - -/* CK_OUT divider */ -#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) -#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ -#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ -#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ -#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ -#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ -#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ -#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ -#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ - -/* CK_PLL divide by 1 or 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */ -#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ - -/* LXTAL drive capability */ -#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) -#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ -#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ -#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ -#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ - -/* RTC clock entry selection */ -#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ -#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ -#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ -#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ - -/* CK_HXTAL divider previous PLL */ -#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) -#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ -#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ -#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ -#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ -#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ -#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ -#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ -#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ -#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ -#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ -#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ -#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ -#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ -#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ -#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ -#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ - -/* USART0 clock source selection */ -#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ -#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ -#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ -#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ - -/* ADC clock source selection */ -#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U /*!< ADC clock source select */ -#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ - -/* IRC28M clock divider for ADC */ -#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U /*!< IRC28M/2 select to ADC clock */ -#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ - -/* Deep-sleep mode voltage */ -#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) -#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ -#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */ - -/* function declarations */ -/* deinitialize the RCU */ -void rcu_deinit(void); -/* enable the peripherals clock */ -void rcu_periph_clock_enable(rcu_periph_enum periph); -/* disable the peripherals clock */ -void rcu_periph_clock_disable(rcu_periph_enum periph); -/* enable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); -/* disable the peripherals clock when sleep mode */ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); -/* reset the peripherals */ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); -/* disable reset the peripheral */ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); -/* reset the BKP */ -void rcu_bkp_reset_enable(void); -/* disable the BKP reset */ -void rcu_bkp_reset_disable(void); - -/* configure the system clock source */ -void rcu_system_clock_source_config(uint32_t ck_sys); -/* get the system clock source */ -uint32_t rcu_system_clock_source_get(void); -/* configure the AHB prescaler selection */ -void rcu_ahb_clock_config(uint32_t ck_ahb); -/* configure the APB1 prescaler selection */ -void rcu_apb1_clock_config(uint32_t ck_apb1); -/* configure the APB2 prescaler selection */ -void rcu_apb2_clock_config(uint32_t ck_apb2); -/* configure the ADC clock source and prescaler selection */ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); -/* configure the CK_OUT clock source and divider */ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); - -/* configure the PLL clock source selection and PLL multiply factor */ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); -/* configure the USART clock source selection */ -void rcu_usart_clock_config(uint32_t ck_usart); -/* configure the RTC clock source selection */ -void rcu_rtc_clock_config(uint32_t rtc_clock_source); -/* configure the HXTAL divider used as input of PLL */ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); -/* configure the LXTAL drive capability */ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); - -/* wait until oscillator stabilization flags is SET */ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); -/* turn on the oscillator */ -void rcu_osci_on(rcu_osci_type_enum osci); -/* turn off the oscillator */ -void rcu_osci_off(rcu_osci_type_enum osci); -/* enable the oscillator bypass mode */ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); -/* disable the oscillator bypass mode */ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); -/* enable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_enable(void); -/* disable the HXTAL clock monitor */ -void rcu_hxtal_clock_monitor_disable(void); - -/* set the IRC8M adjust value */ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); -/* set the IRC28M adjust value */ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); -/* unlock the voltage key */ -void rcu_voltage_key_unlock(void); -/* set the deep sleep mode voltage */ -void rcu_deepsleep_voltage_set(uint32_t dsvol); - -/* get the system clock, bus and peripheral clock frequency */ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); - -/* get the clock stabilization and periphral reset flags */ -FlagStatus rcu_flag_get(rcu_flag_enum flag); -/* clear the reset flag */ -void rcu_all_reset_flag_clear(void); -/* get the clock stabilization interrupt and ckm flags */ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); -/* clear the interrupt flags */ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); -/* enable the stabilization interrupt */ -void rcu_interrupt_enable(rcu_int_enum stab_int); -/* disable the stabilization interrupt */ -void rcu_interrupt_disable(rcu_int_enum stab_int); - -#endif /* GD32E23X_RCU_H */ +/*! + \file gd32e23x_rcu.h + \brief definitions for the RCU + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_RCU_H +#define GD32E23X_RCU_H + +#include "gd32e23x.h" + +/* RCU definitions */ +#define RCU RCU_BASE + +/* registers definitions */ +#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ +#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ +#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ +#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ +#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ +#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ +#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ +#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ +#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ +#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ +#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ +#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ +#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ +#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ +#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ +#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ + +/* bits definitions */ +/* RCU_CTL0 */ +#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ +#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ +#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ +#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ +#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ +#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ +#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ +#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ +#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ +#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ + +/* RCU_CFG0 */ +#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ +#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ +#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ +#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ +#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ +#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ +#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ +#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ +#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ +#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ +#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ +#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ +#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ + +/* RCU_INT */ +#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ +#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ +#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ +#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ +#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ +#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ +#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ +#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ +#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ +#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ +#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ +#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ +#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ +#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ +#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ +#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ +#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ +#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ +#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ +#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ + +/* RCU_APB2RST */ +#define RCU_APB2RST_CFGCMPRST BIT(0) /*!< system configuration and comparator reset */ +#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ +#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ +#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ +#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ +#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ +#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ +#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ + +/* RCU_APB1RST */ +#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ +#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ +#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ +#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ +#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ +#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ +#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ +#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ +#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ + +/* RCU_AHBEN */ +#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ +#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ +#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ +#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ +#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ +#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ +#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ +#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ + +/* RCU_APB2EN */ +#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ +#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ +#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ +#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ +#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ +#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ +#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ +#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ +#define RCU_APB2EN_DBGMCUEN BIT(22) /*!< DBGMCU clock enable */ + +/* RCU_APB1EN */ +#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ +#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ +#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ +#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ +#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ +#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ +#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ +#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ +#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ + +/* RCU_BDCTL */ +#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ +#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ +#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ +#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ +#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ +#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ +#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ + +/* RCU_RSTSCK */ +#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ +#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ +#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ +#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ +#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ +#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ +#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ +#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ +#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ +#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ +#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ + +/* RCU_AHBRST */ +#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ +#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ +#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ +#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ + +/* RCU_CFG1 */ +#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ + +/* RCU_CFG2 */ +#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ +#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ +#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ +#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ + +/* RCU_CTL1 */ +#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ +#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ +#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ +#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ + +/* RCU_VKEY */ +#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ + +/* RCU_DSV */ +#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ + +/* constants definitions */ +/* define the peripheral clock enable bit position and its register index offset */ +#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) +#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) +#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) +/* define the voltage key unlock value */ +#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D) + +/* register index */ +typedef enum +{ + /* peripherals enable */ + IDX_AHBEN = 0x14U, + IDX_APB2EN = 0x18U, + IDX_APB1EN = 0x1CU, + /* peripherals reset */ + IDX_AHBRST = 0x28U, + IDX_APB2RST = 0x0CU, + IDX_APB1RST = 0x10U, + /* clock stabilization */ + IDX_CTL0 = 0x00U, + IDX_BDCTL = 0x20U, + IDX_CTL1 = 0x34U, + /* peripheral reset */ + IDX_RSTSCK = 0x24U, + /* clock stabilization and stuck interrupt */ + IDX_INT = 0x08U, + /* configuration register */ + IDX_CFG0 = 0x04U, + IDX_CFG2 = 0x30U +}reg_idx; + +/* peripheral clock enable */ +typedef enum +{ + /* AHB peripherals */ + RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ + RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ + RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ + RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ + RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ + RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ + + /* APB2 peripherals */ + RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ + RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ + RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ + RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ + RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ + RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ + RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ + RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ + RCU_DBGMCU = RCU_REGIDX_BIT(IDX_APB2EN, 22U), /*!< DBGMCU clock */ + + /* APB1 peripherals */ + RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ + RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ + RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ + RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ + RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ + RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ + RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ + RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ + RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ + + /* Backup domain control(BDCTL) */ + RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U) /*!< RTC clock */ +}rcu_periph_enum; + +/* peripheral clock enable when sleep mode*/ +typedef enum +{ + /* AHB peripherals */ + RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ + RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ +}rcu_periph_sleep_enum; + +/* peripherals reset */ +typedef enum +{ + /* AHB peripherals reset */ + RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ + RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ + RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ + RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ + + /* APB2 peripherals reset */ + RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ + RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ + RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ + RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ + RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ + RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ + RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ + RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ + + /* APB1 peripherals reset */ + RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ + RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ + RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ + RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ + RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ + RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ + RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ + RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ + RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ +}rcu_periph_reset_enum; + +/* clock stabilization and peripheral reset flags */ +typedef enum +{ + RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ + RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ + RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ + RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ + RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ + RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ + + RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ + RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ + RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ + RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ + RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ + RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ + RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ + RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ +}rcu_flag_enum; + +/* clock stabilization and ckm interrupt flags */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ + RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ + RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ + RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ + RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ + RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ + RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ +}rcu_int_flag_enum; + +/* clock stabilization and stuck interrupt flags clear */ +typedef enum +{ + RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ + RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ + RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ + RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ + RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ + RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ +}rcu_int_flag_clear_enum; + +/* clock stabilization interrupt enable or disable */ +typedef enum +{ + RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ + RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ + RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ + RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ + RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ + RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ +}rcu_int_enum; + +/* ADC clock source */ +typedef enum +{ + RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ + RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ + RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ + RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ + RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ + RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ + RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ + RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ + RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ + RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ +}rcu_adc_clock_enum; + +/* oscillator types */ +typedef enum +{ + RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ + RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ + RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ + RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ + RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ + RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ +}rcu_osci_type_enum; + +/* rcu clock frequency */ +typedef enum +{ + CK_SYS = 0U, /*!< system clock */ + CK_AHB, /*!< AHB clock */ + CK_APB1, /*!< APB1 clock */ + CK_APB2, /*!< APB2 clock */ + CK_ADC, /*!< ADC clock */ + CK_USART /*!< USART clock */ +}rcu_clock_freq_enum; + +/* system clock source select */ +#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ +#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ +#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ + +/* system clock source select status */ +#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) +#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ +#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ +#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ + +/* AHB prescaler selection */ +#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) +#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ +#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ +#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ +#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ +#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ +#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ +#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ +#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ +#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ + +/* APB1 prescaler selection */ +#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) +#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ +#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ +#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ +#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ +#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ + +/* APB2 prescaler selection */ +#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) +#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ +#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ +#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ +#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ +#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ + +/* ADC clock prescaler selection */ +#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) +#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ +#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ +#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ +#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ + +/* PLL clock source selection */ +#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U /*!< PLL clock source select IRC8M/2 */ +#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL */ + +/* HXTAL divider for PLL source clock selection */ +#define RCU_PLLPREDV (uint32_t)0x00000000U /*!< HXTAL clock selected */ +#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< HXTAL/2 clock selected */ + +/* PLL multiply factor */ +#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) +#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ +#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ +#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ +#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ +#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ +#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ +#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ +#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ +#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ +#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ +#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ +#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ +#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ +#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ +#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ +#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ +#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ +#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ +#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ +#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ +#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ +#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ +#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ +#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ +#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ +#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ +#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ +#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ +#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ +#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ +#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ + +/* CK_OUT clock source selection */ +#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) +#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ +#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ +#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ +#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ +#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ +#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ +#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ +#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ +#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ + +/* CK_OUT divider */ +#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) +#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ +#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ +#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ +#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ +#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ +#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ +#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ +#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ + +/* CK_PLL divide by 1 or 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */ +#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ + +/* LXTAL drive capability */ +#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) +#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ +#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ +#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ +#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ + +/* RTC clock entry selection */ +#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ +#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ +#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ +#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ + +/* CK_HXTAL divider previous PLL */ +#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) +#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ +#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ +#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ +#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ +#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ +#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ +#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ +#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ +#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ +#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ +#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ +#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ +#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ +#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ +#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ +#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ + +/* USART0 clock source selection */ +#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ +#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ +#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ +#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ + +/* ADC clock source selection */ +#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U /*!< ADC clock source select */ +#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ + +/* IRC28M clock divider for ADC */ +#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U /*!< IRC28M/2 select to ADC clock */ +#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ + +/* Deep-sleep mode voltage */ +#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) +#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ +#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */ + +/* function declarations */ +/* deinitialize the RCU */ +void rcu_deinit(void); +/* enable the peripherals clock */ +void rcu_periph_clock_enable(rcu_periph_enum periph); +/* disable the peripherals clock */ +void rcu_periph_clock_disable(rcu_periph_enum periph); +/* enable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); +/* disable the peripherals clock when sleep mode */ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); +/* reset the peripherals */ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); +/* disable reset the peripheral */ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); +/* reset the BKP */ +void rcu_bkp_reset_enable(void); +/* disable the BKP reset */ +void rcu_bkp_reset_disable(void); + +/* configure the system clock source */ +void rcu_system_clock_source_config(uint32_t ck_sys); +/* get the system clock source */ +uint32_t rcu_system_clock_source_get(void); +/* configure the AHB prescaler selection */ +void rcu_ahb_clock_config(uint32_t ck_ahb); +/* configure the APB1 prescaler selection */ +void rcu_apb1_clock_config(uint32_t ck_apb1); +/* configure the APB2 prescaler selection */ +void rcu_apb2_clock_config(uint32_t ck_apb2); +/* configure the ADC clock source and prescaler selection */ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); +/* configure the CK_OUT clock source and divider */ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); + +/* configure the PLL clock source selection and PLL multiply factor */ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); +/* configure the USART clock source selection */ +void rcu_usart_clock_config(uint32_t ck_usart); +/* configure the RTC clock source selection */ +void rcu_rtc_clock_config(uint32_t rtc_clock_source); +/* configure the HXTAL divider used as input of PLL */ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); +/* configure the LXTAL drive capability */ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); + +/* wait until oscillator stabilization flags is SET */ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); +/* turn on the oscillator */ +void rcu_osci_on(rcu_osci_type_enum osci); +/* turn off the oscillator */ +void rcu_osci_off(rcu_osci_type_enum osci); +/* enable the oscillator bypass mode */ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); +/* disable the oscillator bypass mode */ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); +/* enable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_enable(void); +/* disable the HXTAL clock monitor */ +void rcu_hxtal_clock_monitor_disable(void); + +/* set the IRC8M adjust value */ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); +/* set the IRC28M adjust value */ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); +/* unlock the voltage key */ +void rcu_voltage_key_unlock(void); +/* set the deep sleep mode voltage */ +void rcu_deepsleep_voltage_set(uint32_t dsvol); + +/* get the system clock, bus and peripheral clock frequency */ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); + +/* get the clock stabilization and periphral reset flags */ +FlagStatus rcu_flag_get(rcu_flag_enum flag); +/* clear the reset flag */ +void rcu_all_reset_flag_clear(void); +/* get the clock stabilization interrupt and ckm flags */ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); +/* clear the interrupt flags */ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); +/* enable the stabilization interrupt */ +void rcu_interrupt_enable(rcu_int_enum stab_int); +/* disable the stabilization interrupt */ +void rcu_interrupt_disable(rcu_int_enum stab_int); + +#endif /* GD32E23X_RCU_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rtc.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rtc.h index 190982f..66195a2 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rtc.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_rtc.h @@ -1,559 +1,559 @@ -/*! - \file gd32e23x_rtc.h - \brief definitions for the RTC - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_RTC_H -#define GD32E23X_RTC_H - -#include "gd32e23x.h" - -/* RTC definitions */ -#define RTC RTC_BASE - -/* registers definitions */ -#define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */ -#define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */ -#define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */ -#define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */ -#define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */ -#define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */ -#define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */ -#define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */ -#define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */ -#define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */ -#define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */ -#define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */ -#define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ -#define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */ -#define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */ -#define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */ -#define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */ -#define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */ -#define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */ -#define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */ - -/* bits definitions */ -/* RTC_TIME */ -#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DATE */ -#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ -#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ -#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ - -/* RTC_CTL */ -#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ -#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ -#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ -#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ -#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ -#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ -#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ -#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ -#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ -#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ -#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ -#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ -#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ -#define RTC_CTL_OS BITS(21,22) /*!< output selection */ -#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ - -/* RTC_STAT */ -#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ -#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ -#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ -#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ -#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ -#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ -#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ -#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ -#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ -#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ -#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ -#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ - -/* RTC_PSC */ -#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ -#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ - -/* RTC_ALRM0TD */ -#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ -#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ -#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ -#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ -#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ -#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ -#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ -#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ -#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ -#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ -#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ -#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ - -/* RTC_WPK */ -#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ - -/* RTC_SS */ -#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ - -/* RTC_SHIFTCTL */ -#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ -#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ - -/* RTC_TTS */ -#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ -#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ -#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ -#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ -#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ -#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ -#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ - -/* RTC_DTS */ -#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ -#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ -#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ -#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ -#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ - -/* RTC_SSTS */ -#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ - -/* RTC_HRFC */ -#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ -#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ -#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ - -/* RTC_TAMP */ -#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ -#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ -#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ -#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ -#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ -#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ -#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ -#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ -#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ -#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ -#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ -#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ -#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ -#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ -#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ -#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ - -/* RTC_ALRM0SS */ -#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ -#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ - -/* RTC_BKP0 */ -#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP1 */ -#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP2 */ -#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP3 */ -#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ - -/* RTC_BKP4 */ -#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ - -/* constants definitions */ -/* structure for initialization of the RTC */ -typedef struct -{ - uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ - uint8_t rtc_month; /*!< RTC month value */ - uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_day_of_week; /*!< RTC weekday value */ - uint8_t rtc_hour; /*!< RTC hour value */ - uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ - uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ - uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ - uint32_t rtc_am_pm; /*!< RTC AM/PM value */ - uint32_t rtc_display_format; /*!< RTC time notation */ -}rtc_parameter_struct; - -/* structure for RTC alarm configuration */ -typedef struct -{ - uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ - uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ - uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ - uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ - uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ -}rtc_alarm_struct; - -/* structure for RTC time-stamp configuration */ -typedef struct -{ - uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ - uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ - uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ - uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ - uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ - uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ - uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ -}rtc_timestamp_struct; - -/* structure for RTC tamper configuration */ -typedef struct -{ - uint32_t rtc_tamper_source; /*!< RTC tamper source */ - uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ - uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ - uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ - ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ - uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ - ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ -}rtc_tamper_struct; - -/* time register value */ -#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ -#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ - -#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ -#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ - -#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ -#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ - -#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ -#define RTC_PM RTC_TIME_PM /*!< PM format */ - -/* date register value */ -#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ -#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ - -#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ -#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ -#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ -#define RTC_FEB ((uint8_t)0x02U) /*!< February */ -#define RTC_MAR ((uint8_t)0x03U) /*!< March */ -#define RTC_APR ((uint8_t)0x04U) /*!< April */ -#define RTC_MAY ((uint8_t)0x05U) /*!< May */ -#define RTC_JUN ((uint8_t)0x06U) /*!< June */ -#define RTC_JUL ((uint8_t)0x07U) /*!< July */ -#define RTC_AUG ((uint8_t)0x08U) /*!< August */ -#define RTC_SEP ((uint8_t)0x09U) /*!< September */ -#define RTC_OCT ((uint8_t)0x10U) /*!< October */ -#define RTC_NOV ((uint8_t)0x11U) /*!< November */ -#define RTC_DEC ((uint8_t)0x12U) /*!< December */ - -#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ -#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ -#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ -#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ - -#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ -#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ - -/* ctl register value */ -#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ -#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ -#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ - -#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ -#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ -#define RTC_ALARM_HIGH RTC_OS_ENABLE /*!< enable alarm flag output with high level */ -#define RTC_ALARM_LOW (RTC_OS_ENABLE | RTC_CTL_OPOL) /*!< enable alarm flag output with low level*/ - -#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ -#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ - -#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ -#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ - -/* psc register value */ -#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ -#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ - -#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ -#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ - -/* alrm0td register value */ -#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ -#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ - -#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ -#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ - -#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ -#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ - -#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ -#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ - -#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ -#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ -#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ -#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ -#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ -#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ - -#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ -#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ - -/* wpk register value */ -#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ - -/* ss register value */ -#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ - -/* shiftctl register value */ -#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ - -#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ -#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ - -/* tts register value */ -#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ -#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ - -#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ -#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ - -#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ -#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ - -/* dts register value */ -#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ -#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ - -#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ -#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ - -#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ -#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ - -/* ssts register value */ -#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ - -/* hrfc register value */ -#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ - -#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ -#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ - -#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ -#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ - -/* tamp register value */ -#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ -#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ -#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ - -#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ -#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ -#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ -#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ -#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ - -#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ -#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ -#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ - -#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ -#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ - -#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ -#define RTC_TAMPER_TRIGGER_EDGE_FALLING ((uint32_t)0x00000001U) /*!< tamper detection is in falling edge mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ -#define RTC_TAMPER_TRIGGER_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< tamper detection is in high level mode */ - -#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ - -#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ -#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ - -/* alrm0ss register value */ -#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ - -#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ -#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ -#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ -#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ -#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ -#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ -#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ -#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ -#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ -#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ -#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ -#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ -#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ -#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ -#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ -#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ -#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ - -/* RTC interrupt source */ -#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ -#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ -#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ - -/* write protect key */ -#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ -#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ -#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ - -/* registers reset value */ -#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ -#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ -#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ -#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ - -/* RTC timeout value */ -#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ -#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ -#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ -#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ -#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ - -/* RTC flag */ -#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ -#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ -#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ -#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ -#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ -#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ -#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ -#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ -#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ -#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ -#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ - -/* function declarations */ -/* reset most of the RTC registers */ -ErrStatus rtc_deinit(void); -/* initialize RTC registers */ -ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); -/* enter RTC init mode */ -ErrStatus rtc_init_mode_enter(void); -/* exit RTC init mode */ -void rtc_init_mode_exit(void); -/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ -ErrStatus rtc_register_sync_wait(void); - -/* get current time and date */ -void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); -/* get current subsecond value */ -uint32_t rtc_subsecond_get(void); - -/* configure RTC alarm */ -void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); -/* configure subsecond of RTC alarm */ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); -/* get RTC alarm */ -void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); -/* get RTC alarm subsecond */ -uint32_t rtc_alarm_subsecond_get(void); -/* enable RTC alarm */ -void rtc_alarm_enable(void); -/* disable RTC alarm */ -ErrStatus rtc_alarm_disable(void); - -/* enable RTC time-stamp */ -void rtc_timestamp_enable(uint32_t edge); -/* disable RTC time-stamp */ -void rtc_timestamp_disable(void); -/* get RTC timestamp time and date */ -void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); -/* get RTC time-stamp subsecond */ -uint32_t rtc_timestamp_subsecond_get(void); - -/* enable RTC tamper */ -void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); -/* disable RTC tamper */ -void rtc_tamper_disable(uint32_t source); - -/* enable specified RTC interrupt */ -void rtc_interrupt_enable(uint32_t interrupt); -/* disble specified RTC interrupt */ -void rtc_interrupt_disable(uint32_t interrupt); -/* check specified flag */ -FlagStatus rtc_flag_get(uint32_t flag); -/* clear specified flag */ -void rtc_flag_clear(uint32_t flag); -/* configure RTC alternate output source */ -void rtc_alter_output_config(uint32_t source, uint32_t mode); - -/* configure RTC calibration register */ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); -/* ajust the daylight saving time by adding or substracting one hour from the current time */ -void rtc_hour_adjust(uint32_t operation); -/* ajust RTC second or subsecond value of current time */ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); -/* enable RTC bypass shadow registers function */ -void rtc_bypass_shadow_enable(void); -/* disable RTC bypass shadow registers function */ -void rtc_bypass_shadow_disable(void); -/* enable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_enable(void); -/* disable RTC reference clock detection function */ -ErrStatus rtc_refclock_detection_disable(void); - -#endif /* GD32E23X_RTC_H */ +/*! + \file gd32e23x_rtc.h + \brief definitions for the RTC + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_RTC_H +#define GD32E23X_RTC_H + +#include "gd32e23x.h" + +/* RTC definitions */ +#define RTC RTC_BASE + +/* registers definitions */ +#define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */ +#define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */ +#define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */ +#define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */ +#define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */ +#define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */ +#define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */ +#define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */ +#define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */ +#define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */ +#define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */ +#define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */ +#define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */ +#define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */ +#define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */ +#define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */ +#define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */ +#define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */ +#define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */ +#define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */ + +/* bits definitions */ +/* RTC_TIME */ +#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DATE */ +#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */ +#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */ +#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */ + +/* RTC_CTL */ +#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */ +#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */ +#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */ +#define RTC_CTL_CS BIT(6) /*!< display format of clock system */ +#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */ +#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */ +#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */ +#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */ +#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */ +#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */ +#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */ +#define RTC_CTL_COS BIT(19) /*!< calibration output selection */ +#define RTC_CTL_OPOL BIT(20) /*!< output polarity */ +#define RTC_CTL_OS BITS(21,22) /*!< output selection */ +#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */ + +/* RTC_STAT */ +#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */ +#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */ +#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */ +#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */ +#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */ +#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */ +#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */ +#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */ +#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */ +#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */ +#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */ +#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */ + +/* RTC_PSC */ +#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */ +#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */ + +/* RTC_ALRM0TD */ +#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */ +#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */ +#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */ +#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */ +#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */ +#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */ +#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */ +#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */ +#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */ +#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */ +#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */ +#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */ + +/* RTC_WPK */ +#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */ + +/* RTC_SS */ +#define RTC_SS_SSC BITS(0,15) /*!< sub second value */ + +/* RTC_SHIFTCTL */ +#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */ +#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */ + +/* RTC_TTS */ +#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */ +#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */ +#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */ +#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */ +#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */ +#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */ +#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */ + +/* RTC_DTS */ +#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */ +#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */ +#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */ +#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */ +#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */ + +/* RTC_SSTS */ +#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */ + +/* RTC_HRFC */ +#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */ +#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */ +#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */ + +/* RTC_TAMP */ +#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */ +#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */ +#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */ +#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */ +#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */ +#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */ +#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */ +#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */ +#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */ +#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */ +#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */ +#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */ +#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */ +#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */ +#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */ +#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */ + +/* RTC_ALRM0SS */ +#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */ +#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */ + +/* RTC_BKP0 */ +#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP1 */ +#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP2 */ +#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP3 */ +#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */ + +/* RTC_BKP4 */ +#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */ + +/* constants definitions */ +/* structure for initialization of the RTC */ +typedef struct +{ + uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */ + uint8_t rtc_month; /*!< RTC month value */ + uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_day_of_week; /*!< RTC weekday value */ + uint8_t rtc_hour; /*!< RTC hour value */ + uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */ + uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */ + uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */ + uint32_t rtc_am_pm; /*!< RTC AM/PM value */ + uint32_t rtc_display_format; /*!< RTC time notation */ +}rtc_parameter_struct; + +/* structure for RTC alarm configuration */ +typedef struct +{ + uint32_t rtc_alarm_mask; /*!< RTC alarm mask */ + uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */ + uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/ + uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */ + uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */ +}rtc_alarm_struct; + +/* structure for RTC time-stamp configuration */ +typedef struct +{ + uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */ + uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */ + uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */ + uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */ + uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */ + uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */ + uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */ +}rtc_timestamp_struct; + +/* structure for RTC tamper configuration */ +typedef struct +{ + uint32_t rtc_tamper_source; /*!< RTC tamper source */ + uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */ + uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */ + uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */ + ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */ + uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */ + ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */ +}rtc_tamper_struct; + +/* time register value */ +#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */ +#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */ + +#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */ +#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */ + +#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */ +#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */ + +#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */ +#define RTC_PM RTC_TIME_PM /*!< PM format */ + +/* date register value */ +#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */ +#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */ + +#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */ +#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */ +#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */ +#define RTC_FEB ((uint8_t)0x02U) /*!< February */ +#define RTC_MAR ((uint8_t)0x03U) /*!< March */ +#define RTC_APR ((uint8_t)0x04U) /*!< April */ +#define RTC_MAY ((uint8_t)0x05U) /*!< May */ +#define RTC_JUN ((uint8_t)0x06U) /*!< June */ +#define RTC_JUL ((uint8_t)0x07U) /*!< July */ +#define RTC_AUG ((uint8_t)0x08U) /*!< August */ +#define RTC_SEP ((uint8_t)0x09U) /*!< September */ +#define RTC_OCT ((uint8_t)0x10U) /*!< October */ +#define RTC_NOV ((uint8_t)0x11U) /*!< November */ +#define RTC_DEC ((uint8_t)0x12U) /*!< December */ + +#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */ +#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */ +#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */ +#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ +#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */ +#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */ +#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */ +#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ +#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ + +#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */ +#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */ + +/* ctl register value */ +#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */ +#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */ +#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */ + +#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */ +#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */ +#define RTC_ALARM_HIGH RTC_OS_ENABLE /*!< enable alarm flag output with high level */ +#define RTC_ALARM_LOW (RTC_OS_ENABLE | RTC_CTL_OPOL) /*!< enable alarm flag output with low level*/ + +#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */ +#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */ + +#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */ +#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */ + +/* psc register value */ +#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */ +#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */ + +#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */ +#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */ + +/* alrm0td register value */ +#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */ +#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */ + +#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */ +#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */ + +#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */ +#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */ + +#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */ +#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */ + +#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */ +#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */ +#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */ +#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */ +#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */ +#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */ + +#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */ +#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */ + +/* wpk register value */ +#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */ + +/* ss register value */ +#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */ + +/* shiftctl register value */ +#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */ + +#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */ +#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */ + +/* tts register value */ +#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */ +#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */ + +#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */ +#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */ + +#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */ +#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */ + +/* dts register value */ +#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */ +#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */ + +#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */ +#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */ + +#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */ +#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */ + +/* ssts register value */ +#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */ + +/* hrfc register value */ +#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */ + +#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */ +#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */ + +#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */ +#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */ + +/* tamp register value */ +#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */ +#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */ +#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */ + +#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */ +#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */ +#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */ +#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */ +#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */ + +#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */ +#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */ +#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */ + +#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */ +#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */ + +#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */ +#define RTC_TAMPER_TRIGGER_EDGE_FALLING ((uint32_t)0x00000001U) /*!< tamper detection is in falling edge mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */ +#define RTC_TAMPER_TRIGGER_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< tamper detection is in high level mode */ + +#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */ + +#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */ +#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */ + +/* alrm0ss register value */ +#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */ + +#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */ +#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */ +#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */ +#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */ +#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */ +#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */ +#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */ +#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */ +#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */ +#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */ +#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */ +#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */ +#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */ +#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */ +#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */ +#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */ +#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */ + +/* RTC interrupt source */ +#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */ +#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */ +#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */ + +/* write protect key */ +#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */ +#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */ +#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */ + +/* registers reset value */ +#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */ +#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */ +#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */ +#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */ + +/* RTC timeout value */ +#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */ +#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */ +#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */ +#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */ +#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */ + +/* RTC flag */ +#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */ +#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */ +#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */ +#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */ +#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */ +#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */ +#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */ +#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */ +#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */ +#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */ +#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */ + +/* function declarations */ +/* reset most of the RTC registers */ +ErrStatus rtc_deinit(void); +/* initialize RTC registers */ +ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct); +/* enter RTC init mode */ +ErrStatus rtc_init_mode_enter(void); +/* exit RTC init mode */ +void rtc_init_mode_exit(void); +/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */ +ErrStatus rtc_register_sync_wait(void); + +/* get current time and date */ +void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct); +/* get current subsecond value */ +uint32_t rtc_subsecond_get(void); + +/* configure RTC alarm */ +void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time); +/* configure subsecond of RTC alarm */ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond); +/* get RTC alarm */ +void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time); +/* get RTC alarm subsecond */ +uint32_t rtc_alarm_subsecond_get(void); +/* enable RTC alarm */ +void rtc_alarm_enable(void); +/* disable RTC alarm */ +ErrStatus rtc_alarm_disable(void); + +/* enable RTC time-stamp */ +void rtc_timestamp_enable(uint32_t edge); +/* disable RTC time-stamp */ +void rtc_timestamp_disable(void); +/* get RTC timestamp time and date */ +void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp); +/* get RTC time-stamp subsecond */ +uint32_t rtc_timestamp_subsecond_get(void); + +/* enable RTC tamper */ +void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper); +/* disable RTC tamper */ +void rtc_tamper_disable(uint32_t source); + +/* enable specified RTC interrupt */ +void rtc_interrupt_enable(uint32_t interrupt); +/* disble specified RTC interrupt */ +void rtc_interrupt_disable(uint32_t interrupt); +/* check specified flag */ +FlagStatus rtc_flag_get(uint32_t flag); +/* clear specified flag */ +void rtc_flag_clear(uint32_t flag); +/* configure RTC alternate output source */ +void rtc_alter_output_config(uint32_t source, uint32_t mode); + +/* configure RTC calibration register */ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus); +/* ajust the daylight saving time by adding or substracting one hour from the current time */ +void rtc_hour_adjust(uint32_t operation); +/* ajust RTC second or subsecond value of current time */ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus); +/* enable RTC bypass shadow registers function */ +void rtc_bypass_shadow_enable(void); +/* disable RTC bypass shadow registers function */ +void rtc_bypass_shadow_disable(void); +/* enable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_enable(void); +/* disable RTC reference clock detection function */ +ErrStatus rtc_refclock_detection_disable(void); + +#endif /* GD32E23X_RTC_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_spi.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_spi.h index 1ba94dc..1e4ceb6 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_spi.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_spi.h @@ -1,433 +1,433 @@ -/*! - \file gd32e23x_spi.h - \brief definitions for the SPI - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_SPI_H -#define GD32E23X_SPI_H - -#include "gd32e23x.h" - -/* SPIx(x=0,1) definitions */ -#define SPI0 (SPI_BASE + 0x0000F800U) -#define SPI1 SPI_BASE - -/* registers definitions */ -#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ -#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ -#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ -#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ -#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ -#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ -#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ -#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ -#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ -#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI1) */ - -/* bits definitions */ -/* SPI_CTL0 */ -#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */ -#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ -#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ -#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ -#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ -#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ -#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ -#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ -#define SPI_CTL0_RO BIT(10) /*!< receive only */ -/* only available in SPI0*/ -#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ -/* only available in SPI1*/ -#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */ -#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ -#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ -#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ -#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ - -/* SPI_CTL1 */ -#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */ -#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */ -#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ -#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ -#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ -#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ -#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ -#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ -/* only available in SPI1 */ -#define SPI_CTL1_DZ BITS(8,11) /*!< data size */ -#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */ -#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */ -#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */ - -/* SPI_STAT */ -#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ -#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ -#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ -#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ -#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ -#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ -#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ -#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ -#define SPI_STAT_FERR BIT(8) /*!< format error bit */ -/* only available in SPI1 */ -#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */ -#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */ - -/* SPI_DATA */ -#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ - -/* SPI_CRCPOLY */ -#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ - -/* SPI_RCRC */ -#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ - -/* SPI_TCRC */ -#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ - -/* SPI_I2SCTL */ -#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ -#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ -#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ -#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ -#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ -#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ -#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ -#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ - -/* SPI_I2SPSC */ -#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ -#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ -#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ - -/* SPI_QCTL(only available in SPI1) */ -#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ -#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ -#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ - -/* constants definitions */ -/* SPI and I2S parameter struct definitions */ -typedef struct { - uint32_t device_mode; /*!< SPI master or slave */ - uint32_t trans_mode; /*!< SPI transfer type */ - uint32_t frame_size; /*!< SPI frame size */ - uint32_t nss; /*!< SPI NSS control by handware or software */ - uint32_t endian; /*!< SPI big endian or little endian */ - uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ - uint32_t prescale; /*!< SPI prescaler factor */ -} spi_parameter_struct; - -/* SPI mode definitions */ -#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ -#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ - -/* SPI bidirectional transfer direction */ -#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ -#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ - -/* SPI transmit type */ -#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ -#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ -#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ -#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ - -/* SPI NSS control mode */ -#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ -#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ - -/* SPI transmit way */ -#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ -#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ - -/* SPI clock phase and polarity */ -#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ -#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ -#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ -#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ - -/* SPI clock prescaler factor */ -#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) -#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */ -#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */ -#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */ -#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */ -#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */ -#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */ -#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */ -#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */ - -/* SPIx frame size */ -#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) -#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */ -#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */ -#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */ -#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */ -#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */ -#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */ -#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */ -#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */ -#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */ -#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */ -#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */ -#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */ -#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */ - -/* SPIx CRC length(x=1) */ -#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */ -#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */ - -/* SPIx byte access enable(x=1) */ -#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */ -#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */ - -/* SPIx odd bytes in TX DMA channel(x=1) */ -#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */ -#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */ - -/* SPIx odd bytes in RX DMA channel(x=1) */ -#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */ -#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */ - -/* SPIx TXFIFO level(x=1) */ -#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) -#define SPI_TXLVL_EMPTY CTL1_TXLVL(0) /*!< SPI TXFIFO is empty */ -#define SPI_TXLVL_QUARTER_FULL CTL1_TXLVL(1) /*!< SPI TXFIFO is a quarter of full */ -#define SPI_TXLVL_HAlF_FULL CTL1_TXLVL(2) /*!< SPI TXFIFO is a half of full */ -#define SPI_TXLVL_FULL CTL1_TXLVL(3) /*!< SPI TXFIFO is full */ - -/* SPIx RXFIFO level(x=1) */ -#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */ -#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */ -#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */ -#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */ - -/* I2S audio sample rate */ -#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ -#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ -#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ -#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ -#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ -#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ -#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ -#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ -#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ - -/* I2S frame format */ -#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) -#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ -#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ -#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ - -/* I2S master clock output */ -#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ -#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ - -/* I2S operation mode */ -#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) -#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ -#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ -#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ -#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ - -/* I2S standard */ -#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) -#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */ -#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ -#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ -#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ -#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ - -/* I2S clock polarity */ -#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ -#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ - -/* SPI DMA constants definitions */ -#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ -#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ - -/* SPI CRC constants definitions */ -#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ -#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ - -/* SPI/I2S interrupt enable/disable constants definitions */ -#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */ -#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */ -#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */ - -/* SPI/I2S interrupt flag constants definitions */ -#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ -#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ -#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ -#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ -#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ -#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ - -/* SPI/I2S flag definitions */ -#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ -#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ -#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ -#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ -#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ -#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ -#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ -#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ -#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ -#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ -#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ -/* only for SPI1 */ -#define SPI_FLAG_TXLVL_EMPTY ((uint32_t)0x10000000) /*!< SPI TXFIFO is empty */ -#define SPI_FLAG_TXLVL_QUARTER_FULL SPI_TXLVL_QUARTER_FULL /*!< SPI TXFIFO is a quarter of full */ -#define SPI_FLAG_TXLVL_HAlF_FULL SPI_TXLVL_HAlF_FULL /*!< SPI TXFIFO is a half of full */ -#define SPI_FLAG_TXLVL_FULL SPI_TXLVL_FULL /*!< SPI TXFIFO is full */ -#define SPI_FLAG_RXLVL_EMPTY ((uint32_t)0x20000000) /*!< SPI RXFIFO is empty */ -#define SPI_FLAG_RXLVL_QUARTER_FULL SPI_RXLVL_QUARTER_FULL /*!< SPI RXFIFO is a quarter of full */ -#define SPI_FLAG_RXLVL_HAlF_FULL SPI_RXLVL_HAlF_FULL /*!< SPI RXFIFO is a half of full */ -#define SPI_FLAG_RXLVL_FULL SPI_RXLVL_FULL /*!< SPI RXFIFO is full */ - -/* function declarations */ -/* SPI deinitialization and initialization functions */ -/* reset SPI and I2S */ -void spi_i2s_deinit(uint32_t spi_periph); -/* initialize the parameters of SPI structure with the default values */ -void spi_struct_para_init(spi_parameter_struct *spi_struct); -/* initialize SPI parameters */ -ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); -/* enable SPI */ -void spi_enable(uint32_t spi_periph); -/* disable SPI */ -void spi_disable(uint32_t spi_periph); - -/* I2S initialization functions */ -/* initialize I2S parameters */ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); -/* configure I2S prescaler */ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); -/* enable I2S */ -void i2s_enable(uint32_t spi_periph); -/* disable I2S */ -void i2s_disable(uint32_t spi_periph); - -/* NSS functions */ -/* enable SPI NSS output */ -void spi_nss_output_enable(uint32_t spi_periph); -/* disable SPI NSS output */ -void spi_nss_output_disable(uint32_t spi_periph); -/* SPI NSS pin high level in software mode */ -void spi_nss_internal_high(uint32_t spi_periph); -/* SPI NSS pin low level in software mode */ -void spi_nss_internal_low(uint32_t spi_periph); - -/* DMA functions */ -/* enable SPI DMA */ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma); -/* disable SPI DMA */ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma); -/* configure SPI total number of data to be transmitted by DMA is odd or not */ -void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd); -/* configure SPI total number of data to be received by DMA is odd or not */ -void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd); - -/* communication functions */ -/* configure SPI data frame format */ -ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); -/* configure SPI access size to FIFO(8-bit or 16-bit) */ -void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size); -/* configure SPI bidirectional transfer direction */ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); -/* SPI transmit data */ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); -/* SPI receive data */ -uint16_t spi_i2s_data_receive(uint32_t spi_periph); -/* clear TI Mode Format Error flag status */ -void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag); - -/* SPI CRC functions */ -/* set SPI CRC polynomial */ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); -/* get SPI CRC polynomial */ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph); -/* set CRC length */ -void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length); -/* turn on SPI CRC function */ -void spi_crc_on(uint32_t spi_periph); -/* turn off SPI CRC function */ -void spi_crc_off(uint32_t spi_periph); -/* SPI next data is CRC value */ -void spi_crc_next(uint32_t spi_periph); -/* get SPI CRC send value or receive value */ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); -/* clear SPI CRC error flag status */ -void spi_crc_error_clear(uint32_t spi_periph); - -/* SPI TI mode functions */ -/* enable SPI TI mode */ -void spi_ti_mode_enable(uint32_t spi_periph); -/* disable SPI TI mode */ -void spi_ti_mode_disable(uint32_t spi_periph); - -/* SPI NSS pulse mode functions */ -/* enable SPI NSS pulse mode */ -void spi_nssp_mode_enable(uint32_t spi_periph); -/* disable SPI NSS pulse mode */ -void spi_nssp_mode_disable(uint32_t spi_periph); - -/* quad wire SPI functions */ -/* enable quad wire SPI */ -void spi_quad_enable(uint32_t spi_periph); -/* disable quad wire SPI */ -void spi_quad_disable(uint32_t spi_periph); -/* enable quad wire SPI write */ -void spi_quad_write_enable(uint32_t spi_periph); -/* enable quad wire SPI read */ -void spi_quad_read_enable(uint32_t spi_periph); -/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ -void spi_quad_io23_output_enable(uint32_t spi_periph); -/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ -void spi_quad_io23_output_disable(uint32_t spi_periph); - -/* flag and interrupt functions */ -/* get SPI and I2S flag status */ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); -/* enable SPI and I2S interrupt */ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); -/* disable SPI and I2S interrupt */ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); -/* get SPI and I2S interrupt status */ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); - -#endif /* GD32E23X_SPI_H */ +/*! + \file gd32e23x_spi.h + \brief definitions for the SPI + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_SPI_H +#define GD32E23X_SPI_H + +#include "gd32e23x.h" + +/* SPIx(x=0,1) definitions */ +#define SPI0 (SPI_BASE + 0x0000F800U) +#define SPI1 SPI_BASE + +/* registers definitions */ +#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */ +#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/ +#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */ +#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */ +#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */ +#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */ +#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */ +#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */ +#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */ +#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI1) */ + +/* bits definitions */ +/* SPI_CTL0 */ +#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */ +#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ +#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ +#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ +#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ +#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ +#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ +#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ +#define SPI_CTL0_RO BIT(10) /*!< receive only */ +/* only available in SPI0*/ +#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ +/* only available in SPI1*/ +#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */ +#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ +#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ +#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ +#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ + +/* SPI_CTL1 */ +#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */ +#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */ +#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ +#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ +#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ +#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ +#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ +#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ +/* only available in SPI1 */ +#define SPI_CTL1_DZ BITS(8,11) /*!< data size */ +#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */ +#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */ +#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */ + +/* SPI_STAT */ +#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ +#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ +#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ +#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ +#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ +#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ +#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ +#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ +#define SPI_STAT_FERR BIT(8) /*!< format error bit */ +/* only available in SPI1 */ +#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */ +#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */ + +/* SPI_DATA */ +#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ + +/* SPI_CRCPOLY */ +#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ + +/* SPI_RCRC */ +#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ + +/* SPI_TCRC */ +#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ + +/* SPI_I2SCTL */ +#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ +#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ +#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ +#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ +#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ +#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ +#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ +#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ + +/* SPI_I2SPSC */ +#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ +#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ +#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ + +/* SPI_QCTL(only available in SPI1) */ +#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ +#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ +#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ + +/* constants definitions */ +/* SPI and I2S parameter struct definitions */ +typedef struct { + uint32_t device_mode; /*!< SPI master or slave */ + uint32_t trans_mode; /*!< SPI transfer type */ + uint32_t frame_size; /*!< SPI frame size */ + uint32_t nss; /*!< SPI NSS control by handware or software */ + uint32_t endian; /*!< SPI big endian or little endian */ + uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ + uint32_t prescale; /*!< SPI prescaler factor */ +} spi_parameter_struct; + +/* SPI mode definitions */ +#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ +#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ + +/* SPI bidirectional transfer direction */ +#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ +#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ + +/* SPI transmit type */ +#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ +#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ +#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ +#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ + +/* SPI NSS control mode */ +#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ +#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ + +/* SPI transmit way */ +#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ +#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ + +/* SPI clock phase and polarity */ +#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ +#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ +#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ +#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ + +/* SPI clock prescaler factor */ +#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) +#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */ +#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */ +#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */ +#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */ +#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */ +#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */ +#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */ +#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */ + +/* SPIx frame size */ +#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) +#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */ +#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */ +#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */ +#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */ +#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */ +#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */ +#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */ +#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */ +#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */ +#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */ +#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */ +#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */ +#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */ + +/* SPIx CRC length(x=1) */ +#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */ +#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */ + +/* SPIx byte access enable(x=1) */ +#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */ +#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */ + +/* SPIx odd bytes in TX DMA channel(x=1) */ +#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */ +#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */ + +/* SPIx odd bytes in RX DMA channel(x=1) */ +#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */ +#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */ + +/* SPIx TXFIFO level(x=1) */ +#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) +#define SPI_TXLVL_EMPTY CTL1_TXLVL(0) /*!< SPI TXFIFO is empty */ +#define SPI_TXLVL_QUARTER_FULL CTL1_TXLVL(1) /*!< SPI TXFIFO is a quarter of full */ +#define SPI_TXLVL_HAlF_FULL CTL1_TXLVL(2) /*!< SPI TXFIFO is a half of full */ +#define SPI_TXLVL_FULL CTL1_TXLVL(3) /*!< SPI TXFIFO is full */ + +/* SPIx RXFIFO level(x=1) */ +#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */ +#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */ +#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */ +#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */ + +/* I2S audio sample rate */ +#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ +#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ +#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ +#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ +#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ +#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ +#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ +#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ +#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ + +/* I2S frame format */ +#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) +#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ +#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ +#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ + +/* I2S master clock output */ +#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ +#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ + +/* I2S operation mode */ +#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) +#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ +#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ +#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ +#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ + +/* I2S standard */ +#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) +#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */ +#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ +#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ +#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ +#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ + +/* I2S clock polarity */ +#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ +#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ + +/* SPI DMA constants definitions */ +#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ +#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ + +/* SPI CRC constants definitions */ +#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ +#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ + +/* SPI/I2S interrupt enable/disable constants definitions */ +#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */ +#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */ +#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */ + +/* SPI/I2S interrupt flag constants definitions */ +#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ +#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ +#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ +#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ +#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ +#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ + +/* SPI/I2S flag definitions */ +#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ +#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ +#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ +#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ +#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ +#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ +#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ +#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ +#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ +#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ +#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */ +/* only for SPI1 */ +#define SPI_FLAG_TXLVL_EMPTY ((uint32_t)0x10000000) /*!< SPI TXFIFO is empty */ +#define SPI_FLAG_TXLVL_QUARTER_FULL SPI_TXLVL_QUARTER_FULL /*!< SPI TXFIFO is a quarter of full */ +#define SPI_FLAG_TXLVL_HAlF_FULL SPI_TXLVL_HAlF_FULL /*!< SPI TXFIFO is a half of full */ +#define SPI_FLAG_TXLVL_FULL SPI_TXLVL_FULL /*!< SPI TXFIFO is full */ +#define SPI_FLAG_RXLVL_EMPTY ((uint32_t)0x20000000) /*!< SPI RXFIFO is empty */ +#define SPI_FLAG_RXLVL_QUARTER_FULL SPI_RXLVL_QUARTER_FULL /*!< SPI RXFIFO is a quarter of full */ +#define SPI_FLAG_RXLVL_HAlF_FULL SPI_RXLVL_HAlF_FULL /*!< SPI RXFIFO is a half of full */ +#define SPI_FLAG_RXLVL_FULL SPI_RXLVL_FULL /*!< SPI RXFIFO is full */ + +/* function declarations */ +/* SPI deinitialization and initialization functions */ +/* reset SPI and I2S */ +void spi_i2s_deinit(uint32_t spi_periph); +/* initialize the parameters of SPI structure with the default values */ +void spi_struct_para_init(spi_parameter_struct *spi_struct); +/* initialize SPI parameters */ +ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct); +/* enable SPI */ +void spi_enable(uint32_t spi_periph); +/* disable SPI */ +void spi_disable(uint32_t spi_periph); + +/* I2S initialization functions */ +/* initialize I2S parameters */ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); +/* configure I2S prescaler */ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); +/* enable I2S */ +void i2s_enable(uint32_t spi_periph); +/* disable I2S */ +void i2s_disable(uint32_t spi_periph); + +/* NSS functions */ +/* enable SPI NSS output */ +void spi_nss_output_enable(uint32_t spi_periph); +/* disable SPI NSS output */ +void spi_nss_output_disable(uint32_t spi_periph); +/* SPI NSS pin high level in software mode */ +void spi_nss_internal_high(uint32_t spi_periph); +/* SPI NSS pin low level in software mode */ +void spi_nss_internal_low(uint32_t spi_periph); + +/* DMA functions */ +/* enable SPI DMA */ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma); +/* disable SPI DMA */ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma); +/* configure SPI total number of data to be transmitted by DMA is odd or not */ +void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd); +/* configure SPI total number of data to be received by DMA is odd or not */ +void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd); + +/* communication functions */ +/* configure SPI data frame format */ +ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); +/* configure SPI access size to FIFO(8-bit or 16-bit) */ +void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size); +/* configure SPI bidirectional transfer direction */ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); +/* SPI transmit data */ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); +/* SPI receive data */ +uint16_t spi_i2s_data_receive(uint32_t spi_periph); +/* clear TI Mode Format Error flag status */ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag); + +/* SPI CRC functions */ +/* set SPI CRC polynomial */ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); +/* get SPI CRC polynomial */ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph); +/* set CRC length */ +void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length); +/* turn on SPI CRC function */ +void spi_crc_on(uint32_t spi_periph); +/* turn off SPI CRC function */ +void spi_crc_off(uint32_t spi_periph); +/* SPI next data is CRC value */ +void spi_crc_next(uint32_t spi_periph); +/* get SPI CRC send value or receive value */ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); +/* clear SPI CRC error flag status */ +void spi_crc_error_clear(uint32_t spi_periph); + +/* SPI TI mode functions */ +/* enable SPI TI mode */ +void spi_ti_mode_enable(uint32_t spi_periph); +/* disable SPI TI mode */ +void spi_ti_mode_disable(uint32_t spi_periph); + +/* SPI NSS pulse mode functions */ +/* enable SPI NSS pulse mode */ +void spi_nssp_mode_enable(uint32_t spi_periph); +/* disable SPI NSS pulse mode */ +void spi_nssp_mode_disable(uint32_t spi_periph); + +/* quad wire SPI functions */ +/* enable quad wire SPI */ +void spi_quad_enable(uint32_t spi_periph); +/* disable quad wire SPI */ +void spi_quad_disable(uint32_t spi_periph); +/* enable quad wire SPI write */ +void spi_quad_write_enable(uint32_t spi_periph); +/* enable quad wire SPI read */ +void spi_quad_read_enable(uint32_t spi_periph); +/* enable quad wire SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_enable(uint32_t spi_periph); +/* disable quad wire SPI_IO2 and SPI_IO3 pin output */ +void spi_quad_io23_output_disable(uint32_t spi_periph); + +/* flag and interrupt functions */ +/* get SPI and I2S flag status */ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); +/* enable SPI and I2S interrupt */ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); +/* disable SPI and I2S interrupt */ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); +/* get SPI and I2S interrupt status */ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); + +#endif /* GD32E23X_SPI_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_syscfg.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_syscfg.h index f513184..1d6d908 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_syscfg.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_syscfg.h @@ -1,185 +1,185 @@ -/*! - \file gd32e23x_syscfg.h - \brief definitions for the SYSCFG - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_SYSCFG_H -#define GD32E23X_SYSCFG_H - -#include "gd32e23x.h" - -/* SYSCFG definitions */ -#define SYSCFG SYSCFG_BASE - -/* registers definitions */ -#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ -#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ -#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ -#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ -#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ -#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */ -#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */ - -/* SYSCFG_CFG0 bits definitions */ -#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ -#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */ -#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ -#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ -#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ -#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ -#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ -#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ - -/* SYSCFG_EXTISS0 bits definitions */ -#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ -#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ -#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ -#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ - -/* SYSCFG_EXTISS1 bits definitions */ -#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ -#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ -#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ -#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ - -/* SYSCFG_EXTISS2 bits definitions */ -#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ -#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ -#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ -#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ - -/* SYSCFG_EXTISS3 bits definitions */ -#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ -#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ -#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ -#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ - -/* SYSCFG_CFG2 bits definitions */ -#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ -#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ -#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ - -/* SYSCFG_CPU_IRQ_LAT bits definitions */ -#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */ - -/* constants definitions */ -/* DMA remap definitions */ -#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */ -#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ -#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ -#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ -#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ - -/* high current definitions */ -#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ -#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ - -/* EXTI source select definition */ -#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ -#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ -#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ -#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ - -/* EXTI source select mask bits definition */ -#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ - -/* EXTI source select jumping step definition */ -#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ - -/* EXTI source select moving step definition */ -#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ - -/* EXTI source port definitions */ -#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ -#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ -#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ -#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ - -/* EXTI source pin definitions */ -#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ -#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ -#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ -#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ -#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ -#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ -#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ -#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ -#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ -#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ -#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ -#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ -#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ -#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ -#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ -#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ - -/* lock definitions */ -#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ -#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ -#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ - -/* SRAM parity check error flag definitions */ -#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ - -/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */ -#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */ - -/* function declarations */ -/* deinit syscfg module */ -void syscfg_deinit(void); - -/* enable the DMA channels remapping */ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); -/* disable the DMA channels remapping */ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); - -/* enable PB9 high current capability */ -void syscfg_high_current_enable(void); -/* disable PB9 high current capability */ -void syscfg_high_current_disable(void); - -/* configure the GPIO pin as EXTI Line */ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); -/* connect TIMER0/14/15/16 break input to the selected parameter */ -void syscfg_lock_config(uint32_t syscfg_lock); - -/* set the IRQ_LATENCY value */ -void irq_latency_set(uint8_t irq_latency); - -/* check if the specified flag in SYSCFG_CFG2 is set or not */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag); -/* clear the flag in SYSCFG_CFG2 by writing 1 */ -void syscfg_flag_clear(uint32_t syscfg_flag); - -#endif /* GD32E23X_SYSCFG_H */ +/*! + \file gd32e23x_syscfg.h + \brief definitions for the SYSCFG + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_SYSCFG_H +#define GD32E23X_SYSCFG_H + +#include "gd32e23x.h" + +/* SYSCFG definitions */ +#define SYSCFG SYSCFG_BASE + +/* registers definitions */ +#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */ +#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */ +#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */ +#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */ +#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */ +#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */ +#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */ + +/* SYSCFG_CFG0 bits definitions */ +#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */ +#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */ +#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */ +#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */ +#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */ +#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */ +#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */ +#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */ + +/* SYSCFG_EXTISS0 bits definitions */ +#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */ +#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */ +#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */ +#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */ + +/* SYSCFG_EXTISS1 bits definitions */ +#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */ +#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */ +#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */ +#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */ + +/* SYSCFG_EXTISS2 bits definitions */ +#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */ +#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */ +#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */ +#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */ + +/* SYSCFG_EXTISS3 bits definitions */ +#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */ +#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */ +#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */ +#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */ + +/* SYSCFG_CFG2 bits definitions */ +#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */ +#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */ +#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */ + +/* SYSCFG_CPU_IRQ_LAT bits definitions */ +#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */ + +/* constants definitions */ +/* DMA remap definitions */ +#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */ +#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */ +#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */ +#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */ +#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */ + +/* high current definitions */ +#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */ +#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */ + +/* EXTI source select definition */ +#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */ +#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */ +#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */ +#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */ + +/* EXTI source select mask bits definition */ +#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */ + +/* EXTI source select jumping step definition */ +#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */ + +/* EXTI source select moving step definition */ +#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */ + +/* EXTI source port definitions */ +#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */ +#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */ +#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */ +#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */ + +/* EXTI source pin definitions */ +#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */ +#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */ +#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */ +#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */ +#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */ +#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */ +#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */ +#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */ +#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */ +#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */ +#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */ +#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */ +#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */ +#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */ +#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */ +#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */ + +/* lock definitions */ +#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */ +#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */ +#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */ + +/* SRAM parity check error flag definitions */ +#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */ + +/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */ +#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */ + +/* function declarations */ +/* deinit syscfg module */ +void syscfg_deinit(void); + +/* enable the DMA channels remapping */ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap); +/* disable the DMA channels remapping */ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap); + +/* enable PB9 high current capability */ +void syscfg_high_current_enable(void); +/* disable PB9 high current capability */ +void syscfg_high_current_disable(void); + +/* configure the GPIO pin as EXTI Line */ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin); +/* connect TIMER0/14/15/16 break input to the selected parameter */ +void syscfg_lock_config(uint32_t syscfg_lock); + +/* set the IRQ_LATENCY value */ +void irq_latency_set(uint8_t irq_latency); + +/* check if the specified flag in SYSCFG_CFG2 is set or not */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag); +/* clear the flag in SYSCFG_CFG2 by writing 1 */ +void syscfg_flag_clear(uint32_t syscfg_flag); + +#endif /* GD32E23X_SYSCFG_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_timer.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_timer.h index 15f9990..a6abe44 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_timer.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_timer.h @@ -1,758 +1,758 @@ -/*! - \file gd32e23x_timer.h - \brief definitions for the TIMER - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_TIMER_H -#define GD32E23X_TIMER_H - -#include "gd32e23x.h" - -/* TIMERx(x=0,1,2,5,13..16) definitions */ -#define TIMER0 (TIMER_BASE + 0x00012C00U) -#define TIMER2 (TIMER_BASE + 0x00000400U) -#define TIMER5 (TIMER_BASE + 0x00001000U) -#define TIMER13 (TIMER_BASE + 0x00002000U) -#define TIMER14 (TIMER_BASE + 0x00014000U) -#define TIMER15 (TIMER_BASE + 0x00014400U) -#define TIMER16 (TIMER_BASE + 0x00014800U) - -/* registers definitions */ -#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ -#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ -#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ -#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ -#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ -#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ -#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ -#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ -#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ -#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ -#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ -#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ -#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ -#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ -#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ -#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ -#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ -#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ -#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ -#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ -#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ -#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ - -/* bits definitions */ -/* TIMER_CTL0 */ -#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ -#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ -#define TIMER_CTL0_UPS BIT(2) /*!< update source */ -#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ -#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ -#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ -#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ -#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ - -/* TIMER_CTL1 */ -#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ -#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ -#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ -#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ -#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ -#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ -#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ -#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ -#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ -#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ -#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ -#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ - -/* TIMER_SMCFG */ -#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ -#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ -#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ -#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ -#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ -#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ -#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ -#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ - -/* TIMER_DMAINTEN */ -#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ -#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ -#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ -#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ -#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ -#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ -#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ -#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ -#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ -#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ -#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ -#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ - -/* TIMER_INTF */ -#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ -#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ -#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ -#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ -#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ -#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ -#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ -#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ -#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ -#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ -#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ -#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ - -/* TIMER_SWEVG */ -#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ -#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ -#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ -#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ -#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ -#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ -#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ -#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ - -/* TIMER_CHCTL0 */ -/* output compare mode */ -#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ -#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ -#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ -#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ -#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ -#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ -#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ -#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ -#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ -#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ -#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ -#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ -#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ - -/* TIMER_CHCTL1 */ -/* output compare mode */ -#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ -#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ -#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ -#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ -#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ -#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ -#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ -#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ -#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ -#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ -/* input capture mode */ -#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ -#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ -#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ -#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ - -/* TIMER_CHCTL2 */ -#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ -#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ -#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ -#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ -#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ -#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ -#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ -#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ -#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ -#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ -#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ -#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ -#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ -#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ -#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ - -/* TIMER_CNT */ -#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ - -/* TIMER_PSC */ -#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ - -/* TIMER_CAR */ -#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ - -/* TIMER_CREP */ -#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ - -/* TIMER_CH0CV */ -#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ - -/* TIMER_CH1CV */ -#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ - -/* TIMER_CH2CV */ -#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ - -/* TIMER_CH3CV */ -#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ - -/* TIMER_CCHP */ -#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ -#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ -#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ -#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ -#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ -#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ -#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ -#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ - -/* TIMER_DMACFG */ -#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ -#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ - -/* TIMER_DMATB */ -#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ - -/* TIMER_IRMP */ -#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ - -/* TIMER_CFG */ -#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ -#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ - -/* constants definitions */ -/* TIMER init parameter struct definitions*/ -typedef struct -{ - uint16_t prescaler; /*!< prescaler value */ - uint16_t alignedmode; /*!< aligned mode */ - uint16_t counterdirection; /*!< counter direction */ - uint16_t clockdivision; /*!< clock division value */ - uint32_t period; /*!< period value */ - uint8_t repetitioncounter; /*!< the counter repetition value */ -}timer_parameter_struct; - -/* break parameter struct definitions*/ -typedef struct -{ - uint16_t runoffstate; /*!< run mode off-state */ - uint16_t ideloffstate; /*!< idle mode off-state */ - uint16_t deadtime; /*!< dead time */ - uint16_t breakpolarity; /*!< break polarity */ - uint16_t outputautostate; /*!< output automatic enable */ - uint16_t protectmode; /*!< complementary register protect control */ - uint16_t breakstate; /*!< break enable */ -}timer_break_parameter_struct; - -/* channel output parameter struct definitions */ -typedef struct -{ - uint16_t outputstate; /*!< channel output state */ - uint16_t outputnstate; /*!< channel complementary output state */ - uint16_t ocpolarity; /*!< channel output polarity */ - uint16_t ocnpolarity; /*!< channel complementary output polarity */ - uint16_t ocidlestate; /*!< idle state of channel output */ - uint16_t ocnidlestate; /*!< idle state of channel complementary output */ -}timer_oc_parameter_struct; - -/* channel input parameter struct definitions */ -typedef struct -{ - uint16_t icpolarity; /*!< channel input polarity */ - uint16_t icselection; /*!< channel input mode selection */ - uint16_t icprescaler; /*!< channel input capture prescaler */ - uint16_t icfilter; /*!< channel input capture filter control */ -}timer_ic_parameter_struct; - -/* TIMER interrupt enable or disable */ -#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ -#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ -#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ -#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ -#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ -#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ -#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ -#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ - -/* TIMER flag */ -#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ -#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ -#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ -#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ -#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ -#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ -#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ -#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ -#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ -#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ -#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ -#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ - -/* TIMER interrupt flag */ -#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ -#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ -#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ -#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ -#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ -#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ -#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ -#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF - -/* TIMER DMA source enable */ -#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ -#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ -#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ -#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ -#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ -#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ -#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ - -/* channel DMA request source selection */ -#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel y is sent when update event occurs */ -#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when channel y event occurs */ - -/* DMA access base address */ -#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) -#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ -#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ -#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ -#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ -#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ -#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ -#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ -#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ -#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ -#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ -#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ -#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ -#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ -#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ -#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ -#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ -#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ -#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ -#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ - -/* DMA access burst length */ -#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) -#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ -#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ -#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ -#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ -#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ -#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ -#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ -#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ -#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ -#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ -#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ -#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ -#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ -#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ -#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ -#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ -#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ -#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ - -/* TIMER software event generation source */ -#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ -#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ -#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ -#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ -#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ -#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ - -/* center-aligned mode selection */ -#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) -#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ -#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ -#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ -#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ - -/* TIMER prescaler reload mode */ -#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ -#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ - -/* count direction */ -#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ -#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ - -/* specify division ratio between TIMER clock and dead-time and sampling clock */ -#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ -#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ -#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ - -/* single pulse mode */ -#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ -#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ - -/* update source */ -#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ -#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ - -/* run mode off-state configure */ -#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* idle mode off-state configure */ -#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ -#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ - -/* break input polarity */ -#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ -#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ - -/* output automatic enable */ -#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ -#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ - -/* complementary register protect control */ -#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) -#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ -#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ -#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ -#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ - -/* break input enable */ -#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ -#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ - -/* TIMER channel n(n=0,1,2,3) */ -#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0,2,13..16)) */ -#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0,2,14)) */ -#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0,2)) */ -#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0,2)) */ -#define TIMER_CH_0_1 ((uint16_t)0x0004U) /*!< TIMER channel 0 and 1 for function parameter */ - -/* channel enable state*/ -#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ -#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ - -/* channel complementary output enable state*/ -#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ -#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ - -/* channel output polarity */ -#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ -#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ - -/* channel complementary output polarity */ -#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ -#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ - -/* idle state of channel output */ -#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ -#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ - -/* idle state of channel complementary output */ -#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ -#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ - -/* channel output compare mode */ -#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ -#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ -#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ -#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ -#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ -#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ -#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ -#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ - -/* channel output compare shadow enable */ -#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ -#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ - -/* channel output compare fast enable */ -#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ -#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ - -/* channel output compare clear enable */ -#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ -#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ - -/* channel control shadow register update control */ -#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ -#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers are updated when CMTG bit is set or an rising edge of TRGI occurs */ - -/* channel input capture polarity */ -#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ -#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ -#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ - -/* TIMER input capture selection */ -#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ -#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ -#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ - -/* channel input capture prescaler */ -#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ -#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ -#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ -#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ - -/* trigger selection */ -#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ -#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ -#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ -#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ -#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ -#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ -#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ -#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ - -/* master mode control */ -#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) -#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ -#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ -#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ -#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ -#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ -#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ - -/* slave mode control */ -#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) -#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ -#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ -#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ -#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ -#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ -#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ -#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ -#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ - -/* OCPRE clear source selection */ -#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ -#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ -#define TIMER_OCPRE_CLEAR_SOURCE_DISABLE ((uint8_t)0x02U) /*!< OCRC=0, and disable ETI */ - -/* master slave mode selection */ -#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ -#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ - -/* external trigger prescaler */ -#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) -#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ -#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ -#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ -#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ - -/* external trigger polarity */ -#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ -#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ - -/* channel 0 trigger input selection */ -#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ -#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ - -/* TIMERx(x=0,2,13,14,15,16) write cc register selection */ -#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ -#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ - -/* the output value selection */ -#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ -#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ - -/* timer13 channel 0 input remap */ -#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) -#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ -#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ -#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ -#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ - -/* function declarations */ -/* TIMER timebase*/ -/* deinit a TIMER */ -void timer_deinit(uint32_t timer_periph); -/* initialize TIMER init parameter struct */ -void timer_struct_para_init(timer_parameter_struct* initpara); -/* initialize TIMER counter */ -void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); -/* enable a TIMER */ -void timer_enable(uint32_t timer_periph); -/* disable a TIMER */ -void timer_disable(uint32_t timer_periph); -/* enable the auto reload shadow function */ -void timer_auto_reload_shadow_enable(uint32_t timer_periph); -/* disable the auto reload shadow function */ -void timer_auto_reload_shadow_disable(uint32_t timer_periph); -/* enable the update event */ -void timer_update_event_enable(uint32_t timer_periph); -/* disable the update event */ -void timer_update_event_disable(uint32_t timer_periph); -/* set TIMER counter alignment mode */ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); -/* set TIMER counter up direction */ -void timer_counter_up_direction(uint32_t timer_periph); -/* set TIMER counter down direction */ -void timer_counter_down_direction(uint32_t timer_periph); -/* configure TIMER prescaler */ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); -/* configure TIMER repetition register value */ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); -/* configure TIMER autoreload register value */ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); -/* configure TIMER counter register value */ -void timer_counter_value_config(uint32_t timer_periph , uint16_t counter); -/* read TIMER counter value */ -uint32_t timer_counter_read(uint32_t timer_periph); -/* read TIMER prescaler value */ -uint16_t timer_prescaler_read(uint32_t timer_periph); -/* configure TIMER single pulse mode */ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); -/* configure TIMER update source */ -void timer_update_source_config(uint32_t timer_periph, uint32_t update); -/* OCPRE clear source selection */ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); - -/* TIMER interrupt and flag*/ -/* enable the TIMER interrupt */ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); -/* disable the TIMER interrupt */ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); -/* get timer interrupt flag */ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); -/* clear TIMER interrupt flag */ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); -/* get TIMER flags */ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); -/* clear TIMER flags */ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag); - -/* timer DMA and event*/ -/* enable the TIMER DMA */ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma); -/* disable the TIMER DMA */ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma); -/* channel DMA request source selection */ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); -/* configure the TIMER DMA transfer */ -void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); -/* software generate events */ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event); - -/* TIMER channel complementary protection */ -/* initialize TIMER break parameter struct */ -void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); -/* configure TIMER break function */ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); -/* enable TIMER break function */ -void timer_break_enable(uint32_t timer_periph); -/* disable TIMER break function */ -void timer_break_disable(uint32_t timer_periph); -/* enable TIMER output automatic function */ -void timer_automatic_output_enable(uint32_t timer_periph); -/* disable TIMER output automatic function */ -void timer_automatic_output_disable(uint32_t timer_periph); -/* enable or disable TIMER primary output function */ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); -/* enable or disable channel capture/compare control shadow register */ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); -/* configure TIMER channel control shadow register update control */ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); - -/* TIMER channel output */ -/* initialize TIMER channel output parameter struct */ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output function */ -void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); -/* configure TIMER channel output compare mode */ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); -/* configure TIMER channel output pulse value */ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); -/* configure TIMER channel output shadow function */ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); -/* configure TIMER channel output fast function */ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); -/* configure TIMER channel output clear function */ -void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); -/* configure TIMER channel output polarity */ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); -/* configure TIMER channel complementary output polarity */ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); -/* configure TIMER channel enable state */ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); -/* configure TIMER channel complementary output enable state */ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); - -/* TIMER channel input */ -/* initialize TIMER channel input parameter struct */ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); -/* configure TIMER input capture parameter */ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); -/* configure TIMER channel input capture prescaler value */ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); -/* read TIMER channel capture compare register value */ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); -/* configure TIMER input pwm capture function */ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); -/* configure TIMER hall sensor mode */ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); - -/* TIMER master and slave */ -/* select TIMER input trigger source */ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); -/* select TIMER master mode output trigger source */ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); -/* select TIMER slave mode */ -void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); -/* configure TIMER master slave mode */ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); -/* configure TIMER external trigger input */ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER quadrature decoder mode */ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); -/* configure TIMER internal clock mode */ -void timer_internal_clock_config(uint32_t timer_periph); -/* configure TIMER the internal trigger as external clock input */ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); -/* configure TIMER the external trigger as external clock input */ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); -/* configure TIMER the external clock mode 0 */ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* configure TIMER the external clock mode 1 */ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); -/* disable TIMER the external clock mode 1 */ -void timer_external_clock_mode1_disable(uint32_t timer_periph); -/* configure TIMER channel remap function */ -void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); - -/* TIMER configure */ -/* configure TIMER write CHxVAL register selection */ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); -/* configure TIMER output value selection */ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); - -#endif /* GD32E23X_TIMER_H */ +/*! + \file gd32e23x_timer.h + \brief definitions for the TIMER + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_TIMER_H +#define GD32E23X_TIMER_H + +#include "gd32e23x.h" + +/* TIMERx(x=0,1,2,5,13..16) definitions */ +#define TIMER0 (TIMER_BASE + 0x00012C00U) +#define TIMER2 (TIMER_BASE + 0x00000400U) +#define TIMER5 (TIMER_BASE + 0x00001000U) +#define TIMER13 (TIMER_BASE + 0x00002000U) +#define TIMER14 (TIMER_BASE + 0x00014000U) +#define TIMER15 (TIMER_BASE + 0x00014400U) +#define TIMER16 (TIMER_BASE + 0x00014800U) + +/* registers definitions */ +#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ +#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ +#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ +#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ +#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ +#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ +#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ +#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ +#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ +#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ +#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ +#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ +#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ +#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ +#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ +#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ +#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ +#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */ +#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ +#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ +#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ +#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ + +/* bits definitions */ +/* TIMER_CTL0 */ +#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ +#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ +#define TIMER_CTL0_UPS BIT(2) /*!< update source */ +#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ +#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ +#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ +#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ +#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ + +/* TIMER_CTL1 */ +#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ +#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ +#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ +#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ +#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ +#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ +#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ +#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ +#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ +#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ +#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ +#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ + +/* TIMER_SMCFG */ +#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ +#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */ +#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ +#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ +#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ +#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ +#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ +#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ + +/* TIMER_DMAINTEN */ +#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ +#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ +#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ +#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ +#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ +#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ +#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */ +#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */ +#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */ +#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */ +#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ +#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ + +/* TIMER_INTF */ +#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ +#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ +#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ +#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ +#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ +#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ +#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ +#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ +#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ +#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ +#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ +#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ + +/* TIMER_SWEVG */ +#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ +#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ +#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ +#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ +#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ +#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ +#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ +#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ + +/* TIMER_CHCTL0 */ +/* output compare mode */ +#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ +#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ +#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ +#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */ +#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ +#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ +#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ +#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ +#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */ +#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ +#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ +#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ +#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ + +/* TIMER_CHCTL1 */ +/* output compare mode */ +#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ +#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ +#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ +#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */ +#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ +#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ +#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ +#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ +#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */ +#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ +/* input capture mode */ +#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ +#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ +#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ +#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ + +/* TIMER_CHCTL2 */ +#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ +#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ +#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ +#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ +#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ +#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ +#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ +#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ +#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ +#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ +#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ +#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ +#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ +#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ +#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ + +/* TIMER_CNT */ +#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */ + +/* TIMER_PSC */ +#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ + +/* TIMER_CAR */ +#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */ + +/* TIMER_CREP */ +#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ + +/* TIMER_CH0CV */ +#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ + +/* TIMER_CH1CV */ +#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ + +/* TIMER_CH2CV */ +#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ + +/* TIMER_CH3CV */ +#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ + +/* TIMER_CCHP */ +#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ +#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ +#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ +#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ +#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ +#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ +#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ +#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ + +/* TIMER_DMACFG */ +#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ +#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ + +/* TIMER_DMATB */ +#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ + +/* TIMER_IRMP */ +#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */ + +/* TIMER_CFG */ +#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ +#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ + +/* constants definitions */ +/* TIMER init parameter struct definitions*/ +typedef struct +{ + uint16_t prescaler; /*!< prescaler value */ + uint16_t alignedmode; /*!< aligned mode */ + uint16_t counterdirection; /*!< counter direction */ + uint16_t clockdivision; /*!< clock division value */ + uint32_t period; /*!< period value */ + uint8_t repetitioncounter; /*!< the counter repetition value */ +}timer_parameter_struct; + +/* break parameter struct definitions*/ +typedef struct +{ + uint16_t runoffstate; /*!< run mode off-state */ + uint16_t ideloffstate; /*!< idle mode off-state */ + uint16_t deadtime; /*!< dead time */ + uint16_t breakpolarity; /*!< break polarity */ + uint16_t outputautostate; /*!< output automatic enable */ + uint16_t protectmode; /*!< complementary register protect control */ + uint16_t breakstate; /*!< break enable */ +}timer_break_parameter_struct; + +/* channel output parameter struct definitions */ +typedef struct +{ + uint16_t outputstate; /*!< channel output state */ + uint16_t outputnstate; /*!< channel complementary output state */ + uint16_t ocpolarity; /*!< channel output polarity */ + uint16_t ocnpolarity; /*!< channel complementary output polarity */ + uint16_t ocidlestate; /*!< idle state of channel output */ + uint16_t ocnidlestate; /*!< idle state of channel complementary output */ +}timer_oc_parameter_struct; + +/* channel input parameter struct definitions */ +typedef struct +{ + uint16_t icpolarity; /*!< channel input polarity */ + uint16_t icselection; /*!< channel input mode selection */ + uint16_t icprescaler; /*!< channel input capture prescaler */ + uint16_t icfilter; /*!< channel input capture filter control */ +}timer_ic_parameter_struct; + +/* TIMER interrupt enable or disable */ +#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ +#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ +#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ +#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ +#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ +#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ +#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ +#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ + +/* TIMER flag */ +#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ +#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ +#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ +#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ +#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ +#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */ +#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ +#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ +#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ +#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ +#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ +#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ + +/* TIMER interrupt flag */ +#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ +#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ +#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ +#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ +#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ +#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */ +#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ +#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF + +/* TIMER DMA source enable */ +#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ +#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ +#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ +#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ +#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ +#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ +#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ + +/* channel DMA request source selection */ +#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel y is sent when update event occurs */ +#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when channel y event occurs */ + +/* DMA access base address */ +#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) +#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ +#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ +#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ +#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ +#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ +#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ +#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ +#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ +#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ +#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ +#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ +#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ +#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ +#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ +#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ +#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ +#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ +#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ +#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ + +/* DMA access burst length */ +#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) +#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ +#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ +#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ +#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ +#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ +#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ +#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ +#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ +#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ +#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ +#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ +#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ +#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ +#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ +#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ +#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ +#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ +#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ + +/* TIMER software event generation source */ +#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ +#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ +#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ +#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ +#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ +#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ + +/* center-aligned mode selection */ +#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) +#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ +#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ +#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ +#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ + +/* TIMER prescaler reload mode */ +#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ +#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ + +/* count direction */ +#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ +#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ + +/* specify division ratio between TIMER clock and dead-time and sampling clock */ +#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */ +#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */ +#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ + +/* single pulse mode */ +#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ +#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ + +/* update source */ +#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ +#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ + +/* run mode off-state configure */ +#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* idle mode off-state configure */ +#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ +#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */ + +/* break input polarity */ +#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ +#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ + +/* output automatic enable */ +#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ +#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ + +/* complementary register protect control */ +#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) +#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ +#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ +#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ +#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ + +/* break input enable */ +#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ +#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ + +/* TIMER channel n(n=0,1,2,3) */ +#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0,2,13..16)) */ +#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0,2,14)) */ +#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0,2)) */ +#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0,2)) */ +#define TIMER_CH_0_1 ((uint16_t)0x0004U) /*!< TIMER channel 0 and 1 for function parameter */ + +/* channel enable state*/ +#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */ +#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */ + +/* channel complementary output enable state*/ +#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ +#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ + +/* channel output polarity */ +#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ +#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ + +/* channel complementary output polarity */ +#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ +#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ + +/* idle state of channel output */ +#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ +#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ + +/* idle state of channel complementary output */ +#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ +#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ + +/* channel output compare mode */ +#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ +#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ +#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ +#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ +#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ +#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ +#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ +#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ + +/* channel output compare shadow enable */ +#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ +#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ + +/* channel output compare fast enable */ +#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ +#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ + +/* channel output compare clear enable */ +#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ +#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ + +/* channel control shadow register update control */ +#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */ +#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers are updated when CMTG bit is set or an rising edge of TRGI occurs */ + +/* channel input capture polarity */ +#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ +#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ +#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ + +/* TIMER input capture selection */ +#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ +#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ +#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ + +/* channel input capture prescaler */ +#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ +#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ +#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/ +#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ + +/* trigger selection */ +#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ +#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ +#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ +#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ +#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ +#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ +#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ +#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */ + +/* master mode control */ +#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) +#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ +#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ +#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ +#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */ +#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ +#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ + +/* slave mode control */ +#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) +#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ +#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */ +#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */ +#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */ +#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ +#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ +#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ +#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ + +/* OCPRE clear source selection */ +#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */ +#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */ +#define TIMER_OCPRE_CLEAR_SOURCE_DISABLE ((uint8_t)0x02U) /*!< OCRC=0, and disable ETI */ + +/* master slave mode selection */ +#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ +#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ + +/* external trigger prescaler */ +#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) +#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ +#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ +#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ +#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ + +/* external trigger polarity */ +#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ +#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ + +/* channel 0 trigger input selection */ +#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ +#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ + +/* TIMERx(x=0,2,13,14,15,16) write cc register selection */ +#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ +#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ + +/* the output value selection */ +#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ +#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ + +/* timer13 channel 0 input remap */ +#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) +#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */ +#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */ +#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */ +#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */ + +/* function declarations */ +/* TIMER timebase*/ +/* deinit a TIMER */ +void timer_deinit(uint32_t timer_periph); +/* initialize TIMER init parameter struct */ +void timer_struct_para_init(timer_parameter_struct* initpara); +/* initialize TIMER counter */ +void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); +/* enable a TIMER */ +void timer_enable(uint32_t timer_periph); +/* disable a TIMER */ +void timer_disable(uint32_t timer_periph); +/* enable the auto reload shadow function */ +void timer_auto_reload_shadow_enable(uint32_t timer_periph); +/* disable the auto reload shadow function */ +void timer_auto_reload_shadow_disable(uint32_t timer_periph); +/* enable the update event */ +void timer_update_event_enable(uint32_t timer_periph); +/* disable the update event */ +void timer_update_event_disable(uint32_t timer_periph); +/* set TIMER counter alignment mode */ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); +/* set TIMER counter up direction */ +void timer_counter_up_direction(uint32_t timer_periph); +/* set TIMER counter down direction */ +void timer_counter_down_direction(uint32_t timer_periph); +/* configure TIMER prescaler */ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload); +/* configure TIMER repetition register value */ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); +/* configure TIMER autoreload register value */ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); +/* configure TIMER counter register value */ +void timer_counter_value_config(uint32_t timer_periph , uint16_t counter); +/* read TIMER counter value */ +uint32_t timer_counter_read(uint32_t timer_periph); +/* read TIMER prescaler value */ +uint16_t timer_prescaler_read(uint32_t timer_periph); +/* configure TIMER single pulse mode */ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); +/* configure TIMER update source */ +void timer_update_source_config(uint32_t timer_periph, uint32_t update); +/* OCPRE clear source selection */ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear); + +/* TIMER interrupt and flag*/ +/* enable the TIMER interrupt */ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); +/* disable the TIMER interrupt */ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); +/* get timer interrupt flag */ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); +/* clear TIMER interrupt flag */ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); +/* get TIMER flags */ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); +/* clear TIMER flags */ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag); + +/* timer DMA and event*/ +/* enable the TIMER DMA */ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma); +/* disable the TIMER DMA */ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma); +/* channel DMA request source selection */ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request); +/* configure the TIMER DMA transfer */ +void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth); +/* software generate events */ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event); + +/* TIMER channel complementary protection */ +/* initialize TIMER break parameter struct */ +void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); +/* configure TIMER break function */ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); +/* enable TIMER break function */ +void timer_break_enable(uint32_t timer_periph); +/* disable TIMER break function */ +void timer_break_disable(uint32_t timer_periph); +/* enable TIMER output automatic function */ +void timer_automatic_output_enable(uint32_t timer_periph); +/* disable TIMER output automatic function */ +void timer_automatic_output_disable(uint32_t timer_periph); +/* enable or disable TIMER primary output function */ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); +/* enable or disable channel capture/compare control shadow register */ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); +/* configure TIMER channel control shadow register update control */ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl); + +/* TIMER channel output */ +/* initialize TIMER channel output parameter struct */ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output function */ +void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara); +/* configure TIMER channel output compare mode */ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode); +/* configure TIMER channel output pulse value */ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); +/* configure TIMER channel output shadow function */ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); +/* configure TIMER channel output fast function */ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); +/* configure TIMER channel output clear function */ +void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear); +/* configure TIMER channel output polarity */ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); +/* configure TIMER channel complementary output polarity */ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); +/* configure TIMER channel enable state */ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); +/* configure TIMER channel complementary output enable state */ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); + +/* TIMER channel input */ +/* initialize TIMER channel input parameter struct */ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); +/* configure TIMER input capture parameter */ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); +/* configure TIMER channel input capture prescaler value */ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); +/* read TIMER channel capture compare register value */ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); +/* configure TIMER input pwm capture function */ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); +/* configure TIMER hall sensor mode */ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); + +/* TIMER master and slave */ +/* select TIMER input trigger source */ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); +/* select TIMER master mode output trigger source */ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); +/* select TIMER slave mode */ +void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode); +/* configure TIMER master slave mode */ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); +/* configure TIMER external trigger input */ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER quadrature decoder mode */ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); +/* configure TIMER internal clock mode */ +void timer_internal_clock_config(uint32_t timer_periph); +/* configure TIMER the internal trigger as external clock input */ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); +/* configure TIMER the external trigger as external clock input */ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter); +/* configure TIMER the external clock mode 0 */ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* configure TIMER the external clock mode 1 */ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); +/* disable TIMER the external clock mode 1 */ +void timer_external_clock_mode1_disable(uint32_t timer_periph); +/* configure TIMER channel remap function */ +void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap); + +/* TIMER configure */ +/* configure TIMER write CHxVAL register selection */ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); +/* configure TIMER output value selection */ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); + +#endif /* GD32E23X_TIMER_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_usart.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_usart.h index 4ff6179..9fdcfba 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_usart.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_usart.h @@ -1,591 +1,591 @@ -/*! - \file gd32e23x_usart.h - \brief definitions for the USART - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_USART_H -#define GD32E23X_USART_H - -#include "gd32e23x.h" - -/* USARTx(x=0,1) definitions */ -#define USART0 (USART_BASE + 0x0000F400U) -#define USART1 USART_BASE - -/* registers definitions */ -#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ -#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ -#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ -#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ -#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ -#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ -#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ -#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ -#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ -#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ -#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ -#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */ -#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ - -/* bits definitions */ -/* USARTx_CTL0 */ -#define USART_CTL0_UEN BIT(0) /*!< USART enable */ -#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ -#define USART_CTL0_REN BIT(2) /*!< receiver enable */ -#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ -#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ -#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ -#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ -#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ -#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ -#define USART_CTL0_PM BIT(9) /*!< parity mode */ -#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ -#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ -#define USART_CTL0_WL BIT(12) /*!< word length */ -#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ -#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ -#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ -#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ -#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ -#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ -#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ - -/* USARTx_CTL1 */ -#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ -#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ -#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ -#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ -#define USART_CTL1_CPH BIT(9) /*!< clock phase */ -#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ -#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ -#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ -#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ -#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ -#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ -#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ -#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ -#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ -#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ -#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ - -/* USARTx_CTL2 */ -#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ -#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ -#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ -#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ -#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ -#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ -#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ -#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ -#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ -#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ -#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ -#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ -#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ -#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ -#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ -#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ -#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ -#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ -#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ - -/* USARTx_BAUD */ -#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ -#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ - -/* USARTx_GP */ -#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ -#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ - -/* USARTx_RT */ -#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ -#define USART_RT_BL BITS(24,31) /*!< block length */ - -/* USARTx_CMD */ -#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ -#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ -#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ -#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ - -/* USARTx_STAT */ -#define USART_STAT_PERR BIT(0) /*!< parity error flag */ -#define USART_STAT_FERR BIT(1) /*!< frame error flag */ -#define USART_STAT_NERR BIT(2) /*!< noise error flag */ -#define USART_STAT_ORERR BIT(3) /*!< overrun error */ -#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ -#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ -#define USART_STAT_TC BIT(6) /*!< transmission completed */ -#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ -#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ -#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ -#define USART_STAT_CTS BIT(10) /*!< CTS level */ -#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ -#define USART_STAT_EBF BIT(12) /*!< end of block flag */ -#define USART_STAT_BSY BIT(16) /*!< busy flag */ -#define USART_STAT_AMF BIT(17) /*!< address match flag */ -#define USART_STAT_SBF BIT(18) /*!< send break flag */ -#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ -#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ -#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ -#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ - -/* USARTx_INTC */ -#define USART_INTC_PEC BIT(0) /*!< parity error clear */ -#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ -#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ -#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ -#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ -#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ -#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ -#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ -#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ -#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ -#define USART_INTC_AMC BIT(17) /*!< address match clear */ -#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ - -/* USARTx_RDATA */ -#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ - -/* USARTx_TDATA */ -#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ - -/* USARTx_CHC */ -#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ -#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ - -/* USARTx_RFCS */ -#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ -#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ -#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ -#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ -#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ -#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ -#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ - -/* constants definitions */ -/* define the USART bit position and its register index offset */ -#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) -#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) -#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) -#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ - | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) -#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) -#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) - -/* register offset */ -#define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ -#define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ -#define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ -#define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ -#define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ -#define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ - -/* USART flags */ -typedef enum{ - /* flags in STAT register */ - USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ - USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ - USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */ - USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ - USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ - USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ - USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ - USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ - USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ - USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ - USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ - USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ - USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ - USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ - USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ - USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ - USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ - USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ - USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ - USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ - /* flags in CHC register */ - USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ - /* flags in RFCS register */ - USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ - USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ - USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ -}usart_flag_enum; - -/* USART interrupt flags */ -typedef enum -{ - /* interrupt flags in CTL0 register */ - USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ - USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ - USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ - USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ - USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ - USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ - USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ - USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ - USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ - /* interrupt flags in CTL1 register */ - USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ - /* interrupt flags in CTL2 register */ - USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ - USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ - USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ - USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ - USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ - /* interrupt flags in RFCS register */ - USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ -}usart_interrupt_flag_enum; - -/* USART interrupt enable or disable */ -typedef enum -{ - /* interrupt in CTL0 register */ - USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ - USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ - USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ - USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ - USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ - USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ - USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ - USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ - /* interrupt in CTL1 register */ - USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ - /* interrupt in CTL2 register */ - USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ - USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ - USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ - /* interrupt in RFCS register */ - USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ -}usart_interrupt_enum; - -/* USART invert configure */ -typedef enum { - /* data bit level inversion */ - USART_DINV_ENABLE, /*!< data bit level inversion */ - USART_DINV_DISABLE, /*!< data bit level not inversion */ - /* TX pin level inversion */ - USART_TXPIN_ENABLE, /*!< TX pin level inversion */ - USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ - /* RX pin level inversion */ - USART_RXPIN_ENABLE, /*!< RX pin level inversion */ - USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ - /* swap TX/RX pins */ - USART_SWAP_ENABLE, /*!< swap TX/RX pins */ - USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ -}usart_invert_enum; - -/* USART receiver configure */ -#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ -#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ - -/* USART transmitter configure */ -#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) -#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ -#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ - -/* USART parity bits definitions */ -#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) -#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ -#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ -#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ - -/* USART wakeup method in mute mode */ -#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ -#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ - -/* USART word length definitions */ -#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) -#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ -#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ - -/* USART oversample mode */ -#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ -#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ - -/* USART address detection mode */ -#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) -#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ -#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ - -/* USART LIN break frame length */ -#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) -#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ -#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ - -/* USART last bit clock pulse */ -#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ -#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ - -/* USART clock phase */ -#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ -#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ - -/* USART clock polarity */ -#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) -#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ -#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ - -/* USART stop bits definitions */ -#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) -#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ -#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ -#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ -#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ - -/* USART data is transmitted/received with the LSB/MSB first */ -#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) -#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ -#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ - -/* USART IrDA low-power enable */ -#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) -#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ -#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ - -/* DMA enable for reception */ -#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) -#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ -#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ - -/* DMA enable for transmission */ -#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) -#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ -#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ - -/* USART RTS hardware flow control configure */ -#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) -#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ -#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ - -/* USART CTS hardware flow control configure */ -#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) -#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ -#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ - -/* USART one sample bit method configure */ -#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) -#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ -#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ - -/* USART driver enable polarity mode */ -#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) -#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ -#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ - -/* USART wakeup mode from deep-sleep mode */ -#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) -#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ -#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ -#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ - -/* USART hardware flow control coherence mode */ -#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) -#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ -#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ - -/* function declarations */ -/* initialization functions */ -/* reset USART */ -void usart_deinit(uint32_t usart_periph); -/* configure USART baud rate value */ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); -/* configure USART parity function */ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); -/* configure USART word length */ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); -/* configure USART stop bit length */ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); -/* enable USART */ -void usart_enable(uint32_t usart_periph); -/* disable USART */ -void usart_disable(uint32_t usart_periph); -/* configure USART transmitter */ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); -/* configure USART receiver */ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); - -/* USART normal mode communication */ -/* data is transmitted/received with the LSB/MSB first */ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); -/* configure USART inverted */ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); -/* enable the USART overrun function */ -void usart_overrun_enable(uint32_t usart_periph); -/* disable the USART overrun function */ -void usart_overrun_disable(uint32_t usart_periph); -/* configure the USART oversample mode */ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); -/* configure sample bit method */ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); -/* enable receiver timeout */ -void usart_receiver_timeout_enable(uint32_t usart_periph); -/* disable receiver timeout */ -void usart_receiver_timeout_disable(uint32_t usart_periph); -/* configure receiver timeout threshold */ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); -/* USART transmit data function */ -void usart_data_transmit(uint32_t usart_periph, uint32_t data); -/* USART receive data function */ -uint16_t usart_data_receive(uint32_t usart_periph); - -/* multi-processor communication */ -/* configure address of the USART */ -void usart_address_config(uint32_t usart_periph, uint8_t addr); -/* configure address detection mode */ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); -/* enable mute mode */ -void usart_mute_mode_enable(uint32_t usart_periph); -/* disable mute mode */ -void usart_mute_mode_disable(uint32_t usart_periph); -/* configure wakeup method in mute mode */ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); - -/* LIN mode communication */ -/* enable LIN mode */ -void usart_lin_mode_enable(uint32_t usart_periph); -/* disable LIN mode */ -void usart_lin_mode_disable(uint32_t usart_periph); -/* LIN break detection length */ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); - -/* half-duplex communication */ -/* enable half-duplex mode */ -void usart_halfduplex_enable(uint32_t usart_periph); -/* disable half-duplex mode */ -void usart_halfduplex_disable(uint32_t usart_periph); - -/* synchronous communication */ -/* enable clock */ -void usart_clock_enable(uint32_t usart_periph); -/* disable clock */ -void usart_clock_disable(uint32_t usart_periph); -/* configure USART synchronous mode parameters */ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); - -/* smartcard communication */ -/* configure guard time value in smartcard mode */ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); -/* enable smartcard mode */ -void usart_smartcard_mode_enable(uint32_t usart_periph); -/* disable smartcard mode */ -void usart_smartcard_mode_disable(uint32_t usart_periph); -/* enable NACK in smartcard mode */ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph); -/* disable NACK in smartcard mode */ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph); -/* enable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); -/* disable early NACK in smartcard mode */ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); -/* configure smartcard auto-retry number */ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); -/* configure block length */ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl); - -/* IrDA communication */ -/* enable IrDA mode */ -void usart_irda_mode_enable(uint32_t usart_periph); -/* disable IrDA mode */ -void usart_irda_mode_disable(uint32_t usart_periph); -/* configure the peripheral clock prescaler */ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); -/* configure IrDA low-power */ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); - -/* hardware flow communication */ -/* configure hardware flow control RTS */ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); -/* configure hardware flow control CTS */ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); - -/* coherence control */ -/* configure hardware flow control coherence mode */ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); - -/* enable RS485 driver */ -void usart_rs485_driver_enable(uint32_t usart_periph); -/* disable RS485 driver */ -void usart_rs485_driver_disable(uint32_t usart_periph); -/* configure driver enable assertion time */ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); -/* configure driver enable de-assertion time */ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); -/* configure driver enable polarity mode */ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); - -/* USART DMA */ -/* configure USART DMA for reception */ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); -/* configure USART DMA for transmission */ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); -/* disable DMA on reception error */ -void usart_reception_error_dma_disable(uint32_t usart_periph); -/* enable DMA on reception error */ -void usart_reception_error_dma_enable(uint32_t usart_periph); - -/* enable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_enable(uint32_t usart_periph); -/* disable USART to wakeup the mcu from deep-sleep mode */ -void usart_wakeup_disable(uint32_t usart_periph); -/* configure the USART wakeup mode from deep-sleep mode */ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); - -/* USART receive FIFO */ -/* enable receive FIFO */ -void usart_receive_fifo_enable(uint32_t usart_periph); -/* disable receive FIFO */ -void usart_receive_fifo_disable(uint32_t usart_periph); -/* read receive FIFO counter number */ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); - -/* flag & interrupt functions */ -/* get flag in STAT/RFCS register */ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); -/* clear USART status */ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); -/* enable USART interrupt */ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* disable USART interrupt */ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); -/* enable USART command */ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); -/* get USART interrupt and flag status */ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); -/* clear USART interrupt flag */ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag); - -#endif /* GD32E23X_USART_H */ +/*! + \file gd32e23x_usart.h + \brief definitions for the USART + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_USART_H +#define GD32E23X_USART_H + +#include "gd32e23x.h" + +/* USARTx(x=0,1) definitions */ +#define USART0 (USART_BASE + 0x0000F400U) +#define USART1 USART_BASE + +/* registers definitions */ +#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ +#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ +#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ +#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ +#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ +#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ +#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ +#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ +#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ +#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ +#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ +#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */ +#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ + +/* bits definitions */ +/* USARTx_CTL0 */ +#define USART_CTL0_UEN BIT(0) /*!< USART enable */ +#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */ +#define USART_CTL0_REN BIT(2) /*!< receiver enable */ +#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ +#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ +#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ +#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ +#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ +#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ +#define USART_CTL0_PM BIT(9) /*!< parity mode */ +#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */ +#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ +#define USART_CTL0_WL BIT(12) /*!< word length */ +#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */ +#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ +#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ +#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ +#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ +#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */ +#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */ + +/* USARTx_CTL1 */ +#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ +#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ +#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ +#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ +#define USART_CTL1_CPH BIT(9) /*!< clock phase */ +#define USART_CTL1_CPL BIT(10) /*!< clock polarity */ +#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ +#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ +#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ +#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ +#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ +#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ +#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ +#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ +#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ +#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */ + +/* USARTx_CTL2 */ +#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ +#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ +#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ +#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ +#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ +#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ +#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ +#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ +#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ +#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ +#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ +#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ +#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */ +#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ +#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */ +#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ +#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ +#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ +#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ + +/* USARTx_BAUD */ +#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ +#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ + +/* USARTx_GP */ +#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ +#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ + +/* USARTx_RT */ +#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ +#define USART_RT_BL BITS(24,31) /*!< block length */ + +/* USARTx_CMD */ +#define USART_CMD_SBKCMD BIT(1) /*!< send break command */ +#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ +#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ +#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ + +/* USARTx_STAT */ +#define USART_STAT_PERR BIT(0) /*!< parity error flag */ +#define USART_STAT_FERR BIT(1) /*!< frame error flag */ +#define USART_STAT_NERR BIT(2) /*!< noise error flag */ +#define USART_STAT_ORERR BIT(3) /*!< overrun error */ +#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ +#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ +#define USART_STAT_TC BIT(6) /*!< transmission completed */ +#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ +#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ +#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ +#define USART_STAT_CTS BIT(10) /*!< CTS level */ +#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ +#define USART_STAT_EBF BIT(12) /*!< end of block flag */ +#define USART_STAT_BSY BIT(16) /*!< busy flag */ +#define USART_STAT_AMF BIT(17) /*!< address match flag */ +#define USART_STAT_SBF BIT(18) /*!< send break flag */ +#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ +#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ +#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ +#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ + +/* USARTx_INTC */ +#define USART_INTC_PEC BIT(0) /*!< parity error clear */ +#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */ +#define USART_INTC_NEC BIT(2) /*!< noise detected clear */ +#define USART_INTC_OREC BIT(3) /*!< overrun error clear */ +#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ +#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */ +#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */ +#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */ +#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */ +#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */ +#define USART_INTC_AMC BIT(17) /*!< address match clear */ +#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ + +/* USARTx_RDATA */ +#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ + +/* USARTx_TDATA */ +#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ + +/* USARTx_CHC */ +#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ +#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ + +/* USARTx_RFCS */ +#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ +#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */ +#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */ +#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ +#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ +#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ +#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ + +/* constants definitions */ +/* define the USART bit position and its register index offset */ +#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) +#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) +#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) +#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ + | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) +#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) +#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) + +/* register offset */ +#define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ +#define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ +#define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ +#define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ +#define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ +#define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ + +/* USART flags */ +typedef enum{ + /* flags in STAT register */ + USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ + USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ + USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */ + USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ + USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ + USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ + USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ + USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ + USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ + USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ + USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ + USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ + USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ + USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ + USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ + USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ + USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ + USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ + USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ + USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ + /* flags in CHC register */ + USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ + /* flags in RFCS register */ + USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ + USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ + USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ +}usart_flag_enum; + +/* USART interrupt flags */ +typedef enum +{ + /* interrupt flags in CTL0 register */ + USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ + USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ + USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ + USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ + USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ + USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ + USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ + USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ + USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ + /* interrupt flags in CTL1 register */ + USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ + /* interrupt flags in CTL2 register */ + USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ + USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ + USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ + USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ + USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ + /* interrupt flags in RFCS register */ + USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ +}usart_interrupt_flag_enum; + +/* USART interrupt enable or disable */ +typedef enum +{ + /* interrupt in CTL0 register */ + USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ + USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ + USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ + USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ + USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ + USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ + USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ + USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ + /* interrupt in CTL1 register */ + USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ + /* interrupt in CTL2 register */ + USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ + USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ + USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ + /* interrupt in RFCS register */ + USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ +}usart_interrupt_enum; + +/* USART invert configure */ +typedef enum { + /* data bit level inversion */ + USART_DINV_ENABLE, /*!< data bit level inversion */ + USART_DINV_DISABLE, /*!< data bit level not inversion */ + /* TX pin level inversion */ + USART_TXPIN_ENABLE, /*!< TX pin level inversion */ + USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ + /* RX pin level inversion */ + USART_RXPIN_ENABLE, /*!< RX pin level inversion */ + USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ + /* swap TX/RX pins */ + USART_SWAP_ENABLE, /*!< swap TX/RX pins */ + USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ +}usart_invert_enum; + +/* USART receiver configure */ +#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ +#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ + +/* USART transmitter configure */ +#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) +#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ +#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ + +/* USART parity bits definitions */ +#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) +#define USART_PM_NONE CTL0_PM(0) /*!< no parity */ +#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ +#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ + +/* USART wakeup method in mute mode */ +#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ +#define USART_WM_ADDR CTL0_WM(1) /*!< address match */ + +/* USART word length definitions */ +#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) +#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ +#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ + +/* USART oversample mode */ +#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ +#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ + +/* USART address detection mode */ +#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) +#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ +#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ + +/* USART LIN break frame length */ +#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) +#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ +#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ + +/* USART last bit clock pulse */ +#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ +#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ + +/* USART clock phase */ +#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ +#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ + +/* USART clock polarity */ +#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) +#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ +#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ + +/* USART stop bits definitions */ +#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) +#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ +#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ +#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ +#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ + +/* USART data is transmitted/received with the LSB/MSB first */ +#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) +#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ +#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ + +/* USART IrDA low-power enable */ +#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) +#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ +#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ + +/* DMA enable for reception */ +#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) +#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ +#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ + +/* DMA enable for transmission */ +#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) +#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ +#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ + +/* USART RTS hardware flow control configure */ +#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) +#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ +#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ + +/* USART CTS hardware flow control configure */ +#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) +#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ +#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ + +/* USART one sample bit method configure */ +#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) +#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ +#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ + +/* USART driver enable polarity mode */ +#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) +#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ +#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ + +/* USART wakeup mode from deep-sleep mode */ +#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) +#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ +#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ +#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ + +/* USART hardware flow control coherence mode */ +#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) +#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ +#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ + +/* function declarations */ +/* initialization functions */ +/* reset USART */ +void usart_deinit(uint32_t usart_periph); +/* configure USART baud rate value */ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); +/* configure USART parity function */ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); +/* configure USART word length */ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); +/* configure USART stop bit length */ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); +/* enable USART */ +void usart_enable(uint32_t usart_periph); +/* disable USART */ +void usart_disable(uint32_t usart_periph); +/* configure USART transmitter */ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); +/* configure USART receiver */ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); + +/* USART normal mode communication */ +/* data is transmitted/received with the LSB/MSB first */ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); +/* configure USART inverted */ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); +/* enable the USART overrun function */ +void usart_overrun_enable(uint32_t usart_periph); +/* disable the USART overrun function */ +void usart_overrun_disable(uint32_t usart_periph); +/* configure the USART oversample mode */ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); +/* configure sample bit method */ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); +/* enable receiver timeout */ +void usart_receiver_timeout_enable(uint32_t usart_periph); +/* disable receiver timeout */ +void usart_receiver_timeout_disable(uint32_t usart_periph); +/* configure receiver timeout threshold */ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); +/* USART transmit data function */ +void usart_data_transmit(uint32_t usart_periph, uint32_t data); +/* USART receive data function */ +uint16_t usart_data_receive(uint32_t usart_periph); + +/* multi-processor communication */ +/* configure address of the USART */ +void usart_address_config(uint32_t usart_periph, uint8_t addr); +/* configure address detection mode */ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); +/* enable mute mode */ +void usart_mute_mode_enable(uint32_t usart_periph); +/* disable mute mode */ +void usart_mute_mode_disable(uint32_t usart_periph); +/* configure wakeup method in mute mode */ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); + +/* LIN mode communication */ +/* enable LIN mode */ +void usart_lin_mode_enable(uint32_t usart_periph); +/* disable LIN mode */ +void usart_lin_mode_disable(uint32_t usart_periph); +/* LIN break detection length */ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); + +/* half-duplex communication */ +/* enable half-duplex mode */ +void usart_halfduplex_enable(uint32_t usart_periph); +/* disable half-duplex mode */ +void usart_halfduplex_disable(uint32_t usart_periph); + +/* synchronous communication */ +/* enable clock */ +void usart_clock_enable(uint32_t usart_periph); +/* disable clock */ +void usart_clock_disable(uint32_t usart_periph); +/* configure USART synchronous mode parameters */ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); + +/* smartcard communication */ +/* configure guard time value in smartcard mode */ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); +/* enable smartcard mode */ +void usart_smartcard_mode_enable(uint32_t usart_periph); +/* disable smartcard mode */ +void usart_smartcard_mode_disable(uint32_t usart_periph); +/* enable NACK in smartcard mode */ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph); +/* disable NACK in smartcard mode */ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph); +/* enable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); +/* disable early NACK in smartcard mode */ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); +/* configure smartcard auto-retry number */ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); +/* configure block length */ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl); + +/* IrDA communication */ +/* enable IrDA mode */ +void usart_irda_mode_enable(uint32_t usart_periph); +/* disable IrDA mode */ +void usart_irda_mode_disable(uint32_t usart_periph); +/* configure the peripheral clock prescaler */ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); +/* configure IrDA low-power */ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); + +/* hardware flow communication */ +/* configure hardware flow control RTS */ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); +/* configure hardware flow control CTS */ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); + +/* coherence control */ +/* configure hardware flow control coherence mode */ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); + +/* enable RS485 driver */ +void usart_rs485_driver_enable(uint32_t usart_periph); +/* disable RS485 driver */ +void usart_rs485_driver_disable(uint32_t usart_periph); +/* configure driver enable assertion time */ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); +/* configure driver enable de-assertion time */ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); +/* configure driver enable polarity mode */ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); + +/* USART DMA */ +/* configure USART DMA for reception */ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); +/* configure USART DMA for transmission */ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); +/* disable DMA on reception error */ +void usart_reception_error_dma_disable(uint32_t usart_periph); +/* enable DMA on reception error */ +void usart_reception_error_dma_enable(uint32_t usart_periph); + +/* enable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_enable(uint32_t usart_periph); +/* disable USART to wakeup the mcu from deep-sleep mode */ +void usart_wakeup_disable(uint32_t usart_periph); +/* configure the USART wakeup mode from deep-sleep mode */ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); + +/* USART receive FIFO */ +/* enable receive FIFO */ +void usart_receive_fifo_enable(uint32_t usart_periph); +/* disable receive FIFO */ +void usart_receive_fifo_disable(uint32_t usart_periph); +/* read receive FIFO counter number */ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); + +/* flag & interrupt functions */ +/* get flag in STAT/RFCS register */ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); +/* clear USART status */ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); +/* enable USART interrupt */ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* disable USART interrupt */ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); +/* enable USART command */ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); +/* get USART interrupt and flag status */ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); +/* clear USART interrupt flag */ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag); + +#endif /* GD32E23X_USART_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_wwdgt.h b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_wwdgt.h index 39d8bcb..e6a4f4c 100644 --- a/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_wwdgt.h +++ b/SDK/GD32E23x_standard_peripheral/Include/gd32e23x_wwdgt.h @@ -1,91 +1,91 @@ -/*! - \file gd32e23x_wwdgt.h - \brief definitions for the WWDGT - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#ifndef GD32E23X_WWDGT_H -#define GD32E23X_WWDGT_H - -#include "gd32e23x.h" - -/* WWDGT definitions */ -#define WWDGT WWDGT_BASE - -/* registers definitions */ -#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ -#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ -#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ - -/* bits definitions */ -/* WWDGT_CTL */ -#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ -#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ - -/* WWDGT_CFG */ -#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ -#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ -#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ - -/* WWDGT_STAT */ -#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ - -/* constants definitions */ -#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ -#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ -#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ -#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ -#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ - -/*!< write value to WWDGT_CTL_CNT bit field */ -#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) -/*!< write value to WWDGT_CFG_WIN bit field */ -#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) - -/* function declarations */ -/* reset the window watchdog timer configuration */ -void wwdgt_deinit(void); -/* start the window watchdog timer counter */ -void wwdgt_enable(void); - -/* configure the window watchdog timer counter value */ -void wwdgt_counter_update(uint16_t counter_value); -/* configure counter value, window value, and prescaler divider value */ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); - -/* check early wakeup interrupt state of WWDGT */ -FlagStatus wwdgt_flag_get(void); -/* clear early wakeup interrupt state of WWDGT */ -void wwdgt_flag_clear(void); -/* enable early wakeup interrupt of WWDGT */ -void wwdgt_interrupt_enable(void); - -#endif /* GD32E23X_WWDGT_H */ +/*! + \file gd32e23x_wwdgt.h + \brief definitions for the WWDGT + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#ifndef GD32E23X_WWDGT_H +#define GD32E23X_WWDGT_H + +#include "gd32e23x.h" + +/* WWDGT definitions */ +#define WWDGT WWDGT_BASE + +/* registers definitions */ +#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ +#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ +#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ + +/* bits definitions */ +/* WWDGT_CTL */ +#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ +#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ + +/* WWDGT_CFG */ +#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ +#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */ +#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ + +/* WWDGT_STAT */ +#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ + +/* constants definitions */ +#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */ +#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ +#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ +#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ +#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ + +/*!< write value to WWDGT_CTL_CNT bit field */ +#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) +/*!< write value to WWDGT_CFG_WIN bit field */ +#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) + +/* function declarations */ +/* reset the window watchdog timer configuration */ +void wwdgt_deinit(void); +/* start the window watchdog timer counter */ +void wwdgt_enable(void); + +/* configure the window watchdog timer counter value */ +void wwdgt_counter_update(uint16_t counter_value); +/* configure counter value, window value, and prescaler divider value */ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); + +/* check early wakeup interrupt state of WWDGT */ +FlagStatus wwdgt_flag_get(void); +/* clear early wakeup interrupt state of WWDGT */ +void wwdgt_flag_clear(void); +/* enable early wakeup interrupt of WWDGT */ +void wwdgt_interrupt_enable(void); + +#endif /* GD32E23X_WWDGT_H */ diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c index 1ced783..5f53d31 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_adc.c @@ -1,842 +1,842 @@ -/*! - \file gd32e23x_adc.c - \brief ADC driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_adc.h" - -/*! - \brief reset ADC - \param[in] none - \param[out] none - \retval none -*/ -void adc_deinit(void) -{ - rcu_periph_reset_enable(RCU_ADCRST); - rcu_periph_reset_disable(RCU_ADCRST); -} - -/*! - \brief enable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_enable(void) -{ - if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)) { - ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; - } -} - -/*! - \brief disable ADC interface - \param[in] none - \param[out] none - \retval none -*/ -void adc_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); -} - -/*! - \brief ADC calibration and reset calibration - \param[in] none - \param[out] none - \retval none -*/ -void adc_calibration_enable(void) -{ - /* reset the selected ADC calibration register */ - ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; - /* check the RSTCLB bit state */ - while((ADC_CTL1 & ADC_CTL1_RSTCLB)) { - } - - /* enable ADC calibration process */ - ADC_CTL1 |= ADC_CTL1_CLB; - /* check the CLB bit state */ - while((ADC_CTL1 & ADC_CTL1_CLB)) { - } -} - -/*! - \brief enable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_enable(void) -{ - ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); -} - -/*! - \brief disable DMA request - \param[in] none - \param[out] none - \retval none -*/ -void adc_dma_mode_disable(void) -{ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); -} - -/*! - \brief enable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_enable(void) -{ - /* enable the temperature sensor and Vrefint channel */ - ADC_CTL1 |= ADC_CTL1_TSVREN; -} - -/*! - \brief disable the temperature sensor and Vrefint channel - \param[in] none - \param[out] none - \retval none -*/ -void adc_tempsensor_vrefint_disable(void) -{ - /* disable the temperature sensor and Vrefint channel */ - ADC_CTL1 &= ~ADC_CTL1_TSVREN; -} - -/*! - \brief configure ADC discontinuous mode - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel - \param[in] length: number of conversions in discontinuous mode, the number can be 1..8 - for regular channel, the number has no effect for inserted channel - \param[out] none - \retval none -*/ -void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) -{ - ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); - - switch(channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure the number of conversions in discontinuous mode */ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); - ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; - break; - case ADC_CHANNEL_DISCON_DISABLE: - default: - break; - } -} - -/*! - \brief configure ADC special function - \param[in] function: the function to configure - one or more parameters can be selected which is shown as below: - \arg ADC_SCAN_MODE: scan mode select - \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically - \arg ADC_CONTINUOUS_MODE: continuous mode select - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_special_function_config(uint32_t function, ControlStatus newvalue) -{ - if(newvalue) { - /* enable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)) { - ADC_CTL0 |= ADC_SCAN_MODE; - } - /* enable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { - ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; - } - /* enable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)) { - ADC_CTL1 |= ADC_CONTINUOUS_MODE; - } - } else { - /* disable ADC scan mode */ - if(RESET != (function & ADC_SCAN_MODE)) { - ADC_CTL0 &= ~ADC_SCAN_MODE; - } - /* disable ADC inserted channel group convert automatically */ - if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { - ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; - } - /* disable ADC continuous mode */ - if(RESET != (function & ADC_CONTINUOUS_MODE)) { - ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; - } - } -} - -/*! - \brief configure ADC data alignment - \param[in] data_alignment: data alignment select - only one parameter can be selected which is shown as below: - \arg ADC_DATAALIGN_RIGHT: right alignment - \arg ADC_DATAALIGN_LEFT: left alignment - \param[out] none - \retval none -*/ -void adc_data_alignment_config(uint32_t data_alignment) -{ - if(ADC_DATAALIGN_RIGHT != data_alignment) { - ADC_CTL1 |= ADC_CTL1_DAL; - } else { - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); - } -} - -/*! - \brief configure the length of regular channel group or inserted channel group - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] length: the length of the channel - regular channel 1-16 - inserted channel 1-4 - \param[out] none - \retval none -*/ -void adc_channel_length_config(uint8_t channel_group, uint32_t length) -{ - switch(channel_group) { - case ADC_REGULAR_CHANNEL: - /* configure the length of regular channel group */ - ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); - ADC_RSQ0 |= RSQ0_RL((uint32_t)(length - 1U)); - break; - case ADC_INSERTED_CHANNEL: - /* configure the length of inserted channel group */ - ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); - ADC_ISQ |= ISQ_IL((uint32_t)(length - 1U)); - break; - default: - break; - } -} - -/*! - \brief configure ADC regular channel - \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[in] sample_time: the sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint32_t rsq, sampt; - - /* configure ADC regular sequence */ - if(rank < 6U) { - rsq = ADC_RSQ2; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * rank))); - rsq |= ((uint32_t)channel << (5U * rank)); - ADC_RSQ2 = rsq; - } else if(rank < 12U) { - rsq = ADC_RSQ1; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 6U)))); - rsq |= ((uint32_t)channel << (5U * (rank - 6U))); - ADC_RSQ1 = rsq; - } else if(rank < 16U) { - rsq = ADC_RSQ0; - rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 12U)))); - rsq |= ((uint32_t)channel << (5U * (rank - 12U))); - ADC_RSQ0 = rsq; - } else { - } - - /* configure ADC sampling time */ - if(channel < 10U) { - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); - sampt |= (uint32_t)(sample_time << (3U * channel)); - ADC_SAMPT1 = sampt; - } else if(channel < 19U) { - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); - sampt |= (uint32_t)(sample_time << (3U * (channel - 10U))); - ADC_SAMPT0 = sampt; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel - \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[in] sample_time: The sample time value - only one parameter can be selected which is shown as below: - \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles - \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles - \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles - \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles - \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles - \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles - \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles - \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles - \param[out] none - \retval none -*/ -void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) -{ - uint8_t inserted_length; - uint32_t isq, sampt; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); - - isq = ADC_ISQ; - isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank) * 5U))); - isq |= ((uint32_t)channel << (15U - (inserted_length - rank) * 5U)); - ADC_ISQ = isq; - - /* configure ADC sampling time */ - if(channel < 10U) { - sampt = ADC_SAMPT1; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); - sampt |= (uint32_t) sample_time << (3U * channel); - ADC_SAMPT1 = sampt; - } else if(channel < 19U) { - sampt = ADC_SAMPT0; - sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); - sampt |= ((uint32_t)sample_time << (3U * (channel - 10U))); - ADC_SAMPT0 = sampt; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure ADC inserted channel offset - \param[in] inserted_channel: insert channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[in] offset: the offset data - \param[out] none - \retval none -*/ -void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) -{ - uint8_t inserted_length; - uint32_t num = 0U; - - inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); - num = 3U - (inserted_length - inserted_channel); - - if(num <= 3U) { - /* calculate the offset of the register */ - num = num * 4U; - /* configure the offset of the selected channels */ - REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); - } -} - -/*! - \brief enable or disable ADC external trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) -{ - if(newvalue) { - /* external trigger enable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { - ADC_CTL1 |= ADC_CTL1_ETERC; - } - /* external trigger enable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { - ADC_CTL1 |= ADC_CTL1_ETEIC; - } - } else { - /* external trigger disable for regular channel */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { - ADC_CTL1 &= ~ADC_CTL1_ETERC; - } - /* external trigger disable for inserted channel */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { - ADC_CTL1 &= ~ADC_CTL1_ETEIC; - } - } -} - -/*! - \brief configure ADC external trigger source - \param[in] channel_group: select the channel group - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[in] external_trigger_source: regular or inserted group trigger source - only one parameter can be selected which is shown as below: - for regular channel: - \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select - \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select - \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select - \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select - \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 - \arg ADC_EXTTRIG_REGULAR_NONE: software trigger - for inserted channel: - \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select - \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select - \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select - \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 - \arg ADC_EXTTRIG_INSERTED_NONE: software trigger - \param[out] none - \retval none -*/ -void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) -{ - switch(channel_group) { - case ADC_REGULAR_CHANNEL: - /* external trigger select for regular channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - case ADC_INSERTED_CHANNEL: - /* external trigger select for inserted channel */ - ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); - ADC_CTL1 |= (uint32_t)external_trigger_source; - break; - default: - break; - } -} - -/*! - \brief enable ADC software trigger - \param[in] channel_group: select the channel group - one or more parameters can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \param[out] none - \retval none -*/ -void adc_software_trigger_enable(uint8_t channel_group) -{ - /* enable regular group channel software trigger */ - if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { - ADC_CTL1 |= ADC_CTL1_SWRCST; - } - /* enable inserted channel group software trigger */ - if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { - ADC_CTL1 |= ADC_CTL1_SWICST; - } -} - -/*! - \brief read ADC regular group data register - \param[in] none - \param[out] none - \retval the conversion value -*/ -uint16_t adc_regular_data_read(void) -{ - return ((uint16_t)ADC_RDATA); -} - -/*! - \brief read ADC inserted group data register - \param[in] inserted_channel: inserted channel select - only one parameter can be selected which is shown as below: - \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 - \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 - \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 - \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 - \param[out] none - \retval the conversion value -*/ -uint16_t adc_inserted_data_read(uint8_t inserted_channel) -{ - uint32_t idata; - /* read the data of the selected channel */ - switch(inserted_channel) { - case ADC_INSERTED_CHANNEL_0: - idata = ADC_IDATA0; - break; - case ADC_INSERTED_CHANNEL_1: - idata = ADC_IDATA1; - break; - case ADC_INSERTED_CHANNEL_2: - idata = ADC_IDATA2; - break; - case ADC_INSERTED_CHANNEL_3: - idata = ADC_IDATA3; - break; - default: - idata = 0U; - break; - } - return (uint16_t)idata; -} - -/*! - \brief get the ADC flag bits - \param[in] flag: the adc flag bits - only one parameter can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_flag_get(uint32_t flag) -{ - FlagStatus reval = RESET; - - if(ADC_STAT & flag) { - reval = SET; - } - return reval; -} - -/*! - \brief clear the ADC flag - \param[in] flag: the adc flag - one or more parameters can be selected which is shown as below: - \arg ADC_FLAG_WDE: analog watchdog event flag - \arg ADC_FLAG_EOC: end of group conversion flag - \arg ADC_FLAG_EOIC: end of inserted group conversion flag - \arg ADC_FLAG_STIC: start flag of inserted channel group - \arg ADC_FLAG_STRC: start flag of regular channel group - \param[out] none - \retval none -*/ -void adc_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief get the ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus adc_interrupt_flag_get(uint32_t flag) -{ - FlagStatus interrupt_flag = RESET; - uint32_t state; - - /* check the interrupt bits */ - switch(flag) { - case ADC_INT_FLAG_WDE: - state = ADC_STAT & ADC_STAT_WDE; - if((ADC_CTL0 & ADC_CTL0_WDEIE) && state) { - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOC: - state = ADC_STAT & ADC_STAT_EOC; - if((ADC_CTL0 & ADC_CTL0_EOCIE) && state) { - interrupt_flag = SET; - } - break; - case ADC_INT_FLAG_EOIC: - state = ADC_STAT & ADC_STAT_EOIC; - if((ADC_CTL0 & ADC_CTL0_EOICIE) && state) { - interrupt_flag = SET; - } - break; - default: - break; - } - return interrupt_flag; -} - -/*! - \brief clear ADC interrupt flag - \param[in] flag: the adc interrupt flag - only one parameter can be selected which is shown as below: - \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag - \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag - \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag - \param[out] none - \retval none -*/ -void adc_interrupt_flag_clear(uint32_t flag) -{ - ADC_STAT &= ~((uint32_t)flag); -} - -/*! - \brief enable ADC interrupt - \param[in] interrupt: the adc interrupt - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_enable(uint32_t interrupt) -{ - /* enable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)) { - ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; - } - - /* enable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)) { - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; - } - - /* enable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)) { - ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief disable ADC interrupt - \param[in] interrupt: the adc interrupt flag - one or more parameters can be selected which is shown as below: - \arg ADC_INT_WDE: analog watchdog interrupt - \arg ADC_INT_EOC: end of group conversion interrupt - \arg ADC_INT_EOIC: end of inserted group conversion interrupt - \param[out] none - \retval none -*/ -void adc_interrupt_disable(uint32_t interrupt) -{ - /* disable analog watchdog interrupt */ - if(RESET != (interrupt & ADC_INT_WDE)) { - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; - } - - /* disable end of group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOC)) { - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; - } - - /* disable end of inserted group conversion interrupt */ - if(RESET != (interrupt & ADC_INT_EOIC)) { - ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; - } -} - -/*! - \brief configure ADC analog watchdog single channel - \param[in] channel: the selected ADC channel - only one parameter can be selected which is shown as below: - \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx - \param[out] none - \retval none -*/ -void adc_watchdog_single_channel_enable(uint8_t channel) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); - - ADC_CTL0 |= (uint32_t)channel; - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); -} - -/*! - \brief configure ADC analog watchdog group channel - \param[in] channel_group: the channel group use analog watchdog - only one parameter can be selected which is shown as below: - \arg ADC_REGULAR_CHANNEL: regular channel group - \arg ADC_INSERTED_CHANNEL: inserted channel group - \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group - \param[out] none - \retval none -*/ -void adc_watchdog_group_channel_enable(uint8_t channel_group) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); - - /* select the group */ - switch(channel_group) { - case ADC_REGULAR_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; - break; - case ADC_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; - break; - case ADC_REGULAR_INSERTED_CHANNEL: - ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); - break; - default: - break; - } -} - -/*! - \brief disable ADC analog watchdog - \param[in] none - \param[out] none - \retval none -*/ -void adc_watchdog_disable(void) -{ - ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); -} - -/*! - \brief configure ADC analog watchdog threshold - \param[in] low_threshold: analog watchdog low threshold,0..4095 - \param[in] high_threshold: analog watchdog high threshold,0..4095 - \param[out] none - \retval none -*/ -void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) -{ - ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); - ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); -} - - -/*! - \brief configure ADC resolution - \param[in] resolution: ADC resolution - only one parameter can be selected which is shown as below: - \arg ADC_RESOLUTION_12B: 12-bit ADC resolution - \arg ADC_RESOLUTION_10B: 10-bit ADC resolution - \arg ADC_RESOLUTION_8B: 8-bit ADC resolution - \arg ADC_RESOLUTION_6B: 6-bit ADC resolution - \param[out] none - \retval none -*/ -void adc_resolution_config(uint32_t resolution) -{ - ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); - ADC_CTL0 |= (uint32_t)resolution; -} - -/*! - \brief configure ADC oversample mode - \param[in] mode: ADC oversampling mode - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger - \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger - \param[in] shift: ADC oversampling shift - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift - \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift - \param[in] ratio: ADC oversampling ratio - only one parameter can be selected which is shown as below: - \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 - \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 - \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 - \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 - \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 - \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 - \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 - \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 - \param[out] none - \retval none -*/ -void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) -{ - /* configure ADC oversampling mode */ - if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { - ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; - } else { - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); - } - - /* configure the shift and ratio */ - ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); - ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); -} - -/*! - \brief enable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_enable(void) -{ - ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; -} - -/*! - \brief disable ADC oversample mode - \param[in] none - \param[out] none - \retval none -*/ -void adc_oversample_mode_disable(void) -{ - ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); -} +/*! + \file gd32e23x_adc.c + \brief ADC driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_adc.h" + +/*! + \brief reset ADC + \param[in] none + \param[out] none + \retval none +*/ +void adc_deinit(void) +{ + rcu_periph_reset_enable(RCU_ADCRST); + rcu_periph_reset_disable(RCU_ADCRST); +} + +/*! + \brief enable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_enable(void) +{ + if(RESET == (ADC_CTL1 & ADC_CTL1_ADCON)) { + ADC_CTL1 |= (uint32_t)ADC_CTL1_ADCON; + } +} + +/*! + \brief disable ADC interface + \param[in] none + \param[out] none + \retval none +*/ +void adc_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ADCON); +} + +/*! + \brief ADC calibration and reset calibration + \param[in] none + \param[out] none + \retval none +*/ +void adc_calibration_enable(void) +{ + /* reset the selected ADC calibration register */ + ADC_CTL1 |= (uint32_t) ADC_CTL1_RSTCLB; + /* check the RSTCLB bit state */ + while((ADC_CTL1 & ADC_CTL1_RSTCLB)) { + } + + /* enable ADC calibration process */ + ADC_CTL1 |= ADC_CTL1_CLB; + /* check the CLB bit state */ + while((ADC_CTL1 & ADC_CTL1_CLB)) { + } +} + +/*! + \brief enable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_enable(void) +{ + ADC_CTL1 |= (uint32_t)(ADC_CTL1_DMA); +} + +/*! + \brief disable DMA request + \param[in] none + \param[out] none + \retval none +*/ +void adc_dma_mode_disable(void) +{ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DMA); +} + +/*! + \brief enable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_enable(void) +{ + /* enable the temperature sensor and Vrefint channel */ + ADC_CTL1 |= ADC_CTL1_TSVREN; +} + +/*! + \brief disable the temperature sensor and Vrefint channel + \param[in] none + \param[out] none + \retval none +*/ +void adc_tempsensor_vrefint_disable(void) +{ + /* disable the temperature sensor and Vrefint channel */ + ADC_CTL1 &= ~ADC_CTL1_TSVREN; +} + +/*! + \brief configure ADC discontinuous mode + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular and inserted channel + \param[in] length: number of conversions in discontinuous mode, the number can be 1..8 + for regular channel, the number has no effect for inserted channel + \param[out] none + \retval none +*/ +void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length) +{ + ADC_CTL0 &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC)); + + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* configure the number of conversions in discontinuous mode */ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DISNUM); + ADC_CTL0 |= CTL0_DISNUM(((uint32_t)length - 1U)); + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISRC; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_DISIC; + break; + case ADC_CHANNEL_DISCON_DISABLE: + default: + break; + } +} + +/*! + \brief configure ADC special function + \param[in] function: the function to configure + one or more parameters can be selected which is shown as below: + \arg ADC_SCAN_MODE: scan mode select + \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically + \arg ADC_CONTINUOUS_MODE: continuous mode select + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_special_function_config(uint32_t function, ControlStatus newvalue) +{ + if(newvalue) { + /* enable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)) { + ADC_CTL0 |= ADC_SCAN_MODE; + } + /* enable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0 |= ADC_INSERTED_CHANNEL_AUTO; + } + /* enable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1 |= ADC_CONTINUOUS_MODE; + } + } else { + /* disable ADC scan mode */ + if(RESET != (function & ADC_SCAN_MODE)) { + ADC_CTL0 &= ~ADC_SCAN_MODE; + } + /* disable ADC inserted channel group convert automatically */ + if(RESET != (function & ADC_INSERTED_CHANNEL_AUTO)) { + ADC_CTL0 &= ~ADC_INSERTED_CHANNEL_AUTO; + } + /* disable ADC continuous mode */ + if(RESET != (function & ADC_CONTINUOUS_MODE)) { + ADC_CTL1 &= ~ADC_CONTINUOUS_MODE; + } + } +} + +/*! + \brief configure ADC data alignment + \param[in] data_alignment: data alignment select + only one parameter can be selected which is shown as below: + \arg ADC_DATAALIGN_RIGHT: right alignment + \arg ADC_DATAALIGN_LEFT: left alignment + \param[out] none + \retval none +*/ +void adc_data_alignment_config(uint32_t data_alignment) +{ + if(ADC_DATAALIGN_RIGHT != data_alignment) { + ADC_CTL1 |= ADC_CTL1_DAL; + } else { + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_DAL); + } +} + +/*! + \brief configure the length of regular channel group or inserted channel group + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] length: the length of the channel + regular channel 1-16 + inserted channel 1-4 + \param[out] none + \retval none +*/ +void adc_channel_length_config(uint8_t channel_group, uint32_t length) +{ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* configure the length of regular channel group */ + ADC_RSQ0 &= ~((uint32_t)ADC_RSQ0_RL); + ADC_RSQ0 |= RSQ0_RL((uint32_t)(length - 1U)); + break; + case ADC_INSERTED_CHANNEL: + /* configure the length of inserted channel group */ + ADC_ISQ &= ~((uint32_t)ADC_ISQ_IL); + ADC_ISQ |= ISQ_IL((uint32_t)(length - 1U)); + break; + default: + break; + } +} + +/*! + \brief configure ADC regular channel + \param[in] rank: the regular group sequence rank, this parameter must be between 0 to 15 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx + \param[in] sample_time: the sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint32_t rsq, sampt; + + /* configure ADC regular sequence */ + if(rank < 6U) { + rsq = ADC_RSQ2; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * rank))); + rsq |= ((uint32_t)channel << (5U * rank)); + ADC_RSQ2 = rsq; + } else if(rank < 12U) { + rsq = ADC_RSQ1; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 6U)))); + rsq |= ((uint32_t)channel << (5U * (rank - 6U))); + ADC_RSQ1 = rsq; + } else if(rank < 16U) { + rsq = ADC_RSQ0; + rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (5U * (rank - 12U)))); + rsq |= ((uint32_t)channel << (5U * (rank - 12U))); + ADC_RSQ0 = rsq; + } else { + } + + /* configure ADC sampling time */ + if(channel < 10U) { + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); + sampt |= (uint32_t)(sample_time << (3U * channel)); + ADC_SAMPT1 = sampt; + } else if(channel < 19U) { + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); + sampt |= (uint32_t)(sample_time << (3U * (channel - 10U))); + ADC_SAMPT0 = sampt; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel + \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3 + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx + \param[in] sample_time: The sample time value + only one parameter can be selected which is shown as below: + \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles + \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles + \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles + \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles + \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles + \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles + \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles + \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles + \param[out] none + \retval none +*/ +void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time) +{ + uint8_t inserted_length; + uint32_t isq, sampt; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); + + isq = ADC_ISQ; + isq &= ~((uint32_t)(ADC_ISQ_ISQN << (15U - (inserted_length - rank) * 5U))); + isq |= ((uint32_t)channel << (15U - (inserted_length - rank) * 5U)); + ADC_ISQ = isq; + + /* configure ADC sampling time */ + if(channel < 10U) { + sampt = ADC_SAMPT1; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * channel))); + sampt |= (uint32_t) sample_time << (3U * channel); + ADC_SAMPT1 = sampt; + } else if(channel < 19U) { + sampt = ADC_SAMPT0; + sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (3U * (channel - 10U)))); + sampt |= ((uint32_t)sample_time << (3U * (channel - 10U))); + ADC_SAMPT0 = sampt; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure ADC inserted channel offset + \param[in] inserted_channel: insert channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[in] offset: the offset data + \param[out] none + \retval none +*/ +void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset) +{ + uint8_t inserted_length; + uint32_t num = 0U; + + inserted_length = (uint8_t)GET_BITS(ADC_ISQ, 20U, 21U); + num = 3U - (inserted_length - inserted_channel); + + if(num <= 3U) { + /* calculate the offset of the register */ + num = num * 4U; + /* configure the offset of the selected channels */ + REG32((ADC) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset); + } +} + +/*! + \brief enable or disable ADC external trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue) +{ + if(newvalue) { + /* external trigger enable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_ETERC; + } + /* external trigger enable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_ETEIC; + } + } else { + /* external trigger disable for regular channel */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 &= ~ADC_CTL1_ETERC; + } + /* external trigger disable for inserted channel */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 &= ~ADC_CTL1_ETEIC; + } + } +} + +/*! + \brief configure ADC external trigger source + \param[in] channel_group: select the channel group + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[in] external_trigger_source: regular or inserted group trigger source + only one parameter can be selected which is shown as below: + for regular channel: + \arg ADC_EXTTRIG_REGULAR_T0_CH0: TIMER0 CH0 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH1: TIMER0 CH1 event select + \arg ADC_EXTTRIG_REGULAR_T0_CH2: TIMER0 CH2 event select + \arg ADC_EXTTRIG_REGULAR_T2_TRGO: TIMER2 TRGO event select + \arg ADC_EXTTRIG_REGULAR_T14_CH0: TIMER14 CH0 event select + \arg ADC_EXTTRIG_REGULAR_EXTI_11: external interrupt line 11 + \arg ADC_EXTTRIG_REGULAR_NONE: software trigger + for inserted channel: + \arg ADC_EXTTRIG_INSERTED_T0_TRGO: TIMER0 TRGO event select + \arg ADC_EXTTRIG_INSERTED_T0_CH3: TIMER0 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T2_CH3: TIMER2 CH3 event select + \arg ADC_EXTTRIG_INSERTED_T14_TRGO: TIMER14 TRGO event select + \arg ADC_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15 + \arg ADC_EXTTRIG_INSERTED_NONE: software trigger + \param[out] none + \retval none +*/ +void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source) +{ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + /* external trigger select for regular channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSRC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + case ADC_INSERTED_CHANNEL: + /* external trigger select for inserted channel */ + ADC_CTL1 &= ~((uint32_t)ADC_CTL1_ETSIC); + ADC_CTL1 |= (uint32_t)external_trigger_source; + break; + default: + break; + } +} + +/*! + \brief enable ADC software trigger + \param[in] channel_group: select the channel group + one or more parameters can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \param[out] none + \retval none +*/ +void adc_software_trigger_enable(uint8_t channel_group) +{ + /* enable regular group channel software trigger */ + if(RESET != (channel_group & ADC_REGULAR_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_SWRCST; + } + /* enable inserted channel group software trigger */ + if(RESET != (channel_group & ADC_INSERTED_CHANNEL)) { + ADC_CTL1 |= ADC_CTL1_SWICST; + } +} + +/*! + \brief read ADC regular group data register + \param[in] none + \param[out] none + \retval the conversion value +*/ +uint16_t adc_regular_data_read(void) +{ + return ((uint16_t)ADC_RDATA); +} + +/*! + \brief read ADC inserted group data register + \param[in] inserted_channel: inserted channel select + only one parameter can be selected which is shown as below: + \arg ADC_INSERTED_CHANNEL_0: ADC inserted channel 0 + \arg ADC_INSERTED_CHANNEL_1: ADC inserted channel 1 + \arg ADC_INSERTED_CHANNEL_2: ADC inserted channel 2 + \arg ADC_INSERTED_CHANNEL_3: ADC inserted channel 3 + \param[out] none + \retval the conversion value +*/ +uint16_t adc_inserted_data_read(uint8_t inserted_channel) +{ + uint32_t idata; + /* read the data of the selected channel */ + switch(inserted_channel) { + case ADC_INSERTED_CHANNEL_0: + idata = ADC_IDATA0; + break; + case ADC_INSERTED_CHANNEL_1: + idata = ADC_IDATA1; + break; + case ADC_INSERTED_CHANNEL_2: + idata = ADC_IDATA2; + break; + case ADC_INSERTED_CHANNEL_3: + idata = ADC_IDATA3; + break; + default: + idata = 0U; + break; + } + return (uint16_t)idata; +} + +/*! + \brief get the ADC flag bits + \param[in] flag: the adc flag bits + only one parameter can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_flag_get(uint32_t flag) +{ + FlagStatus reval = RESET; + + if(ADC_STAT & flag) { + reval = SET; + } + return reval; +} + +/*! + \brief clear the ADC flag + \param[in] flag: the adc flag + one or more parameters can be selected which is shown as below: + \arg ADC_FLAG_WDE: analog watchdog event flag + \arg ADC_FLAG_EOC: end of group conversion flag + \arg ADC_FLAG_EOIC: end of inserted group conversion flag + \arg ADC_FLAG_STIC: start flag of inserted channel group + \arg ADC_FLAG_STRC: start flag of regular channel group + \param[out] none + \retval none +*/ +void adc_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} + +/*! + \brief get the ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus adc_interrupt_flag_get(uint32_t flag) +{ + FlagStatus interrupt_flag = RESET; + uint32_t state; + + /* check the interrupt bits */ + switch(flag) { + case ADC_INT_FLAG_WDE: + state = ADC_STAT & ADC_STAT_WDE; + if((ADC_CTL0 & ADC_CTL0_WDEIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOC: + state = ADC_STAT & ADC_STAT_EOC; + if((ADC_CTL0 & ADC_CTL0_EOCIE) && state) { + interrupt_flag = SET; + } + break; + case ADC_INT_FLAG_EOIC: + state = ADC_STAT & ADC_STAT_EOIC; + if((ADC_CTL0 & ADC_CTL0_EOICIE) && state) { + interrupt_flag = SET; + } + break; + default: + break; + } + return interrupt_flag; +} + +/*! + \brief clear ADC interrupt flag + \param[in] flag: the adc interrupt flag + only one parameter can be selected which is shown as below: + \arg ADC_INT_FLAG_WDE: analog watchdog interrupt flag + \arg ADC_INT_FLAG_EOC: end of group conversion interrupt flag + \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt flag + \param[out] none + \retval none +*/ +void adc_interrupt_flag_clear(uint32_t flag) +{ + ADC_STAT &= ~((uint32_t)flag); +} + +/*! + \brief enable ADC interrupt + \param[in] interrupt: the adc interrupt + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_enable(uint32_t interrupt) +{ + /* enable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_WDEIE; + } + + /* enable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOCIE; + } + + /* enable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)) { + ADC_CTL0 |= (uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief disable ADC interrupt + \param[in] interrupt: the adc interrupt flag + one or more parameters can be selected which is shown as below: + \arg ADC_INT_WDE: analog watchdog interrupt + \arg ADC_INT_EOC: end of group conversion interrupt + \arg ADC_INT_EOIC: end of inserted group conversion interrupt + \param[out] none + \retval none +*/ +void adc_interrupt_disable(uint32_t interrupt) +{ + /* disable analog watchdog interrupt */ + if(RESET != (interrupt & ADC_INT_WDE)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_WDEIE; + } + + /* disable end of group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOC)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOCIE; + } + + /* disable end of inserted group conversion interrupt */ + if(RESET != (interrupt & ADC_INT_EOIC)) { + ADC_CTL0 &= ~(uint32_t)ADC_CTL0_EOICIE; + } +} + +/*! + \brief configure ADC analog watchdog single channel + \param[in] channel: the selected ADC channel + only one parameter can be selected which is shown as below: + \arg ADC_CHANNEL_x(x=0..9,16,17): ADC Channelx + \param[out] none + \retval none +*/ +void adc_watchdog_single_channel_enable(uint8_t channel) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); + + ADC_CTL0 |= (uint32_t)channel; + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); +} + +/*! + \brief configure ADC analog watchdog group channel + \param[in] channel_group: the channel group use analog watchdog + only one parameter can be selected which is shown as below: + \arg ADC_REGULAR_CHANNEL: regular channel group + \arg ADC_INSERTED_CHANNEL: inserted channel group + \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group + \param[out] none + \retval none +*/ +void adc_watchdog_group_channel_enable(uint8_t channel_group) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC); + + /* select the group */ + switch(channel_group) { + case ADC_REGULAR_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_RWDEN; + break; + case ADC_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)ADC_CTL0_IWDEN; + break; + case ADC_REGULAR_INSERTED_CHANNEL: + ADC_CTL0 |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN); + break; + default: + break; + } +} + +/*! + \brief disable ADC analog watchdog + \param[in] none + \param[out] none + \retval none +*/ +void adc_watchdog_disable(void) +{ + ADC_CTL0 &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL); +} + +/*! + \brief configure ADC analog watchdog threshold + \param[in] low_threshold: analog watchdog low threshold,0..4095 + \param[in] high_threshold: analog watchdog high threshold,0..4095 + \param[out] none + \retval none +*/ +void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold) +{ + ADC_WDLT = (uint32_t)WDLT_WDLT(low_threshold); + ADC_WDHT = (uint32_t)WDHT_WDHT(high_threshold); +} + + +/*! + \brief configure ADC resolution + \param[in] resolution: ADC resolution + only one parameter can be selected which is shown as below: + \arg ADC_RESOLUTION_12B: 12-bit ADC resolution + \arg ADC_RESOLUTION_10B: 10-bit ADC resolution + \arg ADC_RESOLUTION_8B: 8-bit ADC resolution + \arg ADC_RESOLUTION_6B: 6-bit ADC resolution + \param[out] none + \retval none +*/ +void adc_resolution_config(uint32_t resolution) +{ + ADC_CTL0 &= ~((uint32_t)ADC_CTL0_DRES); + ADC_CTL0 |= (uint32_t)resolution; +} + +/*! + \brief configure ADC oversample mode + \param[in] mode: ADC oversampling mode + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger + \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger + \param[in] shift: ADC oversampling shift + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift + \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift + \param[in] ratio: ADC oversampling ratio + only one parameter can be selected which is shown as below: + \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2 + \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4 + \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8 + \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16 + \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32 + \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64 + \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128 + \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256 + \param[out] none + \retval none +*/ +void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio) +{ + /* configure ADC oversampling mode */ + if(ADC_OVERSAMPLING_ONE_CONVERT == mode) { + ADC_OVSAMPCTL |= (uint32_t)ADC_OVSAMPCTL_TOVS; + } else { + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_TOVS); + } + + /* configure the shift and ratio */ + ADC_OVSAMPCTL &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS)); + ADC_OVSAMPCTL |= ((uint32_t)shift | (uint32_t)ratio); +} + +/*! + \brief enable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_enable(void) +{ + ADC_OVSAMPCTL |= ADC_OVSAMPCTL_OVSEN; +} + +/*! + \brief disable ADC oversample mode + \param[in] none + \param[out] none + \retval none +*/ +void adc_oversample_mode_disable(void) +{ + ADC_OVSAMPCTL &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN); +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c index 359ac2d..d4aff8f 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_cmp.c @@ -1,212 +1,212 @@ -/*! - \file gd32e23x_cmp.c - \brief CMP driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_cmp.h" - -/*! - \brief CMP deinit - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[out] none - \retval none -*/ -void cmp_deinit(cmp_enum cmp_periph) -{ - if(CMP0 == cmp_periph) { - CMP_CS &= ((uint32_t)0xFFFF0000U); - } else { - } -} - -/*! - \brief CMP mode init - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[in] operating_mode - \arg CMP_MODE_HIGHSPEED: high speed mode - \arg CMP_MODE_MIDDLESPEED: medium speed mode - \arg CMP_MODE_LOWSPEED: low speed mode - \arg CMP_MODE_VERYLOWSPEED: very-low speed mode - \param[in] inverting_input - \arg CMP_INVERTING_INPUT_1_4VREFINT: VREFINT *1/4 input - \arg CMP_INVERTING_INPUT_1_2VREFINT: VREFINT *1/2 input - \arg CMP_INVERTING_INPUT_3_4VREFINT: VREFINT *3/4 input - \arg CMP_INVERTING_INPUT_VREFINT: VREFINT input - \arg CMP_INVERTING_INPUT_PA4: PA4 input - \arg CMP_INVERTING_INPUT_PA5: PA5 input - \arg CMP_INVERTING_INPUT_PA0: PA0 input - \arg CMP_INVERTING_INPUT_PA2: PA2 input - \param[in] output_hysteresis - \arg CMP_HYSTERESIS_NO: output no hysteresis - \arg CMP_HYSTERESIS_LOW: output low hysteresis - \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis - \arg CMP_HYSTERESIS_HIGH: output high hysteresis - \param[out] none - \retval none -*/ -void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis) -{ - uint32_t temp = 0U; - - if(CMP0 == cmp_periph) { - /* initialize comparator 0 mode */ - temp = CMP_CS; - temp &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST); - temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis); - CMP_CS = temp; - } else { - } -} - -/*! - \brief CMP output init - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[in] output_selection - \arg CMP_OUTPUT_NONE: CMP output none - \arg CMP_OUTPUT_TIMER0_BKIN: CMP output TIMER0 break input - \arg CMP_OUTPUT_TIMER0_IC0: CMP output TIMER0_CH0 input capture - \arg CMP_OUTPUT_TIMER0_OCPRECLR: CMP output TIMER0 OCPRE_CLR input - \arg CMP_OUTPUT_TIMER2_IC0: CMP output TIMER2_CH0 input capture - \arg CMP_OUTPUT_TIMER2_OCPRECLR: CMP output TIMER2 OCPRE_CLR input - \param[in] output_polarity - \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted - \arg CMP_OUTPUT_POLARITY_NONINVERTED: output is not inverted - \param[out] none - \retval none -*/ -void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity) -{ - uint32_t temp = 0U; - - if(CMP0 == cmp_periph) { - /* initialize comparator 0 output */ - temp = CMP_CS; - temp &= ~(uint32_t)CMP_CS_CMP0OSEL; - temp |= (uint32_t)output_selection; - /* output polarity */ - if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) { - temp |= (uint32_t)CMP_CS_CMP0PL; - } else { - temp &= ~(uint32_t)CMP_CS_CMP0PL; - } - CMP_CS = temp; - } else { - } -} - -/*! - \brief enable CMP - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[out] none - \retval none -*/ -void cmp_enable(cmp_enum cmp_periph) -{ - if(CMP0 == cmp_periph) { - CMP_CS |= (uint32_t)CMP_CS_CMP0EN; - } else { - } -} - -/*! - \brief disable CMP - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[out] none - \retval none -*/ -void cmp_disable(cmp_enum cmp_periph) -{ - if(CMP0 == cmp_periph) { - CMP_CS &= ~(uint32_t)CMP_CS_CMP0EN; - } else { - } -} - -/*! - \brief enable CMP switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_enable(void) -{ - CMP_CS |= (uint32_t)CMP_CS_CMP0SW; -} - -/*! - \brief disable CMP switch - \param[in] none - \param[out] none - \retval none -*/ -void cmp_switch_disable(void) -{ - CMP_CS &= ~(uint32_t)CMP_CS_CMP0SW; -} - -/*! - \brief lock the CMP - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[out] none - \retval none -*/ -void cmp_lock_enable(cmp_enum cmp_periph) -{ - if(CMP0 == cmp_periph) { - /* lock CMP0 */ - CMP_CS |= (uint32_t)CMP_CS_CMP0LK; - } else { - } -} - -/*! - \brief get output level - \param[in] cmp_periph - \arg CMP0: comparator 0 - \param[out] none - \retval the output level -*/ -uint32_t cmp_output_level_get(cmp_enum cmp_periph) -{ - /* get output level of CMP0 */ - if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) { - return CMP_OUTPUTLEVEL_HIGH; - } else { - return CMP_OUTPUTLEVEL_LOW; - } -} +/*! + \file gd32e23x_cmp.c + \brief CMP driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_cmp.h" + +/*! + \brief CMP deinit + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[out] none + \retval none +*/ +void cmp_deinit(cmp_enum cmp_periph) +{ + if(CMP0 == cmp_periph) { + CMP_CS &= ((uint32_t)0xFFFF0000U); + } else { + } +} + +/*! + \brief CMP mode init + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[in] operating_mode + \arg CMP_MODE_HIGHSPEED: high speed mode + \arg CMP_MODE_MIDDLESPEED: medium speed mode + \arg CMP_MODE_LOWSPEED: low speed mode + \arg CMP_MODE_VERYLOWSPEED: very-low speed mode + \param[in] inverting_input + \arg CMP_INVERTING_INPUT_1_4VREFINT: VREFINT *1/4 input + \arg CMP_INVERTING_INPUT_1_2VREFINT: VREFINT *1/2 input + \arg CMP_INVERTING_INPUT_3_4VREFINT: VREFINT *3/4 input + \arg CMP_INVERTING_INPUT_VREFINT: VREFINT input + \arg CMP_INVERTING_INPUT_PA4: PA4 input + \arg CMP_INVERTING_INPUT_PA5: PA5 input + \arg CMP_INVERTING_INPUT_PA0: PA0 input + \arg CMP_INVERTING_INPUT_PA2: PA2 input + \param[in] output_hysteresis + \arg CMP_HYSTERESIS_NO: output no hysteresis + \arg CMP_HYSTERESIS_LOW: output low hysteresis + \arg CMP_HYSTERESIS_MIDDLE: output middle hysteresis + \arg CMP_HYSTERESIS_HIGH: output high hysteresis + \param[out] none + \retval none +*/ +void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis) +{ + uint32_t temp = 0U; + + if(CMP0 == cmp_periph) { + /* initialize comparator 0 mode */ + temp = CMP_CS; + temp &= ~(uint32_t)(CMP_CS_CMP0M | CMP_CS_CMP0MSEL | CMP_CS_CMP0HST); + temp |= (uint32_t)(operating_mode | inverting_input | output_hysteresis); + CMP_CS = temp; + } else { + } +} + +/*! + \brief CMP output init + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[in] output_selection + \arg CMP_OUTPUT_NONE: CMP output none + \arg CMP_OUTPUT_TIMER0_BKIN: CMP output TIMER0 break input + \arg CMP_OUTPUT_TIMER0_IC0: CMP output TIMER0_CH0 input capture + \arg CMP_OUTPUT_TIMER0_OCPRECLR: CMP output TIMER0 OCPRE_CLR input + \arg CMP_OUTPUT_TIMER2_IC0: CMP output TIMER2_CH0 input capture + \arg CMP_OUTPUT_TIMER2_OCPRECLR: CMP output TIMER2 OCPRE_CLR input + \param[in] output_polarity + \arg CMP_OUTPUT_POLARITY_INVERTED: output is inverted + \arg CMP_OUTPUT_POLARITY_NONINVERTED: output is not inverted + \param[out] none + \retval none +*/ +void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity) +{ + uint32_t temp = 0U; + + if(CMP0 == cmp_periph) { + /* initialize comparator 0 output */ + temp = CMP_CS; + temp &= ~(uint32_t)CMP_CS_CMP0OSEL; + temp |= (uint32_t)output_selection; + /* output polarity */ + if(CMP_OUTPUT_POLARITY_INVERTED == output_polarity) { + temp |= (uint32_t)CMP_CS_CMP0PL; + } else { + temp &= ~(uint32_t)CMP_CS_CMP0PL; + } + CMP_CS = temp; + } else { + } +} + +/*! + \brief enable CMP + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[out] none + \retval none +*/ +void cmp_enable(cmp_enum cmp_periph) +{ + if(CMP0 == cmp_periph) { + CMP_CS |= (uint32_t)CMP_CS_CMP0EN; + } else { + } +} + +/*! + \brief disable CMP + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[out] none + \retval none +*/ +void cmp_disable(cmp_enum cmp_periph) +{ + if(CMP0 == cmp_periph) { + CMP_CS &= ~(uint32_t)CMP_CS_CMP0EN; + } else { + } +} + +/*! + \brief enable CMP switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_enable(void) +{ + CMP_CS |= (uint32_t)CMP_CS_CMP0SW; +} + +/*! + \brief disable CMP switch + \param[in] none + \param[out] none + \retval none +*/ +void cmp_switch_disable(void) +{ + CMP_CS &= ~(uint32_t)CMP_CS_CMP0SW; +} + +/*! + \brief lock the CMP + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[out] none + \retval none +*/ +void cmp_lock_enable(cmp_enum cmp_periph) +{ + if(CMP0 == cmp_periph) { + /* lock CMP0 */ + CMP_CS |= (uint32_t)CMP_CS_CMP0LK; + } else { + } +} + +/*! + \brief get output level + \param[in] cmp_periph + \arg CMP0: comparator 0 + \param[out] none + \retval the output level +*/ +uint32_t cmp_output_level_get(cmp_enum cmp_periph) +{ + /* get output level of CMP0 */ + if((uint32_t)RESET != (CMP_CS & CMP_CS_CMP0O)) { + return CMP_OUTPUTLEVEL_HIGH; + } else { + return CMP_OUTPUTLEVEL_LOW; + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c index 4b24cbd..bc5c24c 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_crc.c @@ -1,241 +1,241 @@ -/*! - \file gd32e23x_crc.c - \brief CRC driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_crc.h" - -/*! - \brief deinit CRC calculation unit - \param[in] none - \param[out] none - \retval none -*/ -void crc_deinit(void) -{ - CRC_IDATA = (uint32_t)0xFFFFFFFFU; - CRC_DATA = (uint32_t)0xFFFFFFFFU; - CRC_FDATA = (uint32_t)0x00000000U; - CRC_POLY = (uint32_t)0x04C11DB7U; - CRC_CTL = CRC_CTL_RST; -} - -/*! - \brief enable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_enable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); - CRC_CTL |= (uint32_t)CRC_CTL_REV_O; -} - -/*! - \brief disable the reverse operation of output data - \param[in] none - \param[out] none - \retval none -*/ -void crc_reverse_output_data_disable(void) -{ - CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); -} - -/*! - \brief reset data register to the value of initializaiton data register - \param[in] none - \param[out] none - \retval none -*/ -void crc_data_register_reset(void) -{ - CRC_CTL |= (uint32_t)CRC_CTL_RST; -} - -/*! - \brief read the data register - \param[in] none - \param[out] none - \retval 32-bit value of the data register -*/ -uint32_t crc_data_register_read(void) -{ - uint32_t data; - data = CRC_DATA; - return (data); -} - -/*! - \brief read the free data register - \param[in] none - \param[out] none - \retval 8-bit value of the free data register -*/ -uint8_t crc_free_data_register_read(void) -{ - uint8_t fdata; - fdata = (uint8_t)CRC_FDATA; - return (fdata); -} - -/*! - \brief write the free data register - \param[in] free_data: specify 8-bit data - \param[out] none - \retval none -*/ -void crc_free_data_register_write(uint8_t free_data) -{ - CRC_FDATA = (uint32_t)free_data; -} - -/*! - \brief write the initializaiton data register - \param[in] init_data:specify 32-bit data - \param[out] none - \retval none -*/ -void crc_init_data_register_write(uint32_t init_data) -{ - CRC_IDATA = (uint32_t)init_data; -} - -/*! - \brief configure the CRC input data function - \param[in] data_reverse: specify input data reverse function - only one parameter can be selected which is shown as below: - \arg CRC_INPUT_DATA_NOT: input data is not reversed - \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits - \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits - \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits - \param[out] none - \retval none -*/ -void crc_input_data_reverse_config(uint32_t data_reverse) -{ - CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); - CRC_CTL |= (uint32_t)data_reverse; -} - -/*! - \brief configure the CRC size of polynomial function - \param[in] poly_size: size of polynomial - only one parameter can be selected which is shown as below: - \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation - \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation - \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation - \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation - \param[out] none - \retval none -*/ -void crc_polynomial_size_set(uint32_t poly_size) -{ - CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); - CRC_CTL |= (uint32_t)poly_size; -} - -/*! - \brief configure the CRC polynomial value function - \param[in] poly: configurable polynomial value - \param[out] none - \retval none -*/ -void crc_polynomial_set(uint32_t poly) -{ - CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); - CRC_POLY = poly; -} - -/*! - \brief CRC calculate single data - \param[in] sdata: specify input data - \param[in] data_format: input data format - only one parameter can be selected which is shown as below: - \arg INPUT_FORMAT_WORD: input data in word format - \arg INPUT_FORMAT_HALFWORD: input data in half-word format - \arg INPUT_FORMAT_BYTE: input data in byte format - \param[out] none - \retval CRC calculate value -*/ -uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format) -{ - if(INPUT_FORMAT_WORD == data_format) { - REG32(CRC) = sdata; - } else if(INPUT_FORMAT_HALFWORD == data_format) { - REG16(CRC) = (uint16_t)sdata; - } else { - REG8(CRC) = (uint8_t)sdata; - } - - return(CRC_DATA); -} - -/*! - \brief CRC calculate a data array - \param[in] array: pointer to the input data array - \param[in] size: size of the array - \param[in] data_format: input data format - only one parameter can be selected which is shown as below: - \arg INPUT_FORMAT_WORD: input data in word format - \arg INPUT_FORMAT_HALFWORD: input data in half-word format - \arg INPUT_FORMAT_BYTE: input data in byte format - \param[out] none - \retval CRC calculate value -*/ -uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format) -{ - uint8_t *data8; - uint16_t *data16; - uint32_t *data32; - uint32_t index; - - if(INPUT_FORMAT_WORD == data_format) { - data32 = (uint32_t *)array; - for(index = 0U; index < size; index++) { - REG32(CRC) = data32[index]; - } - } else if(INPUT_FORMAT_HALFWORD == data_format) { - data16 = (uint16_t *)array; - for(index = 0U; index < size; index++) { - REG16(CRC) = data16[index]; - } - } else { - data8 = (uint8_t *)array; - for(index = 0U; index < size; index++) { - REG8(CRC) = data8[index]; - } - } - - return (CRC_DATA); -} +/*! + \file gd32e23x_crc.c + \brief CRC driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_crc.h" + +/*! + \brief deinit CRC calculation unit + \param[in] none + \param[out] none + \retval none +*/ +void crc_deinit(void) +{ + CRC_IDATA = (uint32_t)0xFFFFFFFFU; + CRC_DATA = (uint32_t)0xFFFFFFFFU; + CRC_FDATA = (uint32_t)0x00000000U; + CRC_POLY = (uint32_t)0x04C11DB7U; + CRC_CTL = CRC_CTL_RST; +} + +/*! + \brief enable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_enable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); + CRC_CTL |= (uint32_t)CRC_CTL_REV_O; +} + +/*! + \brief disable the reverse operation of output data + \param[in] none + \param[out] none + \retval none +*/ +void crc_reverse_output_data_disable(void) +{ + CRC_CTL &= (uint32_t)(~ CRC_CTL_REV_O); +} + +/*! + \brief reset data register to the value of initializaiton data register + \param[in] none + \param[out] none + \retval none +*/ +void crc_data_register_reset(void) +{ + CRC_CTL |= (uint32_t)CRC_CTL_RST; +} + +/*! + \brief read the data register + \param[in] none + \param[out] none + \retval 32-bit value of the data register +*/ +uint32_t crc_data_register_read(void) +{ + uint32_t data; + data = CRC_DATA; + return (data); +} + +/*! + \brief read the free data register + \param[in] none + \param[out] none + \retval 8-bit value of the free data register +*/ +uint8_t crc_free_data_register_read(void) +{ + uint8_t fdata; + fdata = (uint8_t)CRC_FDATA; + return (fdata); +} + +/*! + \brief write the free data register + \param[in] free_data: specify 8-bit data + \param[out] none + \retval none +*/ +void crc_free_data_register_write(uint8_t free_data) +{ + CRC_FDATA = (uint32_t)free_data; +} + +/*! + \brief write the initializaiton data register + \param[in] init_data:specify 32-bit data + \param[out] none + \retval none +*/ +void crc_init_data_register_write(uint32_t init_data) +{ + CRC_IDATA = (uint32_t)init_data; +} + +/*! + \brief configure the CRC input data function + \param[in] data_reverse: specify input data reverse function + only one parameter can be selected which is shown as below: + \arg CRC_INPUT_DATA_NOT: input data is not reversed + \arg CRC_INPUT_DATA_BYTE: input data is reversed on 8 bits + \arg CRC_INPUT_DATA_HALFWORD: input data is reversed on 16 bits + \arg CRC_INPUT_DATA_WORD: input data is reversed on 32 bits + \param[out] none + \retval none +*/ +void crc_input_data_reverse_config(uint32_t data_reverse) +{ + CRC_CTL &= (uint32_t)(~CRC_CTL_REV_I); + CRC_CTL |= (uint32_t)data_reverse; +} + +/*! + \brief configure the CRC size of polynomial function + \param[in] poly_size: size of polynomial + only one parameter can be selected which is shown as below: + \arg CRC_CTL_PS_32: 32-bit polynomial for CRC calculation + \arg CRC_CTL_PS_16: 16-bit polynomial for CRC calculation + \arg CRC_CTL_PS_8: 8-bit polynomial for CRC calculation + \arg CRC_CTL_PS_7: 7-bit polynomial for CRC calculation + \param[out] none + \retval none +*/ +void crc_polynomial_size_set(uint32_t poly_size) +{ + CRC_CTL &= (uint32_t)(~(CRC_CTL_PS)); + CRC_CTL |= (uint32_t)poly_size; +} + +/*! + \brief configure the CRC polynomial value function + \param[in] poly: configurable polynomial value + \param[out] none + \retval none +*/ +void crc_polynomial_set(uint32_t poly) +{ + CRC_POLY &= (uint32_t)(~CRC_POLY_POLY); + CRC_POLY = poly; +} + +/*! + \brief CRC calculate single data + \param[in] sdata: specify input data + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format) +{ + if(INPUT_FORMAT_WORD == data_format) { + REG32(CRC) = sdata; + } else if(INPUT_FORMAT_HALFWORD == data_format) { + REG16(CRC) = (uint16_t)sdata; + } else { + REG8(CRC) = (uint8_t)sdata; + } + + return(CRC_DATA); +} + +/*! + \brief CRC calculate a data array + \param[in] array: pointer to the input data array + \param[in] size: size of the array + \param[in] data_format: input data format + only one parameter can be selected which is shown as below: + \arg INPUT_FORMAT_WORD: input data in word format + \arg INPUT_FORMAT_HALFWORD: input data in half-word format + \arg INPUT_FORMAT_BYTE: input data in byte format + \param[out] none + \retval CRC calculate value +*/ +uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format) +{ + uint8_t *data8; + uint16_t *data16; + uint32_t *data32; + uint32_t index; + + if(INPUT_FORMAT_WORD == data_format) { + data32 = (uint32_t *)array; + for(index = 0U; index < size; index++) { + REG32(CRC) = data32[index]; + } + } else if(INPUT_FORMAT_HALFWORD == data_format) { + data16 = (uint16_t *)array; + for(index = 0U; index < size; index++) { + REG16(CRC) = data16[index]; + } + } else { + data8 = (uint8_t *)array; + for(index = 0U; index < size; index++) { + REG8(CRC) = data8[index]; + } + } + + return (CRC_DATA); +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c index 78cf418..13aa724 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dbg.c @@ -1,138 +1,138 @@ -/*! - \file gd32e23x_dbg.c - \brief DBG driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_dbg.h" - -#define DBG_RESET_VAL 0x00000000U - -/*! - \brief deinitialize the DBG - \param[in] none - \param[out] none - \retval none -*/ -void dbg_deinit(void) -{ - DBG_CTL0 = DBG_RESET_VAL; - DBG_CTL1 = DBG_RESET_VAL; -} - -/*! - \brief read DBG_ID code register - \param[in] none - \param[out] none - \retval DBG_ID code -*/ -uint32_t dbg_id_get(void) -{ - return DBG_ID; -} - -/*! - \brief enable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_enable(uint32_t dbg_low_power) -{ - DBG_CTL0 |= dbg_low_power; -} - -/*! - \brief disable low power behavior when the mcu is in debug mode - \param[in] dbg_low_power: - this parameter can be any combination of the following values: - \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode - \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode - \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode - \param[out] none - \retval none -*/ -void dbg_low_power_disable(uint32_t dbg_low_power) -{ - DBG_CTL0 &= ~dbg_low_power; -} - -/*! - \brief enable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: DBG peripheral - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted - \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted - \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted - \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_enable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); -} - -/*! - \brief disable peripheral behavior when the mcu is in debug mode - \param[in] dbg_periph: DBG peripheral - only one parameter can be selected which is shown as below: - \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted - \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted - \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted - \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted - \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted - \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted - \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted - \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted - \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted - \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted - \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted - \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted - \param[out] none - \retval none -*/ -void dbg_periph_disable(dbg_periph_enum dbg_periph) -{ - DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); -} +/*! + \file gd32e23x_dbg.c + \brief DBG driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_dbg.h" + +#define DBG_RESET_VAL 0x00000000U + +/*! + \brief deinitialize the DBG + \param[in] none + \param[out] none + \retval none +*/ +void dbg_deinit(void) +{ + DBG_CTL0 = DBG_RESET_VAL; + DBG_CTL1 = DBG_RESET_VAL; +} + +/*! + \brief read DBG_ID code register + \param[in] none + \param[out] none + \retval DBG_ID code +*/ +uint32_t dbg_id_get(void) +{ + return DBG_ID; +} + +/*! + \brief enable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_enable(uint32_t dbg_low_power) +{ + DBG_CTL0 |= dbg_low_power; +} + +/*! + \brief disable low power behavior when the mcu is in debug mode + \param[in] dbg_low_power: + this parameter can be any combination of the following values: + \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode + \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode + \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode + \param[out] none + \retval none +*/ +void dbg_low_power_disable(uint32_t dbg_low_power) +{ + DBG_CTL0 &= ~dbg_low_power; +} + +/*! + \brief enable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: DBG peripheral + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted + \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted + \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted + \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_enable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph)); +} + +/*! + \brief disable peripheral behavior when the mcu is in debug mode + \param[in] dbg_periph: DBG peripheral + only one parameter can be selected which is shown as below: + \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted + \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted + \arg DBG_TIMER0_HOLD: TIMER0 counter kept when core is halted + \arg DBG_TIMER2_HOLD: TIMER2 counter kept when core is halted + \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted + \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted + \arg DBG_TIMER14_HOLD: hold TIMER14 counter when core is halted + \arg DBG_TIMER15_HOLD: hold TIMER15 counter when core is halted + \arg DBG_TIMER16_HOLD: hold TIMER16 counter when core is halted + \arg DBG_I2C0_HOLD: hold I2C0 SMBUS when core is halted + \arg DBG_I2C1_HOLD: hold I2C1 SMBUS when core is halted + \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted + \param[out] none + \retval none +*/ +void dbg_periph_disable(dbg_periph_enum dbg_periph) +{ + DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph)); +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c index 60e691d..bb11479 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_dma.c @@ -1,560 +1,560 @@ -/*! - \file gd32e23x_dma.c - \brief DMA driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_dma.h" - -/*! - \brief deinitialize DMA a channel registers - \param[in] channelx: specify which DMA channel is deinitialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_deinit(dma_channel_enum channelx) -{ - /* disable DMA a channel */ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; - /* reset DMA channel registers */ - DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; - DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; - DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; - DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; - DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); -} - -/*! - \brief initialize the parameters of DMA struct with the default values - \param[in] init_struct: the initialization data needed to initialize DMA channel - \param[out] none - \retval none -*/ -void dma_struct_para_init(dma_parameter_struct *init_struct) -{ - /* set the DMA struct with the default values */ - init_struct->periph_addr = 0U; - init_struct->periph_width = 0U; - init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; - init_struct->memory_addr = 0U; - init_struct->memory_width = 0U; - init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; - init_struct->number = 0U; - init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; - init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; -} - -/*! - \brief initialize DMA channel - \param[in] channelx: specify which DMA channel is initialized - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] init_struct: the data needed to initialize DMA channel - periph_addr: peripheral base address - periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT - periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE - memory_addr: memory base address - memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT - memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE - direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL - number: the number of remaining data to be transferred by the DMA - priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH - \param[out] none - \retval none -*/ -void dma_init(dma_channel_enum channelx, dma_parameter_struct *init_struct) -{ - uint32_t ctl; - - dma_channel_disable(channelx); - - /* configure peripheral base address */ - DMA_CHPADDR(channelx) = init_struct->periph_addr; - - /* configure memory base address */ - DMA_CHMADDR(channelx) = init_struct->memory_addr; - - /* configure the number of remaining data to be transferred */ - DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); - - /* configure peripheral transfer width,memory transfer width,channel priotity */ - ctl = DMA_CHCTL(channelx); - ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); - ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); - DMA_CHCTL(channelx) = ctl; - - /* configure peripheral increasing mode */ - if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; - } else { - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; - } - - /* configure memory increasing mode */ - if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; - } else { - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; - } - - /* configure the direction of data transfer */ - if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief enable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; -} - -/*! - \brief disable DMA circulation mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_circulation_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; -} - -/*! - \brief enable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; -} - -/*! - \brief disable memory to memory mode - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_to_memory_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; -} - -/*! - \brief enable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; -} - -/*! - \brief disable DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_channel_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; -} - -/*! - \brief set DMA peripheral base address - \param[in] channelx: specify which DMA channel to set peripheral base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] address: peripheral base address - \param[out] none - \retval none -*/ -void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHPADDR(channelx) = address; -} - -/*! - \brief set DMA memory base address - \param[in] channelx: specify which DMA channel to set memory base address - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] address: memory base address - \param[out] none - \retval none -*/ -void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) -{ - DMA_CHMADDR(channelx) = address; -} - -/*! - \brief set the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] number: the number of remaining data to be transferred by the DMA - \param[out] none - \retval none -*/ -void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) -{ - DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); -} - -/*! - \brief get the number of remaining data to be transferred by the DMA - \param[in] channelx: specify which DMA channel to set number - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval the number of remaining data to be transferred by the DMA -*/ -uint32_t dma_transfer_number_get(dma_channel_enum channelx) -{ - return (uint32_t)DMA_CHCNT(channelx); -} - -/*! - \brief configure priority level of DMA channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] priority: priority level of this channel - only one parameter can be selected which is shown as below: - \arg DMA_PRIORITY_LOW: low priority - \arg DMA_PRIORITY_MEDIUM: medium priority - \arg DMA_PRIORITY_HIGH: high priority - \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority - \param[out] none - \retval none -*/ -void dma_priority_config(dma_channel_enum channelx, uint32_t priority) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PRIO; - ctl |= priority; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] mwidth: transfer data width of memory - only one parameter can be selected which is shown as below: - \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit - \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit - \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit - \param[out] none - \retval none -*/ -void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_MWIDTH; - ctl |= mwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief configure transfer data width of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] pwidth: transfer data width of peripheral - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit - \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit - \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit - \param[out] none - \retval none -*/ -void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) -{ - uint32_t ctl; - - /* acquire DMA_CHxCTL register */ - ctl = DMA_CHCTL(channelx); - /* assign regiser */ - ctl &= ~DMA_CHXCTL_PWIDTH; - ctl |= pwidth; - DMA_CHCTL(channelx) = ctl; -} - -/*! - \brief enable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; -} - -/*! - \brief disable next address increasement algorithm of memory - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_memory_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; -} - -/*! - \brief enable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_enable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; -} - -/*! - \brief disable next address increasement algorithm of peripheral - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[out] none - \retval none -*/ -void dma_periph_increase_disable(dma_channel_enum channelx) -{ - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; -} - -/*! - \brief configure the direction of data transfer on the channel - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] direction: specify the direction of data transfer - only one parameter can be selected which is shown as below: - \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory - \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral - \param[out] none - \retval none -*/ -void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction) -{ - if(DMA_PERIPHERAL_TO_MEMORY == direction) { - DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; - } else { - DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; - } -} - -/*! - \brief check DMA flag is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - FlagStatus reval; - - if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))) { - reval = SET; - } else { - reval = RESET; - } - - return reval; -} - -/*! - \brief clear DMA a channel flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_FLAG_G: global interrupt flag of channel - \arg DMA_FLAG_FTF: full transfer finish flag of channel - \arg DMA_FLAG_HTF: half transfer finish flag of channel - \arg DMA_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief check DMA flag and interrupt enable bit is set or not - \param[in] channelx: specify which DMA channel to get flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) -{ - uint32_t interrupt_enable = 0U, interrupt_flag = 0U; - - switch(flag) { - case DMA_INT_FLAG_FTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; - break; - case DMA_INT_FLAG_HTF: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; - break; - case DMA_INT_FLAG_ERR: - interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); - interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; - break; - default: - break; - } - - if(interrupt_flag && interrupt_enable) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear DMA a channel interrupt flag - \param[in] channelx: specify which DMA channel to clear flag - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] flag: specify get which flag - only one parameter can be selected which is shown as below: - \arg DMA_INT_FLAG_G: global interrupt flag of channel - \arg DMA_INT_FLAG_FTF: transfer finish flag of channel - \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel - \arg DMA_INT_FLAG_ERR: error flag of channel - \param[out] none - \retval none -*/ -void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) -{ - DMA_INTC |= DMA_FLAG_ADD(flag, channelx); -} - -/*! - \brief enable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to enable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) |= source; -} - -/*! - \brief disable DMA interrupt - \param[in] channelx: specify which DMA channel to set - only one parameter can be selected which is shown as below: - \arg DMA_CHx(x=0..4) - \param[in] source: specify which interrupt to disable - only one parameter can be selected which is shown as below: - \arg DMA_INT_ERR: channel error interrupt - \arg DMA_INT_HTF: channel half transfer finish interrupt - \arg DMA_INT_FTF: channel full transfer finish interrupt - \param[out] none - \retval none -*/ -void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) -{ - DMA_CHCTL(channelx) &= ~source; -} +/*! + \file gd32e23x_dma.c + \brief DMA driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_dma.h" + +/*! + \brief deinitialize DMA a channel registers + \param[in] channelx: specify which DMA channel is deinitialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_deinit(dma_channel_enum channelx) +{ + /* disable DMA a channel */ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; + /* reset DMA channel registers */ + DMA_CHCTL(channelx) = DMA_CHCTL_RESET_VALUE; + DMA_CHCNT(channelx) = DMA_CHCNT_RESET_VALUE; + DMA_CHPADDR(channelx) = DMA_CHPADDR_RESET_VALUE; + DMA_CHMADDR(channelx) = DMA_CHMADDR_RESET_VALUE; + DMA_INTC |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx); +} + +/*! + \brief initialize the parameters of DMA struct with the default values + \param[in] init_struct: the initialization data needed to initialize DMA channel + \param[out] none + \retval none +*/ +void dma_struct_para_init(dma_parameter_struct *init_struct) +{ + /* set the DMA struct with the default values */ + init_struct->periph_addr = 0U; + init_struct->periph_width = 0U; + init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE; + init_struct->memory_addr = 0U; + init_struct->memory_width = 0U; + init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE; + init_struct->number = 0U; + init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY; + init_struct->priority = (uint32_t)DMA_PRIORITY_LOW; +} + +/*! + \brief initialize DMA channel + \param[in] channelx: specify which DMA channel is initialized + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] init_struct: the data needed to initialize DMA channel + periph_addr: peripheral base address + periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT + periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE + memory_addr: memory base address + memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT + memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE + direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL + number: the number of remaining data to be transferred by the DMA + priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH + \param[out] none + \retval none +*/ +void dma_init(dma_channel_enum channelx, dma_parameter_struct *init_struct) +{ + uint32_t ctl; + + dma_channel_disable(channelx); + + /* configure peripheral base address */ + DMA_CHPADDR(channelx) = init_struct->periph_addr; + + /* configure memory base address */ + DMA_CHMADDR(channelx) = init_struct->memory_addr; + + /* configure the number of remaining data to be transferred */ + DMA_CHCNT(channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK); + + /* configure peripheral transfer width,memory transfer width,channel priotity */ + ctl = DMA_CHCTL(channelx); + ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO); + ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority); + DMA_CHCTL(channelx) = ctl; + + /* configure peripheral increasing mode */ + if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) { + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; + } else { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; + } + + /* configure memory increasing mode */ + if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) { + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; + } else { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; + } + + /* configure the direction of data transfer */ + if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief enable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CMEN; +} + +/*! + \brief disable DMA circulation mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_circulation_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CMEN; +} + +/*! + \brief enable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_M2M; +} + +/*! + \brief disable memory to memory mode + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_to_memory_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_M2M; +} + +/*! + \brief enable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_CHEN; +} + +/*! + \brief disable DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_channel_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_CHEN; +} + +/*! + \brief set DMA peripheral base address + \param[in] channelx: specify which DMA channel to set peripheral base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] address: peripheral base address + \param[out] none + \retval none +*/ +void dma_periph_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHPADDR(channelx) = address; +} + +/*! + \brief set DMA memory base address + \param[in] channelx: specify which DMA channel to set memory base address + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] address: memory base address + \param[out] none + \retval none +*/ +void dma_memory_address_config(dma_channel_enum channelx, uint32_t address) +{ + DMA_CHMADDR(channelx) = address; +} + +/*! + \brief set the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] number: the number of remaining data to be transferred by the DMA + \param[out] none + \retval none +*/ +void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number) +{ + DMA_CHCNT(channelx) = (number & DMA_CHANNEL_CNT_MASK); +} + +/*! + \brief get the number of remaining data to be transferred by the DMA + \param[in] channelx: specify which DMA channel to set number + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval the number of remaining data to be transferred by the DMA +*/ +uint32_t dma_transfer_number_get(dma_channel_enum channelx) +{ + return (uint32_t)DMA_CHCNT(channelx); +} + +/*! + \brief configure priority level of DMA channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] priority: priority level of this channel + only one parameter can be selected which is shown as below: + \arg DMA_PRIORITY_LOW: low priority + \arg DMA_PRIORITY_MEDIUM: medium priority + \arg DMA_PRIORITY_HIGH: high priority + \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority + \param[out] none + \retval none +*/ +void dma_priority_config(dma_channel_enum channelx, uint32_t priority) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PRIO; + ctl |= priority; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] mwidth: transfer data width of memory + only one parameter can be selected which is shown as below: + \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit + \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit + \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit + \param[out] none + \retval none +*/ +void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_MWIDTH; + ctl |= mwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief configure transfer data width of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] pwidth: transfer data width of peripheral + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit + \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit + \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit + \param[out] none + \retval none +*/ +void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth) +{ + uint32_t ctl; + + /* acquire DMA_CHxCTL register */ + ctl = DMA_CHCTL(channelx); + /* assign regiser */ + ctl &= ~DMA_CHXCTL_PWIDTH; + ctl |= pwidth; + DMA_CHCTL(channelx) = ctl; +} + +/*! + \brief enable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_MNAGA; +} + +/*! + \brief disable next address increasement algorithm of memory + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_memory_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_MNAGA; +} + +/*! + \brief enable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_enable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) |= DMA_CHXCTL_PNAGA; +} + +/*! + \brief disable next address increasement algorithm of peripheral + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[out] none + \retval none +*/ +void dma_periph_increase_disable(dma_channel_enum channelx) +{ + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_PNAGA; +} + +/*! + \brief configure the direction of data transfer on the channel + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] direction: specify the direction of data transfer + only one parameter can be selected which is shown as below: + \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory + \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral + \param[out] none + \retval none +*/ +void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction) +{ + if(DMA_PERIPHERAL_TO_MEMORY == direction) { + DMA_CHCTL(channelx) &= ~DMA_CHXCTL_DIR; + } else { + DMA_CHCTL(channelx) |= DMA_CHXCTL_DIR; + } +} + +/*! + \brief check DMA flag is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + FlagStatus reval; + + if(RESET != (DMA_INTF & DMA_FLAG_ADD(flag, channelx))) { + reval = SET; + } else { + reval = RESET; + } + + return reval; +} + +/*! + \brief clear DMA a channel flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_FLAG_G: global interrupt flag of channel + \arg DMA_FLAG_FTF: full transfer finish flag of channel + \arg DMA_FLAG_HTF: half transfer finish flag of channel + \arg DMA_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief check DMA flag and interrupt enable bit is set or not + \param[in] channelx: specify which DMA channel to get flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag) +{ + uint32_t interrupt_enable = 0U, interrupt_flag = 0U; + + switch(flag) { + case DMA_INT_FLAG_FTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_FTFIE; + break; + case DMA_INT_FLAG_HTF: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_HTFIE; + break; + case DMA_INT_FLAG_ERR: + interrupt_flag = DMA_INTF & DMA_FLAG_ADD(flag, channelx); + interrupt_enable = DMA_CHCTL(channelx) & DMA_CHXCTL_ERRIE; + break; + default: + break; + } + + if(interrupt_flag && interrupt_enable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear DMA a channel interrupt flag + \param[in] channelx: specify which DMA channel to clear flag + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] flag: specify get which flag + only one parameter can be selected which is shown as below: + \arg DMA_INT_FLAG_G: global interrupt flag of channel + \arg DMA_INT_FLAG_FTF: transfer finish flag of channel + \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel + \arg DMA_INT_FLAG_ERR: error flag of channel + \param[out] none + \retval none +*/ +void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag) +{ + DMA_INTC |= DMA_FLAG_ADD(flag, channelx); +} + +/*! + \brief enable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to enable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) |= source; +} + +/*! + \brief disable DMA interrupt + \param[in] channelx: specify which DMA channel to set + only one parameter can be selected which is shown as below: + \arg DMA_CHx(x=0..4) + \param[in] source: specify which interrupt to disable + only one parameter can be selected which is shown as below: + \arg DMA_INT_ERR: channel error interrupt + \arg DMA_INT_HTF: channel half transfer finish interrupt + \arg DMA_INT_FTF: channel full transfer finish interrupt + \param[out] none + \retval none +*/ +void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source) +{ + DMA_CHCTL(channelx) &= ~source; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c index a25194b..cacb699 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_exti.c @@ -1,251 +1,251 @@ -/*! - \file gd32e23x_exti.c - \brief EXTI driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_exti.h" - -#define EXTI_INTEN_RESET_VAL ((uint32_t)0x0F900000U) -#define EXTI_REG_RESET_VAL ((uint32_t)0x00000000U) - - -/*! - \brief reset the value of all EXTI registers with initial values - \param[in] none - \param[out] none - \retval none -*/ -void exti_deinit(void) -{ - /* reset the value of the EXTI registers */ - EXTI_INTEN = EXTI_INTEN_RESET_VAL; - EXTI_EVEN = EXTI_REG_RESET_VAL; - EXTI_RTEN = EXTI_REG_RESET_VAL; - EXTI_FTEN = EXTI_REG_RESET_VAL; - EXTI_SWIEV = EXTI_REG_RESET_VAL; -} - -/*! - \brief initialize the EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[in] mode: interrupt or event mode, refer to exti_mode_enum - only one parameter can be selected which is shown as below: - \arg EXTI_INTERRUPT: interrupt mode - \arg EXTI_EVENT: event mode - \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum - only one parameter can be selected which is shown as below: - \arg EXTI_TRIG_RISING: rising edge trigger - \arg EXTI_TRIG_FALLING: falling trigger - \arg EXTI_TRIG_BOTH: rising and falling trigger - \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger - \param[out] none - \retval none -*/ -void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) -{ - /* reset the EXTI line x */ - EXTI_INTEN &= ~(uint32_t)linex; - EXTI_EVEN &= ~(uint32_t)linex; - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - - /* set the EXTI mode and enable the interrupts or events from EXTI line x */ - switch(mode) { - case EXTI_INTERRUPT: - EXTI_INTEN |= (uint32_t)linex; - break; - case EXTI_EVENT: - EXTI_EVEN |= (uint32_t)linex; - break; - default: - break; - } - - /* set the EXTI trigger type */ - switch(trig_type) { - case EXTI_TRIG_RISING: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN &= ~(uint32_t)linex; - break; - case EXTI_TRIG_FALLING: - EXTI_RTEN &= ~(uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_BOTH: - EXTI_RTEN |= (uint32_t)linex; - EXTI_FTEN |= (uint32_t)linex; - break; - case EXTI_TRIG_NONE: - default: - break; - } -} - -/*! - \brief enable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_enable(exti_line_enum linex) -{ - EXTI_INTEN |= (uint32_t)linex; -} - -/*! - \brief disable the interrupts from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_disable(exti_line_enum linex) -{ - EXTI_INTEN &= ~(uint32_t)linex; -} - -/*! - \brief enable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_enable(exti_line_enum linex) -{ - EXTI_EVEN |= (uint32_t)linex; -} - -/*! - \brief disable the events from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..27): EXTI line x - \param[out] none - \retval none -*/ -void exti_event_disable(exti_line_enum linex) -{ - EXTI_EVEN &= ~(uint32_t)linex; -} - -/*! - \brief enable the software interrupt event from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_enable(exti_line_enum linex) -{ - EXTI_SWIEV |= (uint32_t)linex; -} - -/*! - \brief disable the software interrupt event from EXTI line x - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_software_interrupt_disable(exti_line_enum linex) -{ - EXTI_SWIEV &= ~(uint32_t)linex; -} - -/*! - \brief get EXTI line x interrupt pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI line x interrupt pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} - -/*! - \brief get EXTI line x interrupt pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval FlagStatus: status of flag (RESET or SET) -*/ -FlagStatus exti_interrupt_flag_get(exti_line_enum linex) -{ - if(RESET != (EXTI_PD & (uint32_t)linex)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear EXTI line x interrupt pending flag - \param[in] linex: EXTI line number, refer to exti_line_enum - only one parameter can be selected which is shown as below: - \arg EXTI_x (x=0..17,19,21): EXTI line x - \param[out] none - \retval none -*/ -void exti_interrupt_flag_clear(exti_line_enum linex) -{ - EXTI_PD = (uint32_t)linex; -} +/*! + \file gd32e23x_exti.c + \brief EXTI driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_exti.h" + +#define EXTI_INTEN_RESET_VAL ((uint32_t)0x0F900000U) +#define EXTI_REG_RESET_VAL ((uint32_t)0x00000000U) + + +/*! + \brief reset the value of all EXTI registers with initial values + \param[in] none + \param[out] none + \retval none +*/ +void exti_deinit(void) +{ + /* reset the value of the EXTI registers */ + EXTI_INTEN = EXTI_INTEN_RESET_VAL; + EXTI_EVEN = EXTI_REG_RESET_VAL; + EXTI_RTEN = EXTI_REG_RESET_VAL; + EXTI_FTEN = EXTI_REG_RESET_VAL; + EXTI_SWIEV = EXTI_REG_RESET_VAL; +} + +/*! + \brief initialize the EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[in] mode: interrupt or event mode, refer to exti_mode_enum + only one parameter can be selected which is shown as below: + \arg EXTI_INTERRUPT: interrupt mode + \arg EXTI_EVENT: event mode + \param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum + only one parameter can be selected which is shown as below: + \arg EXTI_TRIG_RISING: rising edge trigger + \arg EXTI_TRIG_FALLING: falling trigger + \arg EXTI_TRIG_BOTH: rising and falling trigger + \arg EXTI_TRIG_NONE: without rising edge or falling edge trigger + \param[out] none + \retval none +*/ +void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type) +{ + /* reset the EXTI line x */ + EXTI_INTEN &= ~(uint32_t)linex; + EXTI_EVEN &= ~(uint32_t)linex; + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + + /* set the EXTI mode and enable the interrupts or events from EXTI line x */ + switch(mode) { + case EXTI_INTERRUPT: + EXTI_INTEN |= (uint32_t)linex; + break; + case EXTI_EVENT: + EXTI_EVEN |= (uint32_t)linex; + break; + default: + break; + } + + /* set the EXTI trigger type */ + switch(trig_type) { + case EXTI_TRIG_RISING: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN &= ~(uint32_t)linex; + break; + case EXTI_TRIG_FALLING: + EXTI_RTEN &= ~(uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_BOTH: + EXTI_RTEN |= (uint32_t)linex; + EXTI_FTEN |= (uint32_t)linex; + break; + case EXTI_TRIG_NONE: + default: + break; + } +} + +/*! + \brief enable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_enable(exti_line_enum linex) +{ + EXTI_INTEN |= (uint32_t)linex; +} + +/*! + \brief disable the interrupts from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_disable(exti_line_enum linex) +{ + EXTI_INTEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_enable(exti_line_enum linex) +{ + EXTI_EVEN |= (uint32_t)linex; +} + +/*! + \brief disable the events from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..27): EXTI line x + \param[out] none + \retval none +*/ +void exti_event_disable(exti_line_enum linex) +{ + EXTI_EVEN &= ~(uint32_t)linex; +} + +/*! + \brief enable the software interrupt event from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_enable(exti_line_enum linex) +{ + EXTI_SWIEV |= (uint32_t)linex; +} + +/*! + \brief disable the software interrupt event from EXTI line x + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval none +*/ +void exti_software_interrupt_disable(exti_line_enum linex) +{ + EXTI_SWIEV &= ~(uint32_t)linex; +} + +/*! + \brief get EXTI line x interrupt pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI line x interrupt pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval none +*/ +void exti_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} + +/*! + \brief get EXTI line x interrupt pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval FlagStatus: status of flag (RESET or SET) +*/ +FlagStatus exti_interrupt_flag_get(exti_line_enum linex) +{ + if(RESET != (EXTI_PD & (uint32_t)linex)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear EXTI line x interrupt pending flag + \param[in] linex: EXTI line number, refer to exti_line_enum + only one parameter can be selected which is shown as below: + \arg EXTI_x (x=0..17,19,21): EXTI line x + \param[out] none + \retval none +*/ +void exti_interrupt_flag_clear(exti_line_enum linex) +{ + EXTI_PD = (uint32_t)linex; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c index a55b4a9..082b427 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fmc.c @@ -1,825 +1,825 @@ -/*! - \file gd32e23x_fmc.c - \brief FMC driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_fmc.h" - -/* FMC register bit offset */ -#define OB_HIGH_WP_OFFSET ((uint32_t)8U) -#define FMC_OBSTAT_USER_OFFSET ((uint32_t)8U) -#define FMC_OBSTAT_DATA_OFFSET ((uint32_t)16U) - -/*! - \brief unlock the main FMC operation - it is better to used in pairs with fmc_lock - \param[in] none - \param[out] none - \retval none -*/ -void fmc_unlock(void) -{ - if((RESET != (FMC_CTL & FMC_CTL_LK))) { - /* write the FMC key */ - FMC_KEY = UNLOCK_KEY0; - FMC_KEY = UNLOCK_KEY1; - } -} - -/*! - \brief lock the main FMC operation - it is better to used in pairs with fmc_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void fmc_lock(void) -{ - /* set the LK bit*/ - FMC_CTL |= FMC_CTL_LK; -} - -/*! - \brief set the wait state counter value - \param[in] wscnt: wait state counter value - \arg WS_WSCNT_0: 0 wait state added - \arg WS_WSCNT_1: 1 wait state added - \arg WS_WSCNT_2: 2 wait state added - \param[out] none - \retval none -*/ -void fmc_wscnt_set(uint8_t wscnt) -{ - uint32_t reg; - - reg = FMC_WS; - /* set the wait state counter value */ - reg &= ~FMC_WS_WSCNT; - FMC_WS = (reg | wscnt); -} - -/*! - \brief pre-fetch enable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_enable(void) -{ - FMC_WS |= FMC_WS_PFEN; -} - -/*! - \brief pre-fetch disable - \param[in] none - \param[out] none - \retval none -*/ -void fmc_prefetch_disable(void) -{ - FMC_WS &= ~FMC_WS_PFEN; -} - -/*! - \brief erase page - \param[in] page_address: target page start address - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_page_erase(uint32_t page_address) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - /* start page erase */ - FMC_CTL |= FMC_CTL_PER; - FMC_ADDR = page_address; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PER bit */ - FMC_CTL &= ~FMC_CTL_PER; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief erase whole chip - \param[in] none - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_mass_erase(void) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - /* start chip erase */ - FMC_CTL |= FMC_CTL_MER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the MER bit */ - FMC_CTL &= ~FMC_CTL_MER; - } - - /* return the fmc state */ - return fmc_state; -} - -/*! - \brief program a double word at the corresponding address in main flash, this - function also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming - \param[in] address: address to program - \param[in] data: double word to program - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) -{ - uint32_t data0, data1; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - data0 = (uint32_t)(data & 0xFFFFFFFFU); - data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); - - /* configure program width */ - FMC_WS |= FMC_WS_PGW; - if(FMC_READY == fmc_state) { - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - REG32(address) = data0; - REG32(address + 4U) = data1; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - FMC_WS &= ~(FMC_WS_PGW); - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program a word at the corresponding address in main flash, this function - also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming - \param[in] address: address to program - \param[in] data: word to program - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - /* set the PG bit to start program */ - FMC_CTL |= FMC_CTL_PG; - - REG32(address) = data; - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* reset the PG bit */ - FMC_CTL &= ~FMC_CTL_PG; - } - - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief unlock the option byte operation - it is better to used in pairs with ob_lock - \param[in] none - \param[out] none - \retval none -*/ -void ob_unlock(void) -{ - if(RESET == (FMC_CTL & FMC_CTL_OBWEN)) { - /* write the FMC key */ - FMC_OBKEY = UNLOCK_KEY0; - FMC_OBKEY = UNLOCK_KEY1; - } - /* wait until OBWEN bit is set by hardware */ - while(RESET == (FMC_CTL & FMC_CTL_OBWEN)) { - } -} - -/*! - \brief lock the option byte operation - it is better to used in pairs with ob_unlock after an operation - \param[in] none - \param[out] none - \retval none -*/ -void ob_lock(void) -{ - /* reset the OBWE bit */ - FMC_CTL &= ~FMC_CTL_OBWEN; -} - -/*! - \brief reload the option byte and generate a system reset - \param[in] none - \param[out] none - \retval none -*/ -void ob_reset(void) -{ - /* set the OBRLD bit */ - FMC_CTL |= FMC_CTL_OBRLD; -} - -/*! - \brief get option byte value - \param[in] addr: address of option byte - \arg OB_SPC_USER_ADDRESS: address of option byte security protection and user - \arg OB_DATA_ADDRESS: address of option byte data - \arg OB_WP_ADDRESS: address of option byte write protection - \param[out] option byte value -*/ -uint32_t option_byte_value_get(uint32_t addr) -{ - return *(volatile uint32_t *)(addr); -} - -/*! - \brief erase the option byte - programmer must ensure FMC & option byte are both unlocked before calling this function - \param[in] none - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_erase(void) -{ - uint16_t fmc_spc; - uint32_t val; - uint32_t fmc_plevel = ob_obstat_plevel_get(); - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - /* get the original option byte security protection code */ - if(OB_OBSTAT_PLEVEL_NO == fmc_plevel) { - fmc_spc = FMC_NSPC; - } else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel) { - fmc_spc = FMC_LSPC; - } else { - fmc_spc = FMC_HSPC; - fmc_state = FMC_OB_HSPC; - } - val = HIGH_16BITS_MASK | (uint32_t)fmc_spc; - - if(FMC_READY == fmc_state) { - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - - /* restore the last get option byte security protection code */ - OB_SPC_USER = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } else { - if(FMC_TOERR != fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief enable option byte write protection (OB_WP) - \param[in] ob_wp: write protection configuration data. Notice that set the - bit to 1 if you want to protect the corresponding pages. - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) -{ - uint32_t ob_wrp_val = 0U; - - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - ob_wp = ~ob_wp; - ob_wrp_val |= (uint32_t)ob_wp & 0x00FFU; - ob_wrp_val |= (((uint32_t)ob_wp & 0xFF00U) >> 8U) << 16U; - - if(FMC_READY == fmc_state) { - /* set the OBPG bit*/ - FMC_CTL |= FMC_CTL_OBPG; - - if(0xFFFFFFFFU != ob_wrp_val) { - OB_WP = ob_wrp_val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - - ob_wrp_val |= (uint32_t)(ob_wp >> 16) & 0x00FFU; - ob_wrp_val |= (((uint32_t)(ob_wp >> 16) & 0xFF00U) >> 8U) << 16U; - if(0xFFFFFFFFU != ob_wrp_val) { - REG32((OB) + 0x0CU) = ob_wrp_val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - } - - if(FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief configure security protection - \param[in] ob_spc: specify security protection code - \arg FMC_NSPC: no security protection - \arg FMC_LSPC: low security protection - \arg FMC_HSPC: high security protection - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_security_protection_config(uint16_t ob_spc) -{ - uint32_t val; - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - val = option_byte_value_get(OB_SPC_USER_ADDRESS); - /* the OB_SPC byte cannot be reprogrammed if protection level is high */ - if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()) { - fmc_state = FMC_OB_HSPC; - } - - val &= ~LOW_16BITS_MASK; - val |= (uint32_t)ob_spc; - - if(FMC_READY == fmc_state) { - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - OB_SPC_USER = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } else { - if(FMC_TOERR != fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC user option byte - this function can only clear the corresponding bits to be 0 rather than 1. - the function ob_erase is used to set all the bits to be 1. - \param[in] ob_user: user option byte - one or more parameters (bitwise AND) can be selected which are shown as below: - \arg OB_FWDGT_HW: hardware free watchdog timer - \arg OB_DEEPSLEEP_RST: no reset when entering deepsleep mode - \arg OB_STDBY_RST: no reset when entering standby mode - \arg OB_BOOT1_SET_1: BOOT1 bit is 1 - \arg OB_VDDA_DISABLE: disable VDDA monitor - \arg OB_SRAM_PARITY_ENABLE: enable sram parity check - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_user_write(uint8_t ob_user) -{ - uint32_t val_spc_user; - /* check whether FMC is ready or not */ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - val_spc_user = option_byte_value_get(OB_SPC_USER_ADDRESS); - - val_spc_user &= ~HIGH_16BITS_MASK; - - val_spc_user |= ((uint32_t)ob_user << 16U); - - if(FMC_READY == fmc_state) { - /* start erase the option byte */ - FMC_CTL |= FMC_CTL_OBER; - FMC_CTL |= FMC_CTL_START; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_READY == fmc_state) { - - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - - /* enable the option bytes programming */ - FMC_CTL |= FMC_CTL_OBPG; - - OB_SPC_USER = val_spc_user; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } else { - if(FMC_TOERR != fmc_state) { - /* reset the OBER bit */ - FMC_CTL &= ~FMC_CTL_OBER; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief program the FMC data option byte - \param[in] data: the data to be programmed, OB_DATA[0:15] - \param[out] none - \retval fmc_state: state of FMC - \arg FMC_READY: the operation has been completed - \arg FMC_BUSY: the operation is in progress - \arg FMC_PGERR: program error - \arg FMC_PGAERR: program alignment error - \arg FMC_WPERR: erase/program protection error - \arg FMC_TOERR: timeout error - \arg FMC_OB_HSPC: option byte security protection code high -*/ -fmc_state_enum ob_data_program(uint16_t data) -{ - fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - uint32_t val = 0U; - - val |= (uint32_t)data & 0x00FFU; - val |= (((uint32_t)data & 0xFF00U) >> 8U) << 16U; - - if(FMC_READY == fmc_state) { - /* set the OBPG bit */ - FMC_CTL |= FMC_CTL_OBPG; - OB_DATA = val; - - /* wait for the FMC ready */ - fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); - - if(FMC_TOERR != fmc_state) { - /* reset the OBPG bit */ - FMC_CTL &= ~FMC_CTL_OBPG; - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief get OB_USER in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_user -*/ -uint8_t ob_user_get(void) -{ - return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET); -} - -/*! - \brief get OB_DATA in register FMC_OBSTAT - \param[in] none - \param[out] none - \retval ob_data -*/ -uint16_t ob_data_get(void) -{ - return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET); -} - -/*! - \brief get the FMC option byte write protection (OB_WP) in register FMC_WP - \param[in] none - \param[out] none - \retval OB_WP -*/ -uint32_t ob_write_protection_get(void) -{ - return (uint32_t)(FMC_WP); -} - -/*! - \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register - \param[in] none - \param[out] none - \retval the value of PLEVEL - \arg OB_OBSTAT_PLEVEL_NO: no security protection - \arg OB_OBSTAT_PLEVEL_LOW: low security protection - \arg OB_OBSTAT_PLEVEL_HIGH: high security protection -*/ -uint32_t ob_obstat_plevel_get(void) -{ - return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); -} - -/* FMC interrupts and flags management functions */ -/*! - \brief enable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_enable(uint32_t interrupt) -{ - FMC_CTL |= interrupt; -} - -/*! - \brief disable FMC interrupt - \param[in] interrupt: the FMC interrupt source - \arg FMC_INTEN_END: FMC end of operation interrupt - \arg FMC_INTEN_ERR: FMC error interrupt - \param[out] none - \retval none -*/ -void fmc_interrupt_disable(uint32_t interrupt) -{ - FMC_CTL &= ~(uint32_t)interrupt; -} - -/*! - \brief get flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_FLAG_BUSY: FMC busy flag - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_flag_get(uint32_t flag) -{ - FlagStatus status = RESET; - - if(FMC_STAT & flag) { - status = SET; - } - /* return the state of corresponding FMC flag */ - return status; -} - -/*! - \brief clear the FMC pending flag by writing 1 - \param[in] flag: clear FMC flag - one or more parameters can be selected which is shown as below: - \arg FMC_FLAG_PGERR: FMC programming error flag - \arg FMC_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_FLAG_WPERR: FMC write protection error flag - \arg FMC_FLAG_END: FMC end of programming flag - \param[out] none - \retval none -*/ -void fmc_flag_clear(uint32_t flag) -{ - /* clear the flags */ - FMC_STAT = flag; -} - -/*! - \brief get intrrupt flag set or reset - \param[in] flag: check FMC flag - only one parameter can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC programming error flag - \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_INT_FLAG_WPERR: FMC write protection error flag - \arg FMC_INT_FLAG_END: FMC end of programming flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fmc_interrupt_flag_get(uint32_t int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - - if(FMC_INT_FLAG_END == int_flag) { - /* get the interrupt enable bit status */ - intenable = FMC_CTL & FMC_INTEN_END; - /* get the corresponding flag bit status */ - flagstatus = FMC_STAT & int_flag; - if(intenable && flagstatus) { - return SET; - } else { - return RESET; - } - } else { - /* get the interrupt enable bit status */ - intenable = FMC_CTL & FMC_INTEN_ERR; - /* get the corresponding flag bit status */ - flagstatus = FMC_STAT & int_flag; - if(intenable && flagstatus) { - return SET; - } else { - return RESET; - } - } -} - -/*! - \brief clear the FMC interrupt pending flag by writing 1 - \param[in] flag: clear FMC flag - one or more parameters can be selected which is shown as below: - \arg FMC_INT_FLAG_PGERR: FMC programming error flag - \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag - \arg FMC_INT_FLAG_WPERR: FMC write protection error flag - \arg FMC_INT_FLAG_END: FMC end of programming flag - \param[out] none - \retval none -*/ -void fmc_interrupt_flag_clear(uint32_t int_flag) -{ - /* clear the flags */ - FMC_STAT = int_flag; -} - -/*! - \brief get the FMC state - \param[in] none - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_state_get(void) -{ - fmc_state_enum fmc_state = FMC_READY; - - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { - fmc_state = FMC_BUSY; - } else { - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { - fmc_state = FMC_WPERR; - } else { - if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)) { - fmc_state = FMC_PGERR; - } - } - } - /* return the FMC state */ - return fmc_state; -} - -/*! - \brief check whether FMC is ready or not - \param[in] timeout: timeout count - \param[out] none - \retval fmc_state -*/ -fmc_state_enum fmc_ready_wait(uint32_t timeout) -{ - fmc_state_enum fmc_state = FMC_BUSY; - - /* wait for FMC ready */ - do { - /* get FMC state */ - fmc_state = fmc_state_get(); - timeout--; - } while((FMC_BUSY == fmc_state) && (0U != timeout)); - - if(FMC_BUSY == fmc_state) { - fmc_state = FMC_TOERR; - } - /* return the FMC state */ - return fmc_state; -} +/*! + \file gd32e23x_fmc.c + \brief FMC driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_fmc.h" + +/* FMC register bit offset */ +#define OB_HIGH_WP_OFFSET ((uint32_t)8U) +#define FMC_OBSTAT_USER_OFFSET ((uint32_t)8U) +#define FMC_OBSTAT_DATA_OFFSET ((uint32_t)16U) + +/*! + \brief unlock the main FMC operation + it is better to used in pairs with fmc_lock + \param[in] none + \param[out] none + \retval none +*/ +void fmc_unlock(void) +{ + if((RESET != (FMC_CTL & FMC_CTL_LK))) { + /* write the FMC key */ + FMC_KEY = UNLOCK_KEY0; + FMC_KEY = UNLOCK_KEY1; + } +} + +/*! + \brief lock the main FMC operation + it is better to used in pairs with fmc_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void fmc_lock(void) +{ + /* set the LK bit*/ + FMC_CTL |= FMC_CTL_LK; +} + +/*! + \brief set the wait state counter value + \param[in] wscnt: wait state counter value + \arg WS_WSCNT_0: 0 wait state added + \arg WS_WSCNT_1: 1 wait state added + \arg WS_WSCNT_2: 2 wait state added + \param[out] none + \retval none +*/ +void fmc_wscnt_set(uint8_t wscnt) +{ + uint32_t reg; + + reg = FMC_WS; + /* set the wait state counter value */ + reg &= ~FMC_WS_WSCNT; + FMC_WS = (reg | wscnt); +} + +/*! + \brief pre-fetch enable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_prefetch_enable(void) +{ + FMC_WS |= FMC_WS_PFEN; +} + +/*! + \brief pre-fetch disable + \param[in] none + \param[out] none + \retval none +*/ +void fmc_prefetch_disable(void) +{ + FMC_WS &= ~FMC_WS_PFEN; +} + +/*! + \brief erase page + \param[in] page_address: target page start address + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum fmc_page_erase(uint32_t page_address) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start page erase */ + FMC_CTL |= FMC_CTL_PER; + FMC_ADDR = page_address; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PER bit */ + FMC_CTL &= ~FMC_CTL_PER; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief erase whole chip + \param[in] none + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum fmc_mass_erase(void) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* start chip erase */ + FMC_CTL |= FMC_CTL_MER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the MER bit */ + FMC_CTL &= ~FMC_CTL_MER; + } + + /* return the fmc state */ + return fmc_state; +} + +/*! + \brief program a double word at the corresponding address in main flash, this + function also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming + \param[in] address: address to program + \param[in] data: double word to program + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data) +{ + uint32_t data0, data1; + + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + data0 = (uint32_t)(data & 0xFFFFFFFFU); + data1 = (uint32_t)((data >> 32U) & 0xFFFFFFFFU); + + /* configure program width */ + FMC_WS |= FMC_WS_PGW; + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + REG32(address) = data0; + REG32(address + 4U) = data1; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + FMC_WS &= ~(FMC_WS_PGW); + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program a word at the corresponding address in main flash, this function + also applies to OTP(address 0x1FFF_7000~0x1FFF_73FF) programming + \param[in] address: address to program + \param[in] data: word to program + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum fmc_word_program(uint32_t address, uint32_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* set the PG bit to start program */ + FMC_CTL |= FMC_CTL_PG; + + REG32(address) = data; + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* reset the PG bit */ + FMC_CTL &= ~FMC_CTL_PG; + } + + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief unlock the option byte operation + it is better to used in pairs with ob_lock + \param[in] none + \param[out] none + \retval none +*/ +void ob_unlock(void) +{ + if(RESET == (FMC_CTL & FMC_CTL_OBWEN)) { + /* write the FMC key */ + FMC_OBKEY = UNLOCK_KEY0; + FMC_OBKEY = UNLOCK_KEY1; + } + /* wait until OBWEN bit is set by hardware */ + while(RESET == (FMC_CTL & FMC_CTL_OBWEN)) { + } +} + +/*! + \brief lock the option byte operation + it is better to used in pairs with ob_unlock after an operation + \param[in] none + \param[out] none + \retval none +*/ +void ob_lock(void) +{ + /* reset the OBWE bit */ + FMC_CTL &= ~FMC_CTL_OBWEN; +} + +/*! + \brief reload the option byte and generate a system reset + \param[in] none + \param[out] none + \retval none +*/ +void ob_reset(void) +{ + /* set the OBRLD bit */ + FMC_CTL |= FMC_CTL_OBRLD; +} + +/*! + \brief get option byte value + \param[in] addr: address of option byte + \arg OB_SPC_USER_ADDRESS: address of option byte security protection and user + \arg OB_DATA_ADDRESS: address of option byte data + \arg OB_WP_ADDRESS: address of option byte write protection + \param[out] option byte value +*/ +uint32_t option_byte_value_get(uint32_t addr) +{ + return *(volatile uint32_t *)(addr); +} + +/*! + \brief erase the option byte + programmer must ensure FMC & option byte are both unlocked before calling this function + \param[in] none + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum ob_erase(void) +{ + uint16_t fmc_spc; + uint32_t val; + uint32_t fmc_plevel = ob_obstat_plevel_get(); + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + /* get the original option byte security protection code */ + if(OB_OBSTAT_PLEVEL_NO == fmc_plevel) { + fmc_spc = FMC_NSPC; + } else if(OB_OBSTAT_PLEVEL_LOW == fmc_plevel) { + fmc_spc = FMC_LSPC; + } else { + fmc_spc = FMC_HSPC; + fmc_state = FMC_OB_HSPC; + } + val = HIGH_16BITS_MASK | (uint32_t)fmc_spc; + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + + /* restore the last get option byte security protection code */ + OB_SPC_USER = val; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief enable option byte write protection (OB_WP) + \param[in] ob_wp: write protection configuration data. Notice that set the + bit to 1 if you want to protect the corresponding pages. + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum ob_write_protection_enable(uint32_t ob_wp) +{ + uint32_t ob_wrp_val = 0U; + + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + ob_wp = ~ob_wp; + ob_wrp_val |= (uint32_t)ob_wp & 0x00FFU; + ob_wrp_val |= (((uint32_t)ob_wp & 0xFF00U) >> 8U) << 16U; + + if(FMC_READY == fmc_state) { + /* set the OBPG bit*/ + FMC_CTL |= FMC_CTL_OBPG; + + if(0xFFFFFFFFU != ob_wrp_val) { + OB_WP = ob_wrp_val; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + ob_wrp_val |= (uint32_t)(ob_wp >> 16) & 0x00FFU; + ob_wrp_val |= (((uint32_t)(ob_wp >> 16) & 0xFF00U) >> 8U) << 16U; + if(0xFFFFFFFFU != ob_wrp_val) { + REG32((OB) + 0x0CU) = ob_wrp_val; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + } + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief configure security protection + \param[in] ob_spc: specify security protection code + \arg FMC_NSPC: no security protection + \arg FMC_LSPC: low security protection + \arg FMC_HSPC: high security protection + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum ob_security_protection_config(uint16_t ob_spc) +{ + uint32_t val; + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + val = option_byte_value_get(OB_SPC_USER_ADDRESS); + /* the OB_SPC byte cannot be reprogrammed if protection level is high */ + if(OB_OBSTAT_PLEVEL_HIGH == ob_obstat_plevel_get()) { + fmc_state = FMC_OB_HSPC; + } + + val &= ~LOW_16BITS_MASK; + val |= (uint32_t)ob_spc; + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + OB_SPC_USER = val; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC user option byte + this function can only clear the corresponding bits to be 0 rather than 1. + the function ob_erase is used to set all the bits to be 1. + \param[in] ob_user: user option byte + one or more parameters (bitwise AND) can be selected which are shown as below: + \arg OB_FWDGT_HW: hardware free watchdog timer + \arg OB_DEEPSLEEP_RST: no reset when entering deepsleep mode + \arg OB_STDBY_RST: no reset when entering standby mode + \arg OB_BOOT1_SET_1: BOOT1 bit is 1 + \arg OB_VDDA_DISABLE: disable VDDA monitor + \arg OB_SRAM_PARITY_ENABLE: enable sram parity check + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum ob_user_write(uint8_t ob_user) +{ + uint32_t val_spc_user; + /* check whether FMC is ready or not */ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + val_spc_user = option_byte_value_get(OB_SPC_USER_ADDRESS); + + val_spc_user &= ~HIGH_16BITS_MASK; + + val_spc_user |= ((uint32_t)ob_user << 16U); + + if(FMC_READY == fmc_state) { + /* start erase the option byte */ + FMC_CTL |= FMC_CTL_OBER; + FMC_CTL |= FMC_CTL_START; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_READY == fmc_state) { + + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + + /* enable the option bytes programming */ + FMC_CTL |= FMC_CTL_OBPG; + + OB_SPC_USER = val_spc_user; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } else { + if(FMC_TOERR != fmc_state) { + /* reset the OBER bit */ + FMC_CTL &= ~FMC_CTL_OBER; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief program the FMC data option byte + \param[in] data: the data to be programmed, OB_DATA[0:15] + \param[out] none + \retval fmc_state: state of FMC + \arg FMC_READY: the operation has been completed + \arg FMC_BUSY: the operation is in progress + \arg FMC_PGERR: program error + \arg FMC_PGAERR: program alignment error + \arg FMC_WPERR: erase/program protection error + \arg FMC_TOERR: timeout error + \arg FMC_OB_HSPC: option byte security protection code high +*/ +fmc_state_enum ob_data_program(uint16_t data) +{ + fmc_state_enum fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + uint32_t val = 0U; + + val |= (uint32_t)data & 0x00FFU; + val |= (((uint32_t)data & 0xFF00U) >> 8U) << 16U; + + if(FMC_READY == fmc_state) { + /* set the OBPG bit */ + FMC_CTL |= FMC_CTL_OBPG; + OB_DATA = val; + + /* wait for the FMC ready */ + fmc_state = fmc_ready_wait(FMC_TIMEOUT_COUNT); + + if(FMC_TOERR != fmc_state) { + /* reset the OBPG bit */ + FMC_CTL &= ~FMC_CTL_OBPG; + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief get OB_USER in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_user +*/ +uint8_t ob_user_get(void) +{ + return (uint8_t)(FMC_OBSTAT >> FMC_OBSTAT_USER_OFFSET); +} + +/*! + \brief get OB_DATA in register FMC_OBSTAT + \param[in] none + \param[out] none + \retval ob_data +*/ +uint16_t ob_data_get(void) +{ + return (uint16_t)(FMC_OBSTAT >> FMC_OBSTAT_DATA_OFFSET); +} + +/*! + \brief get the FMC option byte write protection (OB_WP) in register FMC_WP + \param[in] none + \param[out] none + \retval OB_WP +*/ +uint32_t ob_write_protection_get(void) +{ + return (uint32_t)(FMC_WP); +} + +/*! + \brief get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register + \param[in] none + \param[out] none + \retval the value of PLEVEL + \arg OB_OBSTAT_PLEVEL_NO: no security protection + \arg OB_OBSTAT_PLEVEL_LOW: low security protection + \arg OB_OBSTAT_PLEVEL_HIGH: high security protection +*/ +uint32_t ob_obstat_plevel_get(void) +{ + return (FMC_OBSTAT & (FMC_OBSTAT_PLEVEL_BIT0 | FMC_OBSTAT_PLEVEL_BIT1)); +} + +/* FMC interrupts and flags management functions */ +/*! + \brief enable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_enable(uint32_t interrupt) +{ + FMC_CTL |= interrupt; +} + +/*! + \brief disable FMC interrupt + \param[in] interrupt: the FMC interrupt source + \arg FMC_INTEN_END: FMC end of operation interrupt + \arg FMC_INTEN_ERR: FMC error interrupt + \param[out] none + \retval none +*/ +void fmc_interrupt_disable(uint32_t interrupt) +{ + FMC_CTL &= ~(uint32_t)interrupt; +} + +/*! + \brief get flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_FLAG_BUSY: FMC busy flag + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_PGAERR: FMC program alignment error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_flag_get(uint32_t flag) +{ + FlagStatus status = RESET; + + if(FMC_STAT & flag) { + status = SET; + } + /* return the state of corresponding FMC flag */ + return status; +} + +/*! + \brief clear the FMC pending flag by writing 1 + \param[in] flag: clear FMC flag + one or more parameters can be selected which is shown as below: + \arg FMC_FLAG_PGERR: FMC programming error flag + \arg FMC_FLAG_PGAERR: FMC program alignment error flag + \arg FMC_FLAG_WPERR: FMC write protection error flag + \arg FMC_FLAG_END: FMC end of programming flag + \param[out] none + \retval none +*/ +void fmc_flag_clear(uint32_t flag) +{ + /* clear the flags */ + FMC_STAT = flag; +} + +/*! + \brief get intrrupt flag set or reset + \param[in] flag: check FMC flag + only one parameter can be selected which is shown as below: + \arg FMC_INT_FLAG_PGERR: FMC programming error flag + \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag + \arg FMC_INT_FLAG_WPERR: FMC write protection error flag + \arg FMC_INT_FLAG_END: FMC end of programming flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fmc_interrupt_flag_get(uint32_t int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + + if(FMC_INT_FLAG_END == int_flag) { + /* get the interrupt enable bit status */ + intenable = FMC_CTL & FMC_INTEN_END; + /* get the corresponding flag bit status */ + flagstatus = FMC_STAT & int_flag; + if(intenable && flagstatus) { + return SET; + } else { + return RESET; + } + } else { + /* get the interrupt enable bit status */ + intenable = FMC_CTL & FMC_INTEN_ERR; + /* get the corresponding flag bit status */ + flagstatus = FMC_STAT & int_flag; + if(intenable && flagstatus) { + return SET; + } else { + return RESET; + } + } +} + +/*! + \brief clear the FMC interrupt pending flag by writing 1 + \param[in] flag: clear FMC flag + one or more parameters can be selected which is shown as below: + \arg FMC_INT_FLAG_PGERR: FMC programming error flag + \arg FMC_INT_FLAG_PGAERR: FMC program alignment error flag + \arg FMC_INT_FLAG_WPERR: FMC write protection error flag + \arg FMC_INT_FLAG_END: FMC end of programming flag + \param[out] none + \retval none +*/ +void fmc_interrupt_flag_clear(uint32_t int_flag) +{ + /* clear the flags */ + FMC_STAT = int_flag; +} + +/*! + \brief get the FMC state + \param[in] none + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_state_get(void) +{ + fmc_state_enum fmc_state = FMC_READY; + + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_BUSY)) { + fmc_state = FMC_BUSY; + } else { + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_WPERR)) { + fmc_state = FMC_WPERR; + } else { + if((uint32_t)0x00U != (FMC_STAT & FMC_STAT_PGERR)) { + fmc_state = FMC_PGERR; + } + } + } + /* return the FMC state */ + return fmc_state; +} + +/*! + \brief check whether FMC is ready or not + \param[in] timeout: timeout count + \param[out] none + \retval fmc_state +*/ +fmc_state_enum fmc_ready_wait(uint32_t timeout) +{ + fmc_state_enum fmc_state = FMC_BUSY; + + /* wait for FMC ready */ + do { + /* get FMC state */ + fmc_state = fmc_state_get(); + timeout--; + } while((FMC_BUSY == fmc_state) && (0U != timeout)); + + if(FMC_BUSY == fmc_state) { + fmc_state = FMC_TOERR; + } + /* return the FMC state */ + return fmc_state; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c index 7a637b3..53080be 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_fwdgt.c @@ -1,245 +1,245 @@ -/*! - \file gd32e23x_fwdgt.c - \brief FWDGT driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_fwdgt.h" - -/*! - \brief enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_enable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; -} - -/*! - \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_write_disable(void) -{ - FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; -} - -/*! - \brief start the free watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_enable(void) -{ - FWDGT_CTL = FWDGT_KEY_ENABLE; -} - -/*! - \brief configure the free watchdog timer counter prescaler value - \param[in] prescaler_value: specify prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status) { - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_value; - - return SUCCESS; -} - -/*! - \brief configure the free watchdog timer counter reload value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_reload_value_config(uint16_t reload_value) -{ - uint32_t timeout = FWDGT_RLD_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the RUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status) { - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - return SUCCESS; -} - -/*! - \brief configure the free watchdog timer counter window value - \param[in] window_value: specify window value(0x0000 - 0x0FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_window_value_config(uint16_t window_value) -{ - uint32_t time_index = FWDGT_WND_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_WND */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the WUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_WUD; - } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status) { - return ERROR; - } - - FWDGT_WND = WND_WND(window_value); - - return SUCCESS; -} - -/*! - \brief reload the counter of FWDGT - \param[in] none - \param[out] none - \retval none -*/ -void fwdgt_counter_reload(void) -{ - FWDGT_CTL = FWDGT_KEY_RELOAD; -} - -/*! - \brief configure counter reload value, and prescaler divider value - \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) - \param[in] prescaler_div: FWDGT prescaler value - only one parameter can be selected which is shown as below: - \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 - \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 - \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 - \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 - \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 - \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 - \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) -{ - uint32_t timeout = FWDGT_PSC_TIMEOUT; - uint32_t flag_status = RESET; - - /* enable write access to FWDGT_PSC,and FWDGT_RLD */ - FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; - - /* wait until the PUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_PUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status) { - return ERROR; - } - - /* configure FWDGT */ - FWDGT_PSC = (uint32_t)prescaler_div; - - timeout = FWDGT_RLD_TIMEOUT; - /* wait until the RUD flag to be reset */ - do { - flag_status = FWDGT_STAT & FWDGT_STAT_RUD; - } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET != flag_status) { - return ERROR; - } - - FWDGT_RLD = RLD_RLD(reload_value); - - /* reload the counter */ - FWDGT_CTL = FWDGT_KEY_RELOAD; - - return SUCCESS; -} - -/*! - \brief get flag state of FWDGT - \param[in] flag: flag to get - only one parameter can be selected which is shown as below: - \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going - \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going - \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus fwdgt_flag_get(uint16_t flag) -{ - if(RESET != (FWDGT_STAT & flag)) { - return SET; - } - return RESET; -} +/*! + \file gd32e23x_fwdgt.c + \brief FWDGT driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_fwdgt.h" + +/*! + \brief enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_enable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; +} + +/*! + \brief disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_write_disable(void) +{ + FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE; +} + +/*! + \brief start the free watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_enable(void) +{ + FWDGT_CTL = FWDGT_KEY_ENABLE; +} + +/*! + \brief configure the free watchdog timer counter prescaler value + \param[in] prescaler_value: specify prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_value; + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter reload value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_reload_value_config(uint16_t reload_value) +{ + uint32_t timeout = FWDGT_RLD_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the RUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + return SUCCESS; +} + +/*! + \brief configure the free watchdog timer counter window value + \param[in] window_value: specify window value(0x0000 - 0x0FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_window_value_config(uint16_t window_value) +{ + uint32_t time_index = FWDGT_WND_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_WND */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the WUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_WUD; + } while((--time_index > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { + return ERROR; + } + + FWDGT_WND = WND_WND(window_value); + + return SUCCESS; +} + +/*! + \brief reload the counter of FWDGT + \param[in] none + \param[out] none + \retval none +*/ +void fwdgt_counter_reload(void) +{ + FWDGT_CTL = FWDGT_KEY_RELOAD; +} + +/*! + \brief configure counter reload value, and prescaler divider value + \param[in] reload_value: specify reload value(0x0000 - 0x0FFF) + \param[in] prescaler_div: FWDGT prescaler value + only one parameter can be selected which is shown as below: + \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4 + \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8 + \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16 + \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32 + \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64 + \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128 + \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256 + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div) +{ + uint32_t timeout = FWDGT_PSC_TIMEOUT; + uint32_t flag_status = RESET; + + /* enable write access to FWDGT_PSC,and FWDGT_RLD */ + FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE; + + /* wait until the PUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_PUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { + return ERROR; + } + + /* configure FWDGT */ + FWDGT_PSC = (uint32_t)prescaler_div; + + timeout = FWDGT_RLD_TIMEOUT; + /* wait until the RUD flag to be reset */ + do { + flag_status = FWDGT_STAT & FWDGT_STAT_RUD; + } while((--timeout > 0U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET != flag_status) { + return ERROR; + } + + FWDGT_RLD = RLD_RLD(reload_value); + + /* reload the counter */ + FWDGT_CTL = FWDGT_KEY_RELOAD; + + return SUCCESS; +} + +/*! + \brief get flag state of FWDGT + \param[in] flag: flag to get + only one parameter can be selected which is shown as below: + \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going + \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going + \arg FWDGT_FLAG_WUD: a write operation to FWDGT_WND register is on going + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus fwdgt_flag_get(uint16_t flag) +{ + if(RESET != (FWDGT_STAT & flag)) { + return SET; + } + return RESET; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c index 3c36825..5968a02 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_gpio.c @@ -1,399 +1,399 @@ -/*! - \file gd32e23x_gpio.c - \brief GPIO driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_gpio.h" - -/*! - \brief reset GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval none -*/ -void gpio_deinit(uint32_t gpio_periph) -{ - switch(gpio_periph) { - case GPIOA: - /* reset GPIOA */ - rcu_periph_reset_enable(RCU_GPIOARST); - rcu_periph_reset_disable(RCU_GPIOARST); - break; - case GPIOB: - /* reset GPIOB */ - rcu_periph_reset_enable(RCU_GPIOBRST); - rcu_periph_reset_disable(RCU_GPIOBRST); - break; - case GPIOC: - /* reset GPIOC */ - rcu_periph_reset_enable(RCU_GPIOCRST); - rcu_periph_reset_disable(RCU_GPIOCRST); - break; - case GPIOF: - /* reset GPIOF */ - rcu_periph_reset_enable(RCU_GPIOFRST); - rcu_periph_reset_disable(RCU_GPIOFRST); - break; - default: - break; - } -} - -/*! - \brief set GPIO mode - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] mode: gpio pin mode - \arg GPIO_MODE_INPUT: input mode - \arg GPIO_MODE_OUTPUT: output mode - \arg GPIO_MODE_AF: alternate function mode - \arg GPIO_MODE_ANALOG: analog mode - \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor - \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors - \arg GPIO_PUPD_PULLUP: with pull-up resistor - \arg GPIO_PUPD_PULLDOWN:with pull-down resistor - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) -{ - uint16_t i; - uint32_t ctl, pupd; - - ctl = GPIO_CTL(gpio_periph); - pupd = GPIO_PUD(gpio_periph); - - for(i = 0U; i < 16U; i++) { - if((1U << i) & pin) { - /* clear the specified pin mode bits */ - ctl &= ~GPIO_MODE_MASK(i); - /* set the specified pin mode bits */ - ctl |= GPIO_MODE_SET(i, mode); - - /* clear the specified pin pupd bits */ - pupd &= ~GPIO_PUPD_MASK(i); - /* set the specified pin pupd bits */ - pupd |= GPIO_PUPD_SET(i, pull_up_down); - } - } - - GPIO_CTL(gpio_periph) = ctl; - GPIO_PUD(gpio_periph) = pupd; -} - -/*! - \brief set GPIO output type and speed - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] otype: gpio pin output mode - \arg GPIO_OTYPE_PP: push pull mode - \arg GPIO_OTYPE_OD: open drain mode - \param[in] speed: gpio pin output max speed - \arg GPIO_OSPEED_2MHZ: output max speed 2MHz - \arg GPIO_OSPEED_10MHZ: output max speed 10MHz - \arg GPIO_OSPEED_50MHZ: output max speed 50MHz - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) -{ - uint16_t i; - uint32_t ospeed; - - if(GPIO_OTYPE_OD == otype) { - GPIO_OMODE(gpio_periph) |= (uint32_t)pin; - } else { - GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); - } - - /* get the specified pin output speed bits value */ - ospeed = GPIO_OSPD(gpio_periph); - - for(i = 0U; i < 16U; i++) { - if((1U << i) & pin) { - /* clear the specified pin output speed bits */ - ospeed &= ~GPIO_OSPEED_MASK(i); - /* set the specified pin output speed bits */ - ospeed |= GPIO_OSPEED_SET(i, speed); - } - } - GPIO_OSPD(gpio_periph) = ospeed; -} - -/*! - \brief set GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BOP(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief reset GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_BC(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief write data to the specified GPIO pin - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[in] bit_value: SET or RESET - \arg RESET: clear the port pin - \arg SET: set the port pin - \param[out] none - \retval none -*/ -void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) -{ - if(RESET != bit_value) { - GPIO_BOP(gpio_periph) = (uint32_t)pin; - } else { - GPIO_BC(gpio_periph) = (uint32_t)pin; - } -} - -/*! - \brief write data to the specified GPIO port - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] data: specify the value to be written to the port output control register - \param[out] none - \retval none -*/ -void gpio_port_write(uint32_t gpio_periph, uint16_t data) -{ - GPIO_OCTL(gpio_periph) = (uint32_t)data; -} - -/*! - \brief get GPIO pin input status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO all pins input status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_input_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_ISTAT(gpio_periph); -} - -/*! - \brief get GPIO pin output status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval SET or RESET -*/ -FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) -{ - if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief get GPIO all pins output status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval state of GPIO all pins -*/ -uint16_t gpio_output_port_get(uint32_t gpio_periph) -{ - return (uint16_t)GPIO_OCTL(gpio_periph); -} - -/*! - \brief set GPIO alternate function - \param[in] gpio_periph: GPIOx(x = A,B,C) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C) - \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet - \arg GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, - I2C0, I2C1, SWDIO, SWCLK - \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1 - \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 - \arg GPIO_AF_3: I2C0, TIMER14 - \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 - \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0 - \arg GPIO_AF_6(port A,B only): SPI1 - \arg GPIO_AF_7(port A,B only): CMP - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) -{ - uint16_t i; - uint32_t afrl, afrh; - - afrl = GPIO_AFSEL0(gpio_periph); - afrh = GPIO_AFSEL1(gpio_periph); - - for(i = 0U; i < 8U; i++) { - if((1U << i) & pin) { - /* clear the specified pin alternate function bits */ - afrl &= ~GPIO_AFR_MASK(i); - afrl |= GPIO_AFR_SET(i, alt_func_num); - } - } - - for(i = 8U; i < 16U; i++) { - if((1U << i) & pin) { - /* clear the specified pin alternate function bits */ - afrh &= ~GPIO_AFR_MASK(i - 8U); - afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); - } - } - - GPIO_AFSEL0(gpio_periph) = afrl; - GPIO_AFSEL1(gpio_periph) = afrh; -} - -/*! - \brief lock GPIO pin bit - \param[in] gpio_periph: GPIOx(x = A,B) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) -{ - uint32_t lock = 0x00010000U; - lock |= pin; - - /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - GPIO_LOCK(gpio_periph) = (uint32_t)pin; - GPIO_LOCK(gpio_periph) = (uint32_t)lock; - lock = GPIO_LOCK(gpio_periph); - lock = GPIO_LOCK(gpio_periph); -} - -/*! - \brief toggle GPIO pin status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[in] pin: GPIO pin - one or more parameters can be selected which are shown as below: - \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL - \param[out] none - \retval none -*/ -void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) -{ - GPIO_TG(gpio_periph) = (uint32_t)pin; -} - -/*! - \brief toggle GPIO port status - \param[in] gpio_periph: GPIOx(x = A,B,C,F) - only one parameter can be selected which is shown as below: - \arg GPIOx(x = A,B,C,F) - \param[out] none - \retval none -*/ -void gpio_port_toggle(uint32_t gpio_periph) -{ - GPIO_TG(gpio_periph) = 0x0000FFFFU; -} +/*! + \file gd32e23x_gpio.c + \brief GPIO driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_gpio.h" + +/*! + \brief reset GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[out] none + \retval none +*/ +void gpio_deinit(uint32_t gpio_periph) +{ + switch(gpio_periph) { + case GPIOA: + /* reset GPIOA */ + rcu_periph_reset_enable(RCU_GPIOARST); + rcu_periph_reset_disable(RCU_GPIOARST); + break; + case GPIOB: + /* reset GPIOB */ + rcu_periph_reset_enable(RCU_GPIOBRST); + rcu_periph_reset_disable(RCU_GPIOBRST); + break; + case GPIOC: + /* reset GPIOC */ + rcu_periph_reset_enable(RCU_GPIOCRST); + rcu_periph_reset_disable(RCU_GPIOCRST); + break; + case GPIOF: + /* reset GPIOF */ + rcu_periph_reset_enable(RCU_GPIOFRST); + rcu_periph_reset_disable(RCU_GPIOFRST); + break; + default: + break; + } +} + +/*! + \brief set GPIO mode + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] mode: gpio pin mode + \arg GPIO_MODE_INPUT: input mode + \arg GPIO_MODE_OUTPUT: output mode + \arg GPIO_MODE_AF: alternate function mode + \arg GPIO_MODE_ANALOG: analog mode + \param[in] pull_up_down: gpio pin with pull-up or pull-down resistor + \arg GPIO_PUPD_NONE: floating mode, no pull-up and pull-down resistors + \arg GPIO_PUPD_PULLUP: with pull-up resistor + \arg GPIO_PUPD_PULLDOWN:with pull-down resistor + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin) +{ + uint16_t i; + uint32_t ctl, pupd; + + ctl = GPIO_CTL(gpio_periph); + pupd = GPIO_PUD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin mode bits */ + ctl &= ~GPIO_MODE_MASK(i); + /* set the specified pin mode bits */ + ctl |= GPIO_MODE_SET(i, mode); + + /* clear the specified pin pupd bits */ + pupd &= ~GPIO_PUPD_MASK(i); + /* set the specified pin pupd bits */ + pupd |= GPIO_PUPD_SET(i, pull_up_down); + } + } + + GPIO_CTL(gpio_periph) = ctl; + GPIO_PUD(gpio_periph) = pupd; +} + +/*! + \brief set GPIO output type and speed + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] otype: gpio pin output mode + \arg GPIO_OTYPE_PP: push pull mode + \arg GPIO_OTYPE_OD: open drain mode + \param[in] speed: gpio pin output max speed + \arg GPIO_OSPEED_2MHZ: output max speed 2MHz + \arg GPIO_OSPEED_10MHZ: output max speed 10MHz + \arg GPIO_OSPEED_50MHZ: output max speed 50MHz + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin) +{ + uint16_t i; + uint32_t ospeed; + + if(GPIO_OTYPE_OD == otype) { + GPIO_OMODE(gpio_periph) |= (uint32_t)pin; + } else { + GPIO_OMODE(gpio_periph) &= (uint32_t)(~pin); + } + + /* get the specified pin output speed bits value */ + ospeed = GPIO_OSPD(gpio_periph); + + for(i = 0U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin output speed bits */ + ospeed &= ~GPIO_OSPEED_MASK(i); + /* set the specified pin output speed bits */ + ospeed |= GPIO_OSPEED_SET(i, speed); + } + } + GPIO_OSPD(gpio_periph) = ospeed; +} + +/*! + \brief set GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_set(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BOP(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief reset GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_BC(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief write data to the specified GPIO pin + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[in] bit_value: SET or RESET + \arg RESET: clear the port pin + \arg SET: set the port pin + \param[out] none + \retval none +*/ +void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value) +{ + if(RESET != bit_value) { + GPIO_BOP(gpio_periph) = (uint32_t)pin; + } else { + GPIO_BC(gpio_periph) = (uint32_t)pin; + } +} + +/*! + \brief write data to the specified GPIO port + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] data: specify the value to be written to the port output control register + \param[out] none + \retval none +*/ +void gpio_port_write(uint32_t gpio_periph, uint16_t data) +{ + GPIO_OCTL(gpio_periph) = (uint32_t)data; +} + +/*! + \brief get GPIO pin input status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins input status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_input_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_ISTAT(gpio_periph); +} + +/*! + \brief get GPIO pin output status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval SET or RESET +*/ +FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin) +{ + if((uint32_t)RESET != (GPIO_OCTL(gpio_periph) & (pin))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief get GPIO all pins output status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[out] none + \retval state of GPIO all pins +*/ +uint16_t gpio_output_port_get(uint32_t gpio_periph) +{ + return (uint16_t)GPIO_OCTL(gpio_periph); +} + +/*! + \brief set GPIO alternate function + \param[in] gpio_periph: GPIOx(x = A,B,C) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C) + \param[in] alt_func_num: GPIO pin af function, please refer to specific device datasheet + \arg GPIO_AF_0: TIMER13, TIMER14, TIMER16, SPI0, SPI1, I2S0, CK_OUT, USART0, + I2C0, I2C1, SWDIO, SWCLK + \arg GPIO_AF_1: USART0, USART1, TIMER2, TIMER14, I2C0, I2C1 + \arg GPIO_AF_2: TIMER0, TIMER1, TIMER15, TIMER16, I2S0 + \arg GPIO_AF_3: I2C0, TIMER14 + \arg GPIO_AF_4(port A,B only): USART1, I2C0, I2C1, TIMER13 + \arg GPIO_AF_5(port A,B only): TIMER15, TIMER16, I2S0 + \arg GPIO_AF_6(port A,B only): SPI1 + \arg GPIO_AF_7(port A,B only): CMP + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin) +{ + uint16_t i; + uint32_t afrl, afrh; + + afrl = GPIO_AFSEL0(gpio_periph); + afrh = GPIO_AFSEL1(gpio_periph); + + for(i = 0U; i < 8U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrl &= ~GPIO_AFR_MASK(i); + afrl |= GPIO_AFR_SET(i, alt_func_num); + } + } + + for(i = 8U; i < 16U; i++) { + if((1U << i) & pin) { + /* clear the specified pin alternate function bits */ + afrh &= ~GPIO_AFR_MASK(i - 8U); + afrh |= GPIO_AFR_SET(i - 8U, alt_func_num); + } + } + + GPIO_AFSEL0(gpio_periph) = afrl; + GPIO_AFSEL1(gpio_periph) = afrh; +} + +/*! + \brief lock GPIO pin bit + \param[in] gpio_periph: GPIOx(x = A,B) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin) +{ + uint32_t lock = 0x00010000U; + lock |= pin; + + /* lock key writing sequence: write 1->write 0->write 1->read 0->read 1 */ + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + GPIO_LOCK(gpio_periph) = (uint32_t)pin; + GPIO_LOCK(gpio_periph) = (uint32_t)lock; + lock = GPIO_LOCK(gpio_periph); + lock = GPIO_LOCK(gpio_periph); +} + +/*! + \brief toggle GPIO pin status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[in] pin: GPIO pin + one or more parameters can be selected which are shown as below: + \arg GPIO_PIN_x(x=0..15), GPIO_PIN_ALL + \param[out] none + \retval none +*/ +void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin) +{ + GPIO_TG(gpio_periph) = (uint32_t)pin; +} + +/*! + \brief toggle GPIO port status + \param[in] gpio_periph: GPIOx(x = A,B,C,F) + only one parameter can be selected which is shown as below: + \arg GPIOx(x = A,B,C,F) + \param[out] none + \retval none +*/ +void gpio_port_toggle(uint32_t gpio_periph) +{ + GPIO_TG(gpio_periph) = 0x0000FFFFU; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c index cddd838..9524600 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_i2c.c @@ -1,818 +1,818 @@ -/*! - \file gd32e23x_i2c.c - \brief I2C driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_i2c.h" - -/* I2C register bit mask */ -#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */ -#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ -#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ -#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ -#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ - -/* I2C register bit offset */ -#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ - -/*! - \brief reset I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_deinit(uint32_t i2c_periph) -{ - switch(i2c_periph) { - case I2C0: - /* reset I2C0 */ - rcu_periph_reset_enable(RCU_I2C0RST); - rcu_periph_reset_disable(RCU_I2C0RST); - break; - case I2C1: - /* reset I2C1 */ - rcu_periph_reset_enable(RCU_I2C1RST); - rcu_periph_reset_disable(RCU_I2C1RST); - break; - default: - break; - } -} - -/*! - \brief configure I2C clock - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) - and fast mode plus (up to 1MHz) - \param[in] dutycyc: duty cycle in fast mode or fast mode plus - only one parameter can be selected which is shown as below: - \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode or fast mode plus - \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode or fast mode plus - \param[out] none - \retval none -*/ -void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) -{ - uint32_t pclk1, clkc, freq, risetime; - uint32_t temp; - - pclk1 = rcu_clock_freq_get(CK_APB1); - /* I2C peripheral clock frequency */ - freq = (uint32_t)(pclk1 / 1000000U); - if(freq >= I2CCLK_MAX) { - freq = I2CCLK_MAX; - } - temp = I2C_CTL1(i2c_periph); - temp &= ~I2C_CTL1_I2CCLK; - temp |= freq; - - I2C_CTL1(i2c_periph) = temp; - - if(100000U >= clkspeed) { - /* the maximum SCL rise time is 1000ns in standard mode */ - risetime = (uint32_t)((pclk1 / 1000000U) + 1U); - if(risetime >= I2CCLK_MAX) { - I2C_RT(i2c_periph) = I2CCLK_MAX; - } else if(risetime <= I2CCLK_MIN) { - I2C_RT(i2c_periph) = I2CCLK_MIN; - } else { - I2C_RT(i2c_periph) = risetime; - } - clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); - if(clkc < 0x04U) { - /* the CLKC in standard mode minmum value is 4 */ - clkc = 0x04U; - } - - I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); - - } else if(400000U >= clkspeed) { - /* the maximum SCL rise time is 300ns in fast mode */ - I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); - if(I2C_DTCY_2 == dutycyc) { - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - } else { - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - if(0U == (clkc & I2C_CKCFG_CLKC)) { - /* the CLKC in fast mode minmum value is 1 */ - clkc |= 0x0001U; - } - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - } else { - /* fast mode plus, the maximum SCL rise time is 120ns */ - I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); - if(I2C_DTCY_2 == dutycyc) { - /* I2C duty cycle is 2 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); - I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; - } else { - /* I2C duty cycle is 16/9 */ - clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; - } - /* enable fast mode */ - I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; - I2C_CKCFG(i2c_periph) |= clkc; - /* enable I2C fast mode plus */ - I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; - } -} - -/*! - \brief configure I2C address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_I2CMODE_ENABLE: I2C mode - \arg I2C_SMBUSMODE_ENABLE: SMBus mode - \param[in] addformat: 7bits or 10bits - only one parameter can be selected which is shown as below: - \arg I2C_ADDFORMAT_7BITS: address format is 7 bits - \arg I2C_ADDFORMAT_10BITS: address format is 10 bits - \param[in] addr: I2C address - \param[out] none - \retval none -*/ -void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) -{ - /* SMBus/I2C mode selected */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SMBEN); - ctl |= mode; - I2C_CTL0(i2c_periph) = ctl; - /* configure address */ - addr = addr & I2C_ADDRESS_MASK; - I2C_SADDR0(i2c_periph) = (addformat | addr); -} - -/*! - \brief select SMBus type - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] type: - only one parameter can be selected which is shown as below: - \arg I2C_SMBUS_DEVICE: SMBus mode device type - \arg I2C_SMBUS_HOST: SMBus mode host type - \param[out] none - \retval none -*/ -void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) -{ - if(I2C_SMBUS_HOST == type) { - I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; - } else { - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); - } -} - -/*! - \brief whether or not to send an ACK - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] ack: - only one parameter can be selected which is shown as below: - \arg I2C_ACK_ENABLE: ACK will be sent - \arg I2C_ACK_DISABLE: ACK will not be sent - \param[out] none - \retval none -*/ -void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) -{ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ACKEN); - ctl |= ack; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief configure I2C POAP position - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pos: - only one parameter can be selected which is shown as below: - \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte - \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte - \param[out] none - \retval none -*/ -void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) -{ - uint32_t ctl = 0U; - /* configure I2C POAP position */ - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_POAP); - ctl |= pos; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief master sends slave address - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: slave address - \param[in] trandirection: transmitter or receiver - only one parameter can be selected which is shown as below: - \arg I2C_TRANSMITTER: transmitter - \arg I2C_RECEIVER: receiver - \param[out] none - \retval none -*/ -void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) -{ - /* master is a transmitter or a receiver */ - if(I2C_TRANSMITTER == trandirection) { - addr = addr & I2C_TRANSMITTER; - } else { - addr = addr | I2C_RECEIVER; - } - /* send slave address */ - I2C_DATA(i2c_periph) = addr; -} - -/*! - \brief enable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] addr: the second address in dual-address mode - \param[out] none - \retval none -*/ -void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) -{ - /* configure address */ - addr = addr & I2C_ADDRESS2_MASK; - I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); -} - -/*! - \brief disable dual-address mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_dualaddr_disable(uint32_t i2c_periph) -{ - I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); -} - -/*! - \brief enable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_enable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; -} - -/*! - \brief disable I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_disable(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); -} - -/*! - \brief generate a START condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_start_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_START; -} - -/*! - \brief generate a STOP condition on I2C bus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_stop_on_bus(uint32_t i2c_periph) -{ - I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; -} - -/*! - \brief I2C transmit data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) -{ - I2C_DATA(i2c_periph) = DATA_TRANS(data); -} - -/*! - \brief I2C receive data function - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval data of received -*/ -uint8_t i2c_data_receive(uint32_t i2c_periph) -{ - return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); -} - -/*! - \brief configure I2C DMA mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmastate: - only one parameter can be selected which is shown as below: - \arg I2C_DMA_ON: enable DMA mode - \arg I2C_DMA_OFF: disable DMA mode - \param[out] none - \retval none -*/ -void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) -{ - /* configure I2C DMA function */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMAON); - ctl |= dmastate; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure whether next DMA EOT is DMA last transfer or not - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] dmalast: - only one parameter can be selected which is shown as below: - \arg I2C_DMALST_ON: next DMA EOT is the last transfer - \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer - \param[out] none - \retval none -*/ -void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) -{ - /* configure DMA last transfer */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_DMALST); - ctl |= dmalast; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief configure RBNE clear mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] mode: - only one parameter can be selected which is shown as below: - \arg I2C_RBNE_CLEAR_BTC_0: RBNE can be cleared when I2C_DATA is read and BTC is cleared - \arg I2C_RBNE_CLEAR: RBNE can be cleared when I2C_DATA is read - \param[out] none - \retval none -*/ -void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode) -{ - /* configure RBNE clear mode */ - uint32_t ctl = 0U; - - ctl = I2C_CTL1(i2c_periph); - ctl &= ~(I2C_CTL1_RBNECM); - ctl |= mode; - I2C_CTL1(i2c_periph) = ctl; -} - -/*! - \brief whether to stretch SCL low when data is not ready in slave mode - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] stretchpara: - only one parameter can be selected which is shown as below: - \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching - \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching - \param[out] none - \retval none -*/ -void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) -{ - /* configure I2C SCL strerching */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SS); - ctl |= stretchpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief whether or not to response to a general call - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] gcallpara: - only one parameter can be selected which is shown as below: - \arg I2C_GCEN_ENABLE: slave will response to a general call - \arg I2C_GCEN_DISABLE: slave will not response to a general call - \param[out] none - \retval none -*/ -void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) -{ - /* configure slave response to a general call enable or disable */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_GCEN); - ctl |= gcallpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief configure software reset of I2C - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] sreset: - only one parameter can be selected which is shown as below: - \arg I2C_SRESET_SET: I2C is under reset - \arg I2C_SRESET_RESET: I2C is not under reset - \param[out] none - \retval none -*/ -void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) -{ - /* modify CTL0 and configure software reset I2C state */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SRESET); - ctl |= sreset; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief configure I2C PEC calculation - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecstate: - only one parameter can be selected which is shown as below: - \arg I2C_PEC_ENABLE: PEC calculation on - \arg I2C_PEC_DISABLE: PEC calculation off - \param[out] none - \retval none -*/ -void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) -{ - /* on/off PEC calculation */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECEN); - ctl |= pecstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief configure whether to transfer PEC value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] pecpara: - only one parameter can be selected which is shown as below: - \arg I2C_PECTRANS_ENABLE: transfer PEC value - \arg I2C_PECTRANS_DISABLE: not transfer PEC value - \param[out] none - \retval none -*/ -void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) -{ - /* whether to transfer PEC */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_PECTRANS); - ctl |= pecpara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief get packet error checking value - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval PEC value -*/ -uint8_t i2c_pec_value_get(uint32_t i2c_periph) -{ - return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); -} - -/*! - \brief configure I2C alert through SMBA pin - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] smbuspara: - only one parameter can be selected which is shown as below: - \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin - \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin - \param[out] none - \retval none -*/ -void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) -{ - /* configure smubus alert through SMBA pin */ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_SALT); - ctl |= smbuspara; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief configure I2C ARP protocol in SMBus - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] arpstate: - only one parameter can be selected which is shown as below: - \arg I2C_ARP_ENABLE: enable ARP - \arg I2C_ARP_DISABLE: disable ARP - \param[out] none - \retval none -*/ -void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) -{ - /* enable or disable I2C ARP protocol*/ - uint32_t ctl = 0U; - - ctl = I2C_CTL0(i2c_periph); - ctl &= ~(I2C_CTL0_ARPEN); - ctl |= arpstate; - I2C_CTL0(i2c_periph) = ctl; -} - -/*! - \brief enable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; -} - -/*! - \brief disable SAM_V interface - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); -} - -/*! - \brief enable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_enable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; -} - -/*! - \brief disable SAM_V interface timeout detect - \param[in] i2c_periph: I2Cx(x=0,1) - \param[out] none - \retval none -*/ -void i2c_sam_timeout_disable(uint32_t i2c_periph) -{ - I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); -} - -/*! - \brief get I2C flag status - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SBSEND: start condition sent out in master mode - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_BTC: byte transmission finishes - \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode - \arg I2C_FLAG_STPDET: stop condition detected in slave mode - \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving - \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode - \arg I2C_FLAG_I2CBSY: busy flag - \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver - \arg I2C_FLAG_RXGC: general call address (00h) received - \arg I2C_FLAG_DEFSMB: default address of SMBus device - \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode - \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C flag status - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] flag: I2C flags, refer to i2c_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_FLAG_SMBALT: SMBus alert status - \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode - \arg I2C_FLAG_PECERR: PEC error when receiving data - \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode - \arg I2C_FLAG_AERR: acknowledge error - \arg I2C_FLAG_LOSTARB: arbitration lost in master mode - \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus - \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode - \arg I2C_FLAG_TFF: txframe fall flag - \arg I2C_FLAG_TFR: txframe rise flag - \arg I2C_FLAG_RFF: rxframe fall flag - \arg I2C_FLAG_RFR: rxframe rise flag - \param[out] none - \retval none -*/ -void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) -{ - if(I2C_FLAG_ADDSEND == flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); - } -} - -/*! - \brief enable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt - \arg I2C_INT_EV: event interrupt - \arg I2C_INT_BUF: buffer interrupt - \arg I2C_INT_TFF: txframe fall interrupt - \arg I2C_INT_TFR: txframe rise interrupt - \arg I2C_INT_RFF: rxframe fall interrupt - \arg I2C_INT_RFR: rxframe rise interrupt - \param[out] none - \retval none -*/ -void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief disable I2C interrupt - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_ERR: error interrupt - \arg I2C_INT_EV: event interrupt - \arg I2C_INT_BUF: buffer interrupt - \arg I2C_INT_TFF: txframe fall interrupt - \arg I2C_INT_TFR: txframe rise interrupt - \arg I2C_INT_RFF: rxframe fall interrupt - \arg I2C_INT_RFR: rxframe rise interrupt - \param[out] none - \retval none -*/ -void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) -{ - I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); -} - -/*! - \brief get I2C interrupt flag status - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag - \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag - \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag - \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag - \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U, bufie; - - /* check BUFIE */ - bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; - - /* get the interrupt enable bit status */ - intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); - - if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { - if(intenable && bufie) { - intenable = 1U; - } else { - intenable = 0U; - } - } - if((0U != flagstatus) && (0U != intenable)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear I2C interrupt flag status - \param[in] i2c_periph: I2Cx(x=0,1) - \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag - \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag - \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag - \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag - \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag - \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag - \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag - \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag - \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag - \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag - \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag - \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag - \param[out] none - \retval none -*/ -void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) -{ - if(I2C_INT_FLAG_ADDSEND == int_flag) { - /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ - I2C_STAT0(i2c_periph); - I2C_STAT1(i2c_periph); - } else { - I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); - } -} +/*! + \file gd32e23x_i2c.c + \brief I2C driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_i2c.h" + +/* I2C register bit mask */ +#define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */ +#define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ +#define I2C_FLAG_MASK ((uint32_t)0x0000FFFFU) /*!< i2c flag mask */ +#define I2C_ADDRESS_MASK ((uint32_t)0x000003FFU) /*!< i2c address mask */ +#define I2C_ADDRESS2_MASK ((uint32_t)0x000000FEU) /*!< the second i2c address mask */ + +/* I2C register bit offset */ +#define STAT1_PECV_OFFSET ((uint32_t)0x00000008U) /* bit offset of PECV in I2C_STAT1 */ + +/*! + \brief reset I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_deinit(uint32_t i2c_periph) +{ + switch(i2c_periph) { + case I2C0: + /* reset I2C0 */ + rcu_periph_reset_enable(RCU_I2C0RST); + rcu_periph_reset_disable(RCU_I2C0RST); + break; + case I2C1: + /* reset I2C1 */ + rcu_periph_reset_enable(RCU_I2C1RST); + rcu_periph_reset_disable(RCU_I2C1RST); + break; + default: + break; + } +} + +/*! + \brief configure I2C clock + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] clkspeed: I2C clock speed, supports standard mode (up to 100 kHz), fast mode (up to 400 kHz) + and fast mode plus (up to 1MHz) + \param[in] dutycyc: duty cycle in fast mode or fast mode plus + only one parameter can be selected which is shown as below: + \arg I2C_DTCY_2: T_low/T_high = 2 in fast mode or fast mode plus + \arg I2C_DTCY_16_9: T_low/T_high = 16/9 in fast mode or fast mode plus + \param[out] none + \retval none +*/ +void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc) +{ + uint32_t pclk1, clkc, freq, risetime; + uint32_t temp; + + pclk1 = rcu_clock_freq_get(CK_APB1); + /* I2C peripheral clock frequency */ + freq = (uint32_t)(pclk1 / 1000000U); + if(freq >= I2CCLK_MAX) { + freq = I2CCLK_MAX; + } + temp = I2C_CTL1(i2c_periph); + temp &= ~I2C_CTL1_I2CCLK; + temp |= freq; + + I2C_CTL1(i2c_periph) = temp; + + if(100000U >= clkspeed) { + /* the maximum SCL rise time is 1000ns in standard mode */ + risetime = (uint32_t)((pclk1 / 1000000U) + 1U); + if(risetime >= I2CCLK_MAX) { + I2C_RT(i2c_periph) = I2CCLK_MAX; + } else if(risetime <= I2CCLK_MIN) { + I2C_RT(i2c_periph) = I2CCLK_MIN; + } else { + I2C_RT(i2c_periph) = risetime; + } + clkc = (uint32_t)(pclk1 / (clkspeed * 2U)); + if(clkc < 0x04U) { + /* the CLKC in standard mode minmum value is 4 */ + clkc = 0x04U; + } + + I2C_CKCFG(i2c_periph) |= (I2C_CKCFG_CLKC & clkc); + + } else if(400000U >= clkspeed) { + /* the maximum SCL rise time is 300ns in fast mode */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)300U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + if(0U == (clkc & I2C_CKCFG_CLKC)) { + /* the CLKC in fast mode minmum value is 1 */ + clkc |= 0x0001U; + } + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + } else { + /* fast mode plus, the maximum SCL rise time is 120ns */ + I2C_RT(i2c_periph) = (uint32_t)(((freq * (uint32_t)120U) / (uint32_t)1000U) + (uint32_t)1U); + if(I2C_DTCY_2 == dutycyc) { + /* I2C duty cycle is 2 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 3U)); + I2C_CKCFG(i2c_periph) &= ~I2C_CKCFG_DTCY; + } else { + /* I2C duty cycle is 16/9 */ + clkc = (uint32_t)(pclk1 / (clkspeed * 25U)); + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_DTCY; + } + /* enable fast mode */ + I2C_CKCFG(i2c_periph) |= I2C_CKCFG_FAST; + I2C_CKCFG(i2c_periph) |= clkc; + /* enable I2C fast mode plus */ + I2C_FMPCFG(i2c_periph) = I2C_FMPCFG_FMPEN; + } +} + +/*! + \brief configure I2C address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_I2CMODE_ENABLE: I2C mode + \arg I2C_SMBUSMODE_ENABLE: SMBus mode + \param[in] addformat: 7bits or 10bits + only one parameter can be selected which is shown as below: + \arg I2C_ADDFORMAT_7BITS: address format is 7 bits + \arg I2C_ADDFORMAT_10BITS: address format is 10 bits + \param[in] addr: I2C address + \param[out] none + \retval none +*/ +void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr) +{ + /* SMBus/I2C mode selected */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SMBEN); + ctl |= mode; + I2C_CTL0(i2c_periph) = ctl; + /* configure address */ + addr = addr & I2C_ADDRESS_MASK; + I2C_SADDR0(i2c_periph) = (addformat | addr); +} + +/*! + \brief select SMBus type + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] type: + only one parameter can be selected which is shown as below: + \arg I2C_SMBUS_DEVICE: SMBus mode device type + \arg I2C_SMBUS_HOST: SMBus mode host type + \param[out] none + \retval none +*/ +void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type) +{ + if(I2C_SMBUS_HOST == type) { + I2C_CTL0(i2c_periph) |= I2C_CTL0_SMBSEL; + } else { + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_SMBSEL); + } +} + +/*! + \brief whether or not to send an ACK + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] ack: + only one parameter can be selected which is shown as below: + \arg I2C_ACK_ENABLE: ACK will be sent + \arg I2C_ACK_DISABLE: ACK will not be sent + \param[out] none + \retval none +*/ +void i2c_ack_config(uint32_t i2c_periph, uint32_t ack) +{ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ACKEN); + ctl |= ack; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C POAP position + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pos: + only one parameter can be selected which is shown as below: + \arg I2C_ACKPOS_CURRENT: ACKEN bit decides whether or not to send ACK or not for the current byte + \arg I2C_ACKPOS_NEXT: ACKEN bit decides whether or not to send ACK for the next byte + \param[out] none + \retval none +*/ +void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos) +{ + uint32_t ctl = 0U; + /* configure I2C POAP position */ + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_POAP); + ctl |= pos; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief master sends slave address + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: slave address + \param[in] trandirection: transmitter or receiver + only one parameter can be selected which is shown as below: + \arg I2C_TRANSMITTER: transmitter + \arg I2C_RECEIVER: receiver + \param[out] none + \retval none +*/ +void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection) +{ + /* master is a transmitter or a receiver */ + if(I2C_TRANSMITTER == trandirection) { + addr = addr & I2C_TRANSMITTER; + } else { + addr = addr | I2C_RECEIVER; + } + /* send slave address */ + I2C_DATA(i2c_periph) = addr; +} + +/*! + \brief enable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] addr: the second address in dual-address mode + \param[out] none + \retval none +*/ +void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr) +{ + /* configure address */ + addr = addr & I2C_ADDRESS2_MASK; + I2C_SADDR1(i2c_periph) = (I2C_SADDR1_DUADEN | addr); +} + +/*! + \brief disable dual-address mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_dualaddr_disable(uint32_t i2c_periph) +{ + I2C_SADDR1(i2c_periph) &= ~(I2C_SADDR1_DUADEN); +} + +/*! + \brief enable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_enable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_I2CEN; +} + +/*! + \brief disable I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_disable(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) &= ~(I2C_CTL0_I2CEN); +} + +/*! + \brief generate a START condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_start_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_START; +} + +/*! + \brief generate a STOP condition on I2C bus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_stop_on_bus(uint32_t i2c_periph) +{ + I2C_CTL0(i2c_periph) |= I2C_CTL0_STOP; +} + +/*! + \brief I2C transmit data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void i2c_data_transmit(uint32_t i2c_periph, uint8_t data) +{ + I2C_DATA(i2c_periph) = DATA_TRANS(data); +} + +/*! + \brief I2C receive data function + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval data of received +*/ +uint8_t i2c_data_receive(uint32_t i2c_periph) +{ + return (uint8_t)DATA_RECV(I2C_DATA(i2c_periph)); +} + +/*! + \brief configure I2C DMA mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmastate: + only one parameter can be selected which is shown as below: + \arg I2C_DMA_ON: enable DMA mode + \arg I2C_DMA_OFF: disable DMA mode + \param[out] none + \retval none +*/ +void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate) +{ + /* configure I2C DMA function */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMAON); + ctl |= dmastate; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure whether next DMA EOT is DMA last transfer or not + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] dmalast: + only one parameter can be selected which is shown as below: + \arg I2C_DMALST_ON: next DMA EOT is the last transfer + \arg I2C_DMALST_OFF: next DMA EOT is not the last transfer + \param[out] none + \retval none +*/ +void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast) +{ + /* configure DMA last transfer */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_DMALST); + ctl |= dmalast; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief configure RBNE clear mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] mode: + only one parameter can be selected which is shown as below: + \arg I2C_RBNE_CLEAR_BTC_0: RBNE can be cleared when I2C_DATA is read and BTC is cleared + \arg I2C_RBNE_CLEAR: RBNE can be cleared when I2C_DATA is read + \param[out] none + \retval none +*/ +void i2c_rbne_clear_config(uint32_t i2c_periph, uint32_t mode) +{ + /* configure RBNE clear mode */ + uint32_t ctl = 0U; + + ctl = I2C_CTL1(i2c_periph); + ctl &= ~(I2C_CTL1_RBNECM); + ctl |= mode; + I2C_CTL1(i2c_periph) = ctl; +} + +/*! + \brief whether to stretch SCL low when data is not ready in slave mode + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] stretchpara: + only one parameter can be selected which is shown as below: + \arg I2C_SCLSTRETCH_ENABLE: enable SCL stretching + \arg I2C_SCLSTRETCH_DISABLE: disable SCL stretching + \param[out] none + \retval none +*/ +void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara) +{ + /* configure I2C SCL strerching */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SS); + ctl |= stretchpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief whether or not to response to a general call + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] gcallpara: + only one parameter can be selected which is shown as below: + \arg I2C_GCEN_ENABLE: slave will response to a general call + \arg I2C_GCEN_DISABLE: slave will not response to a general call + \param[out] none + \retval none +*/ +void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara) +{ + /* configure slave response to a general call enable or disable */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_GCEN); + ctl |= gcallpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure software reset of I2C + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] sreset: + only one parameter can be selected which is shown as below: + \arg I2C_SRESET_SET: I2C is under reset + \arg I2C_SRESET_RESET: I2C is not under reset + \param[out] none + \retval none +*/ +void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset) +{ + /* modify CTL0 and configure software reset I2C state */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SRESET); + ctl |= sreset; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C PEC calculation + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecstate: + only one parameter can be selected which is shown as below: + \arg I2C_PEC_ENABLE: PEC calculation on + \arg I2C_PEC_DISABLE: PEC calculation off + \param[out] none + \retval none +*/ +void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate) +{ + /* on/off PEC calculation */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECEN); + ctl |= pecstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure whether to transfer PEC value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] pecpara: + only one parameter can be selected which is shown as below: + \arg I2C_PECTRANS_ENABLE: transfer PEC value + \arg I2C_PECTRANS_DISABLE: not transfer PEC value + \param[out] none + \retval none +*/ +void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara) +{ + /* whether to transfer PEC */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_PECTRANS); + ctl |= pecpara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief get packet error checking value + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval PEC value +*/ +uint8_t i2c_pec_value_get(uint32_t i2c_periph) +{ + return (uint8_t)((I2C_STAT1(i2c_periph) & I2C_STAT1_PECV) >> STAT1_PECV_OFFSET); +} + +/*! + \brief configure I2C alert through SMBA pin + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] smbuspara: + only one parameter can be selected which is shown as below: + \arg I2C_SALTSEND_ENABLE: issue alert through SMBA pin + \arg I2C_SALTSEND_DISABLE: not issue alert through SMBA pin + \param[out] none + \retval none +*/ +void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara) +{ + /* configure smubus alert through SMBA pin */ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_SALT); + ctl |= smbuspara; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief configure I2C ARP protocol in SMBus + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] arpstate: + only one parameter can be selected which is shown as below: + \arg I2C_ARP_ENABLE: enable ARP + \arg I2C_ARP_DISABLE: disable ARP + \param[out] none + \retval none +*/ +void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate) +{ + /* enable or disable I2C ARP protocol*/ + uint32_t ctl = 0U; + + ctl = I2C_CTL0(i2c_periph); + ctl &= ~(I2C_CTL0_ARPEN); + ctl |= arpstate; + I2C_CTL0(i2c_periph) = ctl; +} + +/*! + \brief enable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_sam_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_SAMEN; +} + +/*! + \brief disable SAM_V interface + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_sam_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_SAMEN); +} + +/*! + \brief enable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_enable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) |= I2C_SAMCS_STOEN; +} + +/*! + \brief disable SAM_V interface timeout detect + \param[in] i2c_periph: I2Cx(x=0,1) + \param[out] none + \retval none +*/ +void i2c_sam_timeout_disable(uint32_t i2c_periph) +{ + I2C_SAMCS(i2c_periph) &= ~(I2C_SAMCS_STOEN); +} + +/*! + \brief get I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SBSEND: start condition sent out in master mode + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_BTC: byte transmission finishes + \arg I2C_FLAG_ADD10SEND: header of 10-bit address is sent in master mode + \arg I2C_FLAG_STPDET: stop condition detected in slave mode + \arg I2C_FLAG_RBNE: I2C_DATA is not empty during receiving + \arg I2C_FLAG_TBE: I2C_DATA is empty during transmitting + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_MASTER: a flag indicating whether I2C block is in master or slave mode + \arg I2C_FLAG_I2CBSY: busy flag + \arg I2C_FLAG_TR: whether the I2C is a transmitter or a receiver + \arg I2C_FLAG_RXGC: general call address (00h) received + \arg I2C_FLAG_DEFSMB: default address of SMBus device + \arg I2C_FLAG_HSTSMB: SMBus host header detected in slave mode + \arg I2C_FLAG_DUMOD: dual flag in slave mode indicating which address is matched in dual-address mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(RESET != (I2C_REG_VAL(i2c_periph, flag) & BIT(I2C_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] flag: I2C flags, refer to i2c_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_FLAG_SMBALT: SMBus alert status + \arg I2C_FLAG_SMBTO: timeout signal in SMBus mode + \arg I2C_FLAG_PECERR: PEC error when receiving data + \arg I2C_FLAG_OUERR: over-run or under-run situation occurs in slave mode + \arg I2C_FLAG_AERR: acknowledge error + \arg I2C_FLAG_LOSTARB: arbitration lost in master mode + \arg I2C_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus + \arg I2C_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode + \arg I2C_FLAG_TFF: txframe fall flag + \arg I2C_FLAG_TFR: txframe rise flag + \arg I2C_FLAG_RFF: rxframe fall flag + \arg I2C_FLAG_RFR: rxframe rise flag + \param[out] none + \retval none +*/ +void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag) +{ + if(I2C_FLAG_ADDSEND == flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL(i2c_periph, flag) &= ~BIT(I2C_BIT_POS(flag)); + } +} + +/*! + \brief enable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) |= BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief disable I2C interrupt + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] interrupt: I2C interrupts, refer to i2c_interrupt_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_ERR: error interrupt + \arg I2C_INT_EV: event interrupt + \arg I2C_INT_BUF: buffer interrupt + \arg I2C_INT_TFF: txframe fall interrupt + \arg I2C_INT_TFR: txframe rise interrupt + \arg I2C_INT_RFF: rxframe fall interrupt + \arg I2C_INT_RFR: rxframe rise interrupt + \param[out] none + \retval none +*/ +void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt) +{ + I2C_REG_VAL(i2c_periph, interrupt) &= ~BIT(I2C_BIT_POS(interrupt)); +} + +/*! + \brief get I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_SBSEND: start condition sent out in master mode interrupt flag + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BTC: byte transmission finishes interrupt flag + \arg I2C_INT_FLAG_ADD10SEND: header of 10-bit address is sent in master mode interrupt flag + \arg I2C_INT_FLAG_STPDET: stop condition detected in slave mode interrupt flag + \arg I2C_INT_FLAG_RBNE: I2C_DATA is not Empty during receiving interrupt flag + \arg I2C_INT_FLAG_TBE: I2C_DATA is empty during transmitting interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U, bufie; + + /* check BUFIE */ + bufie = I2C_CTL1(i2c_periph)&I2C_CTL1_BUFIE; + + /* get the interrupt enable bit status */ + intenable = (I2C_REG_VAL(i2c_periph, int_flag) & BIT(I2C_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (I2C_REG_VAL2(i2c_periph, int_flag) & BIT(I2C_BIT_POS2(int_flag))); + + if((I2C_INT_FLAG_RBNE == int_flag) || (I2C_INT_FLAG_TBE == int_flag)) { + if(intenable && bufie) { + intenable = 1U; + } else { + intenable = 0U; + } + } + if((0U != flagstatus) && (0U != intenable)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear I2C interrupt flag status + \param[in] i2c_periph: I2Cx(x=0,1) + \param[in] int_flag: I2C interrupt flags, refer to i2c_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg I2C_INT_FLAG_ADDSEND: address is sent in master mode or received and matches in slave mode interrupt flag + \arg I2C_INT_FLAG_BERR: a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag + \arg I2C_INT_FLAG_LOSTARB: arbitration lost in master mode interrupt flag + \arg I2C_INT_FLAG_AERR: acknowledge error interrupt flag + \arg I2C_INT_FLAG_OUERR: over-run or under-run situation occurs in slave mode interrupt flag + \arg I2C_INT_FLAG_PECERR: PEC error when receiving data interrupt flag + \arg I2C_INT_FLAG_SMBTO: timeout signal in SMBus mode interrupt flag + \arg I2C_INT_FLAG_SMBALT: SMBus alert status interrupt flag + \arg I2C_INT_FLAG_TFF: txframe fall interrupt flag + \arg I2C_INT_FLAG_TFR: txframe rise interrupt flag + \arg I2C_INT_FLAG_RFF: rxframe fall interrupt flag + \arg I2C_INT_FLAG_RFR: rxframe rise interrupt flag + \param[out] none + \retval none +*/ +void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag) +{ + if(I2C_INT_FLAG_ADDSEND == int_flag) { + /* read I2C_STAT0 and then read I2C_STAT1 to clear ADDSEND */ + I2C_STAT0(i2c_periph); + I2C_STAT1(i2c_periph); + } else { + I2C_REG_VAL2(i2c_periph, int_flag) &= ~BIT(I2C_BIT_POS2(int_flag)); + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c index 3f44f71..2868322 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_misc.c @@ -1,141 +1,141 @@ -/*! - \file gd32e23x_misc.c - \brief MISC driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_misc.h" - -/*! - \brief enable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[in] nvic_irq_priority: the priority needed to set (0-3) - \param[out] none - \retval none -*/ -void nvic_irq_enable(IRQn_Type nvic_irq, - uint8_t nvic_irq_priority) -{ - /* set the priority and enable the selected IRQ */ - NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority); - NVIC_EnableIRQ((IRQn_Type)nvic_irq); -} - -/*! - \brief disable NVIC request - \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type - \param[out] none - \retval none -*/ -void nvic_irq_disable(IRQn_Type nvic_irq) -{ - /* disable the selected IRQ.*/ - NVIC_DisableIRQ((IRQn_Type)nvic_irq); -} - -/* */ -/*! - \brief initiates a system reset request to reset the MCU - \param[in] none - \param[out] none - \retval none -*/ -void nvic_system_reset(void) -{ - NVIC_SystemReset(); -} - -/*! - \brief set the NVIC vector table base address - \param[in] nvic_vict_tab: the RAM or FLASH base address - \arg NVIC_VECTTAB_RAM: RAM base address - \arg NVIC_VECTTAB_FLASH: Flash base address - \param[in] offset: Vector Table offset - \param[out] none - \retval none -*/ -void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) -{ - SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); - __DSB(); -} - -/*! - \brief set the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up - by all the enable and disable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_set(uint8_t lowpower_mode) -{ - SCB->SCR |= (uint32_t)lowpower_mode; -} - -/*! - \brief reset the state of the low power mode - \param[in] lowpower_mode: the low power mode state - \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power - mode by exiting from ISR - \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode - \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be - woke up by the enable interrupts - \param[out] none - \retval none -*/ -void system_lowpower_reset(uint8_t lowpower_mode) -{ - SCB->SCR &= (~(uint32_t)lowpower_mode); -} - -/*! - \brief set the systick clock source - \param[in] systick_clksource: the systick clock source needed to choose - \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK - \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 - \param[out] none - \retval none -*/ - -void systick_clksource_set(uint32_t systick_clksource) -{ - if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { - /* set the systick clock source from HCLK */ - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } else { - /* set the systick clock source from HCLK/8 */ - SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; - } -} +/*! + \file gd32e23x_misc.c + \brief MISC driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_misc.h" + +/*! + \brief enable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[in] nvic_irq_priority: the priority needed to set (0-3) + \param[out] none + \retval none +*/ +void nvic_irq_enable(IRQn_Type nvic_irq, + uint8_t nvic_irq_priority) +{ + /* set the priority and enable the selected IRQ */ + NVIC_SetPriority((IRQn_Type)nvic_irq, (uint32_t)nvic_irq_priority); + NVIC_EnableIRQ((IRQn_Type)nvic_irq); +} + +/*! + \brief disable NVIC request + \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type + \param[out] none + \retval none +*/ +void nvic_irq_disable(IRQn_Type nvic_irq) +{ + /* disable the selected IRQ.*/ + NVIC_DisableIRQ((IRQn_Type)nvic_irq); +} + +/* */ +/*! + \brief initiates a system reset request to reset the MCU + \param[in] none + \param[out] none + \retval none +*/ +void nvic_system_reset(void) +{ + NVIC_SystemReset(); +} + +/*! + \brief set the NVIC vector table base address + \param[in] nvic_vict_tab: the RAM or FLASH base address + \arg NVIC_VECTTAB_RAM: RAM base address + \arg NVIC_VECTTAB_FLASH: Flash base address + \param[in] offset: Vector Table offset + \param[out] none + \retval none +*/ +void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) +{ + SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); + __DSB(); +} + +/*! + \brief set the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up + by all the enable and disable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_set(uint8_t lowpower_mode) +{ + SCB->SCR |= (uint32_t)lowpower_mode; +} + +/*! + \brief reset the state of the low power mode + \param[in] lowpower_mode: the low power mode state + \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power + mode by exiting from ISR + \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode + \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be + woke up by the enable interrupts + \param[out] none + \retval none +*/ +void system_lowpower_reset(uint8_t lowpower_mode) +{ + SCB->SCR &= (~(uint32_t)lowpower_mode); +} + +/*! + \brief set the systick clock source + \param[in] systick_clksource: the systick clock source needed to choose + \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK + \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8 + \param[out] none + \retval none +*/ + +void systick_clksource_set(uint32_t systick_clksource) +{ + if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) { + /* set the systick clock source from HCLK */ + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } else { + /* set the systick clock source from HCLK/8 */ + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c index ae93753..0d84462 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_pmu.c @@ -1,289 +1,289 @@ -/*! - \file gd32e23x_pmu.c - \brief PMU driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_pmu.h" - -/*! - \brief reset PMU register - \param[in] none - \param[out] none - \retval none -*/ -void pmu_deinit(void) -{ - /* reset PMU */ - rcu_periph_reset_enable(RCU_PMURST); - rcu_periph_reset_disable(RCU_PMURST); -} - -/*! - \brief select low voltage detector threshold - \param[in] lvdt_n: - only one parameter can be selected which is shown as below: - \arg PMU_LVDT_0: voltage threshold is 2.1V - \arg PMU_LVDT_1: voltage threshold is 2.3V - \arg PMU_LVDT_2: voltage threshold is 2.4V - \arg PMU_LVDT_3: voltage threshold is 2.6V - \arg PMU_LVDT_4: voltage threshold is 2.7V - \arg PMU_LVDT_5: voltage threshold is 2.9V - \arg PMU_LVDT_6: voltage threshold is 3.0V - \arg PMU_LVDT_7: voltage threshold is 3.1V - \param[out] none - \retval none -*/ -void pmu_lvd_select(uint32_t lvdt_n) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; - /* clear LVDT bits */ - PMU_CTL &= ~PMU_CTL_LVDT; - /* set LVDT bits according to lvdt_n */ - PMU_CTL |= lvdt_n; - /* enable LVD */ - PMU_CTL |= PMU_CTL_LVDEN; -} - -/*! - \brief select LDO output voltage - these bits set by software when the main PLL closed - \param[in] ldo_output: - only one parameter can be selected which is shown as below: - \arg PMU_LDOVS_LOW: LDO output voltage low mode - \arg PMU_LDOVS_HIGH: LDO output voltage high mode - \param[out] none - \retval none -*/ -void pmu_ldo_output_select(uint32_t ldo_output) -{ - PMU_CTL &= ~PMU_CTL_LDOVS; - PMU_CTL |= ldo_output; -} - -/*! - \brief disable PMU lvd - \param[in] none - \param[out] none - \retval none -*/ -void pmu_lvd_disable(void) -{ - /* disable LVD */ - PMU_CTL &= ~PMU_CTL_LVDEN; -} - -/*! - \brief PMU work at sleep mode - \param[in] sleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_sleepmode(uint8_t sleepmodecmd) -{ - /* clear sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - /* select WFI or WFE command to enter sleep mode */ - if(WFI_CMD == sleepmodecmd) { - __WFI(); - } else { - __WFE(); - __WFE(); - } -} - -/*! - \brief PMU work at deepsleep mode - \param[in] ldo: - only one parameter can be selected which is shown as below: - \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode - \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode - \param[in] deepsleepmodecmd: - only one parameter can be selected which is shown as below: - \arg WFI_CMD: use WFI command - \arg WFE_CMD: use WFE command - \param[out] none - \retval none -*/ -void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) -{ - /* clear stbmod and ldolp bits */ - PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); - - /* set ldolp bit according to pmu_ldo */ - PMU_CTL |= ldo; - - /* set sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* select WFI or WFE command to enter deepsleep mode */ - if(WFI_CMD == deepsleepmodecmd) { - __WFI(); - } else { - __SEV(); - __WFE(); - __WFE(); - } - - /* reset sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/*! - \brief pmu work at standby mode - \param[in] none - \param[out] none - \retval none -*/ -void pmu_to_standbymode(void) -{ - /* switch to IRC8M clock as system clock, close HXTAL */ - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - - /* set stbmod bit */ - PMU_CTL |= PMU_CTL_STBMOD; - - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - - /* set sleepdeep bit of Cortex-M23 system control register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - REG32(0xE000E010U) &= 0x00010004U; - REG32(0xE000E180U) = 0XFFFFFFFBU; - REG32(0xE000E184U) = 0XFFFFFFFFU; - REG32(0xE000E188U) = 0xFFFFFFFFU; - - /* select WFI command to enter standby mode */ - __WFI(); -} - -/*! - \brief enable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_enable(uint32_t wakeup_pin) -{ - PMU_CS |= wakeup_pin; -} - -/*! - \brief disable wakeup pin - \param[in] wakeup_pin: - one or more parameters can be selected which are shown as below: - \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) - \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) - \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) - \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) - \param[out] none - \retval none -*/ -void pmu_wakeup_pin_disable(uint32_t wakeup_pin) -{ - PMU_CS &= ~(wakeup_pin); -} - -/*! - \brief enable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_enable(void) -{ - PMU_CTL |= PMU_CTL_BKPWEN; -} - -/*! - \brief disable backup domain write - \param[in] none - \param[out] none - \retval none -*/ -void pmu_backup_write_disable(void) -{ - PMU_CTL &= ~PMU_CTL_BKPWEN; -} - -/*! - \brief get flag state - \param[in] flag: - only one parameter can be selected which is shown as below: - \arg PMU_FLAG_WAKEUP: wakeup flag - \arg PMU_FLAG_STANDBY: standby flag - \arg PMU_FLAG_LVD: lvd flag - \param[out] none - \retval FlagStatus SET or RESET -*/ -FlagStatus pmu_flag_get(uint32_t flag) -{ - FlagStatus ret_status = RESET; - - if(PMU_CS & flag) { - ret_status = SET; - } - - return ret_status; -} - -/*! - \brief clear flag bit - \param[in] flag: - one or more parameters can be selected which are shown as below: - \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag - \arg PMU_FLAG_RESET_STANDBY: reset standby flag - \param[out] none - \retval none -*/ -void pmu_flag_clear(uint32_t flag) -{ - if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)) { - /* reset wakeup flag */ - PMU_CTL |= PMU_CTL_WURST; - } - if(RESET != (flag & PMU_FLAG_RESET_STANDBY)) { - /* reset standby flag */ - PMU_CTL |= PMU_CTL_STBRST; - } -} +/*! + \file gd32e23x_pmu.c + \brief PMU driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_pmu.h" + +/*! + \brief reset PMU register + \param[in] none + \param[out] none + \retval none +*/ +void pmu_deinit(void) +{ + /* reset PMU */ + rcu_periph_reset_enable(RCU_PMURST); + rcu_periph_reset_disable(RCU_PMURST); +} + +/*! + \brief select low voltage detector threshold + \param[in] lvdt_n: + only one parameter can be selected which is shown as below: + \arg PMU_LVDT_0: voltage threshold is 2.1V + \arg PMU_LVDT_1: voltage threshold is 2.3V + \arg PMU_LVDT_2: voltage threshold is 2.4V + \arg PMU_LVDT_3: voltage threshold is 2.6V + \arg PMU_LVDT_4: voltage threshold is 2.7V + \arg PMU_LVDT_5: voltage threshold is 2.9V + \arg PMU_LVDT_6: voltage threshold is 3.0V + \arg PMU_LVDT_7: voltage threshold is 3.1V + \param[out] none + \retval none +*/ +void pmu_lvd_select(uint32_t lvdt_n) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; + /* clear LVDT bits */ + PMU_CTL &= ~PMU_CTL_LVDT; + /* set LVDT bits according to lvdt_n */ + PMU_CTL |= lvdt_n; + /* enable LVD */ + PMU_CTL |= PMU_CTL_LVDEN; +} + +/*! + \brief select LDO output voltage + these bits set by software when the main PLL closed + \param[in] ldo_output: + only one parameter can be selected which is shown as below: + \arg PMU_LDOVS_LOW: LDO output voltage low mode + \arg PMU_LDOVS_HIGH: LDO output voltage high mode + \param[out] none + \retval none +*/ +void pmu_ldo_output_select(uint32_t ldo_output) +{ + PMU_CTL &= ~PMU_CTL_LDOVS; + PMU_CTL |= ldo_output; +} + +/*! + \brief disable PMU lvd + \param[in] none + \param[out] none + \retval none +*/ +void pmu_lvd_disable(void) +{ + /* disable LVD */ + PMU_CTL &= ~PMU_CTL_LVDEN; +} + +/*! + \brief PMU work at sleep mode + \param[in] sleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_sleepmode(uint8_t sleepmodecmd) +{ + /* clear sleepdeep bit of Cortex-M23 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + /* select WFI or WFE command to enter sleep mode */ + if(WFI_CMD == sleepmodecmd) { + __WFI(); + } else { + __WFE(); + __WFE(); + } +} + +/*! + \brief PMU work at deepsleep mode + \param[in] ldo: + only one parameter can be selected which is shown as below: + \arg PMU_LDO_NORMAL: LDO operates normally when pmu enter deepsleep mode + \arg PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter deepsleep mode + \param[in] deepsleepmodecmd: + only one parameter can be selected which is shown as below: + \arg WFI_CMD: use WFI command + \arg WFE_CMD: use WFE command + \param[out] none + \retval none +*/ +void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd) +{ + /* clear stbmod and ldolp bits */ + PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP)); + + /* set ldolp bit according to pmu_ldo */ + PMU_CTL |= ldo; + + /* set sleepdeep bit of Cortex-M23 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* select WFI or WFE command to enter deepsleep mode */ + if(WFI_CMD == deepsleepmodecmd) { + __WFI(); + } else { + __SEV(); + __WFE(); + __WFE(); + } + + /* reset sleepdeep bit of Cortex-M23 system control register */ + SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/*! + \brief pmu work at standby mode + \param[in] none + \param[out] none + \retval none +*/ +void pmu_to_standbymode(void) +{ + /* switch to IRC8M clock as system clock, close HXTAL */ + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + + /* set stbmod bit */ + PMU_CTL |= PMU_CTL_STBMOD; + + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + + /* set sleepdeep bit of Cortex-M23 system control register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + REG32(0xE000E010U) &= 0x00010004U; + REG32(0xE000E180U) = 0XFFFFFFFBU; + REG32(0xE000E184U) = 0XFFFFFFFFU; + REG32(0xE000E188U) = 0xFFFFFFFFU; + + /* select WFI command to enter standby mode */ + __WFI(); +} + +/*! + \brief enable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_enable(uint32_t wakeup_pin) +{ + PMU_CS |= wakeup_pin; +} + +/*! + \brief disable wakeup pin + \param[in] wakeup_pin: + one or more parameters can be selected which are shown as below: + \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0) + \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13) + \arg PMU_WAKEUP_PIN5: WKUP Pin 5 (PB5) + \arg PMU_WAKEUP_PIN6: WKUP Pin 6 (PB15) + \param[out] none + \retval none +*/ +void pmu_wakeup_pin_disable(uint32_t wakeup_pin) +{ + PMU_CS &= ~(wakeup_pin); +} + +/*! + \brief enable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_enable(void) +{ + PMU_CTL |= PMU_CTL_BKPWEN; +} + +/*! + \brief disable backup domain write + \param[in] none + \param[out] none + \retval none +*/ +void pmu_backup_write_disable(void) +{ + PMU_CTL &= ~PMU_CTL_BKPWEN; +} + +/*! + \brief get flag state + \param[in] flag: + only one parameter can be selected which is shown as below: + \arg PMU_FLAG_WAKEUP: wakeup flag + \arg PMU_FLAG_STANDBY: standby flag + \arg PMU_FLAG_LVD: lvd flag + \param[out] none + \retval FlagStatus SET or RESET +*/ +FlagStatus pmu_flag_get(uint32_t flag) +{ + FlagStatus ret_status = RESET; + + if(PMU_CS & flag) { + ret_status = SET; + } + + return ret_status; +} + +/*! + \brief clear flag bit + \param[in] flag: + one or more parameters can be selected which are shown as below: + \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag + \arg PMU_FLAG_RESET_STANDBY: reset standby flag + \param[out] none + \retval none +*/ +void pmu_flag_clear(uint32_t flag) +{ + if(RESET != (flag & PMU_FLAG_RESET_WAKEUP)) { + /* reset wakeup flag */ + PMU_CTL |= PMU_CTL_WURST; + } + if(RESET != (flag & PMU_FLAG_RESET_STANDBY)) { + /* reset standby flag */ + PMU_CTL |= PMU_CTL_STBRST; + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c index 26d02da..c3ffa8a 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rcu.c @@ -1,1058 +1,1058 @@ -/*! - \file gd32e23x_rcu.c - \brief RCU driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_rcu.h" - -/* define clock source */ -#define SEL_IRC8M 0x00U -#define SEL_HXTAL 0x01U -#define SEL_PLL 0x02U - -/* define startup timeout count */ -#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) -#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) - -/*! - \brief deinitialize the RCU - \param[in] none - \param[out] none - \retval none -*/ -void rcu_deinit(void) -{ - /* enable IRC8M */ - RCU_CTL0 |= RCU_CTL0_IRC8MEN; - while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) { - } - RCU_CFG0 &= ~RCU_CFG0_SCS; - RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); - /* reset RCU */ - RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | \ - RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); - RCU_CFG1 &= ~(RCU_CFG1_PREDV); - RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; - RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; - RCU_INT = 0x00000000U; -} - -/*! - \brief enable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_PMU: PMU clock - \arg RCU_RTC: RTC clock - \arg RCU_DBGMCU: DBGMCU clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_enable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock - \param[in] periph: RCU peripherals, refer to rcu_periph_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock - \arg RCU_DMA: DMA clock - \arg RCU_CRC: CRC clock - \arg RCU_CFGCMP: CFGCMP clock - \arg RCU_ADC: ADC clock - \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock - \arg RCU_SPIx (x=0,1): SPI clock - \arg RCU_USARTx (x=0,1): USART clock - \arg RCU_WWDGT: WWDGT clock - \arg RCU_I2Cx (x=0,1): I2C clock - \arg RCU_PMU: PMU clock - \arg RCU_RTC: RTC clock - \arg RCU_DBGMCU: DBGMCU clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_disable(rcu_periph_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief enable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); -} - -/*! - \brief disable the peripherals clock when sleep mode - \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum - only one parameter can be selected which is shown as below: - \arg RCU_FMC_SLP: FMC clock - \arg RCU_SRAM_SLP: SRAM clock - \param[out] none - \retval none -*/ -void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) -{ - RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); -} -/*! - \brief reset the peripherals - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER - \arg RCU_SPIxRST (x=0,1): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_PMURST: reset PMU - \param[out] none - \retval none -*/ -void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief disable reset the peripheral - \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum - only one parameter can be selected which is shown as below: - \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports - \arg RCU_CFGCMPRST: reset CFGCMP - \arg RCU_ADCRST: reset ADC - \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER - \arg RCU_SPIxRST (x=0,1): reset SPI - \arg RCU_USARTxRST (x=0,1): reset USART - \arg RCU_WWDGTRST: reset WWDGT - \arg RCU_I2CxRST (x=0,1): reset I2C - \arg RCU_PMURST: reset PMU - \param[out] none - \retval none -*/ -void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) -{ - RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); -} - -/*! - \brief reset the BKP - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_enable(void) -{ - RCU_BDCTL |= RCU_BDCTL_BKPRST; -} - -/*! - \brief disable the BKP reset - \param[in] none - \param[out] none - \retval none -*/ -void rcu_bkp_reset_disable(void) -{ - RCU_BDCTL &= ~RCU_BDCTL_BKPRST; -} - -/*! - \brief configure the system clock source - \param[in] ck_sys: system clock source select - only one parameter can be selected which is shown as below: - \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source - \param[out] none - \retval none -*/ -void rcu_system_clock_source_config(uint32_t ck_sys) -{ - uint32_t cksys_source = 0U; - cksys_source = RCU_CFG0; - /* reset the SCS bits and set according to ck_sys */ - cksys_source &= ~RCU_CFG0_SCS; - RCU_CFG0 = (ck_sys | cksys_source); -} - -/*! - \brief get the system clock source - \param[in] none - \param[out] none - \retval which clock is selected as CK_SYS source - \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source - \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source - \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source -*/ -uint32_t rcu_system_clock_source_get(void) -{ - return (RCU_CFG0 & RCU_CFG0_SCSS); -} - -/*! - \brief configure the AHB clock prescaler selection - \param[in] ck_ahb: AHB clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_AHB_CKSYS_DIVx(x=1, 2, 4, 8, 16, 64, 128, 256, 512): AHB clock is divided by x - \param[out] none - \retval none -*/ -void rcu_ahb_clock_config(uint32_t ck_ahb) -{ - uint32_t ahbpsc = 0U; - ahbpsc = RCU_CFG0; - /* reset the AHBPSC bits and set according to ck_ahb */ - ahbpsc &= ~RCU_CFG0_AHBPSC; - RCU_CFG0 = (ck_ahb | ahbpsc); -} - -/*! - \brief configure the APB1 clock prescaler selection - \param[in] ck_apb1: APB1 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 - \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 - \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 - \param[out] none - \retval none -*/ -void rcu_apb1_clock_config(uint32_t ck_apb1) -{ - uint32_t apb1psc = 0U; - apb1psc = RCU_CFG0; - /* reset the APB1PSC and set according to ck_apb1 */ - apb1psc &= ~RCU_CFG0_APB1PSC; - RCU_CFG0 = (ck_apb1 | apb1psc); -} - -/*! - \brief configure the APB2 clock prescaler selection - \param[in] ck_apb2: APB2 clock prescaler selection - only one parameter can be selected which is shown as below: - \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 - \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 - \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 - \param[out] none - \retval none -*/ -void rcu_apb2_clock_config(uint32_t ck_apb2) -{ - uint32_t apb2psc = 0U; - apb2psc = RCU_CFG0; - /* reset the APB2PSC and set according to ck_apb2 */ - apb2psc &= ~RCU_CFG0_APB2PSC; - RCU_CFG0 = (ck_apb2 | apb2psc); -} - -/*! - \brief configure the ADC clock prescaler selection - \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum - only one parameter can be selected which is shown as below: - \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC - \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC - \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC - \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC - \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC - \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC - \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC - \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC - \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC - \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC - \param[out] none - \retval none -*/ -void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) -{ - /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ - RCU_CFG0 &= ~RCU_CFG0_ADCPSC; - RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); - - /* set the ADC clock according to ck_adc */ - switch(ck_adc) { - case RCU_ADCCK_IRC28M_DIV2: - RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_IRC28M: - RCU_CFG2 |= RCU_CFG2_IRC28MDIV; - RCU_CFG2 &= ~RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV2: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV3: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV4: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV5: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV6: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV7: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_APB2_DIV8: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - case RCU_ADCCK_AHB_DIV9: - RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; - RCU_CFG2 |= RCU_CFG2_ADCPSC2; - RCU_CFG2 |= RCU_CFG2_ADCSEL; - break; - default: - break; - } -} - -/*! - \brief configure the CK_OUT clock source and divider - \param[in] ckout_src: CK_OUT clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_CKOUTSRC_NONE: no clock selected - \arg RCU_CKOUTSRC_IRC28M: IRC28M selected - \arg RCU_CKOUTSRC_IRC40K: IRC40K selected - \arg RCU_CKOUTSRC_LXTAL: LXTAL selected - \arg RCU_CKOUTSRC_CKSYS: CKSYS selected - \arg RCU_CKOUTSRC_IRC8M: IRC8M selected - \arg RCU_CKOUTSRC_HXTAL: HXTAL selected - \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected - \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected - \param[in] ckout_div: CK_OUT divider - \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x - \param[out] none - \retval none -*/ -void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) -{ - uint32_t ckout = 0U; - ckout = RCU_CFG0; - /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ - ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); - RCU_CFG0 = (ckout | ckout_src | ckout_div); -} - -/*! - \brief configure the PLL clock source selection and PLL multiply factor - \param[in] pll_src: PLL clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock - \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock - \param[in] pll_mul: PLL multiply factor - only one parameter can be selected which is shown as below: - \arg RCU_PLL_MULx(x=2..32): PLL source clock * x - \param[out] none - \retval none -*/ -void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) -{ - RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); - RCU_CFG0 |= (pll_src | pll_mul); -} - -/*! - \brief configure the USART clock source selection - \param[in] ck_usart: USART clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 - \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS - \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL - \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M - \param[out] none - \retval none -*/ -void rcu_usart_clock_config(uint32_t ck_usart) -{ - /* reset the USART0SEL bits and set according to ck_usart */ - RCU_CFG2 &= ~RCU_CFG2_USART0SEL; - RCU_CFG2 |= ck_usart; -} - -/*! - \brief configure the RTC clock source selection - \param[in] rtc_clock_source: RTC clock source selection - only one parameter can be selected which is shown as below: - \arg RCU_RTCSRC_NONE: no clock selected - \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock - \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock - \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock - \param[out] none - \retval none -*/ -void rcu_rtc_clock_config(uint32_t rtc_clock_source) -{ - /* reset the RTCSRC bits and set according to rtc_clock_source */ - RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; - RCU_BDCTL |= rtc_clock_source; -} - -/*! - \brief configure the HXTAL divider used as input of PLL - \param[in] hxtal_prediv: HXTAL divider used as input of PLL - only one parameter can be selected which is shown as below: - \arg RCU_PLL_PREDVx(x=1..16): HXTAL divided x used as input of PLL - \param[out] none - \retval none -*/ -void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) -{ - uint32_t prediv = 0U; - prediv = RCU_CFG1; - /* reset the PREDV bits and set according to hxtal_prediv */ - prediv &= ~RCU_CFG1_PREDV; - RCU_CFG1 = (prediv | hxtal_prediv); -} - -/*! - \brief configure the LXTAL drive capability - \param[in] lxtal_dricap: drive capability of LXTAL - only one parameter can be selected which is shown as below: - \arg RCU_LXTAL_LOWDRI: lower driving capability - \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability - \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability - \arg RCU_LXTAL_HIGHDRI: higher driving capability - \param[out] none - \retval none -*/ -void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) -{ - /* reset the LXTALDRI bits and set according to lxtal_dricap */ - RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; - RCU_BDCTL |= lxtal_dricap; -} - -/*! - \brief wait until oscillator stabilization flags is SET - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval ErrStatus: SUCCESS or ERROR -*/ -ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) -{ - uint32_t stb_cnt = 0U; - ErrStatus reval = ERROR; - FlagStatus osci_stat = RESET; - switch(osci) { - case RCU_HXTAL: - /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ - while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait LXTAL stable */ - case RCU_LXTAL: - while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC8M stable */ - case RCU_IRC8M: - while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC28M stable */ - case RCU_IRC28M: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)) { - reval = SUCCESS; - } - break; - - /* wait IRC40K stable */ - case RCU_IRC40K: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { - reval = SUCCESS; - } - break; - - /* wait PLL stable */ - case RCU_PLL_CK: - while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { - osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); - stb_cnt++; - } - /* check whether flag is set or not */ - if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { - reval = SUCCESS; - } - break; - - default: - break; - } - /* return value */ - return reval; -} - -/*! - \brief turn on the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_on(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief turn off the oscillator - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \arg RCU_IRC8M: IRC8M - \arg RCU_IRC28M: IRC28M - \arg RCU_IRC40K: IRC40K - \arg RCU_PLL_CK: PLL - \param[out] none - \retval none -*/ -void rcu_osci_off(rcu_osci_type_enum osci) -{ - RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); -} - -/*! - \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci) { - case RCU_HXTAL: - /* HXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before enable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it - \param[in] osci: oscillator types, refer to rcu_osci_type_enum - only one parameter can be selected which is shown as below: - \arg RCU_HXTAL: HXTAL - \arg RCU_LXTAL: LXTAL - \param[out] none - \retval none -*/ -void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) -{ - uint32_t reg; - switch(osci) { - case RCU_HXTAL: - /* HXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_CTL0; - RCU_CTL0 &= ~RCU_CTL0_HXTALEN; - RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); - break; - case RCU_LXTAL: - /* LXTALEN must be reset before disable the oscillator bypass mode */ - reg = RCU_BDCTL; - RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; - RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); - break; - case RCU_IRC8M: - case RCU_IRC28M: - case RCU_IRC40K: - case RCU_PLL_CK: - break; - default: - break; - } -} - -/*! - \brief enable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_enable(void) -{ - RCU_CTL0 |= RCU_CTL0_CKMEN; -} - -/*! - \brief disable the HXTAL clock monitor - \param[in] none - \param[out] none - \retval none -*/ -void rcu_hxtal_clock_monitor_disable(void) -{ - RCU_CTL0 &= ~RCU_CTL0_CKMEN; -} - -/*! - \brief set the IRC8M adjust value - \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL0; - /* reset the IRC8MADJ bits and set according to irc8m_adjval */ - adjust &= ~RCU_CTL0_IRC8MADJ; - RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval) << 3)); -} - -/*! - \brief set the IRC28M adjust value - \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F - \param[out] none - \retval none -*/ -void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) -{ - uint32_t adjust = 0U; - adjust = RCU_CTL1; - /* reset the IRC28MADJ bits and set according to irc28m_adjval */ - adjust &= ~RCU_CTL1_IRC28MADJ; - RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval) << 3)); -} - -/*! - \brief unlock the voltage key - \param[in] none - \param[out] none - \retval none -*/ -void rcu_voltage_key_unlock(void) -{ - /* reset the KEY bits and set 0x1A2B3C4D */ - RCU_VKEY &= ~RCU_VKEY_KEY; - RCU_VKEY |= RCU_VKEY_UNLOCK; -} - -/*! - \brief set voltage in deep sleep mode - \param[in] dsvol: deep sleep mode voltage - only one parameter can be selected which is shown as below: - \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V - \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V - \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V - \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V - \param[out] none - \retval none -*/ -void rcu_deepsleep_voltage_set(uint32_t dsvol) -{ - /* reset the DSLPVS bits and set according to dsvol */ - RCU_DSV &= ~RCU_DSV_DSLPVS; - RCU_DSV |= dsvol; -} - -/*! - \brief get the system clock, bus and peripheral clock frequency - \param[in] clock: the clock frequency which to get - only one parameter can be selected which is shown as below: - \arg CK_SYS: system clock frequency - \arg CK_AHB: AHB clock frequency - \arg CK_APB1: APB1 clock frequency - \arg CK_APB2: APB2 clock frequency - \arg CK_ADC: ADC clock frequency - \arg CK_USART: USART0 clock frequency - \param[out] none - \retval clock frequency of system, AHB, APB1, APB2, ADC or USRAT0 -*/ -uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) -{ - uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; - uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; - uint32_t adc_freq = 0U, usart_freq = 0U; - uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; - /* exponent of AHB, APB1 and APB2 clock divider */ - const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - - sws = GET_BITS(RCU_CFG0, 2, 3); - switch(sws) { - /* IRC8M is selected as CK_SYS */ - case SEL_IRC8M: - cksys_freq = IRC8M_VALUE; - break; - /* HXTAL is selected as CK_SYS */ - case SEL_HXTAL: - cksys_freq = HXTAL_VALUE; - break; - /* PLL is selected as CK_SYS */ - case SEL_PLL: - /* get the value of PLLMF[3:0] */ - pllmf = GET_BITS(RCU_CFG0, 18, 21); - pllmf4 = GET_BITS(RCU_CFG0, 27, 27); - /* high 16 bits */ - if(1U == pllmf4) { - pllmf += 17U; - } else if(15U == pllmf) { - pllmf = 16U; - } else { - pllmf += 2U; - } - - /* PLL clock source selection, HXTAL or IRC8M/2 */ - pllsel = GET_BITS(RCU_CFG0, 16, 16); - if(0U != pllsel) { - prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); - cksys_freq = (HXTAL_VALUE / prediv) * pllmf; - } else { - cksys_freq = (IRC8M_VALUE >> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - cksys_freq = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - ahb_freq = cksys_freq >> clk_exp; - - /* calculate APB1 clock frequency */ - idx = GET_BITS(RCU_CFG0, 8, 10); - clk_exp = apb1_exp[idx]; - apb1_freq = ahb_freq >> clk_exp; - - /* calculate APB2 clock frequency */ - idx = GET_BITS(RCU_CFG0, 11, 13); - clk_exp = apb2_exp[idx]; - apb2_freq = ahb_freq >> clk_exp; - - /* return the clocks frequency */ - switch(clock) { - case CK_SYS: - ck_freq = cksys_freq; - break; - case CK_AHB: - ck_freq = ahb_freq; - break; - case CK_APB1: - ck_freq = apb1_freq; - break; - case CK_APB2: - ck_freq = apb2_freq; - break; - case CK_ADC: - /* calculate ADC clock frequency */ - if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)) { - if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)) { - adc_freq = IRC28M_VALUE >> 1; - } else { - adc_freq = IRC28M_VALUE; - } - } else { - /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ - adcps = GET_BITS(RCU_CFG0, 14, 15); - adcps2 = GET_BITS(RCU_CFG2, 31, 31); - switch(adcps) { - case 0: - if(0U == adcps2) { - adc_freq = apb2_freq / 2U; - } else { - adc_freq = ahb_freq / 3U; - } - break; - case 1: - if(0U == adcps2) { - adc_freq = apb2_freq / 4U; - } else { - adc_freq = ahb_freq / 5U; - } - break; - case 2: - if(0U == adcps2) { - adc_freq = apb2_freq / 6U; - } else { - adc_freq = ahb_freq / 7U; - } - break; - case 3: - if(0U == adcps2) { - adc_freq = apb2_freq / 8U; - } else { - adc_freq = ahb_freq / 9U; - } - break; - default: - break; - } - } - ck_freq = adc_freq; - break; - case CK_USART: - /* calculate USART0 clock frequency */ - if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { - usart_freq = apb2_freq; - } else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { - usart_freq = cksys_freq; - } else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { - usart_freq = LXTAL_VALUE; - } else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { - usart_freq = IRC8M_VALUE; - } else { - } - ck_freq = usart_freq; - break; - default: - break; - } - return ck_freq; -} - -/*! - \brief get the clock stabilization and periphral reset flags - \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag - \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag - \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag - \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag - \arg RCU_FLAG_PLLSTB: PLL stabilization flag - \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag - \arg RCU_FLAG_V12RST: V12 domain power reset flag - \arg RCU_FLAG_OBLRST: option byte loader reset flag - \arg RCU_FLAG_EPRST: external pin reset flag - \arg RCU_FLAG_PORRST: power reset flag - \arg RCU_FLAG_SWRST: software reset flag - \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag - \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag - \arg RCU_FLAG_LPRST: low-power reset flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_flag_get(rcu_flag_enum flag) -{ - if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the reset flag - \param[in] none - \param[out] none - \retval none -*/ -void rcu_all_reset_flag_clear(void) -{ - RCU_RSTSCK |= RCU_RSTSCK_RSTFC; -} - -/*! - \brief get the clock stabilization interrupt and ckm flags - \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag - \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag - \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag - \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag - \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag - \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) -{ - if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the interrupt flags - \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear - \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear - \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear - \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear - \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear - \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear - \param[out] none - \retval none -*/ -void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) -{ - RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); -} - -/*! - \brief enable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable - \param[out] none - \retval none -*/ -void rcu_interrupt_enable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); -} - - -/*! - \brief disable the stabilization interrupt - \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum - only one parameter can be selected which is shown as below: - \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable - \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable - \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable - \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable - \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable - \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable - \param[out] none - \retval none -*/ -void rcu_interrupt_disable(rcu_int_enum stab_int) -{ - RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); -} +/*! + \file gd32e23x_rcu.c + \brief RCU driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_rcu.h" + +/* define clock source */ +#define SEL_IRC8M 0x00U +#define SEL_HXTAL 0x01U +#define SEL_PLL 0x02U + +/* define startup timeout count */ +#define OSC_STARTUP_TIMEOUT ((uint32_t)0x000FFFFFU) +#define LXTAL_STARTUP_TIMEOUT ((uint32_t)0x03FFFFFFU) + +/*! + \brief deinitialize the RCU + \param[in] none + \param[out] none + \retval none +*/ +void rcu_deinit(void) +{ + /* enable IRC8M */ + RCU_CTL0 |= RCU_CTL0_IRC8MEN; + while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)) { + } + RCU_CFG0 &= ~RCU_CFG0_SCS; + RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS); + /* reset RCU */ + RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC | \ + RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV); + RCU_CFG1 &= ~(RCU_CFG1_PREDV); + RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL); + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCPSC2; + RCU_CTL1 &= ~RCU_CTL1_IRC28MEN; + RCU_INT = 0x00000000U; +} + +/*! + \brief enable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_PMU: PMU clock + \arg RCU_RTC: RTC clock + \arg RCU_DBGMCU: DBGMCU clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_enable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock + \param[in] periph: RCU peripherals, refer to rcu_periph_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOx (x=A,B,C,F): GPIO ports clock + \arg RCU_DMA: DMA clock + \arg RCU_CRC: CRC clock + \arg RCU_CFGCMP: CFGCMP clock + \arg RCU_ADC: ADC clock + \arg RCU_TIMERx (x=0,2,5,13,14,15,16): TIMER clock + \arg RCU_SPIx (x=0,1): SPI clock + \arg RCU_USARTx (x=0,1): USART clock + \arg RCU_WWDGT: WWDGT clock + \arg RCU_I2Cx (x=0,1): I2C clock + \arg RCU_PMU: PMU clock + \arg RCU_RTC: RTC clock + \arg RCU_DBGMCU: DBGMCU clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_disable(rcu_periph_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief enable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) |= BIT(RCU_BIT_POS(periph)); +} + +/*! + \brief disable the peripherals clock when sleep mode + \param[in] periph: RCU peripherals, refer to rcu_periph_sleep_enum + only one parameter can be selected which is shown as below: + \arg RCU_FMC_SLP: FMC clock + \arg RCU_SRAM_SLP: SRAM clock + \param[out] none + \retval none +*/ +void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph) +{ + RCU_REG_VAL(periph) &= ~BIT(RCU_BIT_POS(periph)); +} +/*! + \brief reset the peripherals + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER + \arg RCU_SPIxRST (x=0,1): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_PMURST: reset PMU + \param[out] none + \retval none +*/ +void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) |= BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief disable reset the peripheral + \param[in] periph_reset: RCU peripherals reset, refer to rcu_periph_reset_enum + only one parameter can be selected which is shown as below: + \arg RCU_GPIOxRST (x=A,B,C,F): reset GPIO ports + \arg RCU_CFGCMPRST: reset CFGCMP + \arg RCU_ADCRST: reset ADC + \arg RCU_TIMERxRST (x=0,2,5,13,14,15,16): reset TIMER + \arg RCU_SPIxRST (x=0,1): reset SPI + \arg RCU_USARTxRST (x=0,1): reset USART + \arg RCU_WWDGTRST: reset WWDGT + \arg RCU_I2CxRST (x=0,1): reset I2C + \arg RCU_PMURST: reset PMU + \param[out] none + \retval none +*/ +void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset) +{ + RCU_REG_VAL(periph_reset) &= ~BIT(RCU_BIT_POS(periph_reset)); +} + +/*! + \brief reset the BKP + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_enable(void) +{ + RCU_BDCTL |= RCU_BDCTL_BKPRST; +} + +/*! + \brief disable the BKP reset + \param[in] none + \param[out] none + \retval none +*/ +void rcu_bkp_reset_disable(void) +{ + RCU_BDCTL &= ~RCU_BDCTL_BKPRST; +} + +/*! + \brief configure the system clock source + \param[in] ck_sys: system clock source select + only one parameter can be selected which is shown as below: + \arg RCU_CKSYSSRC_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_CKSYSSRC_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_CKSYSSRC_PLL: select CK_PLL as the CK_SYS source + \param[out] none + \retval none +*/ +void rcu_system_clock_source_config(uint32_t ck_sys) +{ + uint32_t cksys_source = 0U; + cksys_source = RCU_CFG0; + /* reset the SCS bits and set according to ck_sys */ + cksys_source &= ~RCU_CFG0_SCS; + RCU_CFG0 = (ck_sys | cksys_source); +} + +/*! + \brief get the system clock source + \param[in] none + \param[out] none + \retval which clock is selected as CK_SYS source + \arg RCU_SCSS_IRC8M: select CK_IRC8M as the CK_SYS source + \arg RCU_SCSS_HXTAL: select CK_HXTAL as the CK_SYS source + \arg RCU_SCSS_PLL: select CK_PLL as the CK_SYS source +*/ +uint32_t rcu_system_clock_source_get(void) +{ + return (RCU_CFG0 & RCU_CFG0_SCSS); +} + +/*! + \brief configure the AHB clock prescaler selection + \param[in] ck_ahb: AHB clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_AHB_CKSYS_DIVx(x=1, 2, 4, 8, 16, 64, 128, 256, 512): AHB clock is divided by x + \param[out] none + \retval none +*/ +void rcu_ahb_clock_config(uint32_t ck_ahb) +{ + uint32_t ahbpsc = 0U; + ahbpsc = RCU_CFG0; + /* reset the AHBPSC bits and set according to ck_ahb */ + ahbpsc &= ~RCU_CFG0_AHBPSC; + RCU_CFG0 = (ck_ahb | ahbpsc); +} + +/*! + \brief configure the APB1 clock prescaler selection + \param[in] ck_apb1: APB1 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB1_CKAHB_DIV1: select CK_AHB as CK_APB1 + \arg RCU_APB1_CKAHB_DIV2: select CK_AHB/2 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV4: select CK_AHB/4 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV8: select CK_AHB/8 as CK_APB1 + \arg RCU_APB1_CKAHB_DIV16: select CK_AHB/16 as CK_APB1 + \param[out] none + \retval none +*/ +void rcu_apb1_clock_config(uint32_t ck_apb1) +{ + uint32_t apb1psc = 0U; + apb1psc = RCU_CFG0; + /* reset the APB1PSC and set according to ck_apb1 */ + apb1psc &= ~RCU_CFG0_APB1PSC; + RCU_CFG0 = (ck_apb1 | apb1psc); +} + +/*! + \brief configure the APB2 clock prescaler selection + \param[in] ck_apb2: APB2 clock prescaler selection + only one parameter can be selected which is shown as below: + \arg RCU_APB2_CKAHB_DIV1: select CK_AHB as CK_APB2 + \arg RCU_APB2_CKAHB_DIV2: select CK_AHB/2 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV4: select CK_AHB/4 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV8: select CK_AHB/8 as CK_APB2 + \arg RCU_APB2_CKAHB_DIV16: select CK_AHB/16 as CK_APB2 + \param[out] none + \retval none +*/ +void rcu_apb2_clock_config(uint32_t ck_apb2) +{ + uint32_t apb2psc = 0U; + apb2psc = RCU_CFG0; + /* reset the APB2PSC and set according to ck_apb2 */ + apb2psc &= ~RCU_CFG0_APB2PSC; + RCU_CFG0 = (ck_apb2 | apb2psc); +} + +/*! + \brief configure the ADC clock prescaler selection + \param[in] ck_adc: ADC clock prescaler selection, refer to rcu_adc_clock_enum + only one parameter can be selected which is shown as below: + \arg RCU_ADCCK_IRC28M_DIV2: select CK_IRC28M/2 as CK_ADC + \arg RCU_ADCCK_IRC28M: select CK_IRC28M as CK_ADC + \arg RCU_ADCCK_APB2_DIV2: select CK_APB2/2 as CK_ADC + \arg RCU_ADCCK_AHB_DIV3: select CK_AHB/3 as CK_ADC + \arg RCU_ADCCK_APB2_DIV4: select CK_APB2/4 as CK_ADC + \arg RCU_ADCCK_AHB_DIV5: select CK_AHB/5 as CK_ADC + \arg RCU_ADCCK_APB2_DIV6: select CK_APB2/6 as CK_ADC + \arg RCU_ADCCK_AHB_DIV7: select CK_AHB/7 as CK_ADC + \arg RCU_ADCCK_APB2_DIV8: select CK_APB2/8 as CK_ADC + \arg RCU_ADCCK_AHB_DIV9: select CK_AHB/9 as CK_ADC + \param[out] none + \retval none +*/ +void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc) +{ + /* reset the ADCPSC, ADCSEL, IRC28MDIV bits */ + RCU_CFG0 &= ~RCU_CFG0_ADCPSC; + RCU_CFG2 &= ~(RCU_CFG2_ADCSEL | RCU_CFG2_IRC28MDIV | RCU_CFG2_ADCPSC2); + + /* set the ADC clock according to ck_adc */ + switch(ck_adc) { + case RCU_ADCCK_IRC28M_DIV2: + RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_IRC28M: + RCU_CFG2 |= RCU_CFG2_IRC28MDIV; + RCU_CFG2 &= ~RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV2: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV3: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV2; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV4: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV5: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV4; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV6: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV7: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV6; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_APB2_DIV8: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + case RCU_ADCCK_AHB_DIV9: + RCU_CFG0 |= RCU_ADC_CKAPB2_DIV8; + RCU_CFG2 |= RCU_CFG2_ADCPSC2; + RCU_CFG2 |= RCU_CFG2_ADCSEL; + break; + default: + break; + } +} + +/*! + \brief configure the CK_OUT clock source and divider + \param[in] ckout_src: CK_OUT clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_CKOUTSRC_NONE: no clock selected + \arg RCU_CKOUTSRC_IRC28M: IRC28M selected + \arg RCU_CKOUTSRC_IRC40K: IRC40K selected + \arg RCU_CKOUTSRC_LXTAL: LXTAL selected + \arg RCU_CKOUTSRC_CKSYS: CKSYS selected + \arg RCU_CKOUTSRC_IRC8M: IRC8M selected + \arg RCU_CKOUTSRC_HXTAL: HXTAL selected + \arg RCU_CKOUTSRC_CKPLL_DIV1: CK_PLL selected + \arg RCU_CKOUTSRC_CKPLL_DIV2: CK_PLL/2 selected + \param[in] ckout_div: CK_OUT divider + \arg RCU_CKOUT_DIVx(x=1,2,4,8,16,32,64,128): CK_OUT is divided by x + \param[out] none + \retval none +*/ +void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div) +{ + uint32_t ckout = 0U; + ckout = RCU_CFG0; + /* reset the CKOUTSEL, CKOUTDIV and PLLDV bits and set according to ckout_src and ckout_div */ + ckout &= ~(RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV); + RCU_CFG0 = (ckout | ckout_src | ckout_div); +} + +/*! + \brief configure the PLL clock source selection and PLL multiply factor + \param[in] pll_src: PLL clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_PLLSRC_IRC8M_DIV2: select CK_IRC8M/2 as PLL source clock + \arg RCU_PLLSRC_HXTAL: select HXTAL as PLL source clock + \param[in] pll_mul: PLL multiply factor + only one parameter can be selected which is shown as below: + \arg RCU_PLL_MULx(x=2..32): PLL source clock * x + \param[out] none + \retval none +*/ +void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul) +{ + RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF); + RCU_CFG0 |= (pll_src | pll_mul); +} + +/*! + \brief configure the USART clock source selection + \param[in] ck_usart: USART clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_USART0SRC_CKAPB2: CK_USART0 select CK_APB2 + \arg RCU_USART0SRC_CKSYS: CK_USART0 select CK_SYS + \arg RCU_USART0SRC_LXTAL: CK_USART0 select CK_LXTAL + \arg RCU_USART0SRC_IRC8M: CK_USART0 select CK_IRC8M + \param[out] none + \retval none +*/ +void rcu_usart_clock_config(uint32_t ck_usart) +{ + /* reset the USART0SEL bits and set according to ck_usart */ + RCU_CFG2 &= ~RCU_CFG2_USART0SEL; + RCU_CFG2 |= ck_usart; +} + +/*! + \brief configure the RTC clock source selection + \param[in] rtc_clock_source: RTC clock source selection + only one parameter can be selected which is shown as below: + \arg RCU_RTCSRC_NONE: no clock selected + \arg RCU_RTCSRC_LXTAL: CK_LXTAL selected as RTC source clock + \arg RCU_RTCSRC_IRC40K: CK_IRC40K selected as RTC source clock + \arg RCU_RTCSRC_HXTAL_DIV32: CK_HXTAL/32 selected as RTC source clock + \param[out] none + \retval none +*/ +void rcu_rtc_clock_config(uint32_t rtc_clock_source) +{ + /* reset the RTCSRC bits and set according to rtc_clock_source */ + RCU_BDCTL &= ~RCU_BDCTL_RTCSRC; + RCU_BDCTL |= rtc_clock_source; +} + +/*! + \brief configure the HXTAL divider used as input of PLL + \param[in] hxtal_prediv: HXTAL divider used as input of PLL + only one parameter can be selected which is shown as below: + \arg RCU_PLL_PREDVx(x=1..16): HXTAL divided x used as input of PLL + \param[out] none + \retval none +*/ +void rcu_hxtal_prediv_config(uint32_t hxtal_prediv) +{ + uint32_t prediv = 0U; + prediv = RCU_CFG1; + /* reset the PREDV bits and set according to hxtal_prediv */ + prediv &= ~RCU_CFG1_PREDV; + RCU_CFG1 = (prediv | hxtal_prediv); +} + +/*! + \brief configure the LXTAL drive capability + \param[in] lxtal_dricap: drive capability of LXTAL + only one parameter can be selected which is shown as below: + \arg RCU_LXTAL_LOWDRI: lower driving capability + \arg RCU_LXTAL_MED_LOWDRI: medium low driving capability + \arg RCU_LXTAL_MED_HIGHDRI: medium high driving capability + \arg RCU_LXTAL_HIGHDRI: higher driving capability + \param[out] none + \retval none +*/ +void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap) +{ + /* reset the LXTALDRI bits and set according to lxtal_dricap */ + RCU_BDCTL &= ~RCU_BDCTL_LXTALDRI; + RCU_BDCTL |= lxtal_dricap; +} + +/*! + \brief wait until oscillator stabilization flags is SET + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval ErrStatus: SUCCESS or ERROR +*/ +ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci) +{ + uint32_t stb_cnt = 0U; + ErrStatus reval = ERROR; + FlagStatus osci_stat = RESET; + switch(osci) { + case RCU_HXTAL: + /* wait until HXTAL is stabilization and osci_stat is not more than timeout */ + while((RESET == osci_stat) && (HXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_HXTALSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_HXTALSTB)) { + reval = SUCCESS; + } + break; + + /* wait LXTAL stable */ + case RCU_LXTAL: + while((RESET == osci_stat) && (LXTAL_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_LXTALSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_LXTALSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC8M stable */ + case RCU_IRC8M: + while((RESET == osci_stat) && (IRC8M_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC8MSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC8MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC28M stable */ + case RCU_IRC28M: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC28MSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC28MSTB)) { + reval = SUCCESS; + } + break; + + /* wait IRC40K stable */ + case RCU_IRC40K: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_IRC40KSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_IRC40KSTB)) { + reval = SUCCESS; + } + break; + + /* wait PLL stable */ + case RCU_PLL_CK: + while((RESET == osci_stat) && (OSC_STARTUP_TIMEOUT != stb_cnt)) { + osci_stat = rcu_flag_get(RCU_FLAG_PLLSTB); + stb_cnt++; + } + /* check whether flag is set or not */ + if(RESET != rcu_flag_get(RCU_FLAG_PLLSTB)) { + reval = SUCCESS; + } + break; + + default: + break; + } + /* return value */ + return reval; +} + +/*! + \brief turn on the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_on(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) |= BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief turn off the oscillator + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \arg RCU_IRC8M: IRC8M + \arg RCU_IRC28M: IRC28M + \arg RCU_IRC40K: IRC40K + \arg RCU_PLL_CK: PLL + \param[out] none + \retval none +*/ +void rcu_osci_off(rcu_osci_type_enum osci) +{ + RCU_REG_VAL(osci) &= ~BIT(RCU_BIT_POS(osci)); +} + +/*! + \brief enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci) { + case RCU_HXTAL: + /* HXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg | RCU_CTL0_HXTALBPS); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before enable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg | RCU_BDCTL_LXTALBPS); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it + \param[in] osci: oscillator types, refer to rcu_osci_type_enum + only one parameter can be selected which is shown as below: + \arg RCU_HXTAL: HXTAL + \arg RCU_LXTAL: LXTAL + \param[out] none + \retval none +*/ +void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci) +{ + uint32_t reg; + switch(osci) { + case RCU_HXTAL: + /* HXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_CTL0; + RCU_CTL0 &= ~RCU_CTL0_HXTALEN; + RCU_CTL0 = (reg & (~RCU_CTL0_HXTALBPS)); + break; + case RCU_LXTAL: + /* LXTALEN must be reset before disable the oscillator bypass mode */ + reg = RCU_BDCTL; + RCU_BDCTL &= ~RCU_BDCTL_LXTALEN; + RCU_BDCTL = (reg & (~RCU_BDCTL_LXTALBPS)); + break; + case RCU_IRC8M: + case RCU_IRC28M: + case RCU_IRC40K: + case RCU_PLL_CK: + break; + default: + break; + } +} + +/*! + \brief enable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_enable(void) +{ + RCU_CTL0 |= RCU_CTL0_CKMEN; +} + +/*! + \brief disable the HXTAL clock monitor + \param[in] none + \param[out] none + \retval none +*/ +void rcu_hxtal_clock_monitor_disable(void) +{ + RCU_CTL0 &= ~RCU_CTL0_CKMEN; +} + +/*! + \brief set the IRC8M adjust value + \param[in] irc8m_adjval: IRC8M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL0; + /* reset the IRC8MADJ bits and set according to irc8m_adjval */ + adjust &= ~RCU_CTL0_IRC8MADJ; + RCU_CTL0 = (adjust | (((uint32_t)irc8m_adjval) << 3)); +} + +/*! + \brief set the IRC28M adjust value + \param[in] irc28m_adjval: IRC28M adjust value, must be between 0 and 0x1F + \param[out] none + \retval none +*/ +void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval) +{ + uint32_t adjust = 0U; + adjust = RCU_CTL1; + /* reset the IRC28MADJ bits and set according to irc28m_adjval */ + adjust &= ~RCU_CTL1_IRC28MADJ; + RCU_CTL1 = (adjust | (((uint32_t)irc28m_adjval) << 3)); +} + +/*! + \brief unlock the voltage key + \param[in] none + \param[out] none + \retval none +*/ +void rcu_voltage_key_unlock(void) +{ + /* reset the KEY bits and set 0x1A2B3C4D */ + RCU_VKEY &= ~RCU_VKEY_KEY; + RCU_VKEY |= RCU_VKEY_UNLOCK; +} + +/*! + \brief set voltage in deep sleep mode + \param[in] dsvol: deep sleep mode voltage + only one parameter can be selected which is shown as below: + \arg RCU_DEEPSLEEP_V_1_0: the core voltage is 1.0V + \arg RCU_DEEPSLEEP_V_0_9: the core voltage is 0.9V + \arg RCU_DEEPSLEEP_V_0_8: the core voltage is 0.8V + \arg RCU_DEEPSLEEP_V_1_2: the core voltage is 1.2V + \param[out] none + \retval none +*/ +void rcu_deepsleep_voltage_set(uint32_t dsvol) +{ + /* reset the DSLPVS bits and set according to dsvol */ + RCU_DSV &= ~RCU_DSV_DSLPVS; + RCU_DSV |= dsvol; +} + +/*! + \brief get the system clock, bus and peripheral clock frequency + \param[in] clock: the clock frequency which to get + only one parameter can be selected which is shown as below: + \arg CK_SYS: system clock frequency + \arg CK_AHB: AHB clock frequency + \arg CK_APB1: APB1 clock frequency + \arg CK_APB2: APB2 clock frequency + \arg CK_ADC: ADC clock frequency + \arg CK_USART: USART0 clock frequency + \param[out] none + \retval clock frequency of system, AHB, APB1, APB2, ADC or USRAT0 +*/ +uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock) +{ + uint32_t sws = 0U, adcps = 0U, adcps2 = 0U, ck_freq = 0U; + uint32_t cksys_freq = 0U, ahb_freq = 0U, apb1_freq = 0U, apb2_freq = 0U; + uint32_t adc_freq = 0U, usart_freq = 0U; + uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U; + /* exponent of AHB, APB1 and APB2 clock divider */ + const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t apb1_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t apb2_exp[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + + sws = GET_BITS(RCU_CFG0, 2, 3); + switch(sws) { + /* IRC8M is selected as CK_SYS */ + case SEL_IRC8M: + cksys_freq = IRC8M_VALUE; + break; + /* HXTAL is selected as CK_SYS */ + case SEL_HXTAL: + cksys_freq = HXTAL_VALUE; + break; + /* PLL is selected as CK_SYS */ + case SEL_PLL: + /* get the value of PLLMF[3:0] */ + pllmf = GET_BITS(RCU_CFG0, 18, 21); + pllmf4 = GET_BITS(RCU_CFG0, 27, 27); + /* high 16 bits */ + if(1U == pllmf4) { + pllmf += 17U; + } else if(15U == pllmf) { + pllmf = 16U; + } else { + pllmf += 2U; + } + + /* PLL clock source selection, HXTAL or IRC8M/2 */ + pllsel = GET_BITS(RCU_CFG0, 16, 16); + if(0U != pllsel) { + prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U); + cksys_freq = (HXTAL_VALUE / prediv) * pllmf; + } else { + cksys_freq = (IRC8M_VALUE >> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + cksys_freq = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + ahb_freq = cksys_freq >> clk_exp; + + /* calculate APB1 clock frequency */ + idx = GET_BITS(RCU_CFG0, 8, 10); + clk_exp = apb1_exp[idx]; + apb1_freq = ahb_freq >> clk_exp; + + /* calculate APB2 clock frequency */ + idx = GET_BITS(RCU_CFG0, 11, 13); + clk_exp = apb2_exp[idx]; + apb2_freq = ahb_freq >> clk_exp; + + /* return the clocks frequency */ + switch(clock) { + case CK_SYS: + ck_freq = cksys_freq; + break; + case CK_AHB: + ck_freq = ahb_freq; + break; + case CK_APB1: + ck_freq = apb1_freq; + break; + case CK_APB2: + ck_freq = apb2_freq; + break; + case CK_ADC: + /* calculate ADC clock frequency */ + if(RCU_ADCSRC_AHB_APB2DIV != (RCU_CFG2 & RCU_CFG2_ADCSEL)) { + if(RCU_ADC_IRC28M_DIV1 != (RCU_CFG2 & RCU_CFG2_IRC28MDIV)) { + adc_freq = IRC28M_VALUE >> 1; + } else { + adc_freq = IRC28M_VALUE; + } + } else { + /* ADC clock select CK_APB2 divided by 2/4/6/8 or CK_AHB divided by 3/5/7/9 */ + adcps = GET_BITS(RCU_CFG0, 14, 15); + adcps2 = GET_BITS(RCU_CFG2, 31, 31); + switch(adcps) { + case 0: + if(0U == adcps2) { + adc_freq = apb2_freq / 2U; + } else { + adc_freq = ahb_freq / 3U; + } + break; + case 1: + if(0U == adcps2) { + adc_freq = apb2_freq / 4U; + } else { + adc_freq = ahb_freq / 5U; + } + break; + case 2: + if(0U == adcps2) { + adc_freq = apb2_freq / 6U; + } else { + adc_freq = ahb_freq / 7U; + } + break; + case 3: + if(0U == adcps2) { + adc_freq = apb2_freq / 8U; + } else { + adc_freq = ahb_freq / 9U; + } + break; + default: + break; + } + } + ck_freq = adc_freq; + break; + case CK_USART: + /* calculate USART0 clock frequency */ + if(RCU_USART0SRC_CKAPB2 == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = apb2_freq; + } else if(RCU_USART0SRC_CKSYS == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = cksys_freq; + } else if(RCU_USART0SRC_LXTAL == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = LXTAL_VALUE; + } else if(RCU_USART0SRC_IRC8M == (RCU_CFG2 & RCU_CFG2_USART0SEL)) { + usart_freq = IRC8M_VALUE; + } else { + } + ck_freq = usart_freq; + break; + default: + break; + } + return ck_freq; +} + +/*! + \brief get the clock stabilization and periphral reset flags + \param[in] flag: the clock stabilization and periphral reset flags, refer to rcu_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_FLAG_IRC40KSTB: IRC40K stabilization flag + \arg RCU_FLAG_LXTALSTB: LXTAL stabilization flag + \arg RCU_FLAG_IRC8MSTB: IRC8M stabilization flag + \arg RCU_FLAG_HXTALSTB: HXTAL stabilization flag + \arg RCU_FLAG_PLLSTB: PLL stabilization flag + \arg RCU_FLAG_IRC28MSTB: IRC28M stabilization flag + \arg RCU_FLAG_V12RST: V12 domain power reset flag + \arg RCU_FLAG_OBLRST: option byte loader reset flag + \arg RCU_FLAG_EPRST: external pin reset flag + \arg RCU_FLAG_PORRST: power reset flag + \arg RCU_FLAG_SWRST: software reset flag + \arg RCU_FLAG_FWDGTRST: free watchdog timer reset flag + \arg RCU_FLAG_WWDGTRST: window watchdog timer reset flag + \arg RCU_FLAG_LPRST: low-power reset flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_flag_get(rcu_flag_enum flag) +{ + if(RESET != (RCU_REG_VAL(flag) & BIT(RCU_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the reset flag + \param[in] none + \param[out] none + \retval none +*/ +void rcu_all_reset_flag_clear(void) +{ + RCU_RSTSCK |= RCU_RSTSCK_RSTFC; +} + +/*! + \brief get the clock stabilization interrupt and ckm flags + \param[in] int_flag: interrupt and ckm flags, refer to rcu_int_flag_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB: IRC40K stabilization interrupt flag + \arg RCU_INT_FLAG_LXTALSTB: LXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC8MSTB: IRC8M stabilization interrupt flag + \arg RCU_INT_FLAG_HXTALSTB: HXTAL stabilization interrupt flag + \arg RCU_INT_FLAG_PLLSTB: PLL stabilization interrupt flag + \arg RCU_INT_FLAG_IRC28MSTB: IRC28M stabilization interrupt flag + \arg RCU_INT_FLAG_CKM: HXTAL clock stuck interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag) +{ + if(RESET != (RCU_REG_VAL(int_flag) & BIT(RCU_BIT_POS(int_flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the interrupt flags + \param[in] int_flag_clear: clock stabilization and stuck interrupt flags clear, refer to rcu_int_flag_clear_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_FLAG_IRC40KSTB_CLR: IRC40K stabilization interrupt flag clear + \arg RCU_INT_FLAG_LXTALSTB_CLR: LXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC8MSTB_CLR: IRC8M stabilization interrupt flag clear + \arg RCU_INT_FLAG_HXTALSTB_CLR: HXTAL stabilization interrupt flag clear + \arg RCU_INT_FLAG_PLLSTB_CLR: PLL stabilization interrupt flag clear + \arg RCU_INT_FLAG_IRC28MSTB_CLR: IRC28M stabilization interrupt flag clear + \arg RCU_INT_FLAG_CKM_CLR: clock stuck interrupt flag clear + \param[out] none + \retval none +*/ +void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear) +{ + RCU_REG_VAL(int_flag_clear) |= BIT(RCU_BIT_POS(int_flag_clear)); +} + +/*! + \brief enable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt enable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt enable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt enable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt enable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt enable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt enable + \param[out] none + \retval none +*/ +void rcu_interrupt_enable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) |= BIT(RCU_BIT_POS(stab_int)); +} + + +/*! + \brief disable the stabilization interrupt + \param[in] stab_int: clock stabilization interrupt, refer to rcu_int_enum + only one parameter can be selected which is shown as below: + \arg RCU_INT_IRC40KSTB: IRC40K stabilization interrupt disable + \arg RCU_INT_LXTALSTB: LXTAL stabilization interrupt disable + \arg RCU_INT_IRC8MSTB: IRC8M stabilization interrupt disable + \arg RCU_INT_HXTALSTB: HXTAL stabilization interrupt disable + \arg RCU_INT_PLLSTB: PLL stabilization interrupt disable + \arg RCU_INT_IRC28MSTB: IRC28M stabilization interrupt disable + \param[out] none + \retval none +*/ +void rcu_interrupt_disable(rcu_int_enum stab_int) +{ + RCU_REG_VAL(stab_int) &= ~BIT(RCU_BIT_POS(stab_int)); +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c index ecb1524..1144729 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_rtc.c @@ -1,962 +1,962 @@ -/*! - \file gd32e23x_rtc.c - \brief RTC driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_rtc.h" - -/*! - \brief reset most of the RTC registers - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_deinit(void) -{ - ErrStatus error_status = ERROR; - - /* RTC_TAMP register is not under write protection */ - RTC_TAMP = RTC_REGISTER_RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* reset RTC_CTL register, this can be done without the init mode */ - RTC_CTL &= RTC_REGISTER_RESET; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status) { - /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. - in order to read calendar from shadow register, not the real registers being reset */ - RTC_TIME = RTC_REGISTER_RESET; - RTC_DATE = RTC_DATE_RESET; - - RTC_PSC = RTC_PSC_RESET; - - /* reset RTC_STAT register, also exit init mode. - at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ - RTC_STAT = RTC_STAT_RESET; - - /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ - RTC_ALRM0TD = RTC_REGISTER_RESET; - RTC_ALRM0SS = RTC_REGISTER_RESET; - - /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ - RTC_SHIFTCTL = RTC_REGISTER_RESET; - RTC_HRFC = RTC_REGISTER_RESET; - - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief initialize RTC registers - \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) -{ - ErrStatus error_status = ERROR; - uint32_t reg_time = 0x00U, reg_date = 0x00U; - - reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ - DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ - DATE_MON(rtc_initpara_struct->rtc_month) | \ - DATE_DAY(rtc_initpara_struct->rtc_date)); - - reg_time = (rtc_initpara_struct->rtc_am_pm | \ - TIME_HR(rtc_initpara_struct->rtc_hour) | \ - TIME_MN(rtc_initpara_struct->rtc_minute) | \ - TIME_SC(rtc_initpara_struct->rtc_second)); - - /* 1st: disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* 2nd: enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status) { - RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn) | \ - PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); - - RTC_TIME = (uint32_t)reg_time; - RTC_DATE = (uint32_t)reg_date; - - RTC_CTL &= (uint32_t)(~RTC_CTL_CS); - RTC_CTL |= rtc_initpara_struct->rtc_display_format; - - /* 3rd: exit init mode */ - rtc_init_mode_exit(); - - /* 4th: wait the RSYNF flag to set */ - error_status = rtc_register_sync_wait(); - } - - /* 5th: enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enter RTC init mode - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_init_mode_enter(void) -{ - uint32_t time_index = RTC_INITM_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - /* check whether it has been in init mode */ - if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { - RTC_STAT |= RTC_STAT_INITM; - - /* wait until the INITF flag to be set */ - do { - flag_status = RTC_STAT & RTC_STAT_INITF; - } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status) { - error_status = SUCCESS; - } - } else { - error_status = SUCCESS; - } - return error_status; -} - -/*! - \brief exit RTC init mode - \param[in] none - \param[out] none - \retval none -*/ -void rtc_init_mode_exit(void) -{ - RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); -} - -/*! - \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow - registers are updated - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_register_sync_wait(void) -{ - volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; - uint32_t flag_status = RESET; - ErrStatus error_status = ERROR; - - if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* firstly clear RSYNF flag */ - RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); - - /* wait until RSYNF flag to be set */ - do { - flag_status = RTC_STAT & RTC_STAT_RSYNF; - } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status) { - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - } else { - error_status = SUCCESS; - } - - return error_status; -} - -/*! - \brief get current time and date - \param[in] none - \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains - parameters for initialization of the rtc peripheral - members of the structure and the member values are shown as below: - rtc_year: 0x0 - 0x99(BCD format) - rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_date: 0x1 - 0x31(BCD format) - rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY - RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY - rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose - rtc_minute: 0x0 - 0x59(BCD format) - rtc_second: 0x0 - 0x59(BCD format) - rtc_factor_asyn: 0x0 - 0x7F - rtc_factor_syn: 0x0 - 0x7FFF - rtc_am_pm: RTC_AM, RTC_PM - rtc_display_format: RTC_24HOUR, RTC_12HOUR - \retval none -*/ -void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) -{ - uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; - - temp_tr = (uint32_t)RTC_TIME; - temp_dr = (uint32_t)RTC_DATE; - temp_pscr = (uint32_t)RTC_PSC; - temp_ctlr = (uint32_t)RTC_CTL; - - /* get current time and construct rtc_parameter_struct structure */ - rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); - rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); - rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); - rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); - rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); - rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); - rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); - rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); - rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); - rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); - rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); -} - -/*! - \brief get current subsecond value - \param[in] none - \param[out] none - \retval current subsecond value -*/ -uint32_t rtc_subsecond_get(void) -{ - uint32_t reg = 0x00U; - /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ - reg = (uint32_t)RTC_SS; - /* read RTC_DATE to unlock the 3 shadow registers */ - (void)(RTC_DATE); - - return reg; -} - -/*! - \brief configure RTC alarm - \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \param[out] none - \retval none -*/ -void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ - rtc_alarm_time->rtc_weekday_or_date | \ - rtc_alarm_time->rtc_am_pm | \ - ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ - ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ - ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ - ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0TD = (uint32_t)reg_alrm0td; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure subsecond of RTC alarm - \param[in] mask_subsecond: alarm subsecond mask - only one parameter can be selected which is shown as below: - \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration - \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared - \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared - \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared - \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared - \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared - \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared - \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared - \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared - \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared - \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared - \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared - \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared - \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared - \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared - \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared - \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) - \param[out] none - \retval none -*/ -void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_ALRM0SS = mask_subsecond | subsecond; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC alarm - \param[in] none - \param[out] none - \retval none -*/ -void rtc_alarm_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= RTC_CTL_ALRM0EN; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC alarm - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_alarm_disable(void) -{ - volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the state of alarm */ - RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); - - /* wait until ALRM0WF flag to be set after the alarm is disabled */ - do { - flag_status = RTC_STAT & RTC_STAT_ALRM0WF; - } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); - - if((uint32_t)RESET != flag_status) { - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief get RTC alarm - \param[in] none - \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains - parameters for RTC alarm configuration - members of the structure and the member values are shown as below: - rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK - RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK - rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED - rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set - 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_alarm_minute: 0x0 - 0x59(BCD format) - rtc_alarm_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time) -{ - uint32_t reg_alrm0td = 0x00U; - - /* get the value of RTC_ALRM0TD register */ - reg_alrm0td = RTC_ALRM0TD; - - /* get alarm parameters and construct the rtc_alarm_struct structure */ - rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; - rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); - rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); - rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); - rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); - rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); - rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); -} - -/*! - \brief get RTC alarm subsecond - \param[in] none - \param[out] none - \retval RTC alarm subsecond value -*/ -uint32_t rtc_alarm_subsecond_get(void) -{ - return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); -} - -/*! - \brief enable RTC time-stamp - \param[in] edge: specify which edge to detect of time-stamp - only one parameter can be selected which is shown as below: - \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event - \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event - \param[out] none - \retval none -*/ -void rtc_timestamp_enable(uint32_t edge) -{ - uint32_t reg_ctl = 0x00U; - - /* clear the bits to be configured in RTC_CTL */ - reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); - - /* new configuration */ - reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL = (uint32_t)reg_ctl; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC time-stamp - \param[in] none - \param[out] none - \retval none -*/ -void rtc_timestamp_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* clear the TSEN bit */ - RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief get RTC timestamp time and date - \param[in] none - \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains - parameters for RTC time-stamp configuration - members of the structure and the member values are shown as below: - rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, - RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC - rtc_timestamp_date: 0x1 - 0x31(BCD format) - rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, - RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set - rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format - rtc_timestamp_minute: 0x0 - 0x59(BCD format) - rtc_timestamp_second: 0x0 - 0x59(BCD format) - rtc_am_pm: RTC_AM, RTC_PM - \retval none -*/ -void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) -{ - uint32_t temp_tts = 0x00U, temp_dts = 0x00U; - - /* get the value of time_stamp registers */ - temp_tts = (uint32_t)RTC_TTS; - temp_dts = (uint32_t)RTC_DTS; - - /* get timestamp time and construct the rtc_timestamp_struct structure */ - rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); - rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); - rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); - rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); - rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); - rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); - rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); -} - -/*! - \brief get RTC time-stamp subsecond - \param[in] none - \param[out] none - \retval RTC time-stamp subsecond value -*/ -uint32_t rtc_timestamp_subsecond_get(void) -{ - return ((uint32_t)RTC_SSTS); -} - - -/*! - \brief enable RTC tamper - \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains - parameters for RTC tamper configuration - members of the structure and the member values are shown as below: - rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 - rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING - RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH - rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S - rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, - RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, - RTC_FREQ_DIV512, RTC_FREQ_DIV256 - rtc_tamper_precharge_enable: DISABLE, ENABLE - rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C - rtc_tamper_with_timestamp: DISABLE, ENABLE - \param[out] none - \retval none -*/ -void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); - - /* tamper filter must be used when the tamper source is voltage level detection */ - RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; - - /* the tamper source is voltage level detection */ - if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE) { - RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); - - /* check if the tamper pin need precharge, if need, then configure the precharge time */ - if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable) { - RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; - } else { - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); - } - - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); - } - RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; - - if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp) { - /* the tamper event also cause a time-stamp event */ - RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; - } - /* configure the tamper trigger */ - RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); - if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger) { - RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS); - } - /* enable tamper */ - RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); -} - -/*! - \brief disable RTC tamper - \param[in] source: specify which tamper source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_TAMPER0 - \arg RTC_TAMPER1 - \param[out] none - \retval none -*/ -void rtc_tamper_disable(uint32_t source) -{ - /* disable tamper */ - RTC_TAMP &= (uint32_t)~source; - -} - -/*! - \brief enable specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be enabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_enable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enable the interrupts in RTC_CTL register */ - RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* enable the interrupts in RTC_TAMP register */ - RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disble specified RTC interrupt - \param[in] interrupt: specify which interrupt source to be disabled - only one parameter can be selected which is shown as below: - \arg RTC_INT_TIMESTAMP: timestamp interrupt - \arg RTC_INT_ALARM: alarm interrupt - \arg RTC_INT_TAMP: tamp interrupt - \param[out] none - \retval none -*/ -void rtc_interrupt_disable(uint32_t interrupt) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* disable the interrupts in RTC_CTL register */ - RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); - /* disable the interrupts in RTC_TAMP register */ - RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief check specified flag - \param[in] flag: specify which flag to check - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_RECALIBRATION: recalibration pending flag - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_INIT: init mode event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \arg RTC_FLAG_YCM: year parameter configured event flag - \arg RTC_FLAG_SHIFT: shift operation pending flag - \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus rtc_flag_get(uint32_t flag) -{ - FlagStatus flag_state = RESET; - - if((uint32_t)RESET != (RTC_STAT & flag)) { - flag_state = SET; - } - return flag_state; -} - -/*! - \brief clear specified flag - \param[in] flag: specify which flag to clear - only one parameter can be selected which is shown as below: - \arg RTC_FLAG_TAMP1: tamper 1 event flag - \arg RTC_FLAG_TAMP0: tamper 0 event flag - \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag - \arg RTC_FLAG_TIMESTAMP: time-stamp event flag - \arg RTC_FLAG_ALARM0: alarm event flag - \arg RTC_FLAG_RSYN: time and date registers synchronized event flag - \param[out] none - \retval none -*/ -void rtc_flag_clear(uint32_t flag) -{ - RTC_STAT &= (uint32_t)(~flag); -} - -/*! - \brief configure rtc alternate output source - \param[in] source: specify signal to output - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_512HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_CALIBRATION_1HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC - is the default value, output 512Hz signal - \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high - \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low - \param[in] mode: specify the output pin (PC13) mode when output alarm signal - only one parameter can be selected which is shown as below: - \arg RTC_ALARM_OUTPUT_OD: open drain mode - \arg RTC_ALARM_OUTPUT_PP: push pull mode - \param[out] none - \retval none -*/ -void rtc_alter_output_config(uint32_t source, uint32_t mode) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); - - RTC_CTL |= (uint32_t)(source); - - /* alarm output */ - if((uint32_t)RESET != (source & RTC_OS_ENABLE)) { - RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); - RTC_TAMP |= (uint32_t)(mode); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief configure RTC calibration register - \param[in] window: select calibration window - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz - \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz - \param[in] plus: add RTC clock or not - only one parameter can be selected which is shown as below: - \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock - \arg RTC_CALIBRATION_PLUS_RESET: no effect - \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) -{ - uint32_t time_index = RTC_HRFC_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a calibration operation is ongoing */ - do { - flag_status = RTC_STAT & RTC_STAT_SCPF; - } while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); - - if((uint32_t)RESET == flag_status) { - RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); - error_status = SUCCESS; - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief adjust the daylight saving time by adding or substracting one hour from the current time - \param[in] operation: hour ajustment operation - only one parameter can be selected which is shown as below: - \arg RTC_CTL_A1H: add one hour - \arg RTC_CTL_S1H: substract one hour - \param[out] none - \retval none -*/ -void rtc_hour_adjust(uint32_t operation) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint32_t)(operation); - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief adjust RTC second or subsecond value of current time - \param[in] add: add 1s to current time or not - only one parameter can be selected which is shown as below: - \arg RTC_SHIFT_ADD1S_RESET: no effect - \arg RTC_SHIFT_ADD1S_SET: add 1s to current time - \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) -{ - uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; - ErrStatus error_status = ERROR; - uint32_t flag_status = RESET; - uint32_t temp = 0U; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* check if a shift operation is ongoing */ - do { - flag_status = RTC_STAT & RTC_STAT_SOPF; - } while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); - - temp = RTC_CTL & RTC_CTL_REFEN; - /* check if the function of reference clock detection is disabled */ - if(((uint32_t)RESET == flag_status) && (RESET == temp)) { - RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); - error_status = rtc_register_sync_wait(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief enable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_enable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief disable RTC bypass shadow registers function - \param[in] none - \param[out] none - \retval none -*/ -void rtc_bypass_shadow_disable(void) -{ - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; -} - -/*! - \brief enable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_enable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status) { - RTC_CTL |= (uint32_t)RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} - -/*! - \brief disable RTC reference clock detection function - \param[in] none - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus rtc_refclock_detection_disable(void) -{ - ErrStatus error_status = ERROR; - - /* disable the write protection */ - RTC_WPK = RTC_UNLOCK_KEY1; - RTC_WPK = RTC_UNLOCK_KEY2; - - /* enter init mode */ - error_status = rtc_init_mode_enter(); - - if(ERROR != error_status) { - RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; - /* exit init mode */ - rtc_init_mode_exit(); - } - - /* enable the write protection */ - RTC_WPK = RTC_LOCK_KEY; - - return error_status; -} +/*! + \file gd32e23x_rtc.c + \brief RTC driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_rtc.h" + +/*! + \brief reset most of the RTC registers + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_deinit(void) +{ + ErrStatus error_status = ERROR; + + /* RTC_TAMP register is not under write protection */ + RTC_TAMP = RTC_REGISTER_RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* reset RTC_CTL register, this can be done without the init mode */ + RTC_CTL &= RTC_REGISTER_RESET; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + /* before reset RTC_TIME and RTC_DATE, BPSHAD bit in RTC_CTL should be reset as the condition. + in order to read calendar from shadow register, not the real registers being reset */ + RTC_TIME = RTC_REGISTER_RESET; + RTC_DATE = RTC_DATE_RESET; + + RTC_PSC = RTC_PSC_RESET; + + /* reset RTC_STAT register, also exit init mode. + at the same time, RTC_STAT_SOPF bit is reset, as the condition to reset RTC_SHIFTCTL register later */ + RTC_STAT = RTC_STAT_RESET; + + /* to write RTC_ALRM0SS register, ALRM0EN bit in RTC_CTL register should be reset as the condition */ + RTC_ALRM0TD = RTC_REGISTER_RESET; + RTC_ALRM0SS = RTC_REGISTER_RESET; + + /* reset RTC_SHIFTCTL and RTC_HRFC register, this can be done without the init mode */ + RTC_SHIFTCTL = RTC_REGISTER_RESET; + RTC_HRFC = RTC_REGISTER_RESET; + + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief initialize RTC registers + \param[in] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init(rtc_parameter_struct *rtc_initpara_struct) +{ + ErrStatus error_status = ERROR; + uint32_t reg_time = 0x00U, reg_date = 0x00U; + + reg_date = (DATE_YR(rtc_initpara_struct->rtc_year) | \ + DATE_DOW(rtc_initpara_struct->rtc_day_of_week) | \ + DATE_MON(rtc_initpara_struct->rtc_month) | \ + DATE_DAY(rtc_initpara_struct->rtc_date)); + + reg_time = (rtc_initpara_struct->rtc_am_pm | \ + TIME_HR(rtc_initpara_struct->rtc_hour) | \ + TIME_MN(rtc_initpara_struct->rtc_minute) | \ + TIME_SC(rtc_initpara_struct->rtc_second)); + + /* 1st: disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* 2nd: enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_PSC = (uint32_t)(PSC_FACTOR_A(rtc_initpara_struct->rtc_factor_asyn) | \ + PSC_FACTOR_S(rtc_initpara_struct->rtc_factor_syn)); + + RTC_TIME = (uint32_t)reg_time; + RTC_DATE = (uint32_t)reg_date; + + RTC_CTL &= (uint32_t)(~RTC_CTL_CS); + RTC_CTL |= rtc_initpara_struct->rtc_display_format; + + /* 3rd: exit init mode */ + rtc_init_mode_exit(); + + /* 4th: wait the RSYNF flag to set */ + error_status = rtc_register_sync_wait(); + } + + /* 5th: enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enter RTC init mode + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_init_mode_enter(void) +{ + uint32_t time_index = RTC_INITM_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + /* check whether it has been in init mode */ + if((uint32_t)RESET == (RTC_STAT & RTC_STAT_INITF)) { + RTC_STAT |= RTC_STAT_INITM; + + /* wait until the INITF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_INITF; + } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + } else { + error_status = SUCCESS; + } + return error_status; +} + +/*! + \brief exit RTC init mode + \param[in] none + \param[out] none + \retval none +*/ +void rtc_init_mode_exit(void) +{ + RTC_STAT &= (uint32_t)(~RTC_STAT_INITM); +} + +/*! + \brief wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow + registers are updated + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_register_sync_wait(void) +{ + volatile uint32_t time_index = RTC_RSYNF_TIMEOUT; + uint32_t flag_status = RESET; + ErrStatus error_status = ERROR; + + if((uint32_t)RESET == (RTC_CTL & RTC_CTL_BPSHAD)) { + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* firstly clear RSYNF flag */ + RTC_STAT &= (uint32_t)(~RTC_STAT_RSYNF); + + /* wait until RSYNF flag to be set */ + do { + flag_status = RTC_STAT & RTC_STAT_RSYNF; + } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + } else { + error_status = SUCCESS; + } + + return error_status; +} + +/*! + \brief get current time and date + \param[in] none + \param[out] rtc_initpara_struct: pointer to a rtc_parameter_struct structure which contains + parameters for initialization of the rtc peripheral + members of the structure and the member values are shown as below: + rtc_year: 0x0 - 0x99(BCD format) + rtc_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_date: 0x1 - 0x31(BCD format) + rtc_day_of_week: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY + RTC_FRIDAY, RTC_SATURDAY, RTC_SUNDAY + rtc_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format chose + rtc_minute: 0x0 - 0x59(BCD format) + rtc_second: 0x0 - 0x59(BCD format) + rtc_factor_asyn: 0x0 - 0x7F + rtc_factor_syn: 0x0 - 0x7FFF + rtc_am_pm: RTC_AM, RTC_PM + rtc_display_format: RTC_24HOUR, RTC_12HOUR + \retval none +*/ +void rtc_current_time_get(rtc_parameter_struct *rtc_initpara_struct) +{ + uint32_t temp_tr = 0x00U, temp_dr = 0x00U, temp_pscr = 0x00U, temp_ctlr = 0x00U; + + temp_tr = (uint32_t)RTC_TIME; + temp_dr = (uint32_t)RTC_DATE; + temp_pscr = (uint32_t)RTC_PSC; + temp_ctlr = (uint32_t)RTC_CTL; + + /* get current time and construct rtc_parameter_struct structure */ + rtc_initpara_struct->rtc_year = (uint8_t)GET_DATE_YR(temp_dr); + rtc_initpara_struct->rtc_month = (uint8_t)GET_DATE_MON(temp_dr); + rtc_initpara_struct->rtc_date = (uint8_t)GET_DATE_DAY(temp_dr); + rtc_initpara_struct->rtc_day_of_week = (uint8_t)GET_DATE_DOW(temp_dr); + rtc_initpara_struct->rtc_hour = (uint8_t)GET_TIME_HR(temp_tr); + rtc_initpara_struct->rtc_minute = (uint8_t)GET_TIME_MN(temp_tr); + rtc_initpara_struct->rtc_second = (uint8_t)GET_TIME_SC(temp_tr); + rtc_initpara_struct->rtc_factor_asyn = (uint16_t)GET_PSC_FACTOR_A(temp_pscr); + rtc_initpara_struct->rtc_factor_syn = (uint16_t)GET_PSC_FACTOR_S(temp_pscr); + rtc_initpara_struct->rtc_am_pm = (uint32_t)(temp_tr & RTC_TIME_PM); + rtc_initpara_struct->rtc_display_format = (uint32_t)(temp_ctlr & RTC_CTL_CS); +} + +/*! + \brief get current subsecond value + \param[in] none + \param[out] none + \retval current subsecond value +*/ +uint32_t rtc_subsecond_get(void) +{ + uint32_t reg = 0x00U; + /* if BPSHAD bit is reset, reading RTC_SS will lock RTC_TIME and RTC_DATE automatically */ + reg = (uint32_t)RTC_SS; + /* read RTC_DATE to unlock the 3 shadow registers */ + (void)(RTC_DATE); + + return reg; +} + +/*! + \brief configure RTC alarm + \param[in] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \param[out] none + \retval none +*/ +void rtc_alarm_config(rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + reg_alrm0td = (rtc_alarm_time->rtc_alarm_mask | \ + rtc_alarm_time->rtc_weekday_or_date | \ + rtc_alarm_time->rtc_am_pm | \ + ALRM0TD_DAY(rtc_alarm_time->rtc_alarm_day) | \ + ALRM0TD_HR(rtc_alarm_time->rtc_alarm_hour) | \ + ALRM0TD_MN(rtc_alarm_time->rtc_alarm_minute) | \ + ALRM0TD_SC(rtc_alarm_time->rtc_alarm_second)); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0TD = (uint32_t)reg_alrm0td; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure subsecond of RTC alarm + \param[in] mask_subsecond: alarm subsecond mask + only one parameter can be selected which is shown as below: + \arg RTC_MASKSSC_0_14: mask alarm subsecond configuration + \arg RTC_MASKSSC_1_14: mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared + \arg RTC_MASKSSC_2_14: mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared + \arg RTC_MASKSSC_3_14: mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared + \arg RTC_MASKSSC_4_14: mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared + \arg RTC_MASKSSC_5_14: mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared + \arg RTC_MASKSSC_6_14: mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared + \arg RTC_MASKSSC_7_14: mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared + \arg RTC_MASKSSC_8_14: mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared + \arg RTC_MASKSSC_9_14: mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared + \arg RTC_MASKSSC_10_14: mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared + \arg RTC_MASKSSC_11_14: mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared + \arg RTC_MASKSSC_12_14: mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared + \arg RTC_MASKSSC_13_14: mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared + \arg RTC_MASKSSC_14: mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared + \arg RTC_MASKSSC_NONE: mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared + \param[in] subsecond: alarm subsecond value(0x000 - 0x7FFF) + \param[out] none + \retval none +*/ +void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_ALRM0SS = mask_subsecond | subsecond; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC alarm + \param[in] none + \param[out] none + \retval none +*/ +void rtc_alarm_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= RTC_CTL_ALRM0EN; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC alarm + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_alarm_disable(void) +{ + volatile uint32_t time_index = RTC_ALRM0WF_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the state of alarm */ + RTC_CTL &= (uint32_t)(~RTC_CTL_ALRM0EN); + + /* wait until ALRM0WF flag to be set after the alarm is disabled */ + do { + flag_status = RTC_STAT & RTC_STAT_ALRM0WF; + } while((--time_index > 0x00U) && ((uint32_t)RESET == flag_status)); + + if((uint32_t)RESET != flag_status) { + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief get RTC alarm + \param[in] none + \param[out] rtc_alarm_time: pointer to a rtc_alarm_struct structure which contains + parameters for RTC alarm configuration + members of the structure and the member values are shown as below: + rtc_alarm_mask: RTC_ALARM_NONE_MASK, RTC_ALARM_DATE_MASK, RTC_ALARM_HOUR_MASK + RTC_ALARM_MINUTE_MASK, RTC_ALARM_SECOND_MASK, RTC_ALARM_ALL_MASK + rtc_weekday_or_date: RTC_ALARM_DATE_SELECTED, RTC_ALARM_WEEKDAY_SELECTED + rtc_alarm_day: 1) 0x1 - 0x31(BCD format) if RTC_ALARM_DATE_SELECTED is set + 2) RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_alarm_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_alarm_minute: 0x0 - 0x59(BCD format) + rtc_alarm_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_alarm_get(rtc_alarm_struct *rtc_alarm_time) +{ + uint32_t reg_alrm0td = 0x00U; + + /* get the value of RTC_ALRM0TD register */ + reg_alrm0td = RTC_ALRM0TD; + + /* get alarm parameters and construct the rtc_alarm_struct structure */ + rtc_alarm_time->rtc_alarm_mask = reg_alrm0td & RTC_ALARM_ALL_MASK; + rtc_alarm_time->rtc_am_pm = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_PM); + rtc_alarm_time->rtc_weekday_or_date = (uint32_t)(reg_alrm0td & RTC_ALRM0TD_DOWS); + rtc_alarm_time->rtc_alarm_day = (uint8_t)GET_ALRM0TD_DAY(reg_alrm0td); + rtc_alarm_time->rtc_alarm_hour = (uint8_t)GET_ALRM0TD_HR(reg_alrm0td); + rtc_alarm_time->rtc_alarm_minute = (uint8_t)GET_ALRM0TD_MN(reg_alrm0td); + rtc_alarm_time->rtc_alarm_second = (uint8_t)GET_ALRM0TD_SC(reg_alrm0td); +} + +/*! + \brief get RTC alarm subsecond + \param[in] none + \param[out] none + \retval RTC alarm subsecond value +*/ +uint32_t rtc_alarm_subsecond_get(void) +{ + return ((uint32_t)(RTC_ALRM0SS & RTC_ALRM0SS_SSC)); +} + +/*! + \brief enable RTC time-stamp + \param[in] edge: specify which edge to detect of time-stamp + only one parameter can be selected which is shown as below: + \arg RTC_TIMESTAMP_RISING_EDGE: rising edge is valid event edge for timestamp event + \arg RTC_TIMESTAMP_FALLING_EDGE: falling edge is valid event edge for timestamp event + \param[out] none + \retval none +*/ +void rtc_timestamp_enable(uint32_t edge) +{ + uint32_t reg_ctl = 0x00U; + + /* clear the bits to be configured in RTC_CTL */ + reg_ctl = (uint32_t)(RTC_CTL & (uint32_t)(~(RTC_CTL_TSEG | RTC_CTL_TSEN))); + + /* new configuration */ + reg_ctl |= (uint32_t)(edge | RTC_CTL_TSEN); + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL = (uint32_t)reg_ctl; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC time-stamp + \param[in] none + \param[out] none + \retval none +*/ +void rtc_timestamp_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* clear the TSEN bit */ + RTC_CTL &= (uint32_t)(~ RTC_CTL_TSEN); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief get RTC timestamp time and date + \param[in] none + \param[out] rtc_timestamp: pointer to a rtc_timestamp_struct structure which contains + parameters for RTC time-stamp configuration + members of the structure and the member values are shown as below: + rtc_timestamp_month: RTC_JAN, RTC_FEB, RTC_MAR, RTC_APR, RTC_MAY, RTC_JUN, + RTC_JUL, RTC_AUG, RTC_SEP, RTC_OCT, RTC_NOV, RTC_DEC + rtc_timestamp_date: 0x1 - 0x31(BCD format) + rtc_timestamp_day: RTC_MONDAY, RTC_TUESDAY, RTC_WEDSDAY, RTC_THURSDAY, RTC_FRIDAY, + RTC_SATURDAY, RTC_SUNDAY if RTC_ALARM_WEEKDAY_SELECTED is set + rtc_timestamp_hour: 0x0 - 0x12(BCD format) or 0x0 - 0x23(BCD format) depending on the rtc_display_format + rtc_timestamp_minute: 0x0 - 0x59(BCD format) + rtc_timestamp_second: 0x0 - 0x59(BCD format) + rtc_am_pm: RTC_AM, RTC_PM + \retval none +*/ +void rtc_timestamp_get(rtc_timestamp_struct *rtc_timestamp) +{ + uint32_t temp_tts = 0x00U, temp_dts = 0x00U; + + /* get the value of time_stamp registers */ + temp_tts = (uint32_t)RTC_TTS; + temp_dts = (uint32_t)RTC_DTS; + + /* get timestamp time and construct the rtc_timestamp_struct structure */ + rtc_timestamp->rtc_am_pm = (uint32_t)(temp_tts & RTC_TTS_PM); + rtc_timestamp->rtc_timestamp_month = (uint8_t)GET_DTS_MON(temp_dts); + rtc_timestamp->rtc_timestamp_date = (uint8_t)GET_DTS_DAY(temp_dts); + rtc_timestamp->rtc_timestamp_day = (uint8_t)GET_DTS_DOW(temp_dts); + rtc_timestamp->rtc_timestamp_hour = (uint8_t)GET_TTS_HR(temp_tts); + rtc_timestamp->rtc_timestamp_minute = (uint8_t)GET_TTS_MN(temp_tts); + rtc_timestamp->rtc_timestamp_second = (uint8_t)GET_TTS_SC(temp_tts); +} + +/*! + \brief get RTC time-stamp subsecond + \param[in] none + \param[out] none + \retval RTC time-stamp subsecond value +*/ +uint32_t rtc_timestamp_subsecond_get(void) +{ + return ((uint32_t)RTC_SSTS); +} + + +/*! + \brief enable RTC tamper + \param[in] rtc_tamper: pointer to a rtc_tamper_struct structure which contains + parameters for RTC tamper configuration + members of the structure and the member values are shown as below: + rtc_tamper_source: RTC_TAMPER0, RTC_TAMPER1 + rtc_tamper_trigger: RTC_TAMPER_TRIGGER_EDGE_RISING, RTC_TAMPER_TRIGGER_EDGE_FALLING + RTC_TAMPER_TRIGGER_LEVEL_LOW, RTC_TAMPER_TRIGGER_LEVEL_HIGH + rtc_tamper_filter: RTC_FLT_EDGE, RTC_FLT_2S, RTC_FLT_4S, RTC_FLT_8S + rtc_tamper_sample_frequency: RTC_FREQ_DIV32768, RTC_FREQ_DIV16384, RTC_FREQ_DIV8192, + RTC_FREQ_DIV4096, RTC_FREQ_DIV2048, RTC_FREQ_DIV1024, + RTC_FREQ_DIV512, RTC_FREQ_DIV256 + rtc_tamper_precharge_enable: DISABLE, ENABLE + rtc_tamper_precharge_time: RTC_PRCH_1C, RTC_PRCH_2C, RTC_PRCH_4C, RTC_PRCH_8C + rtc_tamper_with_timestamp: DISABLE, ENABLE + \param[out] none + \retval none +*/ +void rtc_tamper_enable(rtc_tamper_struct *rtc_tamper) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~(rtc_tamper->rtc_tamper_source); + + /* tamper filter must be used when the tamper source is voltage level detection */ + RTC_TAMP &= (uint32_t)~RTC_TAMP_FLT; + + /* the tamper source is voltage level detection */ + if(rtc_tamper->rtc_tamper_filter != RTC_FLT_EDGE) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_DISPU | RTC_TAMP_PRCH | RTC_TAMP_FREQ | RTC_TAMP_FLT); + + /* check if the tamper pin need precharge, if need, then configure the precharge time */ + if(DISABLE == rtc_tamper->rtc_tamper_precharge_enable) { + RTC_TAMP |= (uint32_t)RTC_TAMP_DISPU; + } else { + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_precharge_time); + } + + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_sample_frequency); + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_filter); + } + RTC_TAMP &= (uint32_t)~RTC_TAMP_TPTS; + + if(DISABLE != rtc_tamper->rtc_tamper_with_timestamp) { + /* the tamper event also cause a time-stamp event */ + RTC_TAMP |= (uint32_t)RTC_TAMP_TPTS; + } + /* configure the tamper trigger */ + RTC_TAMP &= ((uint32_t)~((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS)); + if(RTC_TAMPER_TRIGGER_EDGE_RISING != rtc_tamper->rtc_tamper_trigger) { + RTC_TAMP |= (uint32_t)((rtc_tamper->rtc_tamper_source) << RTC_TAMPER_TRIGGER_POS); + } + /* enable tamper */ + RTC_TAMP |= (uint32_t)(rtc_tamper->rtc_tamper_source); +} + +/*! + \brief disable RTC tamper + \param[in] source: specify which tamper source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_TAMPER0 + \arg RTC_TAMPER1 + \param[out] none + \retval none +*/ +void rtc_tamper_disable(uint32_t source) +{ + /* disable tamper */ + RTC_TAMP &= (uint32_t)~source; + +} + +/*! + \brief enable specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be enabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_enable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enable the interrupts in RTC_CTL register */ + RTC_CTL |= (uint32_t)(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* enable the interrupts in RTC_TAMP register */ + RTC_TAMP |= (uint32_t)(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disble specified RTC interrupt + \param[in] interrupt: specify which interrupt source to be disabled + only one parameter can be selected which is shown as below: + \arg RTC_INT_TIMESTAMP: timestamp interrupt + \arg RTC_INT_ALARM: alarm interrupt + \arg RTC_INT_TAMP: tamp interrupt + \param[out] none + \retval none +*/ +void rtc_interrupt_disable(uint32_t interrupt) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* disable the interrupts in RTC_CTL register */ + RTC_CTL &= (uint32_t)~(interrupt & (uint32_t)~RTC_TAMP_TPIE); + /* disable the interrupts in RTC_TAMP register */ + RTC_TAMP &= (uint32_t)~(interrupt & RTC_TAMP_TPIE); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief check specified flag + \param[in] flag: specify which flag to check + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_RECALIBRATION: recalibration pending flag + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_INIT: init mode event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \arg RTC_FLAG_YCM: year parameter configured event flag + \arg RTC_FLAG_SHIFT: shift operation pending flag + \arg RTC_FLAG_ALARM0_WRITTEN: alarm writen available flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus rtc_flag_get(uint32_t flag) +{ + FlagStatus flag_state = RESET; + + if((uint32_t)RESET != (RTC_STAT & flag)) { + flag_state = SET; + } + return flag_state; +} + +/*! + \brief clear specified flag + \param[in] flag: specify which flag to clear + only one parameter can be selected which is shown as below: + \arg RTC_FLAG_TAMP1: tamper 1 event flag + \arg RTC_FLAG_TAMP0: tamper 0 event flag + \arg RTC_FLAG_TIMESTAMP_OVERFLOW: time-stamp overflow event flag + \arg RTC_FLAG_TIMESTAMP: time-stamp event flag + \arg RTC_FLAG_ALARM0: alarm event flag + \arg RTC_FLAG_RSYN: time and date registers synchronized event flag + \param[out] none + \retval none +*/ +void rtc_flag_clear(uint32_t flag) +{ + RTC_STAT &= (uint32_t)(~flag); +} + +/*! + \brief configure rtc alternate output source + \param[in] source: specify signal to output + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_512HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_CALIBRATION_1HZ: when the LXTAL freqency is 32768Hz and the RTC_PSC + is the default value, output 512Hz signal + \arg RTC_ALARM_HIGH: when the alarm flag is set, the output pin is high + \arg RTC_ALARM_LOW: when the Alarm flag is set, the output pin is low + \param[in] mode: specify the output pin (PC13) mode when output alarm signal + only one parameter can be selected which is shown as below: + \arg RTC_ALARM_OUTPUT_OD: open drain mode + \arg RTC_ALARM_OUTPUT_PP: push pull mode + \param[out] none + \retval none +*/ +void rtc_alter_output_config(uint32_t source, uint32_t mode) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint32_t)~(RTC_CTL_COEN | RTC_CTL_OS | RTC_CTL_OPOL | RTC_CTL_COS); + + RTC_CTL |= (uint32_t)(source); + + /* alarm output */ + if((uint32_t)RESET != (source & RTC_OS_ENABLE)) { + RTC_TAMP &= (uint32_t)~(RTC_TAMP_PC13VAL); + RTC_TAMP |= (uint32_t)(mode); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief configure RTC calibration register + \param[in] window: select calibration window + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_WINDOW_32S: 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_16S: 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz + \arg RTC_CALIBRATION_WINDOW_8S: 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz + \param[in] plus: add RTC clock or not + only one parameter can be selected which is shown as below: + \arg RTC_CALIBRATION_PLUS_SET: add one RTC clock every 2048 rtc clock + \arg RTC_CALIBRATION_PLUS_RESET: no effect + \param[in] minus: the RTC clock to minus during the calibration window(0x0 - 0x1FF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus) +{ + uint32_t time_index = RTC_HRFC_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a calibration operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SCPF; + } while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); + + if((uint32_t)RESET == flag_status) { + RTC_HRFC = (uint32_t)(window | plus | HRFC_CMSK(minus)); + error_status = SUCCESS; + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief adjust the daylight saving time by adding or substracting one hour from the current time + \param[in] operation: hour ajustment operation + only one parameter can be selected which is shown as below: + \arg RTC_CTL_A1H: add one hour + \arg RTC_CTL_S1H: substract one hour + \param[out] none + \retval none +*/ +void rtc_hour_adjust(uint32_t operation) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint32_t)(operation); + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief adjust RTC second or subsecond value of current time + \param[in] add: add 1s to current time or not + only one parameter can be selected which is shown as below: + \arg RTC_SHIFT_ADD1S_RESET: no effect + \arg RTC_SHIFT_ADD1S_SET: add 1s to current time + \param[in] minus: number of subsecond to minus from current time(0x0 - 0x7FFF) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus) +{ + uint32_t time_index = RTC_SHIFTCTL_TIMEOUT; + ErrStatus error_status = ERROR; + uint32_t flag_status = RESET; + uint32_t temp = 0U; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* check if a shift operation is ongoing */ + do { + flag_status = RTC_STAT & RTC_STAT_SOPF; + } while((--time_index > 0x00U) && ((uint32_t)RESET != flag_status)); + + temp = RTC_CTL & RTC_CTL_REFEN; + /* check if the function of reference clock detection is disabled */ + if(((uint32_t)RESET == flag_status) && (RESET == temp)) { + RTC_SHIFTCTL = (uint32_t)(add | SHIFTCTL_SFS(minus)); + error_status = rtc_register_sync_wait(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief enable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_enable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL |= (uint8_t)RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief disable RTC bypass shadow registers function + \param[in] none + \param[out] none + \retval none +*/ +void rtc_bypass_shadow_disable(void) +{ + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + RTC_CTL &= (uint8_t)~RTC_CTL_BPSHAD; + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; +} + +/*! + \brief enable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_enable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL |= (uint32_t)RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} + +/*! + \brief disable RTC reference clock detection function + \param[in] none + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus rtc_refclock_detection_disable(void) +{ + ErrStatus error_status = ERROR; + + /* disable the write protection */ + RTC_WPK = RTC_UNLOCK_KEY1; + RTC_WPK = RTC_UNLOCK_KEY2; + + /* enter init mode */ + error_status = rtc_init_mode_enter(); + + if(ERROR != error_status) { + RTC_CTL &= (uint32_t)~RTC_CTL_REFEN; + /* exit init mode */ + rtc_init_mode_exit(); + } + + /* enable the write protection */ + RTC_WPK = RTC_LOCK_KEY; + + return error_status; +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c index 1528aa7..6d0adc8 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_spi.c @@ -1,965 +1,965 @@ -/*! - \file gd32e23x_spi.c - \brief SPI driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_spi.h" - -/* SPI/I2S parameter initialization mask */ -#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI0 parameter initialization mask */ -#define SPI_FIFO_INIT_MASK1 ((uint32_t)0x00003840U) /*!< SPI1 parameter initialization mask1 */ -#define SPI_FIFO_INIT_MASK2 ((uint32_t)0x0000F0FFU) /*!< SPI1 parameter initialization mask2*/ -#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ - -#define SPI_FRAMESIZE_MASK ((uint32_t)0x00000800U) /*!< SPI0 frame size mask */ -#define SPI_BYTEN_MASK ((uint32_t)0x00001000U) /*!< SPI1 access to FIFO mask */ -#define SPI_TXLVL_EMPTY_MASK ((uint32_t)0x00001800U) /*!< SPI1 TXFIFO empty mask */ -#define SPI_RXLVL_EMPTY_MASK ((uint32_t)0x00000600U) /*!< SPI1 RXFIFO empty mask */ - -/* I2S clock source selection, multiplication and division mask */ -#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U) /*!< I2S clock prescaler register reset value */ - -/*! - \brief reset SPI and I2S - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_i2s_deinit(uint32_t spi_periph) -{ - switch(spi_periph) { - case SPI0: - /* reset SPI0 and I2S0 */ - rcu_periph_reset_enable(RCU_SPI0RST); - rcu_periph_reset_disable(RCU_SPI0RST); - break; - case SPI1: - /* reset SPI1 */ - rcu_periph_reset_enable(RCU_SPI1RST); - rcu_periph_reset_disable(RCU_SPI1RST); - break; - default : - break; - } -} - -/*! - \brief initialize the parameters of SPI structure with the default values - \param[in] none - \param[out] spi_parameter_struct: the initialized structure spi_parameter_struct pointer - \retval none -*/ -void spi_struct_para_init(spi_parameter_struct *spi_struct) -{ - /* configure the SPI structure with the default values */ - spi_struct->device_mode = SPI_SLAVE; - spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; - spi_struct->frame_size = SPI_FRAMESIZE_8BIT; - spi_struct->nss = SPI_NSS_HARD; - spi_struct->endian = SPI_ENDIAN_MSB; - spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; - spi_struct->prescale = SPI_PSC_2; -} - -/*! - \brief initialize SPI parameters - \param[in] spi_periph: SPIx(x=0,1) - \param[in] spi_struct: SPI parameter initialization stuct members of the structure - and the member values are shown as below: - device_mode: SPI_MASTER, SPI_SLAVE - trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, - SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT - frame_size: SPI_FRAMESIZE_4BIT, SPI_FRAMESIZE_5BIT - SPI_FRAMESIZE_6BIT, SPI_FRAMESIZE_7BIT - SPI_FRAMESIZE_8BIT, SPI_FRAMESIZE_9BIT - SPI_FRAMESIZE_10BIT, SPI_FRAMESIZE_11BIT - SPI_FRAMESIZE_12BIT, SPI_FRAMESIZE_13BIT - SPI_FRAMESIZE_14BIT, SPI_FRAMESIZE_15BIT - SPI_FRAMESIZE_16BIT - nss: SPI_NSS_SOFT, SPI_NSS_HARD - endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB - clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE - SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE - prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) -{ - uint32_t reg1 = 0U, reg2 = 0U, reg3 = 0U; - - reg1 = SPI_CTL0(spi_periph); - reg1 &= SPI_INIT_MASK; - - reg2 = SPI_CTL0(spi_periph); - reg2 &= SPI_FIFO_INIT_MASK1; - - reg3 = SPI_CTL1(spi_periph); - reg3 &= SPI_FIFO_INIT_MASK2; - - if(SPI0 == spi_periph) { - /* select SPI as master or slave */ - reg1 |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg1 |= spi_struct->trans_mode; - /* select SPI NSS use hardware or software */ - reg1 |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg1 |= spi_struct->endian; - /* select SPI polarity and phase */ - reg1 |= spi_struct->clock_polarity_phase; - /* select SPI prescaler to adjust transmit speed */ - reg1 |= spi_struct->prescale; - /* select SPI frame size */ - /* check SPI0 frame size is 8bits/16bits or not*/ - if((SPI_FRAMESIZE_8BIT != spi_struct->frame_size) && (SPI_FRAMESIZE_16BIT != spi_struct->frame_size)) { - return ERROR; - } else { - reg1 |= (spi_struct->frame_size & SPI_FRAMESIZE_MASK); - } - - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg1; - - } else { - /* select SPI as master or slave */ - reg2 |= spi_struct->device_mode; - /* select SPI transfer mode */ - reg2 |= spi_struct->trans_mode; - /* select SPI NSS use hardware or software */ - reg2 |= spi_struct->nss; - /* select SPI LSB or MSB */ - reg2 |= spi_struct->endian; - /* select SPI polarity and phase */ - reg2 |= spi_struct->clock_polarity_phase; - /* select SPI prescaler to adjust transmit speed */ - reg2 |= spi_struct->prescale; - /* write to SPI_CTL0 register */ - SPI_CTL0(spi_periph) = (uint32_t)reg2; - - /* select SPI data size */ - reg3 |= spi_struct->frame_size; - /* write to SPI_CTL0 register */ - SPI_CTL1(spi_periph) = (uint32_t)reg3; - } - - /* select SPI mode */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); - - return SUCCESS; -} - -/*! - \brief enable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_enable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; -} - -/*! - \brief disable SPI - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_disable(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); -} - -/*! - \brief initialize I2S parameters - \param[in] spi_periph: SPIx(x=0) - \param[in] mode: I2S operation mode - only one parameter can be selected which is shown as below: - \arg I2S_MODE_SLAVETX: I2S slave transmit mode - \arg I2S_MODE_SLAVERX: I2S slave receive mode - \arg I2S_MODE_MASTERTX: I2S master transmit mode - \arg I2S_MODE_MASTERRX: I2S master receive mode - \param[in] standard: I2S standard - only one parameter can be selected which is shown as below: - \arg I2S_STD_PHILIPS: I2S phillips standard - \arg I2S_STD_MSB: I2S MSB standard - \arg I2S_STD_LSB: I2S LSB standard - \arg I2S_STD_PCMSHORT: I2S PCM short standard - \arg I2S_STD_PCMLONG: I2S PCM long standard - \param[in] ckpl: I2S idle state clock polarity - only one parameter can be selected which is shown as below: - \arg I2S_CKPL_LOW: I2S clock polarity low level - \arg I2S_CKPL_HIGH: I2S clock polarity high level - \param[out] none - \retval none -*/ -void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) -{ - uint32_t reg = 0U; - reg = SPI_I2SCTL(spi_periph); - reg &= I2S_INIT_MASK; - - /* enable I2S mode */ - reg |= (uint32_t)SPI_I2SCTL_I2SSEL; - /* select I2S mode */ - reg |= (uint32_t)mode; - /* select I2S standard */ - reg |= (uint32_t)standard; - /* select I2S polarity */ - reg |= (uint32_t)ckpl; - - /* write to SPI_I2SCTL register */ - SPI_I2SCTL(spi_periph) = (uint32_t)reg; -} - -/*! - \brief configure I2S prescaler - \param[in] spi_periph: SPIx(x=0) - \param[in] audiosample: I2S audio sample rate - only one parameter can be selected which is shown as below: - \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz - \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz - \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz - \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz - \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz - \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz - \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz - \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz - \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz - \param[in] frameformat: I2S data length and channel length - only one parameter can be selected which is shown as below: - \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit - \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit - \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit - \param[in] mckout: I2S master clock output - only one parameter can be selected which is shown as below: - \arg I2S_MCKOUT_ENABLE: enable I2S master clock output - \arg I2S_MCKOUT_DISABLE: disable 2S master clock output - \param[out] none - \retval none -*/ -void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) -{ - uint32_t i2sdiv = 2U, i2sof = 0U; - uint32_t clks = 0U; - uint32_t i2sclock = 0U; - - /* deinitialize SPI_I2SPSC register */ - SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET; - - /* get system clock */ - i2sclock = rcu_clock_freq_get(CK_SYS); - - /* configure the prescaler depending on the mclk output state, the frame format and audio sample rate */ - if(I2S_MCKOUT_ENABLE == mckout) { - clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); - } else { - if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { - clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); - } else { - clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); - } - } - - /* remove the floating point */ - clks = (clks + 5U) / 10U; - i2sof = (clks & 0x00000001U); - i2sdiv = ((clks - i2sof) / 2U); - i2sof = (i2sof << 8U); - - /* set the default values */ - if((i2sdiv < 2U) || (i2sdiv > 255U)) { - i2sdiv = 2U; - i2sof = 0U; - } - - /* configure SPI_I2SPSC */ - SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); - - /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); - - /* configure data frame format */ - SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; -} - - -/*! - \brief enable I2S - \param[in] spi_periph: SPIx(x=0) - \param[out] none - \retval none -*/ -void i2s_enable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; -} - -/*! - \brief disable I2S - \param[in] spi_periph: SPIx(x=0) - \param[out] none - \retval none -*/ -void i2s_disable(uint32_t spi_periph) -{ - SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); -} - -/*! - \brief enable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; -} - -/*! - \brief disable SPI NSS output - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_output_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); -} - -/*! - \brief SPI NSS pin high level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_high(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; -} - -/*! - \brief SPI NSS pin low level in software mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nss_internal_low(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); -} - -/*! - \brief enable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_enable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma) { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; - } else { - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; - } -} - -/*! - \brief disable SPI DMA send or receive - \param[in] spi_periph: SPIx(x=0,1) - \param[in] dma: SPI DMA mode - only one parameter can be selected which is shown as below: - \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA - \arg SPI_DMA_RECEIVE: SPI receive data using DMA - \param[out] none - \retval none -*/ -void spi_dma_disable(uint32_t spi_periph, uint8_t dma) -{ - if(SPI_DMA_TRANSMIT == dma) { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); - } else { - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); - } -} - -/*! - \brief configure SPI total number of data to be transmitted by DMA is odd or not - \param[in] spi_periph: SPIx(x=1) - \param[in] odd: odd bytes in TX DMA channel - only one parameter can be selected which is shown as below: - \arg SPI_TXDMA_EVEN: number of byte in TX DMA channel is even - \arg SPI_TXDMA_ODD: number of byte in TX DMA channel is odd - \param[out] none - \retval none -*/ -void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd) -{ - /* clear SPI_CTL1_TXDMA_ODD bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TXDMA_ODD); - /* configure SPI_CTL1_TXDMA_ODD bit */ - SPI_CTL1(spi_periph) |= (uint32_t)odd; -} - -/*! - \brief configure SPI total number of data to be received by DMA is odd or not - \param[in] spi_periph: SPIx(x=1) - \param[in] odd: odd bytes in RX DMA channel - only one parameter can be selected which is shown as below: - \arg SPI_RXDMA_EVEN: number of bytes in RX DMA channel is even - \arg SPI_RXDMA_ODD: number of bytes in RX DMA channel is odd - \param[out] none - \retval none -*/ -void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd) -{ - /* clear SPI_CTL1_RXDMA_ODD bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RXDMA_ODD); - /* configure SPI_CTL1_RXDMA_ODD bit */ - SPI_CTL1(spi_periph) |= (uint32_t)odd; -} - -/*! - \brief configure SPI data frame format - \param[in] spi_periph: SPIx(x=0,1) - \param[in] frame_format: SPI frame size - only one parameter can be selected which is shown as below: - \arg SPI_FRAMESIZE_xBIT(x=4,5..16, for SPI1, x=8,16, for SPI0):SPI frame size is x bits - \param[out] none - \retval ErrStatus: ERROR or SUCCESS -*/ -ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) -{ - uint32_t reg; - if(SPI0 == spi_periph) { - /* check SPI0 frame size is 8bits/16bits or not*/ - if((SPI_FRAMESIZE_8BIT != frame_format) && (SPI_FRAMESIZE_16BIT != frame_format)) { - return ERROR; - } else { - /* clear SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); - /* configure SPI_CTL0_FF16 bit */ - SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK); - } - } else { - reg = SPI_CTL1(spi_periph); - /* clear SPI_CTL1_DZ bits */ - reg &= (uint32_t)(~SPI_CTL1_DZ); - reg |= (uint32_t)frame_format; - /* configure SPI_CTL1_DZ bits */ - SPI_CTL1(spi_periph) = reg; - } - return SUCCESS; -} - -/*! - \brief configure SPI access size to FIFO(8-bit or 16-bit) - \param[in] spi_periph: SPIx(x=1) - \param[in] fifo_access_size: byte access enable - only one parameter can be selected which is shown as below: - \arg SPI_HALFWORD_ACCESS: half-word access to FIFO - \arg SPI_BYTE_ACCESS: byte access to FIFO - \param[out] none - \retval none -*/ -void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size) -{ - /* clear SPI_CTL1_BYTEN bit */ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_BYTEN); - /* confige SPI_CTL1_BYTEN bit */ - SPI_CTL1(spi_periph) |= (uint32_t)fifo_access_size; -} - -/*! - \brief configure SPI bidirectional transfer direction - \param[in] spi_periph: SPIx(x=0,1) - \param[in] transfer_direction: SPI transfer direction - only one parameter can be selected which is shown as below: - \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode - \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode - \param[out] none - \retval none -*/ -void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) -{ - if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { - /* set the transmit-only mode */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; - } else { - /* set the receive-only mode */ - SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; - } -} - -/*! - \brief SPI transmit data - \param[in] spi_periph: SPIx(x=0,1) - \param[in] data: 16-bit data - \param[out] none - \retval none -*/ -void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) -{ - uint32_t reg, byten; - if(SPI0 == spi_periph) { - SPI_DATA(spi_periph) = (uint32_t)data; - } else { - /* get the access size to FIFO */ - byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; - if(RESET != byten) { - reg = spi_periph + 0x0CU; - *(uint8_t *)(reg) = (uint8_t)data; - } else { - SPI_DATA(spi_periph) = (uint16_t)data; - } - } -} - -/*! - \brief SPI receive data - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit data -*/ -uint16_t spi_i2s_data_receive(uint32_t spi_periph) -{ - uint32_t reg, byten; - if(SPI0 == spi_periph) { - return ((uint16_t)SPI_DATA(spi_periph)); - } else { - /* get the access size to FIFO */ - byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; - if(RESET != byten) { - reg = spi_periph + 0x0CU; - return (uint16_t)(*(uint8_t *)(reg)); - } else { - return ((uint16_t)SPI_DATA(spi_periph)); - } - } -} - -/*! - \brief clear SPI/I2S format error flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] flag: SPI/I2S frame format error flag - \arg SPI_FLAG_FERR: only for SPI work in TI mode - \arg I2S_FLAG_FERR: for I2S - \param[out] none - \retval none -*/ -void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag) -{ - SPI_STAT(spi_periph) = (uint32_t)(~flag); -} - -/*! - \brief set SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc_poly: CRC polynomial value - \param[out] none - \retval none -*/ -void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) -{ - /* enable SPI CRC */ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; - /* set SPI CRC polynomial */ - SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; -} - -/*! - \brief get SPI CRC polynomial - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval 16-bit CRC polynomial -*/ -uint16_t spi_crc_polynomial_get(uint32_t spi_periph) -{ - return ((uint16_t)SPI_CRCPOLY(spi_periph)); -} - -/*! - \brief set CRC length - \param[in] spi_periph: SPIx(x=1) - \param[in] crc_length: CRC length - only one parameter can be selected which is shown as below: - \arg SPI_CRC_8BIT: CRC length is 8 bits - \arg SPI_CRC_16BIT: CRC length is 16 bits - \param[out] none - \retval none -*/ -void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length) -{ - /* clear SPI_CTL0_CRCL bit */ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCL); - /* confige SPI_CTL0_CRCL bit */ - SPI_CTL0(spi_periph) |= (uint32_t)crc_length; -} - -/*! - \brief turn on CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_on(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; -} - -/*! - \brief turn off CRC function - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_off(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); -} - -/*! - \brief SPI next data is CRC value - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_next(uint32_t spi_periph) -{ - SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; -} - -/*! - \brief get SPI CRC send value or receive value - \param[in] spi_periph: SPIx(x=0,1) - \param[in] crc: SPI crc value - only one parameter can be selected which is shown as below: - \arg SPI_CRC_TX: get transmit crc value - \arg SPI_CRC_RX: get receive crc value - \param[out] none - \retval 16-bit CRC value -*/ -uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) -{ - if(SPI_CRC_TX == crc) { - return ((uint16_t)(SPI_TCRC(spi_periph))); - } else { - return ((uint16_t)(SPI_RCRC(spi_periph))); - } -} - -/*! - \brief clear SPI CRC error flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_crc_error_clear(uint32_t spi_periph) -{ - SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); -} - -/*! - \brief enable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; -} - -/*! - \brief disable SPI TI mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_ti_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); -} - -/*! - \brief enable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_enable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; -} - -/*! - \brief disable SPI NSS pulse mode - \param[in] spi_periph: SPIx(x=0,1) - \param[out] none - \retval none -*/ -void spi_nssp_mode_disable(uint32_t spi_periph) -{ - SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); -} - -/*! - \brief enable quad wire SPI - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; -} - -/*! - \brief disable quad wire SPI - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); -} - -/*! - \brief enable quad wire SPI write - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_write_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); -} - -/*! - \brief enable quad wire SPI read - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_read_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; -} - -/*! - \brief enable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_io23_output_enable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; -} - -/*! - \brief disable SPI_IO2 and SPI_IO3 pin output - \param[in] spi_periph: SPIx(x=1) - \param[out] none - \retval none -*/ -void spi_quad_io23_output_disable(uint32_t spi_periph) -{ - SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); -} - -/*! - \brief get SPI and I2S flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] flag: SPI/I2S flag status - only one parameter can be selected which are shown as below: - \arg SPI_FLAG_TBE: transmit buffer empty flag - \arg SPI_FLAG_RBNE: receive buffer not empty flag - \arg SPI_FLAG_TRANS: transmit on-going flag - \arg SPI_FLAG_RXORERR: receive overrun error flag - \arg SPI_FLAG_CONFERR: mode config error flag - \arg SPI_FLAG_CRCERR: CRC error flag - \arg SPI_FLAG_FERR: SPI format error interrupt flag - \arg I2S_FLAG_TBE: transmit buffer empty flag - \arg I2S_FLAG_RBNE: receive buffer not empty flag - \arg I2S_FLAG_TRANS: transmit on-going flag - \arg I2S_FLAG_RXORERR: overrun error flag - \arg I2S_FLAG_TXURERR: underrun error flag - \arg I2S_FLAG_CH: channel side flag - \arg I2S_FLAG_FERR: I2S format error interrupt flag - only for SPI1: - \arg SPI_FLAG_TXLVL_EMPTY: SPI TXFIFO is empty - \arg SPI_FLAG_TXLVL_QUARTER_FULL: SPI TXFIFO is a quarter of full - \arg SPI_FLAG_TXLVL_HAlF_FULL: SPI TXFIFO is a half of full - \arg SPI_FLAG_TXLVL_FULL: SPI TXFIFO is full - \arg SPI_FLAG_RXLVL_EMPTY: SPI RXFIFO is empty - \arg SPI_FLAG_RXLVL_QUARTER_FULL: SPI RXFIFO is a quarter of full - \arg SPI_FLAG_RXLVL_HAlF_FULL: SPI RXFIFO is a half of full - \arg SPI_FLAG_RXLVL_FULL: SPI RXFIFO is full - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) -{ - if(RESET != (SPI_STAT(spi_periph) & flag)) { - return SET; - } else { - if(SPI1 == spi_periph) { - /* check TXFIFO is empty or not */ - if(SPI_TXLVL_EMPTY == flag) { - if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)) { - return RESET; - } else { - return SET; - } - } - /* check RXFIFO is empty or not */ - if(SPI_RXLVL_EMPTY == flag) { - if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)) { - return RESET; - } else { - return SET; - } - } - } - return RESET; - } -} - -/*! - \brief enable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) -{ - SPI_CTL1(spi_periph) |= (uint32_t)interrupt; -} - -/*! - \brief disable SPI and I2S interrupt - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt - \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt - \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, - transmission underrun error and format error interrupt - \param[out] none - \retval none -*/ -void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) -{ - SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt; -} - -/*! - \brief get SPI and I2S interrupt flag status - \param[in] spi_periph: SPIx(x=0,1) - \param[in] interrupt: SPI/I2S interrupt flag status - only one parameter can be selected which is shown as below: - \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag - \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag - \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag - \arg SPI_INT_FLAG_CONFERR: config error interrupt flag - \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag - \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag - \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) -{ - uint32_t reg1 = SPI_STAT(spi_periph); - uint32_t reg2 = SPI_CTL1(spi_periph); - - switch(interrupt) { - /* SPI/I2S transmit buffer empty interrupt */ - case SPI_I2S_INT_FLAG_TBE: - reg1 = reg1 & SPI_STAT_TBE; - reg2 = reg2 & SPI_CTL1_TBEIE; - break; - /* SPI/I2S receive buffer not empty interrupt */ - case SPI_I2S_INT_FLAG_RBNE: - reg1 = reg1 & SPI_STAT_RBNE; - reg2 = reg2 & SPI_CTL1_RBNEIE; - break; - /* SPI/I2S overrun interrupt */ - case SPI_I2S_INT_FLAG_RXORERR: - reg1 = reg1 & SPI_STAT_RXORERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI config error interrupt */ - case SPI_INT_FLAG_CONFERR: - reg1 = reg1 & SPI_STAT_CONFERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI CRC error interrupt */ - case SPI_INT_FLAG_CRCERR: - reg1 = reg1 & SPI_STAT_CRCERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* I2S underrun error interrupt */ - case I2S_INT_FLAG_TXURERR: - reg1 = reg1 & SPI_STAT_TXURERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - /* SPI/I2S format error interrupt */ - case SPI_I2S_INT_FLAG_FERR: - reg1 = reg1 & SPI_STAT_FERR; - reg2 = reg2 & SPI_CTL1_ERRIE; - break; - default : - break; - } - /*get SPI/I2S interrupt flag status */ - if((0U != reg1) && (0U != reg2)) { - return SET; - } else { - return RESET; - } -} +/*! + \file gd32e23x_spi.c + \brief SPI driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_spi.h" + +/* SPI/I2S parameter initialization mask */ +#define SPI_INIT_MASK ((uint32_t)0x00003040U) /*!< SPI0 parameter initialization mask */ +#define SPI_FIFO_INIT_MASK1 ((uint32_t)0x00003840U) /*!< SPI1 parameter initialization mask1 */ +#define SPI_FIFO_INIT_MASK2 ((uint32_t)0x0000F0FFU) /*!< SPI1 parameter initialization mask2*/ +#define I2S_INIT_MASK ((uint32_t)0x0000F047U) /*!< I2S parameter initialization mask */ + +#define SPI_FRAMESIZE_MASK ((uint32_t)0x00000800U) /*!< SPI0 frame size mask */ +#define SPI_BYTEN_MASK ((uint32_t)0x00001000U) /*!< SPI1 access to FIFO mask */ +#define SPI_TXLVL_EMPTY_MASK ((uint32_t)0x00001800U) /*!< SPI1 TXFIFO empty mask */ +#define SPI_RXLVL_EMPTY_MASK ((uint32_t)0x00000600U) /*!< SPI1 RXFIFO empty mask */ + +/* I2S clock source selection, multiplication and division mask */ +#define SPI_I2SPSC_RESET ((uint32_t)0x00000002U) /*!< I2S clock prescaler register reset value */ + +/*! + \brief reset SPI and I2S + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_i2s_deinit(uint32_t spi_periph) +{ + switch(spi_periph) { + case SPI0: + /* reset SPI0 and I2S0 */ + rcu_periph_reset_enable(RCU_SPI0RST); + rcu_periph_reset_disable(RCU_SPI0RST); + break; + case SPI1: + /* reset SPI1 */ + rcu_periph_reset_enable(RCU_SPI1RST); + rcu_periph_reset_disable(RCU_SPI1RST); + break; + default : + break; + } +} + +/*! + \brief initialize the parameters of SPI structure with the default values + \param[in] none + \param[out] spi_parameter_struct: the initialized structure spi_parameter_struct pointer + \retval none +*/ +void spi_struct_para_init(spi_parameter_struct *spi_struct) +{ + /* configure the SPI structure with the default values */ + spi_struct->device_mode = SPI_SLAVE; + spi_struct->trans_mode = SPI_TRANSMODE_FULLDUPLEX; + spi_struct->frame_size = SPI_FRAMESIZE_8BIT; + spi_struct->nss = SPI_NSS_HARD; + spi_struct->endian = SPI_ENDIAN_MSB; + spi_struct->clock_polarity_phase = SPI_CK_PL_LOW_PH_1EDGE; + spi_struct->prescale = SPI_PSC_2; +} + +/*! + \brief initialize SPI parameters + \param[in] spi_periph: SPIx(x=0,1) + \param[in] spi_struct: SPI parameter initialization stuct members of the structure + and the member values are shown as below: + device_mode: SPI_MASTER, SPI_SLAVE + trans_mode: SPI_TRANSMODE_FULLDUPLEX, SPI_TRANSMODE_RECEIVEONLY, + SPI_TRANSMODE_BDRECEIVE, SPI_TRANSMODE_BDTRANSMIT + frame_size: SPI_FRAMESIZE_4BIT, SPI_FRAMESIZE_5BIT + SPI_FRAMESIZE_6BIT, SPI_FRAMESIZE_7BIT + SPI_FRAMESIZE_8BIT, SPI_FRAMESIZE_9BIT + SPI_FRAMESIZE_10BIT, SPI_FRAMESIZE_11BIT + SPI_FRAMESIZE_12BIT, SPI_FRAMESIZE_13BIT + SPI_FRAMESIZE_14BIT, SPI_FRAMESIZE_15BIT + SPI_FRAMESIZE_16BIT + nss: SPI_NSS_SOFT, SPI_NSS_HARD + endian: SPI_ENDIAN_MSB, SPI_ENDIAN_LSB + clock_polarity_phase: SPI_CK_PL_LOW_PH_1EDGE, SPI_CK_PL_HIGH_PH_1EDGE + SPI_CK_PL_LOW_PH_2EDGE, SPI_CK_PL_HIGH_PH_2EDGE + prescale: SPI_PSC_n (n=2,4,8,16,32,64,128,256) + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct) +{ + uint32_t reg1 = 0U, reg2 = 0U, reg3 = 0U; + + reg1 = SPI_CTL0(spi_periph); + reg1 &= SPI_INIT_MASK; + + reg2 = SPI_CTL0(spi_periph); + reg2 &= SPI_FIFO_INIT_MASK1; + + reg3 = SPI_CTL1(spi_periph); + reg3 &= SPI_FIFO_INIT_MASK2; + + if(SPI0 == spi_periph) { + /* select SPI as master or slave */ + reg1 |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg1 |= spi_struct->trans_mode; + /* select SPI NSS use hardware or software */ + reg1 |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg1 |= spi_struct->endian; + /* select SPI polarity and phase */ + reg1 |= spi_struct->clock_polarity_phase; + /* select SPI prescaler to adjust transmit speed */ + reg1 |= spi_struct->prescale; + /* select SPI frame size */ + /* check SPI0 frame size is 8bits/16bits or not*/ + if((SPI_FRAMESIZE_8BIT != spi_struct->frame_size) && (SPI_FRAMESIZE_16BIT != spi_struct->frame_size)) { + return ERROR; + } else { + reg1 |= (spi_struct->frame_size & SPI_FRAMESIZE_MASK); + } + + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg1; + + } else { + /* select SPI as master or slave */ + reg2 |= spi_struct->device_mode; + /* select SPI transfer mode */ + reg2 |= spi_struct->trans_mode; + /* select SPI NSS use hardware or software */ + reg2 |= spi_struct->nss; + /* select SPI LSB or MSB */ + reg2 |= spi_struct->endian; + /* select SPI polarity and phase */ + reg2 |= spi_struct->clock_polarity_phase; + /* select SPI prescaler to adjust transmit speed */ + reg2 |= spi_struct->prescale; + /* write to SPI_CTL0 register */ + SPI_CTL0(spi_periph) = (uint32_t)reg2; + + /* select SPI data size */ + reg3 |= spi_struct->frame_size; + /* write to SPI_CTL0 register */ + SPI_CTL1(spi_periph) = (uint32_t)reg3; + } + + /* select SPI mode */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SSEL); + + return SUCCESS; +} + +/*! + \brief enable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_enable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SPIEN; +} + +/*! + \brief disable SPI + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_disable(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SPIEN); +} + +/*! + \brief initialize I2S parameters + \param[in] spi_periph: SPIx(x=0) + \param[in] mode: I2S operation mode + only one parameter can be selected which is shown as below: + \arg I2S_MODE_SLAVETX: I2S slave transmit mode + \arg I2S_MODE_SLAVERX: I2S slave receive mode + \arg I2S_MODE_MASTERTX: I2S master transmit mode + \arg I2S_MODE_MASTERRX: I2S master receive mode + \param[in] standard: I2S standard + only one parameter can be selected which is shown as below: + \arg I2S_STD_PHILIPS: I2S phillips standard + \arg I2S_STD_MSB: I2S MSB standard + \arg I2S_STD_LSB: I2S LSB standard + \arg I2S_STD_PCMSHORT: I2S PCM short standard + \arg I2S_STD_PCMLONG: I2S PCM long standard + \param[in] ckpl: I2S idle state clock polarity + only one parameter can be selected which is shown as below: + \arg I2S_CKPL_LOW: I2S clock polarity low level + \arg I2S_CKPL_HIGH: I2S clock polarity high level + \param[out] none + \retval none +*/ +void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl) +{ + uint32_t reg = 0U; + reg = SPI_I2SCTL(spi_periph); + reg &= I2S_INIT_MASK; + + /* enable I2S mode */ + reg |= (uint32_t)SPI_I2SCTL_I2SSEL; + /* select I2S mode */ + reg |= (uint32_t)mode; + /* select I2S standard */ + reg |= (uint32_t)standard; + /* select I2S polarity */ + reg |= (uint32_t)ckpl; + + /* write to SPI_I2SCTL register */ + SPI_I2SCTL(spi_periph) = (uint32_t)reg; +} + +/*! + \brief configure I2S prescaler + \param[in] spi_periph: SPIx(x=0) + \param[in] audiosample: I2S audio sample rate + only one parameter can be selected which is shown as below: + \arg I2S_AUDIOSAMPLE_8K: audio sample rate is 8KHz + \arg I2S_AUDIOSAMPLE_11K: audio sample rate is 11KHz + \arg I2S_AUDIOSAMPLE_16K: audio sample rate is 16KHz + \arg I2S_AUDIOSAMPLE_22K: audio sample rate is 22KHz + \arg I2S_AUDIOSAMPLE_32K: audio sample rate is 32KHz + \arg I2S_AUDIOSAMPLE_44K: audio sample rate is 44KHz + \arg I2S_AUDIOSAMPLE_48K: audio sample rate is 48KHz + \arg I2S_AUDIOSAMPLE_96K: audio sample rate is 96KHz + \arg I2S_AUDIOSAMPLE_192K: audio sample rate is 192KHz + \param[in] frameformat: I2S data length and channel length + only one parameter can be selected which is shown as below: + \arg I2S_FRAMEFORMAT_DT16B_CH16B: I2S data length is 16 bit and channel length is 16 bit + \arg I2S_FRAMEFORMAT_DT16B_CH32B: I2S data length is 16 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT24B_CH32B: I2S data length is 24 bit and channel length is 32 bit + \arg I2S_FRAMEFORMAT_DT32B_CH32B: I2S data length is 32 bit and channel length is 32 bit + \param[in] mckout: I2S master clock output + only one parameter can be selected which is shown as below: + \arg I2S_MCKOUT_ENABLE: enable I2S master clock output + \arg I2S_MCKOUT_DISABLE: disable 2S master clock output + \param[out] none + \retval none +*/ +void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout) +{ + uint32_t i2sdiv = 2U, i2sof = 0U; + uint32_t clks = 0U; + uint32_t i2sclock = 0U; + + /* deinitialize SPI_I2SPSC register */ + SPI_I2SPSC(spi_periph) = SPI_I2SPSC_RESET; + + /* get system clock */ + i2sclock = rcu_clock_freq_get(CK_SYS); + + /* configure the prescaler depending on the mclk output state, the frame format and audio sample rate */ + if(I2S_MCKOUT_ENABLE == mckout) { + clks = (uint32_t)(((i2sclock / 256U) * 10U) / audiosample); + } else { + if(I2S_FRAMEFORMAT_DT16B_CH16B == frameformat) { + clks = (uint32_t)(((i2sclock / 32U) * 10U) / audiosample); + } else { + clks = (uint32_t)(((i2sclock / 64U) * 10U) / audiosample); + } + } + + /* remove the floating point */ + clks = (clks + 5U) / 10U; + i2sof = (clks & 0x00000001U); + i2sdiv = ((clks - i2sof) / 2U); + i2sof = (i2sof << 8U); + + /* set the default values */ + if((i2sdiv < 2U) || (i2sdiv > 255U)) { + i2sdiv = 2U; + i2sof = 0U; + } + + /* configure SPI_I2SPSC */ + SPI_I2SPSC(spi_periph) = (uint32_t)(i2sdiv | i2sof | mckout); + + /* clear SPI_I2SCTL_DTLEN and SPI_I2SCTL_CHLEN bits */ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~(SPI_I2SCTL_DTLEN | SPI_I2SCTL_CHLEN)); + + /* configure data frame format */ + SPI_I2SCTL(spi_periph) |= (uint32_t)frameformat; +} + + +/*! + \brief enable I2S + \param[in] spi_periph: SPIx(x=0) + \param[out] none + \retval none +*/ +void i2s_enable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) |= (uint32_t)SPI_I2SCTL_I2SEN; +} + +/*! + \brief disable I2S + \param[in] spi_periph: SPIx(x=0) + \param[out] none + \retval none +*/ +void i2s_disable(uint32_t spi_periph) +{ + SPI_I2SCTL(spi_periph) &= (uint32_t)(~SPI_I2SCTL_I2SEN); +} + +/*! + \brief enable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSDRV; +} + +/*! + \brief disable SPI NSS output + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_output_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSDRV); +} + +/*! + \brief SPI NSS pin high level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_high(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_SWNSS; +} + +/*! + \brief SPI NSS pin low level in software mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nss_internal_low(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_SWNSS); +} + +/*! + \brief enable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_enable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMATEN; + } else { + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_DMAREN; + } +} + +/*! + \brief disable SPI DMA send or receive + \param[in] spi_periph: SPIx(x=0,1) + \param[in] dma: SPI DMA mode + only one parameter can be selected which is shown as below: + \arg SPI_DMA_TRANSMIT: SPI transmit data using DMA + \arg SPI_DMA_RECEIVE: SPI receive data using DMA + \param[out] none + \retval none +*/ +void spi_dma_disable(uint32_t spi_periph, uint8_t dma) +{ + if(SPI_DMA_TRANSMIT == dma) { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMATEN); + } else { + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_DMAREN); + } +} + +/*! + \brief configure SPI total number of data to be transmitted by DMA is odd or not + \param[in] spi_periph: SPIx(x=1) + \param[in] odd: odd bytes in TX DMA channel + only one parameter can be selected which is shown as below: + \arg SPI_TXDMA_EVEN: number of byte in TX DMA channel is even + \arg SPI_TXDMA_ODD: number of byte in TX DMA channel is odd + \param[out] none + \retval none +*/ +void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd) +{ + /* clear SPI_CTL1_TXDMA_ODD bit */ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TXDMA_ODD); + /* configure SPI_CTL1_TXDMA_ODD bit */ + SPI_CTL1(spi_periph) |= (uint32_t)odd; +} + +/*! + \brief configure SPI total number of data to be received by DMA is odd or not + \param[in] spi_periph: SPIx(x=1) + \param[in] odd: odd bytes in RX DMA channel + only one parameter can be selected which is shown as below: + \arg SPI_RXDMA_EVEN: number of bytes in RX DMA channel is even + \arg SPI_RXDMA_ODD: number of bytes in RX DMA channel is odd + \param[out] none + \retval none +*/ +void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd) +{ + /* clear SPI_CTL1_RXDMA_ODD bit */ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_RXDMA_ODD); + /* configure SPI_CTL1_RXDMA_ODD bit */ + SPI_CTL1(spi_periph) |= (uint32_t)odd; +} + +/*! + \brief configure SPI data frame format + \param[in] spi_periph: SPIx(x=0,1) + \param[in] frame_format: SPI frame size + only one parameter can be selected which is shown as below: + \arg SPI_FRAMESIZE_xBIT(x=4,5..16, for SPI1, x=8,16, for SPI0):SPI frame size is x bits + \param[out] none + \retval ErrStatus: ERROR or SUCCESS +*/ +ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format) +{ + uint32_t reg; + if(SPI0 == spi_periph) { + /* check SPI0 frame size is 8bits/16bits or not*/ + if((SPI_FRAMESIZE_8BIT != frame_format) && (SPI_FRAMESIZE_16BIT != frame_format)) { + return ERROR; + } else { + /* clear SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_FF16); + /* configure SPI_CTL0_FF16 bit */ + SPI_CTL0(spi_periph) |= ((uint32_t)frame_format & SPI_FRAMESIZE_MASK); + } + } else { + reg = SPI_CTL1(spi_periph); + /* clear SPI_CTL1_DZ bits */ + reg &= (uint32_t)(~SPI_CTL1_DZ); + reg |= (uint32_t)frame_format; + /* configure SPI_CTL1_DZ bits */ + SPI_CTL1(spi_periph) = reg; + } + return SUCCESS; +} + +/*! + \brief configure SPI access size to FIFO(8-bit or 16-bit) + \param[in] spi_periph: SPIx(x=1) + \param[in] fifo_access_size: byte access enable + only one parameter can be selected which is shown as below: + \arg SPI_HALFWORD_ACCESS: half-word access to FIFO + \arg SPI_BYTE_ACCESS: byte access to FIFO + \param[out] none + \retval none +*/ +void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size) +{ + /* clear SPI_CTL1_BYTEN bit */ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_BYTEN); + /* confige SPI_CTL1_BYTEN bit */ + SPI_CTL1(spi_periph) |= (uint32_t)fifo_access_size; +} + +/*! + \brief configure SPI bidirectional transfer direction + \param[in] spi_periph: SPIx(x=0,1) + \param[in] transfer_direction: SPI transfer direction + only one parameter can be selected which is shown as below: + \arg SPI_BIDIRECTIONAL_TRANSMIT: SPI work in transmit-only mode + \arg SPI_BIDIRECTIONAL_RECEIVE: SPI work in receive-only mode + \param[out] none + \retval none +*/ +void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction) +{ + if(SPI_BIDIRECTIONAL_TRANSMIT == transfer_direction) { + /* set the transmit-only mode */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_BIDIRECTIONAL_TRANSMIT; + } else { + /* set the receive-only mode */ + SPI_CTL0(spi_periph) &= SPI_BIDIRECTIONAL_RECEIVE; + } +} + +/*! + \brief SPI transmit data + \param[in] spi_periph: SPIx(x=0,1) + \param[in] data: 16-bit data + \param[out] none + \retval none +*/ +void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data) +{ + uint32_t reg, byten; + if(SPI0 == spi_periph) { + SPI_DATA(spi_periph) = (uint32_t)data; + } else { + /* get the access size to FIFO */ + byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; + if(RESET != byten) { + reg = spi_periph + 0x0CU; + *(uint8_t *)(reg) = (uint8_t)data; + } else { + SPI_DATA(spi_periph) = (uint16_t)data; + } + } +} + +/*! + \brief SPI receive data + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit data +*/ +uint16_t spi_i2s_data_receive(uint32_t spi_periph) +{ + uint32_t reg, byten; + if(SPI0 == spi_periph) { + return ((uint16_t)SPI_DATA(spi_periph)); + } else { + /* get the access size to FIFO */ + byten = SPI_CTL1(spi_periph) & SPI_BYTEN_MASK; + if(RESET != byten) { + reg = spi_periph + 0x0CU; + return (uint16_t)(*(uint8_t *)(reg)); + } else { + return ((uint16_t)SPI_DATA(spi_periph)); + } + } +} + +/*! + \brief clear SPI/I2S format error flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] flag: SPI/I2S frame format error flag + \arg SPI_FLAG_FERR: only for SPI work in TI mode + \arg I2S_FLAG_FERR: for I2S + \param[out] none + \retval none +*/ +void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag) +{ + SPI_STAT(spi_periph) = (uint32_t)(~flag); +} + +/*! + \brief set SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc_poly: CRC polynomial value + \param[out] none + \retval none +*/ +void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly) +{ + /* enable SPI CRC */ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; + /* set SPI CRC polynomial */ + SPI_CRCPOLY(spi_periph) = (uint32_t)crc_poly; +} + +/*! + \brief get SPI CRC polynomial + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval 16-bit CRC polynomial +*/ +uint16_t spi_crc_polynomial_get(uint32_t spi_periph) +{ + return ((uint16_t)SPI_CRCPOLY(spi_periph)); +} + +/*! + \brief set CRC length + \param[in] spi_periph: SPIx(x=1) + \param[in] crc_length: CRC length + only one parameter can be selected which is shown as below: + \arg SPI_CRC_8BIT: CRC length is 8 bits + \arg SPI_CRC_16BIT: CRC length is 16 bits + \param[out] none + \retval none +*/ +void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length) +{ + /* clear SPI_CTL0_CRCL bit */ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCL); + /* confige SPI_CTL0_CRCL bit */ + SPI_CTL0(spi_periph) |= (uint32_t)crc_length; +} + +/*! + \brief turn on CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_on(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCEN; +} + +/*! + \brief turn off CRC function + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_off(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) &= (uint32_t)(~SPI_CTL0_CRCEN); +} + +/*! + \brief SPI next data is CRC value + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_next(uint32_t spi_periph) +{ + SPI_CTL0(spi_periph) |= (uint32_t)SPI_CTL0_CRCNT; +} + +/*! + \brief get SPI CRC send value or receive value + \param[in] spi_periph: SPIx(x=0,1) + \param[in] crc: SPI crc value + only one parameter can be selected which is shown as below: + \arg SPI_CRC_TX: get transmit crc value + \arg SPI_CRC_RX: get receive crc value + \param[out] none + \retval 16-bit CRC value +*/ +uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc) +{ + if(SPI_CRC_TX == crc) { + return ((uint16_t)(SPI_TCRC(spi_periph))); + } else { + return ((uint16_t)(SPI_RCRC(spi_periph))); + } +} + +/*! + \brief clear SPI CRC error flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_crc_error_clear(uint32_t spi_periph) +{ + SPI_STAT(spi_periph) = (uint32_t)(~SPI_FLAG_CRCERR); +} + +/*! + \brief enable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_TMOD; +} + +/*! + \brief disable SPI TI mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_ti_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_TMOD); +} + +/*! + \brief enable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_enable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) |= (uint32_t)SPI_CTL1_NSSP; +} + +/*! + \brief disable SPI NSS pulse mode + \param[in] spi_periph: SPIx(x=0,1) + \param[out] none + \retval none +*/ +void spi_nssp_mode_disable(uint32_t spi_periph) +{ + SPI_CTL1(spi_periph) &= (uint32_t)(~SPI_CTL1_NSSP); +} + +/*! + \brief enable quad wire SPI + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QMOD; +} + +/*! + \brief disable quad wire SPI + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QMOD); +} + +/*! + \brief enable quad wire SPI write + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_write_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_QRD); +} + +/*! + \brief enable quad wire SPI read + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_read_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_QRD; +} + +/*! + \brief enable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_enable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) |= (uint32_t)SPI_QCTL_IO23_DRV; +} + +/*! + \brief disable SPI_IO2 and SPI_IO3 pin output + \param[in] spi_periph: SPIx(x=1) + \param[out] none + \retval none +*/ +void spi_quad_io23_output_disable(uint32_t spi_periph) +{ + SPI_QCTL(spi_periph) &= (uint32_t)(~SPI_QCTL_IO23_DRV); +} + +/*! + \brief get SPI and I2S flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] flag: SPI/I2S flag status + only one parameter can be selected which are shown as below: + \arg SPI_FLAG_TBE: transmit buffer empty flag + \arg SPI_FLAG_RBNE: receive buffer not empty flag + \arg SPI_FLAG_TRANS: transmit on-going flag + \arg SPI_FLAG_RXORERR: receive overrun error flag + \arg SPI_FLAG_CONFERR: mode config error flag + \arg SPI_FLAG_CRCERR: CRC error flag + \arg SPI_FLAG_FERR: SPI format error interrupt flag + \arg I2S_FLAG_TBE: transmit buffer empty flag + \arg I2S_FLAG_RBNE: receive buffer not empty flag + \arg I2S_FLAG_TRANS: transmit on-going flag + \arg I2S_FLAG_RXORERR: overrun error flag + \arg I2S_FLAG_TXURERR: underrun error flag + \arg I2S_FLAG_CH: channel side flag + \arg I2S_FLAG_FERR: I2S format error interrupt flag + only for SPI1: + \arg SPI_FLAG_TXLVL_EMPTY: SPI TXFIFO is empty + \arg SPI_FLAG_TXLVL_QUARTER_FULL: SPI TXFIFO is a quarter of full + \arg SPI_FLAG_TXLVL_HAlF_FULL: SPI TXFIFO is a half of full + \arg SPI_FLAG_TXLVL_FULL: SPI TXFIFO is full + \arg SPI_FLAG_RXLVL_EMPTY: SPI RXFIFO is empty + \arg SPI_FLAG_RXLVL_QUARTER_FULL: SPI RXFIFO is a quarter of full + \arg SPI_FLAG_RXLVL_HAlF_FULL: SPI RXFIFO is a half of full + \arg SPI_FLAG_RXLVL_FULL: SPI RXFIFO is full + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag) +{ + if(RESET != (SPI_STAT(spi_periph) & flag)) { + return SET; + } else { + if(SPI1 == spi_periph) { + /* check TXFIFO is empty or not */ + if(SPI_TXLVL_EMPTY == flag) { + if(RESET != (SPI_STAT(spi_periph) & SPI_TXLVL_EMPTY_MASK)) { + return RESET; + } else { + return SET; + } + } + /* check RXFIFO is empty or not */ + if(SPI_RXLVL_EMPTY == flag) { + if(RESET != (SPI_STAT(spi_periph) & SPI_RXLVL_EMPTY_MASK)) { + return RESET; + } else { + return SET; + } + } + } + return RESET; + } +} + +/*! + \brief enable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt) +{ + SPI_CTL1(spi_periph) |= (uint32_t)interrupt; +} + +/*! + \brief disable SPI and I2S interrupt + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_TBE: transmit buffer empty interrupt + \arg SPI_I2S_INT_RBNE: receive buffer not empty interrupt + \arg SPI_I2S_INT_ERR: CRC error, configuration error, reception overrun error, + transmission underrun error and format error interrupt + \param[out] none + \retval none +*/ +void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt) +{ + SPI_CTL1(spi_periph) &= ~(uint32_t)interrupt; +} + +/*! + \brief get SPI and I2S interrupt flag status + \param[in] spi_periph: SPIx(x=0,1) + \param[in] interrupt: SPI/I2S interrupt flag status + only one parameter can be selected which is shown as below: + \arg SPI_I2S_INT_FLAG_TBE: transmit buffer empty interrupt flag + \arg SPI_I2S_INT_FLAG_RBNE: receive buffer not empty interrupt flag + \arg SPI_I2S_INT_FLAG_RXORERR: overrun interrupt flag + \arg SPI_INT_FLAG_CONFERR: config error interrupt flag + \arg SPI_INT_FLAG_CRCERR: CRC error interrupt flag + \arg I2S_INT_FLAG_TXURERR: underrun error interrupt flag + \arg SPI_I2S_INT_FLAG_FERR: format error interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt) +{ + uint32_t reg1 = SPI_STAT(spi_periph); + uint32_t reg2 = SPI_CTL1(spi_periph); + + switch(interrupt) { + /* SPI/I2S transmit buffer empty interrupt */ + case SPI_I2S_INT_FLAG_TBE: + reg1 = reg1 & SPI_STAT_TBE; + reg2 = reg2 & SPI_CTL1_TBEIE; + break; + /* SPI/I2S receive buffer not empty interrupt */ + case SPI_I2S_INT_FLAG_RBNE: + reg1 = reg1 & SPI_STAT_RBNE; + reg2 = reg2 & SPI_CTL1_RBNEIE; + break; + /* SPI/I2S overrun interrupt */ + case SPI_I2S_INT_FLAG_RXORERR: + reg1 = reg1 & SPI_STAT_RXORERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI config error interrupt */ + case SPI_INT_FLAG_CONFERR: + reg1 = reg1 & SPI_STAT_CONFERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI CRC error interrupt */ + case SPI_INT_FLAG_CRCERR: + reg1 = reg1 & SPI_STAT_CRCERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* I2S underrun error interrupt */ + case I2S_INT_FLAG_TXURERR: + reg1 = reg1 & SPI_STAT_TXURERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + /* SPI/I2S format error interrupt */ + case SPI_I2S_INT_FLAG_FERR: + reg1 = reg1 & SPI_STAT_FERR; + reg2 = reg2 & SPI_CTL1_ERRIE; + break; + default : + break; + } + /*get SPI/I2S interrupt flag status */ + if((0U != reg1) && (0U != reg2)) { + return SET; + } else { + return RESET; + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c index 9fe6355..04dba29 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_syscfg.c @@ -1,205 +1,205 @@ -/*! - \file gd32e23x_syscfg.c - \brief SYSCFG driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_syscfg.h" - -/*! - \brief reset the SYSCFG registers - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_deinit(void) -{ - rcu_periph_reset_enable(RCU_CFGCMPRST); - rcu_periph_reset_disable(RCU_CFGCMPRST); -} - -/*! - \brief enable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 |= syscfg_dma_remap; -} - -/*! - \brief disable the DMA channels remapping - \param[in] syscfg_dma_remap: specify the DMA channels to remap - \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) - \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) - \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) - \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) - \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 - \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 - \param[out] none - \retval none -*/ -void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) -{ - SYSCFG_CFG0 &= ~syscfg_dma_remap; -} - -/*! - \brief enable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_enable(void) -{ - SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; -} - -/*! - \brief disable PB9 high current capability - \param[in] none - \param[out] none - \retval none -*/ -void syscfg_high_current_disable(void) -{ - SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; -} - -/*! - \brief configure the GPIO pin as EXTI Line - \param[in] exti_port: specify the GPIO port used in EXTI - \arg EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port - \param[in] exti_pin: specify the EXTI line - \arg EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin - \param[out] none - \retval none -*/ -void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) -{ - uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); - uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); - - switch(exti_pin / EXTI_SS_JSTEP) { - case EXTISS0: - /* clear EXTI source line(0..3) */ - SYSCFG_EXTISS0 &= clear_exti_mask; - /* configure EXTI soure line(0..3) */ - SYSCFG_EXTISS0 |= config_exti_mask; - break; - case EXTISS1: - /* clear EXTI soure line(4..7) */ - SYSCFG_EXTISS1 &= clear_exti_mask; - /* configure EXTI soure line(4..7) */ - SYSCFG_EXTISS1 |= config_exti_mask; - break; - case EXTISS2: - /* clear EXTI soure line(8..11) */ - SYSCFG_EXTISS2 &= clear_exti_mask; - /* configure EXTI soure line(8..11) */ - SYSCFG_EXTISS2 |= config_exti_mask; - break; - case EXTISS3: - /* clear EXTI soure line(12..15) */ - SYSCFG_EXTISS3 &= clear_exti_mask; - /* configure EXTI soure line(12..15) */ - SYSCFG_EXTISS3 |= config_exti_mask; - break; - default: - break; - } -} - -/*! - \brief connect TIMER0/14/15/16 break input to the selected parameter - \param[in] syscfg_lock: Specify the parameter to be connected - \arg SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input - \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input - \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input - \param[out] none - \retval none -*/ -void syscfg_lock_config(uint32_t syscfg_lock) -{ - SYSCFG_CFG2 |= syscfg_lock; -} - -/*! - \brief set the wait state counter value - \param[in] irq_latency: IRQ_LATENCY value (0x00 - 0xFF) - \param[out] none - \retval none -*/ -void irq_latency_set(uint8_t irq_latency) -{ - uint32_t reg; - - reg = SYSCFG_CPU_IRQ_LAT & (~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY); - reg |= (uint32_t)(IRQ_LATENCY(irq_latency)); - - SYSCFG_CPU_IRQ_LAT = (uint32_t)reg; -} -/*! - \brief check if the specified flag in SYSCFG_CFG2 is set or not. - \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval the syscfg_flag state returned (SET or RESET). - */ -FlagStatus syscfg_flag_get(uint32_t syscfg_flag) -{ - if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear the flag in SYSCFG_CFG2 by writing 1. - \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. - \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. - \param[out] none - \retval none -*/ -void syscfg_flag_clear(uint32_t syscfg_flag) -{ - SYSCFG_CFG2 |= (uint32_t) syscfg_flag; -} - +/*! + \file gd32e23x_syscfg.c + \brief SYSCFG driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_syscfg.h" + +/*! + \brief reset the SYSCFG registers + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_deinit(void) +{ + rcu_periph_reset_enable(RCU_CFGCMPRST); + rcu_periph_reset_disable(RCU_CFGCMPRST); +} + +/*! + \brief enable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 |= syscfg_dma_remap; +} + +/*! + \brief disable the DMA channels remapping + \param[in] syscfg_dma_remap: specify the DMA channels to remap + \arg SYSCFG_DMA_REMAP_TIMER16: remap TIMER16 channel0 and UP DMA requests to channel1(defaut channel0) + \arg SYSCFG_DMA_REMAP_TIMER15: remap TIMER15 channel2 and UP DMA requests to channel3(defaut channel2) + \arg SYSCFG_DMA_REMAP_USART0RX: remap USART0 Rx DMA request to channel4(default channel2) + \arg SYSCFG_DMA_REMAP_USART0TX: remap USART0 Tx DMA request to channel3(default channel1) + \arg SYSCFG_DMA_REMAP_ADC: remap ADC DMA requests from channel0 to channel1 + \arg SYSCFG_PA11_REMAP_PA12: remap PA11 PA12 + \param[out] none + \retval none +*/ +void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap) +{ + SYSCFG_CFG0 &= ~syscfg_dma_remap; +} + +/*! + \brief enable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_enable(void) +{ + SYSCFG_CFG0 |= SYSCFG_HIGH_CURRENT_ENABLE; +} + +/*! + \brief disable PB9 high current capability + \param[in] none + \param[out] none + \retval none +*/ +void syscfg_high_current_disable(void) +{ + SYSCFG_CFG0 &= SYSCFG_HIGH_CURRENT_DISABLE; +} + +/*! + \brief configure the GPIO pin as EXTI Line + \param[in] exti_port: specify the GPIO port used in EXTI + \arg EXTI_SOURCE_GPIOx(x = A,B,C,F): EXTI GPIO port + \param[in] exti_pin: specify the EXTI line + \arg EXTI_SOURCE_PINx(GPIOA x = 0..15,GPIOB x = 0..15,GPIOC x = 13..15,GPIOF x = 0.1.6.7): EXTI GPIO pin + \param[out] none + \retval none +*/ +void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin) +{ + uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin))); + uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin)); + + switch(exti_pin / EXTI_SS_JSTEP) { + case EXTISS0: + /* clear EXTI source line(0..3) */ + SYSCFG_EXTISS0 &= clear_exti_mask; + /* configure EXTI soure line(0..3) */ + SYSCFG_EXTISS0 |= config_exti_mask; + break; + case EXTISS1: + /* clear EXTI soure line(4..7) */ + SYSCFG_EXTISS1 &= clear_exti_mask; + /* configure EXTI soure line(4..7) */ + SYSCFG_EXTISS1 |= config_exti_mask; + break; + case EXTISS2: + /* clear EXTI soure line(8..11) */ + SYSCFG_EXTISS2 &= clear_exti_mask; + /* configure EXTI soure line(8..11) */ + SYSCFG_EXTISS2 |= config_exti_mask; + break; + case EXTISS3: + /* clear EXTI soure line(12..15) */ + SYSCFG_EXTISS3 &= clear_exti_mask; + /* configure EXTI soure line(12..15) */ + SYSCFG_EXTISS3 |= config_exti_mask; + break; + default: + break; + } +} + +/*! + \brief connect TIMER0/14/15/16 break input to the selected parameter + \param[in] syscfg_lock: Specify the parameter to be connected + \arg SYSCFG_LOCK_LOCKUP: Cortex-M23 lockup output connected to the break input + \arg SYSCFG_LOCK_SRAM_PARITY_ERROR: SRAM_PARITY check error connected to the break input + \arg SYSCFG_LOCK_LVD: LVD interrupt connected to the break input + \param[out] none + \retval none +*/ +void syscfg_lock_config(uint32_t syscfg_lock) +{ + SYSCFG_CFG2 |= syscfg_lock; +} + +/*! + \brief set the wait state counter value + \param[in] irq_latency: IRQ_LATENCY value (0x00 - 0xFF) + \param[out] none + \retval none +*/ +void irq_latency_set(uint8_t irq_latency) +{ + uint32_t reg; + + reg = SYSCFG_CPU_IRQ_LAT & (~(uint32_t)SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY); + reg |= (uint32_t)(IRQ_LATENCY(irq_latency)); + + SYSCFG_CPU_IRQ_LAT = (uint32_t)reg; +} +/*! + \brief check if the specified flag in SYSCFG_CFG2 is set or not. + \param[in] syscfg_flag: specify the flag in SYSCFG_CFG2 to check. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval the syscfg_flag state returned (SET or RESET). + */ +FlagStatus syscfg_flag_get(uint32_t syscfg_flag) +{ + if((SYSCFG_CFG2 & syscfg_flag) != (uint32_t)RESET) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear the flag in SYSCFG_CFG2 by writing 1. + \param[in] syscfg_flag: Specify the flag in SYSCFG_CFG2 to clear. + \arg SYSCFG_SRAM_PCEF: SRAM parity check error flag. + \param[out] none + \retval none +*/ +void syscfg_flag_clear(uint32_t syscfg_flag) +{ + SYSCFG_CFG2 |= (uint32_t) syscfg_flag; +} + diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c index 6d1573d..29e0271 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_timer.c @@ -1,2057 +1,2057 @@ -/*! - \file gd32e23x_timer.c - \brief TIMER driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_timer.h" - -/* TIMER init parameter mask */ -#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ -#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ -#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ - -/*! - \brief deinit a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_deinit(uint32_t timer_periph) -{ - switch(timer_periph) { - case TIMER0: - /* reset TIMER0 */ - rcu_periph_reset_enable(RCU_TIMER0RST); - rcu_periph_reset_disable(RCU_TIMER0RST); - break; - case TIMER2: - /* reset TIMER2 */ - rcu_periph_reset_enable(RCU_TIMER2RST); - rcu_periph_reset_disable(RCU_TIMER2RST); - break; - case TIMER5: - /* reset TIMER5 */ - rcu_periph_reset_enable(RCU_TIMER5RST); - rcu_periph_reset_disable(RCU_TIMER5RST); - break; - case TIMER13: - /* reset TIMER13 */ - rcu_periph_reset_enable(RCU_TIMER13RST); - rcu_periph_reset_disable(RCU_TIMER13RST); - break; - case TIMER14: - /* reset TIMER14 */ - rcu_periph_reset_enable(RCU_TIMER14RST); - rcu_periph_reset_disable(RCU_TIMER14RST); - break; - case TIMER15: - /* reset TIMER15 */ - rcu_periph_reset_enable(RCU_TIMER15RST); - rcu_periph_reset_disable(RCU_TIMER15RST); - break; - case TIMER16: - /* reset TIMER16 */ - rcu_periph_reset_enable(RCU_TIMER16RST); - rcu_periph_reset_disable(RCU_TIMER16RST); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER init parameter struct with a default value - \param[in] initpara: init parameter struct - \param[out] none - \retval none -*/ -void timer_struct_para_init(timer_parameter_struct *initpara) -{ - /* initialize the init parameter struct member with the default value */ - initpara->prescaler = 0U; - initpara->alignedmode = TIMER_COUNTER_EDGE; - initpara->counterdirection = TIMER_COUNTER_UP; - initpara->period = 65535U; - initpara->clockdivision = TIMER_CKDIV_DIV1; - initpara->repetitioncounter = 0U; -} - -/*! - \brief initialize TIMER counter - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] initpara: init parameter struct - prescaler: prescaler value of the counter clock, 0~65535 - alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH - counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN - period: counter auto reload value, 0~65535 - clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 - repetitioncounter: counter repetition value, 0~255 - \param[out] none - \retval none -*/ -void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) -{ - /* configure the counter prescaler value */ - TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; - - /* configure the counter direction and aligned mode */ - if((TIMER0 == timer_periph) || (TIMER2 == timer_periph)) { - TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; - } - - /* configure the autoreload value */ - TIMER_CAR(timer_periph) = (uint32_t)initpara->period; - - if((TIMER0 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) - || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { - /* reset the CKDIV bit */ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; - TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; - } - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { - /* configure the repetition counter value */ - TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; - } - - /* generate an update event */ - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; -} - -/*! - \brief enable a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief disable a TIMER - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; -} - -/*! - \brief enable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief disable the auto reload shadow function - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_auto_reload_shadow_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; -} - -/*! - \brief enable the update event - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_update_event_enable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; -} - -/*! - \brief disable the update event - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval none -*/ -void timer_update_event_disable(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; -} - -/*! - \brief set TIMER counter alignment mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] aligned: - only one parameter can be selected which is shown as below: - \arg TIMER_COUNTER_EDGE: edge-aligned mode - \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode - \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode - \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode - \param[out] none - \retval none -*/ -void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; - TIMER_CTL0(timer_periph) |= (uint32_t)aligned; -} - -/*! - \brief set TIMER counter up direction - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_counter_up_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief set TIMER counter down direction - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_counter_down_direction(uint32_t timer_periph) -{ - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; -} - -/*! - \brief configure TIMER prescaler - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] prescaler: prescaler value,0~65535 - \param[in] pscreload: prescaler reload mode - only one parameter can be selected which is shown as below: - \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now - \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event - \param[out] none - \retval none -*/ -void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) -{ - TIMER_PSC(timer_periph) = (uint32_t)prescaler; - - if(TIMER_PSC_RELOAD_NOW == pscreload) { - TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; - } -} - -/*! - \brief configure TIMER repetition register value - \param[in] timer_periph: TIMERx(x=0,15,16) - \param[in] repetition: the counter repetition value,0~255 - \param[out] none - \retval none -*/ -void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) -{ - TIMER_CREP(timer_periph) = (uint32_t)repetition; -} - -/*! - \brief configure TIMER autoreload register value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] autoreload: the counter auto-reload value,0~65535 - \param[out] none - \retval none -*/ -void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) -{ - TIMER_CAR(timer_periph) = (uint32_t)autoreload; -} - -/*! - \brief configure TIMER counter register value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] counter: the counter value,0~65535 - \param[out] none - \retval none -*/ -void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) -{ - TIMER_CNT(timer_periph) = (uint32_t)counter; -} - -/*! - \brief read TIMER counter value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval counter value -*/ -uint32_t timer_counter_read(uint32_t timer_periph) -{ - uint32_t count_value = 0U; - count_value = TIMER_CNT(timer_periph); - return (count_value); -} - -/*! - \brief read TIMER prescaler value - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[out] none - \retval prescaler register value -*/ -uint16_t timer_prescaler_read(uint32_t timer_periph) -{ - uint16_t prescaler_value = 0U; - prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); - return (prescaler_value); -} - -/*! - \brief configure TIMER single pulse mode - \param[in] timer_periph: TIMERx(x=0,2,5,14..16) - \param[in] spmode: - only one parameter can be selected which is shown as below: - \arg TIMER_SP_MODE_SINGLE: single pulse mode - \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode - \param[out] none - \retval none -*/ -void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) -{ - if(TIMER_SP_MODE_SINGLE == spmode) { - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; - } else if(TIMER_SP_MODE_REPETITIVE == spmode) { - TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER update source - \param[in] timer_periph: TIMERx(x=0,2,5,13..16) - \param[in] update: - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger - \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow - \param[out] none - \retval none -*/ -void timer_update_source_config(uint32_t timer_periph, uint32_t update) -{ - if(TIMER_UPDATE_SRC_REGULAR == update) { - TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; - } else if(TIMER_UPDATE_SRC_GLOBAL == update) { - TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER OCPRE clear source selection - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] ocpreclear: - only one parameter can be selected which is shown as below: - \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input - \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF - \param[out] none - \retval none -*/ -void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) -{ - if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear) { - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; - } else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear) { - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; - } else { - /* illegal parameters */ - } -} - -/*! - \brief enable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt enable source - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2) - \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2) - \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14) - \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; -} - -/*! - \brief disable the TIMER interrupt - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: timer interrupt source disable - only one parameter can be selected which is shown as below: - \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0,2,13..16) - \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0,2,14) - \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0,2) - \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0,2) - \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,14..16) - \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0,2,14) - \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); -} - -/*! - \brief get timer interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) -{ - uint32_t val; - val = (TIMER_DMAINTEN(timer_periph) & interrupt); - if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear TIMER interrupt flag - \param[in] timer_periph: please refer to the following parameters - \param[in] interrupt: the timer interrupt bits - only one parameter can be selected which is shown as below: - \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0,2,13..16) - \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0,2) - \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) - \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,2,14) - \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); -} - -/*! - \brief get TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) -{ - if(RESET != (TIMER_INTF(timer_periph) & flag)) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear TIMER flags - \param[in] timer_periph: please refer to the following parameters - \param[in] flag: the timer interrupt flags - only one parameter can be selected which is shown as below: - \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) - \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) - \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) - \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) - \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) - \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) - \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_flag_clear(uint32_t timer_periph, uint32_t flag) -{ - TIMER_INTF(timer_periph) = (~(uint32_t)flag); -} - -/*! - \brief enable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to enable - one or more parameters can be selected which is shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_dma_enable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; -} - -/*! - \brief disable the TIMER DMA - \param[in] timer_periph: please refer to the following parameters - \param[in] dma: specify which DMA to disable - one or more parameters can be selected which are shown as below: - \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) - \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) - \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) - \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) - \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) - \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_dma_disable(uint32_t timer_periph, uint16_t dma) -{ - TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); -} - -/*! - \brief channel DMA request source selection - \param[in] timer_periph: TIMERx(x=0,2,14..16) - \param[in] dma_request: channel DMA request source selection - only one parameter can be selected which is shown as below: - \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs - \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs - \param[out] none - \retval none -*/ -void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) -{ - if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; - } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure the TIMER DMA transfer - \param[in] timer_periph: TIMERx(x=0,2,14..16) - \param[in] dma_baseaddr: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,2,14) - \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,2,14..16) - \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,2,14) - \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,2) - \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) - \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0,2,14..16) - \param[in] dma_lenth: - only one parameter can be selected which is shown as below: - \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time - \param[out] none - \retval none -*/ -void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) -{ - TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); - TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); -} - -/*! - \brief software generate events - \param[in] timer_periph: please refer to the following parameters - \param[in] event: the timer software event generation sources - one or more parameters can be selected which are shown as below: - \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0,2,5,13..16) - \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,2,13..16) - \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,2,14) - \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,2) - \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,2) - \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) - \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,2,14) - \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_event_software_generate(uint32_t timer_periph, uint16_t event) -{ - TIMER_SWEVG(timer_periph) |= (uint32_t)event; -} - -/*! - \brief initialize TIMER break parameter struct with a default value - \param[in] breakpara: TIMER break parameter struct - \param[out] none - \retval none -*/ -void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) -{ - /* initialize the break parameter struct member with the default value */ - breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; - breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; - breakpara->deadtime = 0U; - breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; - breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; - breakpara->protectmode = TIMER_CCHP_PROT_OFF; - breakpara->breakstate = TIMER_BREAK_DISABLE; -} - -/*! - \brief configure TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] breakpara: TIMER break parameter struct - runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE - ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE - deadtime: 0~255 - breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH - outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE - protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 - breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE - \param[out] none - \retval none -*/ -void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) -{ - TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | - ((uint32_t)(breakpara->ideloffstate)) | - ((uint32_t)(breakpara->deadtime)) | - ((uint32_t)(breakpara->breakpolarity)) | - ((uint32_t)(breakpara->outputautostate)) | - ((uint32_t)(breakpara->protectmode)) | - ((uint32_t)(breakpara->breakstate))) ; -} - -/*! - \brief enable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief disable TIMER break function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_break_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; -} - -/*! - \brief enable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_enable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief disable TIMER output automatic function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[out] none - \retval none -*/ -void timer_automatic_output_disable(uint32_t timer_periph) -{ - TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; -} - -/*! - \brief configure TIMER primary output function - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue) { - TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; - } else { - TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); - } -} - -/*! - \brief enable or disable channel capture/compare control shadow register - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] newvalue: ENABLE or DISABLE - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) -{ - if(ENABLE == newvalue) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; - } else { - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); - } -} - -/*! - \brief configure TIMER channel control shadow register update control - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] ccuctl: channel control shadow register update control - only one parameter can be selected which is shown as below: - \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set - \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs - \param[out] none - \retval none -*/ -void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) -{ - if(TIMER_UPDATECTL_CCU == ccuctl) { - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); - } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; - } else { - /* illegal parameters */ - } -} - -/*! - \brief initialize TIMER channel output parameter struct with a default value - \param[in] ocpara: TIMER channel n output parameter struct - \param[out] none - \retval none -*/ -void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) -{ - /* initialize the channel output parameter struct member with the default value */ - ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; - ocpara->outputnstate = TIMER_CCXN_DISABLE; - ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; - ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; - ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; - ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; -} - -/*! - \brief configure TIMER channel output function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,2)) - \param[in] ocpara: TIMER channeln output parameter struct - outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE - outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE - ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW - ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW - ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH - ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH - \param[out] none - \retval none -*/ -void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; - /* reset the CH0P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - /* set the CH0P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; - - if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { - /* reset the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - /* set the CH0NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; - /* reset the CH0NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - /* set the CH0NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; - /* reset the ISO0 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); - /* set the ISO0 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; - /* reset the ISO0N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); - /* set the ISO0N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; - } - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); - /* reset the CH1P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - /* set the CH1P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); - - if(TIMER0 == timer_periph) { - /* reset the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - /* set the CH1NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - /* reset the ISO1N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); - /* set the ISO1N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); - } - - if(TIMER14 == timer_periph) { - /* reset the ISO1 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); - /* set the ISO1 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); - } - - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); - /* reset the CH2P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - /* set the CH2P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); - - if(TIMER0 == timer_periph) { - /* reset the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - /* set the CH2NEN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); - /* reset the CH2NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - /* set the CH2NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); - /* reset the ISO2 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); - /* set the ISO2 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); - /* reset the ISO2N bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); - /* set the ISO2N bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); - } - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); - /* reset the CH3P bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - /* set the CH3P bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); - - if(TIMER0 == timer_periph) { - /* reset the ISO3 bit */ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); - /* set the ISO3 bit */ - TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); - } - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output compare mode - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocmode: channel output compare mode - only one parameter can be selected which is shown as below: - \arg TIMER_OC_MODE_TIMING: timing mode - \arg TIMER_OC_MODE_ACTIVE: active mode - \arg TIMER_OC_MODE_INACTIVE: inactive mode - \arg TIMER_OC_MODE_TOGGLE: toggle mode - \arg TIMER_OC_MODE_LOW: force low mode - \arg TIMER_OC_MODE_HIGH: force high mode - \arg TIMER_OC_MODE_PWM0: PWM0 mode - \arg TIMER_OC_MODE_PWM1: PWM1 mode - \param[out] none - \retval none -*/ -void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output pulse value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] pulse: channel output pulse value,0~65535 - \param[out] none - \retval none -*/ -void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CH0CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CH1CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CH2CV(timer_periph) = (uint32_t)pulse; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CH3CV(timer_periph) = (uint32_t)pulse; - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output shadow function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocshadow: channel output shadow state - only one parameter can be selected which is shown as below: - \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable - \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable - \param[out] none - \retval none -*/ -void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output fast function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocfast: channel output fast function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_FAST_ENABLE: channel output fast function enable - \arg TIMER_OC_FAST_DISABLE: channel output fast function disable - \param[out] none - \retval none -*/ -void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output clear function - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] occlear: channel output clear function - only one parameter can be selected which is shown as below: - \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable - \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable - \param[out] none - \retval none -*/ -void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel output polarity - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] ocpolarity: channel output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high - \arg TIMER_OC_POLARITY_LOW: channel output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output polarity - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel2(TIMERx(x=0,2)) - \param[in] ocnpolarity: channel complementary output polarity - only one parameter can be selected which is shown as below: - \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high - \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel enable state - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] state: TIMER channel enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCX_ENABLE: channel enable - \arg TIMER_CCX_DISABLE: channel disable - \param[out] none - \retval none -*/ -void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)state; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); - break; - default: - break; - } -} - -/*! - \brief configure TIMER channel complementary output enable state - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) - \param[in] ocnstate: TIMER channel complementary output enable state - only one parameter can be selected which is shown as below: - \arg TIMER_CCXN_ENABLE: channel complementary enable - \arg TIMER_CCXN_DISABLE: channel complementary disable - \param[out] none - \retval none -*/ -void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); - break; - default: - break; - } -} - -/*! - \brief initialize TIMER channel input parameter struct with a default value - \param[in] icpara: TIMER channel intput parameter struct - \param[out] none - \retval none -*/ -void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) -{ - /* initialize the channel input parameter struct member with the default value */ - icpara->icpolarity = TIMER_IC_POLARITY_RISING; - icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; - icpara->icprescaler = TIMER_IC_PSC_DIV1; - icpara->icfilter = 0U; -} - -/*! - \brief configure TIMER input capture parameter - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] icpara: TIMER channel intput parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - break; - - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - /* reset the CH2EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); - - /* reset the CH2P and CH2NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); - - /* reset the CH2MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); - - /* reset the CH2CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); - - /* set the CH2EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - /* reset the CH3EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); - - /* reset the CH3P and CH3NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P | TIMER_CHCTL2_CH3NP)); - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); - - /* reset the CH3MS bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); - - /* reset the CH3CAPFLT bit */ - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); - TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); - - /* set the CH3EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; - break; - default: - break; - } - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); -} - -/*! - \brief configure TIMER channel input capture prescaler value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[in] prescaler: channel input capture prescaler value - only one parameter can be selected which is shown as below: - \arg TIMER_IC_PSC_DIV1: no prescaler - \arg TIMER_IC_PSC_DIV2: divided by 2 - \arg TIMER_IC_PSC_DIV4: divided by 4 - \arg TIMER_IC_PSC_DIV8: divided by 8 - \param[out] none - \retval none -*/ -void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) -{ - switch(channel) { - /* configure TIMER_CH_0 */ - case TIMER_CH_0: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); - TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_1 */ - case TIMER_CH_1: - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); - TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - /* configure TIMER_CH_2 */ - case TIMER_CH_2: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); - TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; - break; - /* configure TIMER_CH_3 */ - case TIMER_CH_3: - TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); - TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); - break; - default: - break; - } -} - -/*! - \brief read TIMER channel capture compare register value - \param[in] timer_periph: please refer to the following parameters - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) - \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) - \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) - \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) - \param[out] none - \retval channel capture compare register value -*/ -uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) -{ - uint32_t count_value = 0U; - - switch(channel) { - /* read TIMER channel 0 capture compare register value */ - case TIMER_CH_0: - count_value = TIMER_CH0CV(timer_periph); - break; - /* read TIMER channel 1 capture compare register value */ - case TIMER_CH_1: - count_value = TIMER_CH1CV(timer_periph); - break; - /* read TIMER channel 2 capture compare register value */ - case TIMER_CH_2: - count_value = TIMER_CH2CV(timer_periph); - break; - /* read TIMER channel 3 capture compare register value */ - case TIMER_CH_3: - count_value = TIMER_CH3CV(timer_periph); - break; - default: - break; - } - return (count_value); -} - -/*! - \brief configure TIMER input pwm capture function - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] channel: - only one parameter can be selected which is shown as below: - \arg TIMER_CH_0: TIMER channel0 - \arg TIMER_CH_1: TIMER channel1 - \param[in] icpwm:TIMER channel intput pwm parameter struct - icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING - icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI - icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 - icfilter: 0~15 - \param[out] none - \retval none -*/ -void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) -{ - uint16_t icpolarity = 0x0U; - uint16_t icselection = 0x0U; - - /* Set channel input polarity */ - if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { - icpolarity = TIMER_IC_POLARITY_FALLING; - } else { - icpolarity = TIMER_IC_POLARITY_RISING; - } - - /* Set channel input mode selection */ - if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { - icselection = TIMER_IC_SELECTION_INDIRECTTI; - } else { - icselection = TIMER_IC_SELECTION_DIRECTTI; - } - - if(TIMER_CH_0 == channel) { - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - } else { - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1P and CH1NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); - - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* set the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - /* configure TIMER channel input capture prescaler value */ - timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); - } -} - -/*! - \brief configure TIMER hall sensor mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] hallmode: - only one parameter can be selected which is shown as below: - \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable - \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable - \param[out] none - \retval none -*/ -void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) -{ - if(TIMER_HALLINTERFACE_ENABLE == hallmode) { - TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; - } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { - TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; - } else { - /* illegal parameters */ - } -} - -/*! - \brief select TIMER input trigger source - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0,2)) - \param[out] none - \retval none -*/ -void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); - TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; -} - -/*! - \brief select TIMER master mode output trigger source - \param[in] timer_periph: TIMERx(x=0,2,5,14) - \param[in] outrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,2,5,14)) - \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,2,14)) - \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,2,14)) - \param[out] none - \retval none -*/ -void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) -{ - TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); - TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; -} - -/*! - \brief select TIMER slave mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] slavemode: - only one parameter can be selected which is shown as below: - \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0,2,14)) - \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0,2)) - \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0,2)) - \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0,2)) - \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0,2,14)) - \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0,2,14)) - \param[out] none - \retval none -*/ - -void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - - TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; -} - -/*! - \brief configure TIMER master slave mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] masterslave: - only one parameter can be selected which is shown as below: - \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable - \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable - \param[out] none - \retval none -*/ -void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) -{ - if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; - } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER external trigger input - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); - TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); -} - -/*! - \brief configure TIMER quadrature decoder mode - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] decomode: - only one parameter can be selected which is shown as below: - \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level - \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level - \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input - \param[in] ic0polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[in] ic1polarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: capture rising edge - \arg TIMER_IC_POLARITY_FALLING: capture falling edge - \param[out] none - \retval none -*/ -void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, - uint16_t ic0polarity, uint16_t ic1polarity) -{ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; - - TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); - TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); - - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); -} - -/*! - \brief configure TIMER internal clock mode - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[out] none - \retval none -*/ -void timer_internal_clock_config(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; -} - -/*! - \brief configure TIMER the internal trigger as external clock input - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] intrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) - \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) - \param[out] none - \retval none -*/ -void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) -{ - timer_input_trigger_source_select(timer_periph, intrigger); - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external trigger as external clock input - \param[in] timer_periph: TIMERx(x=0,2,14) - \param[in] extrigger: - only one parameter can be selected which is shown as below: - \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector - \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 - \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_IC_POLARITY_RISING: active high or rising edge active - \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active - \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, - uint16_t extpolarity, uint32_t extfilter) -{ - if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { - /* reset the CH1EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); - /* reset the CH1NP bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); - /* set the CH1NP bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); - /* reset the CH1MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); - /* set the CH1MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); - /* reset the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); - /* set the CH1CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); - /* set the CH1EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; - } else { - /* reset the CH0EN bit */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); - /* reset the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); - /* set the CH0P and CH0NP bits */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; - /* reset the CH0MS bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); - /* set the CH0MS bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); - /* reset the CH0CAPFLT bit */ - TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); - /* set the CH0EN bit */ - TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; - } - /* select TIMER input trigger source */ - timer_input_trigger_source_select(timer_periph, extrigger); - /* reset the SMC bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); - /* set the SMC bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; -} - -/*! - \brief configure TIMER the external clock mode0 - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - /* reset the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); - /* set the SMC bit,TRGS bit */ - TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); -} - -/*! - \brief configure TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0,2) - \param[in] extprescaler: - only one parameter can be selected which is shown as below: - \arg TIMER_EXT_TRI_PSC_OFF: no divided - \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 - \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 - \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 - \param[in] extpolarity: - only one parameter can be selected which is shown as below: - \arg TIMER_ETP_FALLING: active low or falling edge active - \arg TIMER_ETP_RISING: active high or rising edge active - \param[in] extfilter: a value between 0 and 15 - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, - uint32_t extpolarity, uint32_t extfilter) -{ - /* configure TIMER external trigger input */ - timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); - - TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief disable TIMER the external clock mode1 - \param[in] timer_periph: TIMERx(x=0,2) - \param[out] none - \retval none -*/ -void timer_external_clock_mode1_disable(uint32_t timer_periph) -{ - TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; -} - -/*! - \brief configure TIMER channel remap function - \param[in] timer_periph: TIMERx(x=13) - \param[in] remap: - only one parameter can be selected which is shown as below: - \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) - \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK - \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock - \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL - \param[out] none - \retval none -*/ -void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) -{ - TIMER_IRMP(timer_periph) = (uint32_t)remap; -} - -/*! - \brief configure TIMER write CHxVAL register selection - \param[in] timer_periph: TIMERx(x=0,2,13..16) - \param[in] ccsel: - only one parameter can be selected which is shown as below: - \arg TIMER_CHVSEL_DISABLE: no effect - \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored - \param[out] none - \retval none -*/ -void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) -{ - if(TIMER_CHVSEL_ENABLE == ccsel) { - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; - } else if(TIMER_CHVSEL_DISABLE == ccsel) { - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; - } else { - /* illegal parameters */ - } -} - -/*! - \brief configure TIMER output value selection - \param[in] timer_periph: TIMERx(x=0,14..16) - \param[in] outsel: - only one parameter can be selected which is shown as below: - \arg TIMER_OUTSEL_DISABLE: no effect - \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled - \param[out] none - \retval none -*/ -void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) -{ - if(TIMER_OUTSEL_ENABLE == outsel) { - TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; - } else if(TIMER_OUTSEL_DISABLE == outsel) { - TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; - } else { - /* illegal parameters */ - } -} +/*! + \file gd32e23x_timer.c + \brief TIMER driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_timer.h" + +/* TIMER init parameter mask */ +#define ALIGNEDMODE_MASK ((uint32_t)0x00000060U) /*!< TIMER init parameter aligne dmode mask */ +#define COUNTERDIRECTION_MASK ((uint32_t)0x00000010U) /*!< TIMER init parameter counter direction mask */ +#define CLOCKDIVISION_MASK ((uint32_t)0x00000300U) /*!< TIMER init parameter clock division value mask */ + +/*! + \brief deinit a TIMER + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_deinit(uint32_t timer_periph) +{ + switch(timer_periph) { + case TIMER0: + /* reset TIMER0 */ + rcu_periph_reset_enable(RCU_TIMER0RST); + rcu_periph_reset_disable(RCU_TIMER0RST); + break; + case TIMER2: + /* reset TIMER2 */ + rcu_periph_reset_enable(RCU_TIMER2RST); + rcu_periph_reset_disable(RCU_TIMER2RST); + break; + case TIMER5: + /* reset TIMER5 */ + rcu_periph_reset_enable(RCU_TIMER5RST); + rcu_periph_reset_disable(RCU_TIMER5RST); + break; + case TIMER13: + /* reset TIMER13 */ + rcu_periph_reset_enable(RCU_TIMER13RST); + rcu_periph_reset_disable(RCU_TIMER13RST); + break; + case TIMER14: + /* reset TIMER14 */ + rcu_periph_reset_enable(RCU_TIMER14RST); + rcu_periph_reset_disable(RCU_TIMER14RST); + break; + case TIMER15: + /* reset TIMER15 */ + rcu_periph_reset_enable(RCU_TIMER15RST); + rcu_periph_reset_disable(RCU_TIMER15RST); + break; + case TIMER16: + /* reset TIMER16 */ + rcu_periph_reset_enable(RCU_TIMER16RST); + rcu_periph_reset_disable(RCU_TIMER16RST); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER init parameter struct with a default value + \param[in] initpara: init parameter struct + \param[out] none + \retval none +*/ +void timer_struct_para_init(timer_parameter_struct *initpara) +{ + /* initialize the init parameter struct member with the default value */ + initpara->prescaler = 0U; + initpara->alignedmode = TIMER_COUNTER_EDGE; + initpara->counterdirection = TIMER_COUNTER_UP; + initpara->period = 65535U; + initpara->clockdivision = TIMER_CKDIV_DIV1; + initpara->repetitioncounter = 0U; +} + +/*! + \brief initialize TIMER counter + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[in] initpara: init parameter struct + prescaler: prescaler value of the counter clock, 0~65535 + alignedmode: TIMER_COUNTER_EDGE, TIMER_COUNTER_CENTER_DOWN, TIMER_COUNTER_CENTER_UP, TIMER_COUNTER_CENTER_BOTH + counterdirection: TIMER_COUNTER_UP, TIMER_COUNTER_DOWN + period: counter auto reload value, 0~65535 + clockdivision: TIMER_CKDIV_DIV1, TIMER_CKDIV_DIV2, TIMER_CKDIV_DIV4 + repetitioncounter: counter repetition value, 0~255 + \param[out] none + \retval none +*/ +void timer_init(uint32_t timer_periph, timer_parameter_struct *initpara) +{ + /* configure the counter prescaler value */ + TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler; + + /* configure the counter direction and aligned mode */ + if((TIMER0 == timer_periph) || (TIMER2 == timer_periph)) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM); + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection; + } + + /* configure the autoreload value */ + TIMER_CAR(timer_periph) = (uint32_t)initpara->period; + + if((TIMER0 == timer_periph) || (TIMER2 == timer_periph) || (TIMER13 == timer_periph) + || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* reset the CKDIV bit */ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV; + TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision; + } + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* configure the repetition counter value */ + TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter; + } + + /* generate an update event */ + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; +} + +/*! + \brief enable a TIMER + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief disable a TIMER + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN; +} + +/*! + \brief enable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief disable the auto reload shadow function + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_auto_reload_shadow_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE; +} + +/*! + \brief enable the update event + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_update_event_enable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS; +} + +/*! + \brief disable the update event + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval none +*/ +void timer_update_event_disable(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS; +} + +/*! + \brief set TIMER counter alignment mode + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] aligned: + only one parameter can be selected which is shown as below: + \arg TIMER_COUNTER_EDGE: edge-aligned mode + \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode + \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode + \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode + \param[out] none + \retval none +*/ +void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM; + TIMER_CTL0(timer_periph) |= (uint32_t)aligned; +} + +/*! + \brief set TIMER counter up direction + \param[in] timer_periph: TIMERx(x=0,2) + \param[out] none + \retval none +*/ +void timer_counter_up_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief set TIMER counter down direction + \param[in] timer_periph: TIMERx(x=0,2) + \param[out] none + \retval none +*/ +void timer_counter_down_direction(uint32_t timer_periph) +{ + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR; +} + +/*! + \brief configure TIMER prescaler + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[in] prescaler: prescaler value,0~65535 + \param[in] pscreload: prescaler reload mode + only one parameter can be selected which is shown as below: + \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now + \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event + \param[out] none + \retval none +*/ +void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload) +{ + TIMER_PSC(timer_periph) = (uint32_t)prescaler; + + if(TIMER_PSC_RELOAD_NOW == pscreload) { + TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG; + } +} + +/*! + \brief configure TIMER repetition register value + \param[in] timer_periph: TIMERx(x=0,15,16) + \param[in] repetition: the counter repetition value,0~255 + \param[out] none + \retval none +*/ +void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition) +{ + TIMER_CREP(timer_periph) = (uint32_t)repetition; +} + +/*! + \brief configure TIMER autoreload register value + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[in] autoreload: the counter auto-reload value,0~65535 + \param[out] none + \retval none +*/ +void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload) +{ + TIMER_CAR(timer_periph) = (uint32_t)autoreload; +} + +/*! + \brief configure TIMER counter register value + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[in] counter: the counter value,0~65535 + \param[out] none + \retval none +*/ +void timer_counter_value_config(uint32_t timer_periph, uint16_t counter) +{ + TIMER_CNT(timer_periph) = (uint32_t)counter; +} + +/*! + \brief read TIMER counter value + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval counter value +*/ +uint32_t timer_counter_read(uint32_t timer_periph) +{ + uint32_t count_value = 0U; + count_value = TIMER_CNT(timer_periph); + return (count_value); +} + +/*! + \brief read TIMER prescaler value + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[out] none + \retval prescaler register value +*/ +uint16_t timer_prescaler_read(uint32_t timer_periph) +{ + uint16_t prescaler_value = 0U; + prescaler_value = (uint16_t)(TIMER_PSC(timer_periph)); + return (prescaler_value); +} + +/*! + \brief configure TIMER single pulse mode + \param[in] timer_periph: TIMERx(x=0,2,5,14..16) + \param[in] spmode: + only one parameter can be selected which is shown as below: + \arg TIMER_SP_MODE_SINGLE: single pulse mode + \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode + \param[out] none + \retval none +*/ +void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode) +{ + if(TIMER_SP_MODE_SINGLE == spmode) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM; + } else if(TIMER_SP_MODE_REPETITIVE == spmode) { + TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM); + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER update source + \param[in] timer_periph: TIMERx(x=0,2,5,13..16) + \param[in] update: + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger + \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow + \param[out] none + \retval none +*/ +void timer_update_source_config(uint32_t timer_periph, uint32_t update) +{ + if(TIMER_UPDATE_SRC_REGULAR == update) { + TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS; + } else if(TIMER_UPDATE_SRC_GLOBAL == update) { + TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER OCPRE clear source selection + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] ocpreclear: + only one parameter can be selected which is shown as below: + \arg TIMER_OCPRE_CLEAR_SOURCE_CLR: OCPRE_CLR_INT is connected to the OCPRE_CLR input + \arg TIMER_OCPRE_CLEAR_SOURCE_ETIF: OCPRE_CLR_INT is connected to ETIF + \param[out] none + \retval none +*/ +void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear) +{ + if(TIMER_OCPRE_CLEAR_SOURCE_ETIF == ocpreclear) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_OCRC; + } else if(TIMER_OCPRE_CLEAR_SOURCE_CLR == ocpreclear) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_OCRC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief enable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt enable source + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) + \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0,2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0,2,14) + \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0,2) + \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0,2) + \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0,2,14) + \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt; +} + +/*! + \brief disable the TIMER interrupt + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: timer interrupt source disable + only one parameter can be selected which is shown as below: + \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0,2,5,13..16) + \arg TIMER_INT_CH0: channel 0 interrupt disable, TIMERx(x=0,2,13..16) + \arg TIMER_INT_CH1: channel 1 interrupt disable, TIMERx(x=0,2,14) + \arg TIMER_INT_CH2: channel 2 interrupt disable, TIMERx(x=0,2) + \arg TIMER_INT_CH3: channel 3 interrupt disable , TIMERx(x=0,2) + \arg TIMER_INT_CMT: commutation interrupt disable, TIMERx(x=0,14..16) + \arg TIMER_INT_TRG: trigger interrupt disable, TIMERx(x=0,2,14) + \arg TIMER_INT_BRK: break interrupt disable, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt); +} + +/*! + \brief get timer interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0,2,5,13..16) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0,2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0,2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0,2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0,2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,14..16) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt) +{ + uint32_t val; + val = (TIMER_DMAINTEN(timer_periph) & interrupt); + if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER interrupt flag + \param[in] timer_periph: please refer to the following parameters + \param[in] interrupt: the timer interrupt bits + only one parameter can be selected which is shown as below: + \arg TIMER_INT_FLAG_UP: update interrupt flag, TIMERx(x=0,2,5,13..16) + \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag, TIMERx(x=0,2,13..16) + \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag, TIMERx(x=0,2,14) + \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag, TIMERx(x=0,2) + \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag, TIMERx(x=0,2) + \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag, TIMERx(x=0,14..16) + \arg TIMER_INT_FLAG_TRG: trigger interrupt flag, TIMERx(x=0,2,14) + \arg TIMER_INT_FLAG_BRK: break interrupt flag, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)interrupt); +} + +/*! + \brief get TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag) +{ + if(RESET != (TIMER_INTF(timer_periph) & flag)) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear TIMER flags + \param[in] timer_periph: please refer to the following parameters + \param[in] flag: the timer interrupt flags + only one parameter can be selected which is shown as below: + \arg TIMER_FLAG_UP: update flag, TIMERx(x=0,2,5,13..16) + \arg TIMER_FLAG_CH0: channel 0 flag, TIMERx(x=0,2,13..16) + \arg TIMER_FLAG_CH1: channel 1 flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_CH2: channel 2 flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CH3: channel 3 flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CMT: channel control update flag, TIMERx(x=0,14..16) + \arg TIMER_FLAG_TRG: trigger flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,14..16) + \arg TIMER_FLAG_CH0O: channel 0 overcapture flag, TIMERx(x=0,2,13..16) + \arg TIMER_FLAG_CH1O: channel 1 overcapture flag, TIMERx(x=0,2,14) + \arg TIMER_FLAG_CH2O: channel 2 overcapture flag, TIMERx(x=0,2) + \arg TIMER_FLAG_CH3O: channel 3 overcapture flag, TIMERx(x=0,2) + \param[out] none + \retval none +*/ +void timer_flag_clear(uint32_t timer_periph, uint32_t flag) +{ + TIMER_INTF(timer_periph) = (~(uint32_t)flag); +} + +/*! + \brief enable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to enable + one or more parameters can be selected which is shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) + \arg TIMER_DMA_CMTD: commutation DMA request, TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) + \param[out] none + \retval none +*/ +void timer_dma_enable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma; +} + +/*! + \brief disable the TIMER DMA + \param[in] timer_periph: please refer to the following parameters + \param[in] dma: specify which DMA to disable + one or more parameters can be selected which are shown as below: + \arg TIMER_DMA_UPD: update DMA, TIMERx(x=0,2,5,14..16) + \arg TIMER_DMA_CH0D: channel 0 DMA request, TIMERx(x=0,2,14..16) + \arg TIMER_DMA_CH1D: channel 1 DMA request, TIMERx(x=0,2,14) + \arg TIMER_DMA_CH2D: channel 2 DMA request, TIMERx(x=0,2) + \arg TIMER_DMA_CH3D: channel 3 DMA request, TIMERx(x=0,2) + \arg TIMER_DMA_CMTD: commutation DMA request , TIMERx(x=0,14) + \arg TIMER_DMA_TRGD: trigger DMA request, TIMERx(x=0,2,14) + \param[out] none + \retval none +*/ +void timer_dma_disable(uint32_t timer_periph, uint16_t dma) +{ + TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma)); +} + +/*! + \brief channel DMA request source selection + \param[in] timer_periph: TIMERx(x=0,2,14..16) + \param[in] dma_request: channel DMA request source selection + only one parameter can be selected which is shown as below: + \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs + \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs + \param[out] none + \retval none +*/ +void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request) +{ + if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS; + } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure the TIMER DMA transfer + \param[in] timer_periph: TIMERx(x=0,2,14..16) + \param[in] dma_baseaddr: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG, TIMERx(x=0,2,14) + \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1, TIMERx(x=0,2) + \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV, TIMERx(x=0,2,14..16) + \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV, TIMERx(x=0,2,14) + \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV, TIMERx(x=0,2) + \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV, TIMERx(x=0,2) + \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP, TIMERx(x=0,14..16) + \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG, TIMERx(x=0,2,14..16) + \param[in] dma_lenth: + only one parameter can be selected which is shown as below: + \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time + \param[out] none + \retval none +*/ +void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth) +{ + TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC)); + TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth); +} + +/*! + \brief software generate events + \param[in] timer_periph: please refer to the following parameters + \param[in] event: the timer software event generation sources + one or more parameters can be selected which are shown as below: + \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0,2,5,13..16) + \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation, TIMERx(x=0,2,13..16) + \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation, TIMERx(x=0,2,14) + \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation, TIMERx(x=0,2) + \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation, TIMERx(x=0,2) + \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation, TIMERx(x=0,14..16) + \arg TIMER_EVENT_SRC_TRGG: trigger event generation, TIMERx(x=0,2,14) + \arg TIMER_EVENT_SRC_BRKG: break event generation, TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_event_software_generate(uint32_t timer_periph, uint16_t event) +{ + TIMER_SWEVG(timer_periph) |= (uint32_t)event; +} + +/*! + \brief initialize TIMER break parameter struct with a default value + \param[in] breakpara: TIMER break parameter struct + \param[out] none + \retval none +*/ +void timer_break_struct_para_init(timer_break_parameter_struct *breakpara) +{ + /* initialize the break parameter struct member with the default value */ + breakpara->runoffstate = TIMER_ROS_STATE_DISABLE; + breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE; + breakpara->deadtime = 0U; + breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW; + breakpara->outputautostate = TIMER_OUTAUTO_DISABLE; + breakpara->protectmode = TIMER_CCHP_PROT_OFF; + breakpara->breakstate = TIMER_BREAK_DISABLE; +} + +/*! + \brief configure TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] breakpara: TIMER break parameter struct + runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE + ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE + deadtime: 0~255 + breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH + outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE + protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2 + breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE + \param[out] none + \retval none +*/ +void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara) +{ + TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) | + ((uint32_t)(breakpara->ideloffstate)) | + ((uint32_t)(breakpara->deadtime)) | + ((uint32_t)(breakpara->breakpolarity)) | + ((uint32_t)(breakpara->outputautostate)) | + ((uint32_t)(breakpara->protectmode)) | + ((uint32_t)(breakpara->breakstate))) ; +} + +/*! + \brief enable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief disable TIMER break function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_break_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN; +} + +/*! + \brief enable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_enable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief disable TIMER output automatic function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[out] none + \retval none +*/ +void timer_automatic_output_disable(uint32_t timer_periph) +{ + TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN; +} + +/*! + \brief configure TIMER primary output function + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN; + } else { + TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN); + } +} + +/*! + \brief enable or disable channel capture/compare control shadow register + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] newvalue: ENABLE or DISABLE + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue) +{ + if(ENABLE == newvalue) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE; + } else { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE); + } +} + +/*! + \brief configure TIMER channel control shadow register update control + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] ccuctl: channel control shadow register update control + only one parameter can be selected which is shown as below: + \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set + \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs + \param[out] none + \retval none +*/ +void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl) +{ + if(TIMER_UPDATECTL_CCU == ccuctl) { + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC); + } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC; + } else { + /* illegal parameters */ + } +} + +/*! + \brief initialize TIMER channel output parameter struct with a default value + \param[in] ocpara: TIMER channel n output parameter struct + \param[out] none + \retval none +*/ +void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara) +{ + /* initialize the channel output parameter struct member with the default value */ + ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE; + ocpara->outputnstate = TIMER_CCXN_DISABLE; + ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH; + ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH; + ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW; + ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW; +} + +/*! + \brief configure TIMER channel output function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0,2)) + \param[in] ocpara: TIMER channeln output parameter struct + outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE + outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE + ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW + ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW + ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH + ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH + \param[out] none + \retval none +*/ +void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS; + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate; + /* reset the CH0P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + /* set the CH0P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity; + + if((TIMER0 == timer_periph) || (TIMER14 == timer_periph) || (TIMER15 == timer_periph) || (TIMER16 == timer_periph)) { + /* reset the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + /* set the CH0NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate; + /* reset the CH0NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + /* set the CH0NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity; + /* reset the ISO0 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0); + /* set the ISO0 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate; + /* reset the ISO0N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N); + /* set the ISO0N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate; + } + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS; + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U); + /* reset the CH1P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + /* set the CH1P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U); + + if(TIMER0 == timer_periph) { + /* reset the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + /* set the CH1NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U); + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + /* reset the ISO1N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N); + /* set the ISO1N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U); + } + + if(TIMER14 == timer_periph) { + /* reset the ISO1 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1); + /* set the ISO1 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U); + } + + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS; + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U); + /* reset the CH2P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + /* set the CH2P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U); + + if(TIMER0 == timer_periph) { + /* reset the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + /* set the CH2NEN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U); + /* reset the CH2NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + /* set the CH2NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U); + /* reset the ISO2 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2); + /* set the ISO2 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U); + /* reset the ISO2N bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N); + /* set the ISO2N bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U); + } + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS; + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U); + /* reset the CH3P bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + /* set the CH3P bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U); + + if(TIMER0 == timer_periph) { + /* reset the ISO3 bit */ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3); + /* set the ISO3 bit */ + TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U); + } + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output compare mode + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] ocmode: channel output compare mode + only one parameter can be selected which is shown as below: + \arg TIMER_OC_MODE_TIMING: timing mode + \arg TIMER_OC_MODE_ACTIVE: active mode + \arg TIMER_OC_MODE_INACTIVE: inactive mode + \arg TIMER_OC_MODE_TOGGLE: toggle mode + \arg TIMER_OC_MODE_LOW: force low mode + \arg TIMER_OC_MODE_HIGH: force high mode + \arg TIMER_OC_MODE_PWM0: PWM0 mode + \arg TIMER_OC_MODE_PWM1: PWM1 mode + \param[out] none + \retval none +*/ +void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output pulse value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] pulse: channel output pulse value,0~65535 + \param[out] none + \retval none +*/ +void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CH0CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CH1CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CH2CV(timer_periph) = (uint32_t)pulse; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CH3CV(timer_periph) = (uint32_t)pulse; + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output shadow function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] ocshadow: channel output shadow state + only one parameter can be selected which is shown as below: + \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable + \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable + \param[out] none + \retval none +*/ +void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output fast function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] ocfast: channel output fast function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_FAST_ENABLE: channel output fast function enable + \arg TIMER_OC_FAST_DISABLE: channel output fast function disable + \param[out] none + \retval none +*/ +void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output clear function + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] occlear: channel output clear function + only one parameter can be selected which is shown as below: + \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable + \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable + \param[out] none + \retval none +*/ +void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel output polarity + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] ocpolarity: channel output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high + \arg TIMER_OC_POLARITY_LOW: channel output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output polarity + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel2(TIMERx(x=0,2)) + \param[in] ocnpolarity: channel complementary output polarity + only one parameter can be selected which is shown as below: + \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high + \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3NP); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel enable state + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] state: TIMER channel enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCX_ENABLE: channel enable + \arg TIMER_CCX_DISABLE: channel disable + \param[out] none + \retval none +*/ +void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)state; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U); + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U); + break; + default: + break; + } +} + +/*! + \brief configure TIMER channel complementary output enable state + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,14..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0)) + \param[in] ocnstate: TIMER channel complementary output enable state + only one parameter can be selected which is shown as below: + \arg TIMER_CCXN_ENABLE: channel complementary enable + \arg TIMER_CCXN_DISABLE: channel complementary disable + \param[out] none + \retval none +*/ +void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U); + break; + default: + break; + } +} + +/*! + \brief initialize TIMER channel input parameter struct with a default value + \param[in] icpara: TIMER channel intput parameter struct + \param[out] none + \retval none +*/ +void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara) +{ + /* initialize the channel input parameter struct member with the default value */ + icpara->icpolarity = TIMER_IC_POLARITY_RISING; + icpara->icselection = TIMER_IC_SELECTION_DIRECTTI; + icpara->icprescaler = TIMER_IC_PSC_DIV1; + icpara->icfilter = 0U; +} + +/*! + \brief configure TIMER input capture parameter + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] icpara: TIMER channel intput parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + break; + + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + /* reset the CH2EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN); + + /* reset the CH2P and CH2NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U); + + /* reset the CH2MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection)); + + /* reset the CH2CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U); + + /* set the CH2EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + /* reset the CH3EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN); + + /* reset the CH3P and CH3NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P | TIMER_CHCTL2_CH3NP)); + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U); + + /* reset the CH3MS bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U); + + /* reset the CH3CAPFLT bit */ + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT); + TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U); + + /* set the CH3EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN; + break; + default: + break; + } + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler)); +} + +/*! + \brief configure TIMER channel input capture prescaler value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[in] prescaler: channel input capture prescaler value + only one parameter can be selected which is shown as below: + \arg TIMER_IC_PSC_DIV1: no prescaler + \arg TIMER_IC_PSC_DIV2: divided by 2 + \arg TIMER_IC_PSC_DIV4: divided by 4 + \arg TIMER_IC_PSC_DIV8: divided by 8 + \param[out] none + \retval none +*/ +void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler) +{ + switch(channel) { + /* configure TIMER_CH_0 */ + case TIMER_CH_0: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC); + TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_1 */ + case TIMER_CH_1: + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC); + TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + /* configure TIMER_CH_2 */ + case TIMER_CH_2: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC); + TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler; + break; + /* configure TIMER_CH_3 */ + case TIMER_CH_3: + TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC); + TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U); + break; + default: + break; + } +} + +/*! + \brief read TIMER channel capture compare register value + \param[in] timer_periph: please refer to the following parameters + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0,2,13..16)) + \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0,2,14)) + \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0,2)) + \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0,2)) + \param[out] none + \retval channel capture compare register value +*/ +uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel) +{ + uint32_t count_value = 0U; + + switch(channel) { + /* read TIMER channel 0 capture compare register value */ + case TIMER_CH_0: + count_value = TIMER_CH0CV(timer_periph); + break; + /* read TIMER channel 1 capture compare register value */ + case TIMER_CH_1: + count_value = TIMER_CH1CV(timer_periph); + break; + /* read TIMER channel 2 capture compare register value */ + case TIMER_CH_2: + count_value = TIMER_CH2CV(timer_periph); + break; + /* read TIMER channel 3 capture compare register value */ + case TIMER_CH_3: + count_value = TIMER_CH3CV(timer_periph); + break; + default: + break; + } + return (count_value); +} + +/*! + \brief configure TIMER input pwm capture function + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] channel: + only one parameter can be selected which is shown as below: + \arg TIMER_CH_0: TIMER channel0 + \arg TIMER_CH_1: TIMER channel1 + \param[in] icpwm:TIMER channel intput pwm parameter struct + icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING + icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI + icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8 + icfilter: 0~15 + \param[out] none + \retval none +*/ +void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm) +{ + uint16_t icpolarity = 0x0U; + uint16_t icselection = 0x0U; + + /* Set channel input polarity */ + if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) { + icpolarity = TIMER_IC_POLARITY_FALLING; + } else { + icpolarity = TIMER_IC_POLARITY_RISING; + } + + /* Set channel input mode selection */ + if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) { + icselection = TIMER_IC_SELECTION_INDIRECTTI; + } else { + icselection = TIMER_IC_SELECTION_DIRECTTI; + } + + if(TIMER_CH_0 == channel) { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity); + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + } else { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1P and CH1NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler)); + + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* set the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + /* configure TIMER channel input capture prescaler value */ + timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler)); + } +} + +/*! + \brief configure TIMER hall sensor mode + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] hallmode: + only one parameter can be selected which is shown as below: + \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable + \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable + \param[out] none + \retval none +*/ +void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode) +{ + if(TIMER_HALLINTERFACE_ENABLE == hallmode) { + TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S; + } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) { + TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S; + } else { + /* illegal parameters */ + } +} + +/*! + \brief select TIMER input trigger source + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0,2)) + \param[out] none + \retval none +*/ +void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS); + TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger; +} + +/*! + \brief select TIMER master mode output trigger source + \param[in] timer_periph: TIMERx(x=0,2,5,14) + \param[in] outrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0,2,5,14)) + \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0,2,5,14)) + \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0,2,5,14)) + \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0,2,14)) + \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0,2,14)) + \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0,2,14)) + \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0,2,14)) + \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0,2,14)) + \param[out] none + \retval none +*/ +void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger) +{ + TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC); + TIMER_CTL1(timer_periph) |= (uint32_t)outrigger; +} + +/*! + \brief select TIMER slave mode + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] slavemode: + only one parameter can be selected which is shown as below: + \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0,2,14)) + \arg TIMER_QUAD_DECODER_MODE0: quadrature decoder mode 0(TIMERx(x=0,2)) + \arg TIMER_QUAD_DECODER_MODE1: quadrature decoder mode 1(TIMERx(x=0,2)) + \arg TIMER_QUAD_DECODER_MODE2: quadrature decoder mode 2(TIMERx(x=0,2)) + \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0,2,14)) + \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0,2,14)) + \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0,2,14)) + \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0(TIMERx(x=0,2,14)) + \param[out] none + \retval none +*/ + +void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + + TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode; +} + +/*! + \brief configure TIMER master slave mode + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] masterslave: + only one parameter can be selected which is shown as below: + \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable + \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable + \param[out] none + \retval none +*/ +void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave) +{ + if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) { + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM; + } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) { + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER external trigger input + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC)); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity); + TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U); +} + +/*! + \brief configure TIMER quadrature decoder mode + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] decomode: + only one parameter can be selected which is shown as below: + \arg TIMER_QUAD_DECODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level + \arg TIMER_QUAD_DECODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level + \arg TIMER_QUAD_DECODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input + \param[in] ic0polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[in] ic1polarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: capture rising edge + \arg TIMER_IC_POLARITY_FALLING: capture falling edge + \param[out] none + \retval none +*/ +void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, + uint16_t ic0polarity, uint16_t ic1polarity) +{ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + TIMER_SMCFG(timer_periph) |= (uint32_t)decomode; + + TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS))); + TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U)); + + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U)); +} + +/*! + \brief configure TIMER internal clock mode + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[out] none + \retval none +*/ +void timer_internal_clock_config(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; +} + +/*! + \brief configure TIMER the internal trigger as external clock input + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] intrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0,2,14)) + \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0,2)) + \param[out] none + \retval none +*/ +void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger) +{ + timer_input_trigger_source_select(timer_periph, intrigger); + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC; + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external trigger as external clock input + \param[in] timer_periph: TIMERx(x=0,2,14) + \param[in] extrigger: + only one parameter can be selected which is shown as below: + \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector + \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0 + \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_IC_POLARITY_RISING: active high or rising edge active + \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active + \arg TIMER_IC_POLARITY_BOTH_EDGE: active both edge + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, + uint16_t extpolarity, uint32_t extfilter) +{ + if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) { + /* reset the CH1EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN); + /* reset the CH1NP bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP)); + /* set the CH1NP bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U); + /* reset the CH1MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS); + /* set the CH1MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U); + /* reset the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT); + /* set the CH1CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U); + /* set the CH1EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN; + } else { + /* reset the CH0EN bit */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN); + /* reset the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP)); + /* set the CH0P and CH0NP bits */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity; + /* reset the CH0MS bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS); + /* set the CH0MS bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI; + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT); + /* reset the CH0CAPFLT bit */ + TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U); + /* set the CH0EN bit */ + TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN; + } + /* select TIMER input trigger source */ + timer_input_trigger_source_select(timer_periph, extrigger); + /* reset the SMC bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC); + /* set the SMC bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0; +} + +/*! + \brief configure TIMER the external clock mode0 + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + /* reset the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS)); + /* set the SMC bit,TRGS bit */ + TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP); +} + +/*! + \brief configure TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0,2) + \param[in] extprescaler: + only one parameter can be selected which is shown as below: + \arg TIMER_EXT_TRI_PSC_OFF: no divided + \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2 + \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4 + \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8 + \param[in] extpolarity: + only one parameter can be selected which is shown as below: + \arg TIMER_ETP_FALLING: active low or falling edge active + \arg TIMER_ETP_RISING: active high or rising edge active + \param[in] extfilter: a value between 0 and 15 + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, + uint32_t extpolarity, uint32_t extfilter) +{ + /* configure TIMER external trigger input */ + timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter); + + TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief disable TIMER the external clock mode1 + \param[in] timer_periph: TIMERx(x=0,2) + \param[out] none + \retval none +*/ +void timer_external_clock_mode1_disable(uint32_t timer_periph) +{ + TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1; +} + +/*! + \brief configure TIMER channel remap function + \param[in] timer_periph: TIMERx(x=13) + \param[in] remap: + only one parameter can be selected which is shown as below: + \arg TIMER13_CI0_RMP_GPIO: timer13 channel 0 input is connected to GPIO(TIMER13_CH0) + \arg TIMER13_CI0_RMP_RTCCLK: timer13 channel 0 input is connected to the RTCCLK + \arg TIMER13_CI0_RMP_HXTAL_DIV32: timer13 channel 0 input is connected to HXTAL/32 clock + \arg TIMER13_CI0_RMP_CKOUTSEL: timer13 channel 0 input is connected to CKOUTSEL + \param[out] none + \retval none +*/ +void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap) +{ + TIMER_IRMP(timer_periph) = (uint32_t)remap; +} + +/*! + \brief configure TIMER write CHxVAL register selection + \param[in] timer_periph: TIMERx(x=0,2,13..16) + \param[in] ccsel: + only one parameter can be selected which is shown as below: + \arg TIMER_CHVSEL_DISABLE: no effect + \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored + \param[out] none + \retval none +*/ +void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel) +{ + if(TIMER_CHVSEL_ENABLE == ccsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL; + } else if(TIMER_CHVSEL_DISABLE == ccsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL; + } else { + /* illegal parameters */ + } +} + +/*! + \brief configure TIMER output value selection + \param[in] timer_periph: TIMERx(x=0,14..16) + \param[in] outsel: + only one parameter can be selected which is shown as below: + \arg TIMER_OUTSEL_DISABLE: no effect + \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled + \param[out] none + \retval none +*/ +void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel) +{ + if(TIMER_OUTSEL_ENABLE == outsel) { + TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL; + } else if(TIMER_OUTSEL_DISABLE == outsel) { + TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL; + } else { + /* illegal parameters */ + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c index 3e0a0fa..8754ca5 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_usart.c @@ -1,1274 +1,1274 @@ -/*! - \file gd32e23x_usart.c - \brief USART driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_usart.h" - -/*! - \brief reset USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_deinit(uint32_t usart_periph) -{ - switch(usart_periph) { - case USART0: - /* reset USART0 */ - rcu_periph_reset_enable(RCU_USART0RST); - rcu_periph_reset_disable(RCU_USART0RST); - break; - case USART1: - /* reset USART1 */ - rcu_periph_reset_enable(RCU_USART1RST); - rcu_periph_reset_disable(RCU_USART1RST); - break; - default: - break; - } -} - -/*! - \brief configure USART baud rate value - \param[in] usart_periph: USARTx(x=0,1) - \param[in] baudval: baud rate value - \param[out] none - \retval none -*/ -void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) -{ - uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; - switch(usart_periph) { - /* get clock frequency */ - case USART0: - /* get USART0 clock */ - uclk = rcu_clock_freq_get(CK_USART); - break; - case USART1: - /* get USART1 clock */ - uclk = rcu_clock_freq_get(CK_APB1); - break; - default: - break; - } - if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { - /* oversampling by 8, configure the value of USART_BAUD */ - udiv = ((2U * uclk) + baudval / 2U) / baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = (udiv >> 1U) & 0x00000007U; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } else { - /* oversampling by 16, configure the value of USART_BAUD */ - udiv = (uclk + baudval / 2U) / baudval; - intdiv = udiv & 0x0000fff0U; - fradiv = udiv & 0x0000000fU; - USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); - } -} - -/*! - \brief configure USART parity - \param[in] usart_periph: USARTx(x=0,1) - \param[in] paritycfg: USART parity configure - only one parameter can be selected which is shown as below: - \arg USART_PM_NONE: no parity - \arg USART_PM_ODD: odd parity - \arg USART_PM_EVEN: even parity - \param[out] none - \retval none -*/ -void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 PM,PCEN bits */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); - /* configure USART parity mode */ - USART_CTL0(usart_periph) |= paritycfg; -} - -/*! - \brief configure USART word length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wlen: USART word length configure - only one parameter can be selected which is shown as below: - \arg USART_WL_8BIT: 8 bits - \arg USART_WL_9BIT: 9 bits - \param[out] none - \retval none -*/ -void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL0 WL bit */ - USART_CTL0(usart_periph) &= ~USART_CTL0_WL; - /* configure USART word length */ - USART_CTL0(usart_periph) |= wlen; -} - -/*! - \brief configure USART stop bit length - \param[in] usart_periph: USARTx(x=0,1) - \param[in] stblen: USART stop bit configure - only one parameter can be selected which is shown as below: - \arg USART_STB_1BIT: 1 bit - \arg USART_STB_0_5BIT: 0.5bit - \arg USART_STB_2BIT: 2 bits - \arg USART_STB_1_5BIT: 1.5bit - \param[out] none - \retval none -*/ -void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear USART_CTL1 STB bits */ - USART_CTL1(usart_periph) &= ~USART_CTL1_STB; - USART_CTL1(usart_periph) |= stblen; -} - -/*! - \brief enable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UEN; -} - -/*! - \brief disable USART - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); -} - -/*! - \brief configure USART transmitter - \param[in] usart_periph: USARTx(x=0,1) - \param[in] txconfig: enable or disable USART transmitter - only one parameter can be selected which is shown as below: - \arg USART_TRANSMIT_ENABLE: enable USART transmission - \arg USART_TRANSMIT_DISABLE: enable USART transmission - \param[out] none - \retval none -*/ -void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; - /* configure transfer mode */ - USART_CTL0(usart_periph) |= txconfig; -} - -/*! - \brief configure USART receiver - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rxconfig: enable or disable USART receiver - only one parameter can be selected which is shown as below: - \arg USART_RECEIVE_ENABLE: enable USART reception - \arg USART_RECEIVE_DISABLE: disable USART reception - \param[out] none - \retval none -*/ -void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) -{ - USART_CTL0(usart_periph) &= ~USART_CTL0_REN; - /* configure receiver mode */ - USART_CTL0(usart_periph) |= rxconfig; -} - -/*! - \brief data is transmitted/received with the LSB/MSB first - \param[in] usart_periph: USARTx(x=0,1) - \param[in] msbf: LSB/MSB - only one parameter can be selected which is shown as below: - \arg USART_MSBF_LSB: LSB first - \arg USART_MSBF_MSB: MSB first - \param[out] none - \retval none -*/ -void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* configure LSB or MSB first */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); - USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); -} - -/*! - \brief USART inverted configure - \param[in] usart_periph: USARTx(x=0,1) - \param[in] invertpara: refer to usart_invert_enum - only one parameter can be selected which is shown as below: - \arg USART_DINV_ENABLE: data bit level inversion - \arg USART_DINV_DISABLE: data bit level not inversion - \arg USART_TXPIN_ENABLE: TX pin level inversion - \arg USART_TXPIN_DISABLE: TX pin level not inversion - \arg USART_RXPIN_ENABLE: RX pin level inversion - \arg USART_RXPIN_DISABLE: RX pin level not inversion - \arg USART_SWAP_ENABLE: swap TX/RX pins - \arg USART_SWAP_DISABLE: not swap TX/RX pins - \param[out] none - \retval none -*/ -void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* inverted or not the specified signal */ - switch(invertpara) { - case USART_DINV_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_DINV; - break; - case USART_DINV_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); - break; - case USART_TXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_TINV; - break; - case USART_TXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); - break; - case USART_RXPIN_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_RINV; - break; - case USART_RXPIN_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); - break; - case USART_SWAP_ENABLE: - USART_CTL1(usart_periph) |= USART_CTL1_STRP; - break; - case USART_SWAP_DISABLE: - USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); - break; - default: - break; - } -} - -/*! - \brief enable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* enable overrun function */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); -} - -/*! - \brief disable the USART overrun function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_overrun_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* disable overrun function */ - USART_CTL2(usart_periph) |= USART_CTL2_OVRD; -} - -/*! - \brief configure the USART oversample mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] oversamp: oversample value - only one parameter can be selected which is shown as below: - \arg USART_OVSMOD_8: oversampling by 8 - \arg USART_OVSMOD_16: oversampling by 16 - \param[out] none - \retval none -*/ -void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* clear OVSMOD bit */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); - USART_CTL0(usart_periph) |= oversamp; -} - -/*! - \brief configure the sample bit method - \param[in] usart_periph: USARTx(x=0,1) - \param[in] osb: sample bit - only one parameter can be selected which is shown as below: - \arg USART_OSB_1BIT: 1 bit - \arg USART_OSB_3BIT: 3 bits - \param[out] none - \retval none -*/ -void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); - USART_CTL2(usart_periph) |= osb; -} - -/*! - \brief enable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_enable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) |= USART_CTL1_RTEN; -} - -/*! - \brief disable receiver timeout - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_receiver_timeout_disable(uint32_t usart_periph) -{ - USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); -} - -/*! - \brief configure receiver timeout threshold - \param[in] usart_periph: USARTx(x=0) - \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks - \param[out] none - \retval none -*/ -void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) -{ - USART_RT(usart_periph) &= ~(USART_RT_RT); - USART_RT(usart_periph) |= rtimeout; -} - -/*! - \brief USART transmit data function - \param[in] usart_periph: USARTx(x=0,1) - \param[in] data: data of transmission - \param[out] none - \retval none -*/ -void usart_data_transmit(uint32_t usart_periph, uint32_t data) -{ - USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); -} - -/*! - \brief USART receive data function - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval data of received -*/ -uint16_t usart_data_receive(uint32_t usart_periph) -{ - return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); -} - -/*! - \brief address of the USART terminal - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addr: 0x00-0xFF, address of USART terminal - \param[out] none - \retval none -*/ -void usart_address_config(uint32_t usart_periph, uint8_t addr) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); - USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24)); -} - -/*! - \brief configure address detection mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] addmod: address detection mode - only one parameter can be selected which is shown as below: - \arg USART_ADDM_4BIT: 4 bits - \arg USART_ADDM_FULLBIT: full bits - \param[out] none - \retval none -*/ -void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); - USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); -} - -/*! - \brief enable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_MEN; -} - -/*! - \brief disable mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_mute_mode_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); -} - -/*! - \brief configure wakeup method in mute mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] wmethod: two methods be used to enter or exit the mute mode - only one parameter can be selected which is shown as below: - \arg USART_WM_IDLE: idle line - \arg USART_WM_ADDR: address mark - \param[out] none - \retval none -*/ -void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); - USART_CTL0(usart_periph) |= wmethod; -} - -/*! - \brief enable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_LMEN; -} - -/*! - \brief disable LIN mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_lin_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); -} - -/*! - \brief LIN break detection length - \param[in] usart_periph: USARTx(x=0) - \param[in] lblen: LIN break detection length - only one parameter can be selected which is shown as below: - \arg USART_LBLEN_10B: 10 bits break detection - \arg USART_LBLEN_11B: 11 bits break detection - \param[out] none - \retval none -*/ -void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); - USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); -} - -/*! - \brief enable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_HDEN; -} - -/*! - \brief disable half-duplex mode - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_halfduplex_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); -} - -/*! - \brief enable clock - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_clock_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) |= USART_CTL1_CKEN; -} - -/*! - \brief disable clock - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_clock_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); -} - -/*! - \brief configure USART synchronous mode parameters - \param[in] usart_periph: USARTx(x=0,1) - \param[in] clen: last bit clock pulse - only one parameter can be selected which is shown as below: - \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin - \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin - \param[in] cph: clock phase - only one parameter can be selected which is shown as below: - \arg USART_CPH_1CK: first clock transition is the first data capture edge - \arg USART_CPH_2CK: second clock transition is the first data capture edge - \param[in] cpl: clock polarity - only one parameter can be selected which is shown as below: - \arg USART_CPL_LOW: steady low value on CK pin - \arg USART_CPL_HIGH: steady high value on CK pin - \param[out] none - \retval none -*/ -void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset USART_CTL1 CLEN,CPH,CPL bits */ - USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); - - USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); - USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); - USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); -} - -/*! - \brief configure guard time value in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] guat: 0x00-0xFF - \param[out] none - \retval none -*/ -void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_GP(usart_periph) &= ~(USART_GP_GUAT); - USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8)); -} - -/*! - \brief enable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_SCEN; -} - -/*! - \brief disable smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); -} - -/*! - \brief enable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_NKEN; -} - -/*! - \brief disable NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_nack_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); -} - -/*! - \brief enable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; -} - -/*! - \brief disable early NACK in smartcard mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; -} - -/*! - \brief configure smartcard auto-retry number - \param[in] usart_periph: USARTx(x=0) - \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number - \param[out] none - \retval none -*/ -void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); - USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17)); -} - -/*! - \brief configure block length - \param[in] usart_periph: USARTx(x=0) - \param[in] bl: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_block_length_config(uint32_t usart_periph, uint32_t bl) -{ - USART_RT(usart_periph) &= ~(USART_RT_BL); - USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24)); -} - -/*! - \brief enable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_IREN; -} - -/*! - \brief disable IrDA mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_irda_mode_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); -} - -/*! - \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode - \param[in] usart_periph: USARTx(x=0) - \param[in] psc: 0x00000000-0x000000FF - \param[out] none - \retval none -*/ -void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_GP(usart_periph) &= ~(USART_GP_PSC); - USART_GP(usart_periph) |= psc; -} - -/*! - \brief configure IrDA low-power - \param[in] usart_periph: USARTx(x=0) - \param[in] irlp: IrDA low-power or normal - only one parameter can be selected which is shown as below: - \arg USART_IRLP_LOW: low-power - \arg USART_IRLP_NORMAL: normal - \param[out] none - \retval none -*/ -void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); - USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); -} - -/*! - \brief configure hardware flow control RTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] rtsconfig: enable or disable RTS - only one parameter can be selected which is shown as below: - \arg USART_RTS_ENABLE: enable RTS - \arg USART_RTS_DISABLE: disable RTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); - USART_CTL2(usart_periph) |= rtsconfig; -} - -/*! - \brief configure hardware flow control CTS - \param[in] usart_periph: USARTx(x=0,1) - \param[in] ctsconfig: enable or disable CTS - only one parameter can be selected which is shown as below: - \arg USART_CTS_ENABLE: enable CTS - \arg USART_CTS_DISABLE: disable CTS - \param[out] none - \retval none -*/ -void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; - USART_CTL2(usart_periph) |= ctsconfig; -} - -/*! - \brief configure hardware flow control coherence mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] hcm: - only one parameter can be selected which is shown as below: - \arg USART_HCM_NONE: nRTS signal equals to the rxne status register - \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled - \param[out] none - \retval none -*/ -void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) -{ - USART_CHC(usart_periph) &= ~(USART_CHC_HCM); - USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); -} - -/*! - \brief enable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DEM; -} - -/*! - \brief disable RS485 driver - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_rs485_driver_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); -} - -/*! - \brief configure driver enable assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] deatime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); - USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21)); -} - -/*! - \brief configure driver enable de-assertion time - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dedtime: 0x00000000-0x0000001F - \param[out] none - \retval none -*/ -void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); - USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16)); -} - -/*! - \brief configure driver enable polarity mode - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dep: DE signal - only one parameter can be selected which is shown as below: - \arg USART_DEP_HIGH: DE signal is active high - \arg USART_DEP_LOW: DE signal is active low - \param[out] none - \retval none -*/ -void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset DEP bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); - USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); -} - -/*! - \brief configure USART DMA reception - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for reception - only one parameter can be selected which is shown as below: - \arg USART_DENR_ENABLE: DMA enable for reception - \arg USART_DENR_DISABLE: DMA disable for reception - \param[out] none - \retval none -*/ -void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; - /* configure DMA reception */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief configure USART DMA transmission - \param[in] usart_periph: USARTx(x=0,1) - \param[in] dmacmd: enable or disable DMA for transmission - only one parameter can be selected which is shown as below: - \arg USART_DENT_ENABLE: DMA enable for transmission - \arg USART_DENT_DISABLE: DMA disable for transmission - \param[out] none - \retval none -*/ -void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) -{ - USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; - /* configure DMA transmission */ - USART_CTL2(usart_periph) |= dmacmd; -} - -/*! - \brief disable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_disable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) |= USART_CTL2_DDRE; -} - -/*! - \brief enable DMA on reception error - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_reception_error_dma_enable(uint32_t usart_periph) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - - USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); -} - -/*! - \brief enable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_enable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) |= USART_CTL0_UESM; -} - -/*! - \brief disable USART to wakeup the mcu from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[out] none - \retval none -*/ -void usart_wakeup_disable(uint32_t usart_periph) -{ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); -} - -/*! - \brief configure the USART wakeup mode from deep-sleep mode - \param[in] usart_periph: USARTx(x=0) - \param[in] wum: wakeup mode - only one parameter can be selected which is shown as below: - \arg USART_WUM_ADDR: WUF active on address match - \arg USART_WUM_STARTB: WUF active on start bit - \arg USART_WUM_RBNE: WUF active on RBNE - \param[out] none - \retval none -*/ -void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) -{ - /* disable USART */ - USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); - /* reset WUM bit */ - USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); - USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); -} - -/*! - \brief enable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_enable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) |= USART_RFCS_RFEN; -} - -/*! - \brief disable receive FIFO - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval none -*/ -void usart_receive_fifo_disable(uint32_t usart_periph) -{ - USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); -} - -/*! - \brief read receive FIFO counter number - \param[in] usart_periph: USARTx(x=0,1) - \param[out] none - \retval receive FIFO counter number -*/ -uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) -{ - return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); -} - -/*! - \brief get flag in STAT/CHC/RFCS register - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise error flag - \arg USART_FLAG_ORERR: overrun error - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_RBNE: read data buffer not empty - \arg USART_FLAG_TC: transmission completed - \arg USART_FLAG_TBE: transmit data register empty - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_CTS: CTS level - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_BSY: busy flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_SB: send break flag - \arg USART_FLAG_RWU: receiver wakeup from mute mode. - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_TEA: transmit enable acknowledge flag - \arg USART_FLAG_REA: receive enable acknowledge flag - \arg USART_FLAG_EPERR: early parity error flag - \arg USART_FLAG_RFE: receive FIFO empty flag - \arg USART_FLAG_RFF: receive FIFO full flag - \arg USART_FLAG_RFFINT: receive FIFO full interrupt flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) -{ - if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear USART status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: flag type - only one parameter can be selected which is shown as below: - \arg USART_FLAG_PERR: parity error flag - \arg USART_FLAG_FERR: frame error flag - \arg USART_FLAG_NERR: noise detected flag - \arg USART_FLAG_ORERR: overrun error flag - \arg USART_FLAG_IDLE: idle line detected flag - \arg USART_FLAG_TC: transmission complete flag - \arg USART_FLAG_LBD: LIN break detected flag - \arg USART_FLAG_CTSF: CTS change flag - \arg USART_FLAG_RT: receiver timeout flag - \arg USART_FLAG_EB: end of block flag - \arg USART_FLAG_AM: address match flag - \arg USART_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_FLAG_EPERR: early parity error flag - \param[out] none - \retval none -*/ -void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) -{ - USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); -} - -/*! - \brief enable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] inttype: interrupt type - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt enable interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief disable USART interrupt - \param[in] usart_periph: USARTx(x=0,1) - \param[in] inttype: interrupt type - only one parameter can be selected which is shown as below: - \arg USART_INT_IDLE: idle interrupt - \arg USART_INT_RBNE: read data buffer not empty interrupt and - overrun error interrupt - \arg USART_INT_TC: transmission complete interrupt - \arg USART_INT_TBE: transmit data register empty interrupt - \arg USART_INT_PERR: parity error interrupt - \arg USART_INT_AM: address match interrupt - \arg USART_INT_RT: receiver timeout interrupt - \arg USART_INT_EB: end of block interrupt - \arg USART_INT_LBD: LIN break detection interrupt - \arg USART_INT_ERR: error interrupt enable in multibuffer communication - \arg USART_INT_CTS: CTS interrupt - \arg USART_INT_WU: wakeup from deep-sleep mode interrupt - \arg USART_INT_RFF: receive FIFO full interrupt enable - \param[out] none - \retval none -*/ -void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) -{ - USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); -} - -/*! - \brief enable USART command - \param[in] usart_periph: USARTx(x=0,1) - \param[in] cmdtype: command type - only one parameter can be selected which is shown as below: - \arg USART_CMD_SBKCMD: send break command - \arg USART_CMD_MMCMD: mute mode command - \arg USART_CMD_RXFCMD: receive data flush command - \arg USART_CMD_TXFCMD: transmit data flush request - \param[out] none - \retval none -*/ -void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) -{ - USART_CMD(usart_periph) |= (cmdtype); -} - -/*! - \brief get USART interrupt and flag status - \param[in] usart_periph: USARTx(x=0,1) - \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_EB: end of block interrupt and flag - \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag - \arg USART_INT_FLAG_AM: address match interrupt and flag - \arg USART_INT_FLAG_PERR: parity error interrupt and flag - \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag - \arg USART_INT_FLAG_TC: transmission complete interrupt and flag - \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag - \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag - \arg USART_INT_FLAG_CTS: CTS interrupt and flag - \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag - \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) -{ - uint32_t intenable = 0U, flagstatus = 0U; - /* get the interrupt enable bit status */ - intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); - /* get the corresponding flag bit status */ - flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); - - if(flagstatus && intenable) { - return SET; - } else { - return RESET; - } -} - -/*! - \brief clear USART interrupt flag - \param[in] usart_periph: USARTx(x=0,1) - \param[in] flag: USART interrupt flag - only one parameter can be selected which is shown as below: - \arg USART_INT_FLAG_PERR: parity error flag - \arg USART_INT_FLAG_ERR_FERR: frame error flag - \arg USART_INT_FLAG_ERR_NERR: noise detected flag - \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag - \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error - \arg USART_INT_FLAG_IDLE: idle line detected flag - \arg USART_INT_FLAG_TC: transmission complete flag - \arg USART_INT_FLAG_LBD: LIN break detected flag - \arg USART_INT_FLAG_CTS: CTS change flag - \arg USART_INT_FLAG_RT: receiver timeout flag - \arg USART_INT_FLAG_EB: end of block flag - \arg USART_INT_FLAG_AM: address match flag - \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag - \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag - \param[out] none - \retval none -*/ -void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag) -{ - if(USART_INT_FLAG_RFF == flag) { - USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); - } else { - USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag)); - } -} +/*! + \file gd32e23x_usart.c + \brief USART driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_usart.h" + +/*! + \brief reset USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_deinit(uint32_t usart_periph) +{ + switch(usart_periph) { + case USART0: + /* reset USART0 */ + rcu_periph_reset_enable(RCU_USART0RST); + rcu_periph_reset_disable(RCU_USART0RST); + break; + case USART1: + /* reset USART1 */ + rcu_periph_reset_enable(RCU_USART1RST); + rcu_periph_reset_disable(RCU_USART1RST); + break; + default: + break; + } +} + +/*! + \brief configure USART baud rate value + \param[in] usart_periph: USARTx(x=0,1) + \param[in] baudval: baud rate value + \param[out] none + \retval none +*/ +void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval) +{ + uint32_t uclk = 0U, intdiv = 0U, fradiv = 0U, udiv = 0U; + switch(usart_periph) { + /* get clock frequency */ + case USART0: + /* get USART0 clock */ + uclk = rcu_clock_freq_get(CK_USART); + break; + case USART1: + /* get USART1 clock */ + uclk = rcu_clock_freq_get(CK_APB1); + break; + default: + break; + } + if(USART_CTL0(usart_periph) & USART_CTL0_OVSMOD) { + /* oversampling by 8, configure the value of USART_BAUD */ + udiv = ((2U * uclk) + baudval / 2U) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = (udiv >> 1U) & 0x00000007U; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } else { + /* oversampling by 16, configure the value of USART_BAUD */ + udiv = (uclk + baudval / 2U) / baudval; + intdiv = udiv & 0x0000fff0U; + fradiv = udiv & 0x0000000fU; + USART_BAUD(usart_periph) = ((USART_BAUD_FRADIV | USART_BAUD_INTDIV) & (intdiv | fradiv)); + } +} + +/*! + \brief configure USART parity + \param[in] usart_periph: USARTx(x=0,1) + \param[in] paritycfg: USART parity configure + only one parameter can be selected which is shown as below: + \arg USART_PM_NONE: no parity + \arg USART_PM_ODD: odd parity + \arg USART_PM_EVEN: even parity + \param[out] none + \retval none +*/ +void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 PM,PCEN bits */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_PM | USART_CTL0_PCEN); + /* configure USART parity mode */ + USART_CTL0(usart_periph) |= paritycfg; +} + +/*! + \brief configure USART word length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wlen: USART word length configure + only one parameter can be selected which is shown as below: + \arg USART_WL_8BIT: 8 bits + \arg USART_WL_9BIT: 9 bits + \param[out] none + \retval none +*/ +void usart_word_length_set(uint32_t usart_periph, uint32_t wlen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL0 WL bit */ + USART_CTL0(usart_periph) &= ~USART_CTL0_WL; + /* configure USART word length */ + USART_CTL0(usart_periph) |= wlen; +} + +/*! + \brief configure USART stop bit length + \param[in] usart_periph: USARTx(x=0,1) + \param[in] stblen: USART stop bit configure + only one parameter can be selected which is shown as below: + \arg USART_STB_1BIT: 1 bit + \arg USART_STB_0_5BIT: 0.5bit + \arg USART_STB_2BIT: 2 bits + \arg USART_STB_1_5BIT: 1.5bit + \param[out] none + \retval none +*/ +void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear USART_CTL1 STB bits */ + USART_CTL1(usart_periph) &= ~USART_CTL1_STB; + USART_CTL1(usart_periph) |= stblen; +} + +/*! + \brief enable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UEN; +} + +/*! + \brief disable USART + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); +} + +/*! + \brief configure USART transmitter + \param[in] usart_periph: USARTx(x=0,1) + \param[in] txconfig: enable or disable USART transmitter + only one parameter can be selected which is shown as below: + \arg USART_TRANSMIT_ENABLE: enable USART transmission + \arg USART_TRANSMIT_DISABLE: enable USART transmission + \param[out] none + \retval none +*/ +void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_TEN; + /* configure transfer mode */ + USART_CTL0(usart_periph) |= txconfig; +} + +/*! + \brief configure USART receiver + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rxconfig: enable or disable USART receiver + only one parameter can be selected which is shown as below: + \arg USART_RECEIVE_ENABLE: enable USART reception + \arg USART_RECEIVE_DISABLE: disable USART reception + \param[out] none + \retval none +*/ +void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig) +{ + USART_CTL0(usart_periph) &= ~USART_CTL0_REN; + /* configure receiver mode */ + USART_CTL0(usart_periph) |= rxconfig; +} + +/*! + \brief data is transmitted/received with the LSB/MSB first + \param[in] usart_periph: USARTx(x=0,1) + \param[in] msbf: LSB/MSB + only one parameter can be selected which is shown as below: + \arg USART_MSBF_LSB: LSB first + \arg USART_MSBF_MSB: MSB first + \param[out] none + \retval none +*/ +void usart_data_first_config(uint32_t usart_periph, uint32_t msbf) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* configure LSB or MSB first */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_MSBF); + USART_CTL1(usart_periph) |= (USART_CTL1_MSBF & msbf); +} + +/*! + \brief USART inverted configure + \param[in] usart_periph: USARTx(x=0,1) + \param[in] invertpara: refer to usart_invert_enum + only one parameter can be selected which is shown as below: + \arg USART_DINV_ENABLE: data bit level inversion + \arg USART_DINV_DISABLE: data bit level not inversion + \arg USART_TXPIN_ENABLE: TX pin level inversion + \arg USART_TXPIN_DISABLE: TX pin level not inversion + \arg USART_RXPIN_ENABLE: RX pin level inversion + \arg USART_RXPIN_DISABLE: RX pin level not inversion + \arg USART_SWAP_ENABLE: swap TX/RX pins + \arg USART_SWAP_DISABLE: not swap TX/RX pins + \param[out] none + \retval none +*/ +void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* inverted or not the specified signal */ + switch(invertpara) { + case USART_DINV_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_DINV; + break; + case USART_DINV_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_DINV); + break; + case USART_TXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_TINV; + break; + case USART_TXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_TINV); + break; + case USART_RXPIN_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_RINV; + break; + case USART_RXPIN_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_RINV); + break; + case USART_SWAP_ENABLE: + USART_CTL1(usart_periph) |= USART_CTL1_STRP; + break; + case USART_SWAP_DISABLE: + USART_CTL1(usart_periph) &= ~(USART_CTL1_STRP); + break; + default: + break; + } +} + +/*! + \brief enable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* enable overrun function */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_OVRD); +} + +/*! + \brief disable the USART overrun function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_overrun_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* disable overrun function */ + USART_CTL2(usart_periph) |= USART_CTL2_OVRD; +} + +/*! + \brief configure the USART oversample mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] oversamp: oversample value + only one parameter can be selected which is shown as below: + \arg USART_OVSMOD_8: oversampling by 8 + \arg USART_OVSMOD_16: oversampling by 16 + \param[out] none + \retval none +*/ +void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* clear OVSMOD bit */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_OVSMOD); + USART_CTL0(usart_periph) |= oversamp; +} + +/*! + \brief configure the sample bit method + \param[in] usart_periph: USARTx(x=0,1) + \param[in] osb: sample bit + only one parameter can be selected which is shown as below: + \arg USART_OSB_1BIT: 1 bit + \arg USART_OSB_3BIT: 3 bits + \param[out] none + \retval none +*/ +void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_OSB); + USART_CTL2(usart_periph) |= osb; +} + +/*! + \brief enable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_enable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) |= USART_CTL1_RTEN; +} + +/*! + \brief disable receiver timeout + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_receiver_timeout_disable(uint32_t usart_periph) +{ + USART_CTL1(usart_periph) &= ~(USART_CTL1_RTEN); +} + +/*! + \brief configure receiver timeout threshold + \param[in] usart_periph: USARTx(x=0) + \param[in] rtimeout: 0x00000000-0x00FFFFFF, receiver timeout value in terms of number of baud clocks + \param[out] none + \retval none +*/ +void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout) +{ + USART_RT(usart_periph) &= ~(USART_RT_RT); + USART_RT(usart_periph) |= rtimeout; +} + +/*! + \brief USART transmit data function + \param[in] usart_periph: USARTx(x=0,1) + \param[in] data: data of transmission + \param[out] none + \retval none +*/ +void usart_data_transmit(uint32_t usart_periph, uint32_t data) +{ + USART_TDATA(usart_periph) = (USART_TDATA_TDATA & data); +} + +/*! + \brief USART receive data function + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval data of received +*/ +uint16_t usart_data_receive(uint32_t usart_periph) +{ + return (uint16_t)(GET_BITS(USART_RDATA(usart_periph), 0U, 8U)); +} + +/*! + \brief address of the USART terminal + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addr: 0x00-0xFF, address of USART terminal + \param[out] none + \retval none +*/ +void usart_address_config(uint32_t usart_periph, uint8_t addr) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDR); + USART_CTL1(usart_periph) |= (USART_CTL1_ADDR & (((uint32_t)addr) << 24)); +} + +/*! + \brief configure address detection mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] addmod: address detection mode + only one parameter can be selected which is shown as below: + \arg USART_ADDM_4BIT: 4 bits + \arg USART_ADDM_FULLBIT: full bits + \param[out] none + \retval none +*/ +void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_ADDM); + USART_CTL1(usart_periph) |= USART_CTL1_ADDM & (addmod); +} + +/*! + \brief enable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_MEN; +} + +/*! + \brief disable mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_mute_mode_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_MEN); +} + +/*! + \brief configure wakeup method in mute mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] wmethod: two methods be used to enter or exit the mute mode + only one parameter can be selected which is shown as below: + \arg USART_WM_IDLE: idle line + \arg USART_WM_ADDR: address mark + \param[out] none + \retval none +*/ +void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_WM); + USART_CTL0(usart_periph) |= wmethod; +} + +/*! + \brief enable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_LMEN; +} + +/*! + \brief disable LIN mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_lin_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_LMEN); +} + +/*! + \brief LIN break detection length + \param[in] usart_periph: USARTx(x=0) + \param[in] lblen: LIN break detection length + only one parameter can be selected which is shown as below: + \arg USART_LBLEN_10B: 10 bits break detection + \arg USART_LBLEN_11B: 11 bits break detection + \param[out] none + \retval none +*/ +void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL1(usart_periph) &= ~(USART_CTL1_LBLEN); + USART_CTL1(usart_periph) |= USART_CTL1_LBLEN & (lblen); +} + +/*! + \brief enable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_HDEN; +} + +/*! + \brief disable half-duplex mode + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_halfduplex_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_HDEN); +} + +/*! + \brief enable clock + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_clock_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) |= USART_CTL1_CKEN; +} + +/*! + \brief disable clock + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_clock_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL1(usart_periph) &= ~(USART_CTL1_CKEN); +} + +/*! + \brief configure USART synchronous mode parameters + \param[in] usart_periph: USARTx(x=0,1) + \param[in] clen: last bit clock pulse + only one parameter can be selected which is shown as below: + \arg USART_CLEN_NONE: clock pulse of the last data bit (MSB) is not output to the CK pin + \arg USART_CLEN_EN: clock pulse of the last data bit (MSB) is output to the CK pin + \param[in] cph: clock phase + only one parameter can be selected which is shown as below: + \arg USART_CPH_1CK: first clock transition is the first data capture edge + \arg USART_CPH_2CK: second clock transition is the first data capture edge + \param[in] cpl: clock polarity + only one parameter can be selected which is shown as below: + \arg USART_CPL_LOW: steady low value on CK pin + \arg USART_CPL_HIGH: steady high value on CK pin + \param[out] none + \retval none +*/ +void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset USART_CTL1 CLEN,CPH,CPL bits */ + USART_CTL1(usart_periph) &= ~(USART_CTL1_CLEN | USART_CTL1_CPH | USART_CTL1_CPL); + + USART_CTL1(usart_periph) |= (USART_CTL1_CLEN & clen); + USART_CTL1(usart_periph) |= (USART_CTL1_CPH & cph); + USART_CTL1(usart_periph) |= (USART_CTL1_CPL & cpl); +} + +/*! + \brief configure guard time value in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] guat: 0x00-0xFF + \param[out] none + \retval none +*/ +void usart_guard_time_config(uint32_t usart_periph, uint32_t guat) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_GP(usart_periph) &= ~(USART_GP_GUAT); + USART_GP(usart_periph) |= (USART_GP_GUAT & ((guat) << 8)); +} + +/*! + \brief enable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_SCEN; +} + +/*! + \brief disable smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCEN); +} + +/*! + \brief enable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_NKEN; +} + +/*! + \brief disable NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_nack_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_NKEN); +} + +/*! + \brief enable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_ELNACK; +} + +/*! + \brief disable early NACK in smartcard mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~USART_RFCS_ELNACK; +} + +/*! + \brief configure smartcard auto-retry number + \param[in] usart_periph: USARTx(x=0) + \param[in] scrtnum: 0x00000000-0x00000007, smartcard auto-retry number + \param[out] none + \retval none +*/ +void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_SCRTNUM); + USART_CTL2(usart_periph) |= (USART_CTL2_SCRTNUM & (scrtnum << 17)); +} + +/*! + \brief configure block length + \param[in] usart_periph: USARTx(x=0) + \param[in] bl: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_block_length_config(uint32_t usart_periph, uint32_t bl) +{ + USART_RT(usart_periph) &= ~(USART_RT_BL); + USART_RT(usart_periph) |= (USART_RT_BL & ((bl) << 24)); +} + +/*! + \brief enable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_IREN; +} + +/*! + \brief disable IrDA mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_irda_mode_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_IREN); +} + +/*! + \brief configure the peripheral clock prescaler in USART IrDA low-power or SmartCard mode + \param[in] usart_periph: USARTx(x=0) + \param[in] psc: 0x00000000-0x000000FF + \param[out] none + \retval none +*/ +void usart_prescaler_config(uint32_t usart_periph, uint32_t psc) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_GP(usart_periph) &= ~(USART_GP_PSC); + USART_GP(usart_periph) |= psc; +} + +/*! + \brief configure IrDA low-power + \param[in] usart_periph: USARTx(x=0) + \param[in] irlp: IrDA low-power or normal + only one parameter can be selected which is shown as below: + \arg USART_IRLP_LOW: low-power + \arg USART_IRLP_NORMAL: normal + \param[out] none + \retval none +*/ +void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + USART_CTL2(usart_periph) &= ~(USART_CTL2_IRLP); + USART_CTL2(usart_periph) |= (USART_CTL2_IRLP & irlp); +} + +/*! + \brief configure hardware flow control RTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] rtsconfig: enable or disable RTS + only one parameter can be selected which is shown as below: + \arg USART_RTS_ENABLE: enable RTS + \arg USART_RTS_DISABLE: disable RTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_RTSEN); + USART_CTL2(usart_periph) |= rtsconfig; +} + +/*! + \brief configure hardware flow control CTS + \param[in] usart_periph: USARTx(x=0,1) + \param[in] ctsconfig: enable or disable CTS + only one parameter can be selected which is shown as below: + \arg USART_CTS_ENABLE: enable CTS + \arg USART_CTS_DISABLE: disable CTS + \param[out] none + \retval none +*/ +void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~USART_CTL2_CTSEN; + USART_CTL2(usart_periph) |= ctsconfig; +} + +/*! + \brief configure hardware flow control coherence mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] hcm: + only one parameter can be selected which is shown as below: + \arg USART_HCM_NONE: nRTS signal equals to the rxne status register + \arg USART_HCM_EN: nRTS signal is set when the last data bit has been sampled + \param[out] none + \retval none +*/ +void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm) +{ + USART_CHC(usart_periph) &= ~(USART_CHC_HCM); + USART_CHC(usart_periph) |= (USART_CHC_HCM & hcm); +} + +/*! + \brief enable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DEM; +} + +/*! + \brief disable RS485 driver + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_rs485_driver_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEM); +} + +/*! + \brief configure driver enable assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] deatime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DEA); + USART_CTL0(usart_periph) |= (USART_CTL0_DEA & ((deatime) << 21)); +} + +/*! + \brief configure driver enable de-assertion time + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dedtime: 0x00000000-0x0000001F + \param[out] none + \retval none +*/ +void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL0(usart_periph) &= ~(USART_CTL0_DED); + USART_CTL0(usart_periph) |= (USART_CTL0_DED & ((dedtime) << 16)); +} + +/*! + \brief configure driver enable polarity mode + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dep: DE signal + only one parameter can be selected which is shown as below: + \arg USART_DEP_HIGH: DE signal is active high + \arg USART_DEP_LOW: DE signal is active low + \param[out] none + \retval none +*/ +void usart_depolarity_config(uint32_t usart_periph, uint32_t dep) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset DEP bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_DEP); + USART_CTL2(usart_periph) |= (USART_CTL2_DEP & dep); +} + +/*! + \brief configure USART DMA reception + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for reception + only one parameter can be selected which is shown as below: + \arg USART_DENR_ENABLE: DMA enable for reception + \arg USART_DENR_DISABLE: DMA disable for reception + \param[out] none + \retval none +*/ +void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENR; + /* configure DMA reception */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief configure USART DMA transmission + \param[in] usart_periph: USARTx(x=0,1) + \param[in] dmacmd: enable or disable DMA for transmission + only one parameter can be selected which is shown as below: + \arg USART_DENT_ENABLE: DMA enable for transmission + \arg USART_DENT_DISABLE: DMA disable for transmission + \param[out] none + \retval none +*/ +void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd) +{ + USART_CTL2(usart_periph) &= ~USART_CTL2_DENT; + /* configure DMA transmission */ + USART_CTL2(usart_periph) |= dmacmd; +} + +/*! + \brief disable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_disable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) |= USART_CTL2_DDRE; +} + +/*! + \brief enable DMA on reception error + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_reception_error_dma_enable(uint32_t usart_periph) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + + USART_CTL2(usart_periph) &= ~(USART_CTL2_DDRE); +} + +/*! + \brief enable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_enable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) |= USART_CTL0_UESM; +} + +/*! + \brief disable USART to wakeup the mcu from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[out] none + \retval none +*/ +void usart_wakeup_disable(uint32_t usart_periph) +{ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UESM); +} + +/*! + \brief configure the USART wakeup mode from deep-sleep mode + \param[in] usart_periph: USARTx(x=0) + \param[in] wum: wakeup mode + only one parameter can be selected which is shown as below: + \arg USART_WUM_ADDR: WUF active on address match + \arg USART_WUM_STARTB: WUF active on start bit + \arg USART_WUM_RBNE: WUF active on RBNE + \param[out] none + \retval none +*/ +void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum) +{ + /* disable USART */ + USART_CTL0(usart_periph) &= ~(USART_CTL0_UEN); + /* reset WUM bit */ + USART_CTL2(usart_periph) &= ~(USART_CTL2_WUM); + USART_CTL2(usart_periph) |= USART_CTL2_WUM & (wum); +} + +/*! + \brief enable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_enable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) |= USART_RFCS_RFEN; +} + +/*! + \brief disable receive FIFO + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval none +*/ +void usart_receive_fifo_disable(uint32_t usart_periph) +{ + USART_RFCS(usart_periph) &= ~(USART_RFCS_RFEN); +} + +/*! + \brief read receive FIFO counter number + \param[in] usart_periph: USARTx(x=0,1) + \param[out] none + \retval receive FIFO counter number +*/ +uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph) +{ + return (uint8_t)(GET_BITS(USART_RFCS(usart_periph), 12U, 14U)); +} + +/*! + \brief get flag in STAT/CHC/RFCS register + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise error flag + \arg USART_FLAG_ORERR: overrun error + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_RBNE: read data buffer not empty + \arg USART_FLAG_TC: transmission completed + \arg USART_FLAG_TBE: transmit data register empty + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_CTS: CTS level + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_BSY: busy flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_SB: send break flag + \arg USART_FLAG_RWU: receiver wakeup from mute mode. + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_TEA: transmit enable acknowledge flag + \arg USART_FLAG_REA: receive enable acknowledge flag + \arg USART_FLAG_EPERR: early parity error flag + \arg USART_FLAG_RFE: receive FIFO empty flag + \arg USART_FLAG_RFF: receive FIFO full flag + \arg USART_FLAG_RFFINT: receive FIFO full interrupt flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag) +{ + if(RESET != (USART_REG_VAL(usart_periph, flag) & BIT(USART_BIT_POS(flag)))) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: flag type + only one parameter can be selected which is shown as below: + \arg USART_FLAG_PERR: parity error flag + \arg USART_FLAG_FERR: frame error flag + \arg USART_FLAG_NERR: noise detected flag + \arg USART_FLAG_ORERR: overrun error flag + \arg USART_FLAG_IDLE: idle line detected flag + \arg USART_FLAG_TC: transmission complete flag + \arg USART_FLAG_LBD: LIN break detected flag + \arg USART_FLAG_CTSF: CTS change flag + \arg USART_FLAG_RT: receiver timeout flag + \arg USART_FLAG_EB: end of block flag + \arg USART_FLAG_AM: address match flag + \arg USART_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_FLAG_EPERR: early parity error flag + \param[out] none + \retval none +*/ +void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag) +{ + USART_INTC(usart_periph) |= BIT(USART_BIT_POS(flag)); +} + +/*! + \brief enable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] inttype: interrupt type + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt enable interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) |= BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief disable USART interrupt + \param[in] usart_periph: USARTx(x=0,1) + \param[in] inttype: interrupt type + only one parameter can be selected which is shown as below: + \arg USART_INT_IDLE: idle interrupt + \arg USART_INT_RBNE: read data buffer not empty interrupt and + overrun error interrupt + \arg USART_INT_TC: transmission complete interrupt + \arg USART_INT_TBE: transmit data register empty interrupt + \arg USART_INT_PERR: parity error interrupt + \arg USART_INT_AM: address match interrupt + \arg USART_INT_RT: receiver timeout interrupt + \arg USART_INT_EB: end of block interrupt + \arg USART_INT_LBD: LIN break detection interrupt + \arg USART_INT_ERR: error interrupt enable in multibuffer communication + \arg USART_INT_CTS: CTS interrupt + \arg USART_INT_WU: wakeup from deep-sleep mode interrupt + \arg USART_INT_RFF: receive FIFO full interrupt enable + \param[out] none + \retval none +*/ +void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt) +{ + USART_REG_VAL(usart_periph, interrupt) &= ~BIT(USART_BIT_POS(interrupt)); +} + +/*! + \brief enable USART command + \param[in] usart_periph: USARTx(x=0,1) + \param[in] cmdtype: command type + only one parameter can be selected which is shown as below: + \arg USART_CMD_SBKCMD: send break command + \arg USART_CMD_MMCMD: mute mode command + \arg USART_CMD_RXFCMD: receive data flush command + \arg USART_CMD_TXFCMD: transmit data flush request + \param[out] none + \retval none +*/ +void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype) +{ + USART_CMD(usart_periph) |= (cmdtype); +} + +/*! + \brief get USART interrupt and flag status + \param[in] usart_periph: USARTx(x=0,1) + \param[in] int_flag: interrupt and flag type, refer to usart_interrupt_flag_enum + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_EB: end of block interrupt and flag + \arg USART_INT_FLAG_RT: receiver timeout interrupt and flag + \arg USART_INT_FLAG_AM: address match interrupt and flag + \arg USART_INT_FLAG_PERR: parity error interrupt and flag + \arg USART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag + \arg USART_INT_FLAG_TC: transmission complete interrupt and flag + \arg USART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_IDLE: IDLE line detected interrupt and flag + \arg USART_INT_FLAG_LBD: LIN break detected interrupt and flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag + \arg USART_INT_FLAG_CTS: CTS interrupt and flag + \arg USART_INT_FLAG_ERR_NERR: error interrupt and noise error flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_ERR_FERR: error interrupt and frame error flag + \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag) +{ + uint32_t intenable = 0U, flagstatus = 0U; + /* get the interrupt enable bit status */ + intenable = (USART_REG_VAL(usart_periph, int_flag) & BIT(USART_BIT_POS(int_flag))); + /* get the corresponding flag bit status */ + flagstatus = (USART_REG_VAL2(usart_periph, int_flag) & BIT(USART_BIT_POS2(int_flag))); + + if(flagstatus && intenable) { + return SET; + } else { + return RESET; + } +} + +/*! + \brief clear USART interrupt flag + \param[in] usart_periph: USARTx(x=0,1) + \param[in] flag: USART interrupt flag + only one parameter can be selected which is shown as below: + \arg USART_INT_FLAG_PERR: parity error flag + \arg USART_INT_FLAG_ERR_FERR: frame error flag + \arg USART_INT_FLAG_ERR_NERR: noise detected flag + \arg USART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag + \arg USART_INT_FLAG_ERR_ORERR: error interrupt and overrun error + \arg USART_INT_FLAG_IDLE: idle line detected flag + \arg USART_INT_FLAG_TC: transmission complete flag + \arg USART_INT_FLAG_LBD: LIN break detected flag + \arg USART_INT_FLAG_CTS: CTS change flag + \arg USART_INT_FLAG_RT: receiver timeout flag + \arg USART_INT_FLAG_EB: end of block flag + \arg USART_INT_FLAG_AM: address match flag + \arg USART_INT_FLAG_WU: wakeup from deep-sleep mode flag + \arg USART_INT_FLAG_RFF: receive FIFO full interrupt and flag + \param[out] none + \retval none +*/ +void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag) +{ + if(USART_INT_FLAG_RFF == flag) { + USART_RFCS(usart_periph) &= (uint32_t)(~USART_RFCS_RFFINT); + } else { + USART_INTC(usart_periph) |= BIT(USART_BIT_POS2(flag)); + } +} diff --git a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c index 0211ad6..5232aa3 100644 --- a/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c +++ b/SDK/GD32E23x_standard_peripheral/Source/gd32e23x_wwdgt.c @@ -1,126 +1,126 @@ -/*! - \file gd32e23x_wwdgt.c - \brief WWDGT driver - - \version 2025-02-10, V2.3.0, firmware for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_wwdgt.h" - -/*! - \brief reset the window watchdog timer configuration - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_deinit(void) -{ - rcu_periph_reset_enable(RCU_WWDGTRST); - rcu_periph_reset_disable(RCU_WWDGTRST); -} - -/*! - \brief start the window watchdog timer counter - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_enable(void) -{ - WWDGT_CTL |= WWDGT_CTL_WDGTEN; -} - -/*! - \brief configure the window watchdog timer counter value - \param[in] counter_value: 0x00000000 - 0x0000007F - \param[out] none - \retval none -*/ -void wwdgt_counter_update(uint16_t counter_value) -{ - WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); -} - -/*! - \brief configure counter value, window value, and prescaler divider value - \param[in] counter: 0x00000000 - 0x0000007F - \param[in] window: 0x00000000 - 0x0000007F - \param[in] prescaler: wwdgt prescaler value - only one parameter can be selected which is shown as below: - \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 - \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 - \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 - \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 - \param[out] none - \retval none -*/ -void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) -{ - WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); - WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); -} - -/*! - \brief check early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval FlagStatus: SET or RESET -*/ -FlagStatus wwdgt_flag_get(void) -{ - if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)) { - return SET; - } - return RESET; -} - -/*! - \brief clear early wakeup interrupt state of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_flag_clear(void) -{ - WWDGT_STAT &= (~(uint32_t)WWDGT_STAT_EWIF); -} - -/*! - \brief enable early wakeup interrupt of WWDGT - \param[in] none - \param[out] none - \retval none -*/ -void wwdgt_interrupt_enable(void) -{ - WWDGT_CFG |= WWDGT_CFG_EWIE; -} +/*! + \file gd32e23x_wwdgt.c + \brief WWDGT driver + + \version 2025-02-10, V2.3.0, firmware for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_wwdgt.h" + +/*! + \brief reset the window watchdog timer configuration + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_deinit(void) +{ + rcu_periph_reset_enable(RCU_WWDGTRST); + rcu_periph_reset_disable(RCU_WWDGTRST); +} + +/*! + \brief start the window watchdog timer counter + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_enable(void) +{ + WWDGT_CTL |= WWDGT_CTL_WDGTEN; +} + +/*! + \brief configure the window watchdog timer counter value + \param[in] counter_value: 0x00000000 - 0x0000007F + \param[out] none + \retval none +*/ +void wwdgt_counter_update(uint16_t counter_value) +{ + WWDGT_CTL = (uint32_t)(CTL_CNT(counter_value)); +} + +/*! + \brief configure counter value, window value, and prescaler divider value + \param[in] counter: 0x00000000 - 0x0000007F + \param[in] window: 0x00000000 - 0x0000007F + \param[in] prescaler: wwdgt prescaler value + only one parameter can be selected which is shown as below: + \arg WWDGT_CFG_PSC_DIV1: the time base of window watchdog counter = (PCLK1/4096)/1 + \arg WWDGT_CFG_PSC_DIV2: the time base of window watchdog counter = (PCLK1/4096)/2 + \arg WWDGT_CFG_PSC_DIV4: the time base of window watchdog counter = (PCLK1/4096)/4 + \arg WWDGT_CFG_PSC_DIV8: the time base of window watchdog counter = (PCLK1/4096)/8 + \param[out] none + \retval none +*/ +void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler) +{ + WWDGT_CFG = (uint32_t)(CFG_WIN(window) | prescaler); + WWDGT_CTL = (uint32_t)(CTL_CNT(counter)); +} + +/*! + \brief check early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval FlagStatus: SET or RESET +*/ +FlagStatus wwdgt_flag_get(void) +{ + if(RESET != (WWDGT_STAT & WWDGT_STAT_EWIF)) { + return SET; + } + return RESET; +} + +/*! + \brief clear early wakeup interrupt state of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_flag_clear(void) +{ + WWDGT_STAT &= (~(uint32_t)WWDGT_STAT_EWIF); +} + +/*! + \brief enable early wakeup interrupt of WWDGT + \param[in] none + \param[out] none + \retval none +*/ +void wwdgt_interrupt_enable(void) +{ + WWDGT_CFG |= WWDGT_CFG_EWIE; +} diff --git a/Src/board_config.c b/Src/board_config.c index a68f73e..ddb8f78 100644 --- a/Src/board_config.c +++ b/Src/board_config.c @@ -1,52 +1,52 @@ -#include "gd32e23x.h" -#include "board_config.h" -#include "systick.h" - -/******************************************************************************/ - -#define FLASH_SIZE_ADDR (*(const uint8_t *)0x1FFFF7E0) // Flash base address - -/******************************************************************************/ - -/* 前向声明中断处理函数 */ -void usart0_irq_handler(void); -void usart1_irq_handler(void); - -usart_config_t g_usart_config = { - .rcu_usart = RCU_USART1, - .usart_periph = USART1, - .irq_type = USART1_IRQn, - .irq_handler = usart1_irq_handler // 初始化函数指针 -}; - -uint8_t g_mcu_flash_size = 0; - -void mcu_detect_and_config(void) { - g_mcu_flash_size = FLASH_SIZE_ADDR; - - switch (g_mcu_flash_size) { - case GD32E23XF4: - g_usart_config.rcu_usart = RCU_USART0; - g_usart_config.usart_periph = USART0; - g_usart_config.irq_type = USART0_IRQn; - g_usart_config.irq_handler = usart0_irq_handler; // 指向USART0处理函数 - break; - case GD32E23XF6: - g_usart_config.rcu_usart = RCU_USART1; - g_usart_config.usart_periph = USART1; - g_usart_config.irq_type = USART1_IRQn; - g_usart_config.irq_handler = usart1_irq_handler; // 指向USART1处理函数 - break; - default: // Default to GD32E23XF8 - g_usart_config.rcu_usart = RCU_USART1; - g_usart_config.usart_periph = USART1; - g_usart_config.irq_type = USART1_IRQn; - g_usart_config.irq_handler = usart1_irq_handler; // 指向USART1处理函数 - break; - } - -} - -uint8_t get_flash_size(void) { - return g_mcu_flash_size; -} +#include "gd32e23x.h" +#include "board_config.h" +#include "systick.h" + +/******************************************************************************/ + +#define FLASH_SIZE_ADDR (*(const uint8_t *)0x1FFFF7E0) // Flash base address + +/******************************************************************************/ + +/* 前向声明中断处理函数 */ +void usart0_irq_handler(void); +void usart1_irq_handler(void); + +usart_config_t g_usart_config = { + .rcu_usart = RCU_USART1, + .usart_periph = USART1, + .irq_type = USART1_IRQn, + .irq_handler = usart1_irq_handler // 初始化函数指针 +}; + +uint8_t g_mcu_flash_size = 0; + +void mcu_detect_and_config(void) { + g_mcu_flash_size = FLASH_SIZE_ADDR; + + switch (g_mcu_flash_size) { + case GD32E23XF4: + g_usart_config.rcu_usart = RCU_USART0; + g_usart_config.usart_periph = USART0; + g_usart_config.irq_type = USART0_IRQn; + g_usart_config.irq_handler = usart0_irq_handler; // 指向USART0处理函数 + break; + case GD32E23XF6: + g_usart_config.rcu_usart = RCU_USART1; + g_usart_config.usart_periph = USART1; + g_usart_config.irq_type = USART1_IRQn; + g_usart_config.irq_handler = usart1_irq_handler; // 指向USART1处理函数 + break; + default: // Default to GD32E23XF8 + g_usart_config.rcu_usart = RCU_USART1; + g_usart_config.usart_periph = USART1; + g_usart_config.irq_type = USART1_IRQn; + g_usart_config.irq_handler = usart1_irq_handler; // 指向USART1处理函数 + break; + } + +} + +uint8_t get_flash_size(void) { + return g_mcu_flash_size; +} diff --git a/Src/command.c b/Src/command.c index d5fc993..e8170bd 100644 --- a/Src/command.c +++ b/Src/command.c @@ -1,614 +1,475 @@ -/** - * @file command.c - * @brief 串口命令解析与处理模块实现 - * @details 实现基于状态机的协议解析器，支持 D5 03 LEN [cmd] CRC 格式的命令处理， - * 包含命令帧解析、响应生成和传感器状态管理功能。 - * @author Hulk - * @date 2025-08-13 - * @version 1.0.0 - * @ingroup Command - */ - -#include "command.h" -#include "uart_ring_buffer.h" -#include "led.h" -#include -#include -#include -#include "board_config.h" -#include "gd32e23x_usart.h" -#include "ldc1612.h" -#include "tmp112.h" - -/* ============================================================================ - * 协议格式说明 - * ============================================================================ */ - -/** - * @name 协议帧格式 - * @{ - * @details - * Host -> Device 命令帧格式： - * [0] HEADER = 0xD5 // 包头标识 - * [1] BOARD_TYPE = 0x03 // 板卡类型标识 - * [2] LEN = 数据区字节数 // 有效载荷长度 - * [3..(3+LEN-1)] 数据 // 命令数据，如 "M1", "M2S123" - * [last] CRC = 校验码 // 从索引1到(last-1)的累加和低8位 - * - * 最小协议包长度为 6 字节 - * 数据示例（两字节命令）："M1" / "M2" / "M3" - * - * Device -> Host 响应帧格式： - * [0] 0xB5 // 响应包头 - * [1] TYPE // 响应类型（0xF0=成功，0xF1..=错误类型） - * [2] LEN // 响应数据长度 - * [3..(3+LEN-1)] 数据 // 响应数据，如 "ok", "err" - * [last] CRC // 校验码（同命令帧规则） - * @} - */ - -/* ============================================================================ - * 协议常量定义 - * ============================================================================ */ - -/** @name 协议帧标识符 - * @{ */ -#define PROTOCOL_PACKAGE_HEADER 0xD5 /**< 命令帧包头标识 */ -#define PROTOCOL_BOARD_TYPE 0x03 /**< 板卡类型标识 */ -/** @} */ - -/** @name 命令长度限制 - * @{ */ -#define COMMAND_MIN_LEN 2 /**< 最小命令长度，如"M1" */ -#define PROTOCOL_MIN_FRAME_LEN (3 + COMMAND_MIN_LEN + 1) /**< 最小完整帧长度：header+type+len+payload+crc = 6 */ -#define PROTOCOL_MAX_FRAME_LEN 16 /**< 最大完整帧长度 */ -/** @} */ - -/** @name 响应帧标识符 - * @{ */ -#define RESP_HEADER 0xB5 /**< 响应帧包头标识 */ -#define RESP_TYPE_OK 0xF0 /**< 成功响应类型 */ -#define RESP_TYPE_CRC_ERR 0xF1 /**< CRC校验错误 */ -#define RESP_TYPE_HEADER_ERR 0xF2 /**< 包头错误 */ -#define RESP_TYPE_TYPE_ERR 0xF3 /**< 类型错误 */ -#define RESP_TYPE_LEN_ERR 0xF4 /**< 长度错误 */ -/** @} */ - -/* 温度补偿参数定义 - * TEMP_COMP_REF_TEMP_X10000: 参考温度，单位 0.0001°C - * TEMP_COMP_COEFF_NUMERATOR / TEMP_COMP_COEFF_DENOMINATOR: 温漂系数，默认表示 counts/°C - * 补偿公式: compensated = raw - (temp - ref) * coeff - */ -#define TEMP_COMP_REF_TEMP_X10000 (250000L) -#define TEMP_COMP_COEFF_NUMERATOR (0L) -#define TEMP_COMP_COEFF_DENOMINATOR (10000L) - -/* ============================================================================ - * 模块内部变量 - * ============================================================================ */ - -/** @brief 传感器周期上报使能标志 */ -volatile bool g_eddy_current_sensor_report_enabled = false; - -/* Debug output control */ -#ifdef COM_DEBUG - #include - #define COMMAND_DEBUG(fmt, ...) printf("[COMMAND] " fmt "\n", ##__VA_ARGS__) -#else - #define COMMAND_DEBUG(fmt, ...) -#endif - -/** @name 预设响应数据 - * @{ */ -static const uint8_t s_report_status_ok[] = { 'o', 'k' }; /**< 成功响应数据 */ -static const uint8_t s_report_status_err[] = { 'e','r','r' }; /**< 错误响应数据 */ -/** @} */ - -static int32_t tmp112_get_temperature_x10000(void); -static int64_t calculate_temperature_compensation_offset(int32_t temperature_x10000); - -/* ============================================================================ - * 公共接口函数 - * ============================================================================ */ - -/** - * @brief 查询电涡流传感器是否启用周期性传感器上报。 - * @return true 表示启用；false 表示禁用。 - * @ingroup Command - */ -bool get_eddy_sensor_report_enabled(void) -{ - return g_eddy_current_sensor_report_enabled; -} - -/** - * @brief 设置电涡流传感器是否启用周期性传感器上报标志。 - * @details 本模块内部保存的布尔状态，供其他逻辑决定是否进行周期性数据上报； - * 推荐通过本函数修改而非直接访问全局/静态变量，以便后续扩展（如加锁/回调）。 - * @param status true 启用周期上报；false 禁用。 - * @ingroup Command - */ -void set_eddy_sensor_report_status(bool status) -{ - g_eddy_current_sensor_report_enabled = status; -} - -/** - * @brief 计算协议包的 8 位累加校验值（Checksum）。 - * @details 对输入缓冲区逐字节累加并取低 8 位，累加范围为 data[1] 至 data[len-2]， - * 即不包含包头 HEADER（索引 0）与尾部 CRC 字节（索引 len-1）。 - * 当 len 小于最小协议帧长度（PACKAGE_MIN_LENGTH）时返回 0。 - * @param data 指向待校验的完整协议包缓冲区。 - * @param len 缓冲区总长度（字节），应满足 header + type + len + payload + crc 的最小格式。 - * @return uint8_t 计算得到的 8 位校验值。 - * @note 本函数实现为简单求和校验（Checksum），非多项式 CRC；与本协议“从索引 1 累加到 len-2”的规则一致。 - * @ingroup Command - */ -static uint8_t command_sum_crc_calc(const uint8_t *data, uint8_t len) -{ - uint16_t crc = 0; - // 仅在满足协议最小帧长时计算（header + type + len + payload + crc） - if (len < PROTOCOL_MIN_FRAME_LEN) return 0; - - // 累加从索引 1 到 len-2 的字节（不含 header 和 crc 字节） - for (uint8_t i = 1; i < (len - 1); i++) - { - crc += data[i]; - } - return (uint8_t)(crc & 0xFF); -} - -/** - * @brief 发送协议响应帧（使用GD32E230标准库）。 - * @details 构造并发送格式为 B5 TYPE LEN [payload] CRC 的响应帧， - * 自动计算CRC校验值并通过串口输出。 - * @param type 响应类型码（如 RESP_TYPE_OK, RESP_TYPE_CRC_ERR 等）。 - * @param payload 指向响应数据的缓冲区，当len为0时可为NULL。 - * @param len 响应数据长度（字节），为0时不复制payload数据。 - * @note 内部使用固定大小缓冲区，超长响应将被丢弃。 - * @warning 使用GD32E230标准库函数发送，确保串口已正确初始化。 - * @ingroup Command - */ -static void send_response(uint8_t type, const uint8_t *payload, uint8_t len) -{ - uint8_t buf_len = (uint8_t)(3 + len + 1); - uint8_t buf[16]; // 简单场景足够，必要时可增大 - if (buf_len > sizeof(buf)) return; // 防御 - - buf[0] = RESP_HEADER; - buf[1] = type; - buf[2] = len; - - // 简化逻辑：只有当len > 0且payload非空时才复制数据 - if (len > 0 && payload != NULL) { - for (uint8_t i = 0; i < len; i++) { - buf[3 + i] = payload[i]; - } - } - - buf[buf_len - 1] = command_sum_crc_calc(buf, buf_len); - - // 使用GD32E230标准库函数逐字节发送（标准库实现） - for (uint8_t i = 0; i < buf_len; i++) { - // 等待发送缓冲区空 - while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(RS485_PHY, buf[i]); - } - - // 等待发送完成 - while (usart_flag_get(RS485_PHY, USART_FLAG_TC) == RESET) {} - - // // 使用printf发送（通过重定向到串口） - // for (uint8_t i = 0; i < buf_len; i++) { - // printf("%c", buf[i]); - // } - - // // 刷新缓冲区 - // fflush(stdout); -} - -/** - * @brief 判断字符是否为十进制数字字符。 - * @param c 待检查的字符（ASCII码值）。 - * @return bool 判断结果。 - * @retval true 字符为 '0' 到 '9' 之间的数字字符。 - * @retval false 字符不是十进制数字字符。 - * @ingroup Command - */ -static inline bool is_dec_digit(uint8_t c) { return (c >= '0' && c <= '9'); } - -/** - * @brief 将一个无符号整数转换为字符串并追加到缓冲区。 - * @param value 要转换的数字。 - * @param buffer 指向目标缓冲区的指针，转换后的字符串将写入此处。 - * @return uint8_t 写入的字符数。 - */ -static uint8_t uint_to_str(uint32_t value, char *buffer) { - char temp[10]; // 32位无符号整数最多10位 - int i = 0; - - if (value == 0) { - buffer[0] = '0'; - return 1; - } - - // 将数字逆序转换为字符存入临时数组 - while (value > 0) { - temp[i++] = (char)((value % 10) + '0'); - value /= 10; - } - - // 将逆序的字符串反转并存入目标缓冲区 - uint8_t len = (uint8_t)i; - for (int j = 0; j < len; j++) { - buffer[j] = temp[--i]; - } - - return len; -} - -/** - * @brief 从缓冲区解析十进制无符号整数。 - * @details 从指定位置开始连续读取十进制数字字符，累加构成32位无符号整数。 - * 遇到非数字字符或到达长度限制时停止解析。 - * @param s 指向待解析字符缓冲区的起始位置。 - * @param n 允许解析的最大字符数。 - * @param out 输出参数，存储解析结果，可为NULL。 - * @return uint8_t 实际消耗的字符数。 - * @retval 0 首字符不是数字，解析失败。 - * @retval >0 成功解析的数字字符个数。 - * @note 不处理符号、空白字符或进制前缀。 - * @warning 不进行溢出检查，超出uint32_t范围时按无符号算术溢出处理。 - * @ingroup Command - */ -static uint8_t parse_uint_dec(const uint8_t *s, uint8_t n, uint32_t *out) -{ - uint8_t i = 0; - uint32_t v = 0; - while (i < n && is_dec_digit(s[i])) - { - v = v * 10u + (uint32_t)(s[i] - '0'); - i++; - } - if (i == 0) return 0; // 未读到数字 - if (out) *out = v; // - return i; -} - -/* ============================================================================ - * 命令处理函数 - * ============================================================================ */ - -/** - * @brief 解析并处理完整的命令帧。 - * @details 处理经过协议校验的完整命令帧，支持以下命令格式： - * - 无参数命令：M<数字>（如 M1、M2、M10、M201） - * - 带参数命令：M<数字>S<参数>（如 M100S123，参数为十进制） - * - * 支持的命令： - * - M1: 开启LED，启用传感器上报 - * - M2: 关闭LED，禁用传感器上报 - * - M100S: 设置PWM值（示例） - * - * @param frame 指向完整命令帧的缓冲区（从包头0xD5开始）。 - * @param len 命令帧总长度（字节）。 - * @note 函数内部进行帧格式校验，格式错误时自动发送错误响应。 - * @warning 假设输入帧已通过基本协议校验（包头、类型、CRC等）。 - * @ingroup Command - */ -void handle_command(const uint8_t *frame, uint8_t len) { - // 帧格式：D5 03 LEN [cmd] CRC; cmd 支持变长，如 "M1"、"M10"、"M201"、"M123S400"，有最小长度限制和命令长度校验 - uint8_t cmd_len = frame[2]; - if (len < PROTOCOL_MIN_FRAME_LEN || (uint8_t)(3 + cmd_len + 1) != len) return; // 长度不匹配或者小于最小限制 - - const uint8_t *cmd = &frame[3]; // 提取命令部分 - - // 命令必须以 'M' 开头 - if (cmd[0] != 'M'){ - send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); - return; - } - - // 从 'M' 后开始解析 - uint8_t cmd_index = 1; - // 解析M后的十进制数，即命令本体 - uint32_t base_cmd = 0; - uint8_t used_base_cmd = parse_uint_dec(&cmd[cmd_index], (cmd_len - cmd_index), &base_cmd); - if (used_base_cmd == 0) - { - // 'M' 后没有数字，格式错误 - send_response(RESP_TYPE_LEN_ERR, s_report_status_err, sizeof(s_report_status_err)); - return; - } - - cmd_index = (uint8_t)(cmd_index + used_base_cmd); // 更新索引到命令后 - - // 情况A：无附加参数的基础命令 - if (cmd_index == cmd_len) { - // 仅基础命令，如 M1, M2, M3 - switch (base_cmd) { - case 1u: // M1: enable sensor report - set_eddy_sensor_report_status(true); - return; - - case 2u: // M2: disable sensor report - set_eddy_sensor_report_status(false); - send_response(RESP_TYPE_OK, s_report_status_ok, sizeof(s_report_status_ok)); - return; - - case 3u: - eddy_current_report(); - return; - - case 4u: - temperature_raw_value_report(); - return; - - case 5u: - eddy_current_compensated_report(); - return; - - case 6u: - calibration_data_report(); - return; - - // case 201u: // M201命令 - // send_response(RESP_TYPE_OK, s_report_status_ok, sizeof(s_report_status_ok)); - // return; - - /* ========================================== - * M999 输出固件版本号命令 - * ========================================== */ - case 999u: //M999: 输出固件版本号 - { - char version_str[16]; - char *p = version_str; - - *p++ = 'v'; - p += uint_to_str(BOARD_TYPE_CODE, p); - *p++ = '.'; - p += uint_to_str(FW_VERSION_MAJOR, p); - *p++ = '.'; - p += uint_to_str(FW_VERSION_MINOR, p); - *p++ = '.'; - p += uint_to_str(FW_VERSION_PATCH, p); - *p = '\0'; // null-terminate for printf safety - - uint8_t n = (uint8_t)(p - version_str); - send_response(RESP_TYPE_OK, (uint8_t *)version_str, n); - COMMAND_DEBUG("Firmware Version: %s", version_str); - } - return; - - case 9999u: - __disable_irq(); - NVIC_SystemReset(); - return; - - default: - // 其它无参数命令在此扩展（示例：M100）处理逻辑该如何待定 - // send_response(RESP_TYPE_OK, s_report_status_ok, sizeof(s_report_status_ok)); - // return; - break; - } - // 未在处理列表的无参数基础命令，回复错误 - send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); - return; - } - - // 情况B：有附加参数的命令 - if (cmd[cmd_index] == 'S') { - cmd_index++; - uint32_t param_value = 0; - const uint8_t used_param_cmd = parse_uint_dec(&cmd[cmd_index], (uint8_t)(cmd_len - cmd_index), ¶m_value); - if (used_param_cmd == 0) { - // 'S' 后没有数字，格式错误 - send_response(RESP_TYPE_LEN_ERR, s_report_status_err, sizeof(s_report_status_err)); - return; - } - - switch (base_cmd) - { - // case 100u: - // // set_pwm(param_value); - // printf("Set PWM to %u\n", param_value); - // return; - - default: - break; - } - send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); - } -} - -/** - * @brief 处理串口环形缓冲区中的命令数据，解析完整的协议帧。 - * @details 本函数实现一个基于状态机的协议解析器，用于处理格式为 D5 03 LEN [cmd] CRC 的命令帧： - * - 状态1：等待包头字节 PROTOCOL_PACKAGE_HEADER (0xD5) - * - 状态2：接收板卡类型字节 PROTOCOL_BOARD_TYPE (0x03) - * - 状态3：接收长度字段并计算期望的完整帧长度 - * - 状态4：继续接收剩余数据直到完整帧 - * - 状态5：对完整帧进行校验（包头、板卡类型、CRC）并处理 - * - * 函数采用非阻塞方式处理，每次调用处理缓冲区中所有可用数据。 - * 遇到格式错误、长度异常或校验失败时自动重置状态机。 - * - * @note 本函数使用静态变量维护解析状态，因此不可重入。在中断环境中使用需注意并发安全。 - * 协议帧最大长度受 PROTOCOL_MAX_FRAME_LEN 限制，超出范围的帧将被丢弃。 - * - * @warning 函数依赖 uart_ring_buffer_available() 和 uart_ring_buffer_get() - * 正确实现，若这些函数有缺陷可能导致死循环或数据丢失。 - * - * @see handle_command() 用于处理校验通过的完整命令帧 - * @see command_sum_crc_calc() 用于计算和校验 CRC 值 - * @see send_response() 用于发送错误响应 - * - * @ingroup Command - */ -void command_process(void) { - static uint8_t cmd_buf[PROTOCOL_MAX_FRAME_LEN]; - static uint8_t cmd_len = 0; - static uint8_t expected_cmd_len = 0; // 0 表示尚未确定总长度 - - while (uart_ring_buffer_available() > 0) { - int byte = uart_ring_buffer_get(); - if (byte < 0) break; - - if (cmd_len == 0) { - if ((uint8_t)byte == PROTOCOL_PACKAGE_HEADER) { - cmd_buf[cmd_len++] = (uint8_t)byte; - expected_cmd_len = 0; // 等待进一步字段以确定长度 - } else { - // 丢弃非起始字节 - } - continue; - } - - if (cmd_len >= PROTOCOL_MAX_FRAME_LEN) { - // 防御：缓冲溢出，复位状态机 - cmd_len = 0; - expected_cmd_len = 0; - } - - // 缓存后续字节 - cmd_buf[cmd_len++] = (uint8_t)byte; - - // 当到达长度字段（索引 2）后，确定总长度：3 + LEN + 1 - if (cmd_len == 3) { - uint8_t payload_len = cmd_buf[2]; - expected_cmd_len = (uint8_t)(3 + payload_len + 1); - if (expected_cmd_len > PROTOCOL_MAX_FRAME_LEN) { - // 异常：长度超界，复位状态机 - cmd_len = 0; - expected_cmd_len = 0; - } - continue; - } - - if (expected_cmd_len > 0 && cmd_len == expected_cmd_len) { - // 到帧尾，进行各项校验 - bool verification_status = true; - - #ifdef DEBUG_VERBOSE - if (cmd_buf[0] != PROTOCOL_PACKAGE_HEADER) { - send_response(RESP_TYPE_HEADER_ERR, s_report_status_err, sizeof(s_report_status_err)); - verification_status = false; - } - #endif - - if (verification_status && cmd_buf[1] != PROTOCOL_BOARD_TYPE) { - send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); - verification_status = false; - } - if (verification_status) { - uint8_t crc_calc = command_sum_crc_calc(cmd_buf, expected_cmd_len); - uint8_t crc_recv = cmd_buf[expected_cmd_len - 1]; - if (crc_calc != crc_recv) { - send_response(RESP_TYPE_CRC_ERR, s_report_status_err, sizeof(s_report_status_err)); - verification_status = false; - } - } - - if (verification_status) { - handle_command(cmd_buf, expected_cmd_len); - } - - // 复位，等待下一帧 - cmd_len = 0; - expected_cmd_len = 0; - } - } -} - -void eddy_current_report(void) { - // if (!g_eddy_current_sensor_report_enabled) return; - uint32_t raw_result = ldc1612_get_raw_channel_result(CHANNEL_0); - - uint8_t sensor_data[4]; - sensor_data[0] = (uint8_t)(raw_result >> 24); - sensor_data[1] = (uint8_t)(raw_result >> 16); - sensor_data[2] = (uint8_t)(raw_result >> 8); - sensor_data[3] = (uint8_t)(raw_result & 0xFF); - - send_response(RESP_TYPE_OK, sensor_data, sizeof(sensor_data)); -} - -static int32_t tmp112_get_temperature_x10000(void) -{ - uint8_t value[2] = {0}; - int16_t temp_raw; - - tmp112a_get_raw_temperature_value(value); - - temp_raw = (int16_t)(((uint16_t)value[0] << 8) | value[1]); - temp_raw >>= 4; - - return (int32_t)temp_raw * 625; -} - -static int64_t calculate_temperature_compensation_offset(int32_t temperature_x10000) -{ - int32_t delta_temp_x10000 = temperature_x10000 - TEMP_COMP_REF_TEMP_X10000; - - return ((int64_t)delta_temp_x10000 * TEMP_COMP_COEFF_NUMERATOR) / - TEMP_COMP_COEFF_DENOMINATOR; -} - -void temperature_raw_value_report(void) { - uint8_t raw_result[4]; - int32_t raw_value = tmp112_get_temperature_x10000(); - - raw_result[0] = (uint8_t)((uint32_t)raw_value >> 24); - raw_result[1] = (uint8_t)((uint32_t)raw_value >> 16); - raw_result[2] = (uint8_t)((uint32_t)raw_value >> 8); - raw_result[3] = (uint8_t)((uint32_t)raw_value & 0xFF); - - send_response(RESP_TYPE_OK, raw_result, sizeof(raw_result)); -} - -void eddy_current_compensated_report(void) -{ - uint8_t sensor_data[4]; - uint32_t raw_result = ldc1612_get_raw_channel_result(CHANNEL_0); - - if ((raw_result & 0xF0000000u) == 0u) { - int32_t temperature_x10000 = tmp112_get_temperature_x10000(); - int64_t compensated_value = (int64_t)raw_result - - calculate_temperature_compensation_offset(temperature_x10000); - - if (compensated_value < 0) { - raw_result = 0; - } else if (compensated_value > 0x0FFFFFFFLL) { - raw_result = 0x0FFFFFFFu; - } else { - raw_result = (uint32_t)compensated_value; - } - } - - sensor_data[0] = (uint8_t)(raw_result >> 24); - sensor_data[1] = (uint8_t)(raw_result >> 16); - sensor_data[2] = (uint8_t)(raw_result >> 8); - sensor_data[3] = (uint8_t)(raw_result & 0xFF); - - send_response(RESP_TYPE_OK, sensor_data, sizeof(sensor_data)); -} - -void calibration_data_report(void) -{ - uint8_t payload[9]; - uint32_t eddy_raw_value = ldc1612_get_raw_channel_result(CHANNEL_0); - int32_t temperature_raw_value = tmp112_get_temperature_x10000(); - - payload[0] = (uint8_t)(eddy_raw_value >> 24); - payload[1] = (uint8_t)(eddy_raw_value >> 16); - payload[2] = (uint8_t)(eddy_raw_value >> 8); - payload[3] = (uint8_t)(eddy_raw_value & 0xFF); - payload[4] = 0xFF; - payload[5] = (uint8_t)((uint32_t)temperature_raw_value >> 24); - payload[6] = (uint8_t)((uint32_t)temperature_raw_value >> 16); - payload[7] = (uint8_t)((uint32_t)temperature_raw_value >> 8); - payload[8] = (uint8_t)((uint32_t)temperature_raw_value & 0xFF); - - send_response(RESP_TYPE_OK, payload, sizeof(payload)); -} +/** + * @file command.c + * @brief 串口命令解析与处理模块实现 + * @details 实现基于状态机的协议解析器，支持 D5 03 LEN [cmd] CRC 格式的命令处理， + * 包含命令帧解析、响应生成和传感器状态管理功能。 + * @author Hulk + * @date 2025-08-13 + * @version 1.0.0 + * @ingroup Command + */ + +#include "command.h" +#include "uart_ring_buffer.h" +#include "led.h" +#include +#include +#include +#include "board_config.h" +#include "gd32e23x_usart.h" +#include "ldc1612.h" +#include "tmp112.h" + +/* ============================================================================ + * 协议格式说明 + * ============================================================================ */ + +/** + * @name 协议帧格式 + * @{ + * @details + * Host -> Device 命令帧格式： + * [0] HEADER = 0xD5 // 包头标识 + * [1] BOARD_TYPE = 0x03 // 板卡类型标识 + * [2] LEN = 数据区字节数 // 有效载荷长度 + * [3..(3+LEN-1)] 数据 // 命令数据，如 "M1", "M2S123" + * [last] CRC = 校验码 // 从索引1到(last-1)的累加和低8位 + * + * 最小协议包长度为 6 字节 + * 数据示例（两字节命令）："M1" / "M2" / "M3" + * + * Device -> Host 响应帧格式： + * [0] 0xB5 // 响应包头 + * [1] TYPE // 响应类型（0xF0=成功，0xF1..=错误类型） + * [2] LEN // 响应数据长度 + * [3..(3+LEN-1)] 数据 // 响应数据，如 "ok", "err" + * [last] CRC // 校验码（同命令帧规则） + * @} + */ + +/* ============================================================================ + * 协议常量定义 + * ============================================================================ */ + +/** @name 协议帧标识符 + * @{ */ +#define PROTOCOL_PACKAGE_HEADER 0xD5 /**< 命令帧包头标识 */ +#define PROTOCOL_BOARD_TYPE 0x03 /**< 板卡类型标识 */ +/** @} */ + +/** @name 命令长度限制 + * @{ */ +#define COMMAND_MIN_LEN 2 /**< 最小命令长度，如"M1" */ +#define PROTOCOL_MIN_FRAME_LEN (3 + COMMAND_MIN_LEN + 1) /**< 最小完整帧长度：header+type+len+payload+crc = 6 */ +#define PROTOCOL_MAX_FRAME_LEN 16 /**< 最大完整帧长度 */ +/** @} */ + +/** @name 响应帧标识符 + * @{ */ +#define RESP_HEADER 0xB5 /**< 响应帧包头标识 */ +#define RESP_TYPE_OK 0xF0 /**< 成功响应类型 */ +#define RESP_TYPE_CRC_ERR 0xF1 /**< CRC校验错误 */ +#define RESP_TYPE_HEADER_ERR 0xF2 /**< 包头错误 */ +#define RESP_TYPE_TYPE_ERR 0xF3 /**< 类型错误 */ +#define RESP_TYPE_LEN_ERR 0xF4 /**< 长度错误 */ +/** @} */ + +/* ============================================================================ + * 模块内部变量 + * ============================================================================ */ + +/** @brief 传感器周期上报使能标志 */ +volatile bool g_eddy_current_sensor_report_enabled = false; + +/** @name 预设响应数据 + * @{ */ +static const uint8_t s_report_status_ok[] = { 'o', 'k' }; /**< 成功响应数据 */ +static const uint8_t s_report_status_err[] = { 'e','r','r' }; /**< 错误响应数据 */ +/** @} */ + +/* ============================================================================ + * 公共接口函数 + * ============================================================================ */ + +/** + * @brief 查询电涡流传感器是否启用周期性传感器上报。 + * @return true 表示启用；false 表示禁用。 + * @ingroup Command + */ +bool get_eddy_sensor_report_enabled(void) +{ + return g_eddy_current_sensor_report_enabled; +} + +/** + * @brief 设置电涡流传感器是否启用周期性传感器上报标志。 + * @details 本模块内部保存的布尔状态，供其他逻辑决定是否进行周期性数据上报； + * 推荐通过本函数修改而非直接访问全局/静态变量，以便后续扩展（如加锁/回调）。 + * @param status true 启用周期上报；false 禁用。 + * @ingroup Command + */ +void set_eddy_sensor_report_status(bool status) +{ + g_eddy_current_sensor_report_enabled = status; +} + +/** + * @brief 计算协议包的 8 位累加校验值（Checksum）。 + * @details 对输入缓冲区逐字节累加并取低 8 位，累加范围为 data[1] 至 data[len-2]， + * 即不包含包头 HEADER（索引 0）与尾部 CRC 字节（索引 len-1）。 + * 当 len 小于最小协议帧长度（PACKAGE_MIN_LENGTH）时返回 0。 + * @param data 指向待校验的完整协议包缓冲区。 + * @param len 缓冲区总长度（字节），应满足 header + type + len + payload + crc 的最小格式。 + * @return uint8_t 计算得到的 8 位校验值。 + * @note 本函数实现为简单求和校验（Checksum），非多项式 CRC；与本协议“从索引 1 累加到 len-2”的规则一致。 + * @ingroup Command + */ +static uint8_t command_sum_crc_calc(const uint8_t *data, uint8_t len) +{ + uint16_t crc = 0; + // 仅在满足协议最小帧长时计算（header + type + len + payload + crc） + if (len < PROTOCOL_MIN_FRAME_LEN) return 0; + + // 累加从索引 1 到 len-2 的字节（不含 header 和 crc 字节） + for (uint8_t i = 1; i < (len - 1); i++) + { + crc += data[i]; + } + return (uint8_t)(crc & 0xFF); +} + +/** + * @brief 发送协议响应帧（使用GD32E230标准库）。 + * @details 构造并发送格式为 B5 TYPE LEN [payload] CRC 的响应帧， + * 自动计算CRC校验值并通过串口输出。 + * @param type 响应类型码（如 RESP_TYPE_OK, RESP_TYPE_CRC_ERR 等）。 + * @param payload 指向响应数据的缓冲区，当len为0时可为NULL。 + * @param len 响应数据长度（字节），为0时不复制payload数据。 + * @note 内部使用固定大小缓冲区，超长响应将被丢弃。 + * @warning 使用GD32E230标准库函数发送，确保串口已正确初始化。 + * @ingroup Command + */ +static void send_response(uint8_t type, const uint8_t *payload, uint8_t len) +{ + uint8_t buf_len = (uint8_t)(3 + len + 1); + uint8_t buf[16]; // 简单场景足够，必要时可增大 + if (buf_len > sizeof(buf)) return; // 防御 + + buf[0] = RESP_HEADER; + buf[1] = type; + buf[2] = len; + + // 简化逻辑：只有当len > 0且payload非空时才复制数据 + if (len > 0 && payload != NULL) { + for (uint8_t i = 0; i < len; i++) { + buf[3 + i] = payload[i]; + } + } + + buf[buf_len - 1] = command_sum_crc_calc(buf, buf_len); + + // 使用GD32E230标准库函数逐字节发送（标准库实现） + for (uint8_t i = 0; i < buf_len; i++) { + // 等待发送缓冲区空 + while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(RS485_PHY, buf[i]); + } + + // 等待发送完成 + while (usart_flag_get(RS485_PHY, USART_FLAG_TC) == RESET) {} + + // // 使用printf发送（通过重定向到串口） + // for (uint8_t i = 0; i < buf_len; i++) { + // printf("%c", buf[i]); + // } + + // // 刷新缓冲区 + // fflush(stdout); +} + +/** + * @brief 判断字符是否为十进制数字字符。 + * @param c 待检查的字符（ASCII码值）。 + * @return bool 判断结果。 + * @retval true 字符为 '0' 到 '9' 之间的数字字符。 + * @retval false 字符不是十进制数字字符。 + * @ingroup Command + */ +static inline bool is_dec_digit(uint8_t c) { return (c >= '0' && c <= '9'); } + +/** + * @brief 从缓冲区解析十进制无符号整数。 + * @details 从指定位置开始连续读取十进制数字字符，累加构成32位无符号整数。 + * 遇到非数字字符或到达长度限制时停止解析。 + * @param s 指向待解析字符缓冲区的起始位置。 + * @param n 允许解析的最大字符数。 + * @param out 输出参数，存储解析结果，可为NULL。 + * @return uint8_t 实际消耗的字符数。 + * @retval 0 首字符不是数字，解析失败。 + * @retval >0 成功解析的数字字符个数。 + * @note 不处理符号、空白字符或进制前缀。 + * @warning 不进行溢出检查，超出uint32_t范围时按无符号算术溢出处理。 + * @ingroup Command + */ +static uint8_t parse_uint_dec(const uint8_t *s, uint8_t n, uint32_t *out) +{ + uint8_t i = 0; + uint32_t v = 0; + while (i < n && is_dec_digit(s[i])) + { + v = v * 10u + (uint32_t)(s[i] - '0'); + i++; + } + if (i == 0) return 0; // 未读到数字 + if (out) *out = v; // + return i; +} + +/* ============================================================================ + * 命令处理函数 + * ============================================================================ */ + +/** + * @brief 解析并处理完整的命令帧。 + * @details 处理经过协议校验的完整命令帧，支持以下命令格式： + * - 无参数命令：M<数字>（如 M1、M2、M10、M201） + * - 带参数命令：M<数字>S<参数>（如 M100S123，参数为十进制） + * + * 支持的命令： + * - M1: 开启LED，启用传感器上报 + * - M2: 关闭LED，禁用传感器上报 + * - M100S: 设置PWM值（示例） + * + * @param frame 指向完整命令帧的缓冲区（从包头0xD5开始）。 + * @param len 命令帧总长度（字节）。 + * @note 函数内部进行帧格式校验，格式错误时自动发送错误响应。 + * @warning 假设输入帧已通过基本协议校验（包头、类型、CRC等）。 + * @ingroup Command + */ +void handle_command(const uint8_t *frame, uint8_t len) { + // 帧格式：D5 03 LEN [cmd] CRC; cmd 支持变长，如 "M1"、"M10"、"M201"、"M123S400"，有最小长度限制和命令长度校验 + uint8_t cmd_len = frame[2]; + if (len < PROTOCOL_MIN_FRAME_LEN || (uint8_t)(3 + cmd_len + 1) != len) return; // 长度不匹配或者小于最小限制 + + const uint8_t *cmd = &frame[3]; // 提取命令部分 + + // 命令必须以 'M' 开头 + if (cmd[0] != 'M'){ + send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); + return; + } + + // 从 'M' 后开始解析 + uint8_t cmd_index = 1; + // 解析M后的十进制数，即命令本体 + uint32_t base_cmd = 0; + uint8_t used_base_cmd = parse_uint_dec(&cmd[cmd_index], (cmd_len - cmd_index), &base_cmd); + if (used_base_cmd == 0) + { + // 'M' 后没有数字，格式错误 + send_response(RESP_TYPE_LEN_ERR, s_report_status_err, sizeof(s_report_status_err)); + return; + } + + cmd_index = (uint8_t)(cmd_index + used_base_cmd); // 更新索引到命令后 + + // 情况A：无附加参数的基础命令 + if (cmd_index == cmd_len) { + // 仅基础命令，如 M1, M2, M3 + switch (base_cmd) { + case 1u: // M1: enable sensor report + set_eddy_sensor_report_status(true); + return; + + case 2u: // M2: disable sensor report + set_eddy_sensor_report_status(false); + return; + + case 3u: + eddy_current_report(); + return; + + case 4u: + temperature_raw_value_report(); + return; + + // case 201u: // M201命令 + // send_response(RESP_TYPE_OK, s_report_status_ok, sizeof(s_report_status_ok)); + // return; + + case 999u: + char version_str[16]; + int n = snprintf(version_str, sizeof(version_str), "v%u.%u.%u.%u", MCU_CODE, FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_PATCH); + send_response(RESP_TYPE_OK, (uint8_t *)version_str, (uint8_t)n); + return; + + case 9999u: + __disable_irq(); + NVIC_SystemReset(); + return; + + default: + // 其它无参数命令在此扩展（示例：M100）处理逻辑该如何待定 + // send_response(RESP_TYPE_OK, s_report_status_ok, sizeof(s_report_status_ok)); + // return; + break; + } + // 未在处理列表的无参数基础命令，回复错误 + send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); + return; + } + + // 情况B：有附加参数的命令 + if (cmd[cmd_index] == 'S') { + cmd_index++; + uint32_t param_value = 0; + const uint8_t used_param_cmd = parse_uint_dec(&cmd[cmd_index], (uint8_t)(cmd_len - cmd_index), ¶m_value); + if (used_param_cmd == 0) { + // 'S' 后没有数字，格式错误 + send_response(RESP_TYPE_LEN_ERR, s_report_status_err, sizeof(s_report_status_err)); + return; + } + + switch (base_cmd) + { + // case 100u: + // // set_pwm(param_value); + // printf("Set PWM to %u\n", param_value); + // return; + + default: + break; + } + send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); + } +} + +/** + * @brief 处理串口环形缓冲区中的命令数据，解析完整的协议帧。 + * @details 本函数实现一个基于状态机的协议解析器，用于处理格式为 D5 03 LEN [cmd] CRC 的命令帧： + * - 状态1：等待包头字节 PROTOCOL_PACKAGE_HEADER (0xD5) + * - 状态2：接收板卡类型字节 PROTOCOL_BOARD_TYPE (0x03) + * - 状态3：接收长度字段并计算期望的完整帧长度 + * - 状态4：继续接收剩余数据直到完整帧 + * - 状态5：对完整帧进行校验（包头、板卡类型、CRC）并处理 + * + * 函数采用非阻塞方式处理，每次调用处理缓冲区中所有可用数据。 + * 遇到格式错误、长度异常或校验失败时自动重置状态机。 + * + * @note 本函数使用静态变量维护解析状态，因此不可重入。在中断环境中使用需注意并发安全。 + * 协议帧最大长度受 PROTOCOL_MAX_FRAME_LEN 限制，超出范围的帧将被丢弃。 + * + * @warning 函数依赖 uart_ring_buffer_available() 和 uart_ring_buffer_get() + * 正确实现，若这些函数有缺陷可能导致死循环或数据丢失。 + * + * @see handle_command() 用于处理校验通过的完整命令帧 + * @see command_sum_crc_calc() 用于计算和校验 CRC 值 + * @see send_response() 用于发送错误响应 + * + * @ingroup Command + */ +void command_process(void) { + static uint8_t cmd_buf[PROTOCOL_MAX_FRAME_LEN]; + static uint8_t cmd_len = 0; + static uint8_t expected_cmd_len = 0; // 0 表示尚未确定总长度 + + while (uart_ring_buffer_available() > 0) { + int byte = uart_ring_buffer_get(); + if (byte < 0) break; + + if (cmd_len == 0) { + if ((uint8_t)byte == PROTOCOL_PACKAGE_HEADER) { + cmd_buf[cmd_len++] = (uint8_t)byte; + expected_cmd_len = 0; // 等待进一步字段以确定长度 + } else { + // 丢弃非起始字节 + } + continue; + } + + if (cmd_len >= PROTOCOL_MAX_FRAME_LEN) { + // 防御：缓冲溢出，复位状态机 + cmd_len = 0; + expected_cmd_len = 0; + } + + // 缓存后续字节 + cmd_buf[cmd_len++] = (uint8_t)byte; + + // 当到达长度字段（索引 2）后，确定总长度：3 + LEN + 1 + if (cmd_len == 3) { + uint8_t payload_len = cmd_buf[2]; + expected_cmd_len = (uint8_t)(3 + payload_len + 1); + if (expected_cmd_len > PROTOCOL_MAX_FRAME_LEN) { + // 异常：长度超界，复位状态机 + cmd_len = 0; + expected_cmd_len = 0; + } + continue; + } + + if (expected_cmd_len > 0 && cmd_len == expected_cmd_len) { + // 到帧尾，进行各项校验 + bool verification_status = true; + + #ifdef DEBUG_VERBOSE + if (cmd_buf[0] != PROTOCOL_PACKAGE_HEADER) { + send_response(RESP_TYPE_HEADER_ERR, s_report_status_err, sizeof(s_report_status_err)); + verification_status = false; + } + #endif + + if (verification_status && cmd_buf[1] != PROTOCOL_BOARD_TYPE) { + send_response(RESP_TYPE_TYPE_ERR, s_report_status_err, sizeof(s_report_status_err)); + verification_status = false; + } + if (verification_status) { + uint8_t crc_calc = command_sum_crc_calc(cmd_buf, expected_cmd_len); + uint8_t crc_recv = cmd_buf[expected_cmd_len - 1]; + if (crc_calc != crc_recv) { + send_response(RESP_TYPE_CRC_ERR, s_report_status_err, sizeof(s_report_status_err)); + verification_status = false; + } + } + + if (verification_status) { + handle_command(cmd_buf, expected_cmd_len); + } + + // 复位，等待下一帧 + cmd_len = 0; + expected_cmd_len = 0; + } + } +} + +void eddy_current_report(void) { + // if (!g_eddy_current_sensor_report_enabled) return; + uint32_t raw_result = ldc1612_get_raw_channel_result(CHANNEL_0); + + uint8_t sensor_data[4]; + sensor_data[0] = (uint8_t)(raw_result >> 24); + sensor_data[1] = (uint8_t)(raw_result >> 16); + sensor_data[2] = (uint8_t)(raw_result >> 8); + sensor_data[3] = (uint8_t)(raw_result & 0xFF); + + send_response(RESP_TYPE_OK, sensor_data, sizeof(sensor_data)); +} + +void temperature_raw_value_report(void) { + // if (!g_temperature_sensor_report_enabled) return; + uint8_t raw_result[4]; + uint8_t value[2] = {0}; + uint32_t raw_value = 0; + + // i2c_read_16bits(TMP112A_ADDR, TMP112A_TEMP_REG, value); + tmp112a_get_raw_temperature_value(value); + raw_value = (uint32_t)((uint16_t) (value[0] << 4) | (value[1]>>4)) * 625; + raw_result[0] = (uint8_t)(raw_value >> 24); + raw_result[1] = (uint8_t)(raw_value >> 16); + raw_result[2] = (uint8_t)(raw_value >> 8); + raw_result[3] = (uint8_t)(raw_value & 0xFF); + + send_response(RESP_TYPE_OK, raw_result, sizeof(raw_result)); +} \ No newline at end of file diff --git a/Src/gd32e23x_it.c b/Src/gd32e23x_it.c index a640c63..b1073f7 100644 --- a/Src/gd32e23x_it.c +++ b/Src/gd32e23x_it.c @@ -1,117 +1,117 @@ -/*! - \file gd32e23x_it.c - \brief interrupt service routines - - \version 2025-02-10, V2.4.0, demo for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x_it.h" -#include "systick.h" -#include "uart.h" -#include "uart_ring_buffer.h" -#include "led.h" -#include "board_config.h" - -/*! - \brief this function handles NMI exception - \param[in] none - \param[out] none - \retval none -*/ -void NMI_Handler(void) -{ - /* if NMI exception occurs, go to infinite loop */ - while(1) { - } -} - -/*! - \brief this function handles HardFault exception - \param[in] none - \param[out] none - \retval none -*/ -void HardFault_Handler(void) -{ - /* if Hard Fault exception occurs, go to infinite loop */ - while(1) { - } -} - -/*! - \brief this function handles SVC exception - \param[in] none - \param[out] none - \retval none -*/ -void SVC_Handler(void) -{ - /* if SVC exception occurs, go to infinite loop */ - while(1) { - } -} - -/*! - \brief this function handles PendSV exception - \param[in] none - \param[out] none - \retval none -*/ -void PendSV_Handler(void) -{ - /* if PendSV exception occurs, go to infinite loop */ - while(1) { - } -} - -/*! - \brief this function handles SysTick exception - \param[in] none - \param[out] none - \retval none -*/ -void SysTick_Handler(void) { - led_heart_beat(); // LED心跳指示灯 - delay_decrement(); -} - -void USART0_IRQHandler(void) { - // 检查当前配置是否使用USART0，并且函数指针不为空 - if(g_usart_config.usart_periph == USART0 && g_usart_config.irq_handler != 0) { - g_usart_config.irq_handler(); // 通过函数指针调用对应的处理函数 - } -} - -void USART1_IRQHandler(void) { - // 检查当前配置是否使用USART1，并且函数指针不为空 - if(g_usart_config.usart_periph == USART1 && g_usart_config.irq_handler != 0) { - g_usart_config.irq_handler(); // 通过函数指针调用对应的处理函数 - } -} +/*! + \file gd32e23x_it.c + \brief interrupt service routines + + \version 2025-02-10, V2.4.0, demo for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x_it.h" +#include "systick.h" +#include "uart.h" +#include "uart_ring_buffer.h" +#include "led.h" +#include "board_config.h" + +/*! + \brief this function handles NMI exception + \param[in] none + \param[out] none + \retval none +*/ +void NMI_Handler(void) +{ + /* if NMI exception occurs, go to infinite loop */ + while(1) { + } +} + +/*! + \brief this function handles HardFault exception + \param[in] none + \param[out] none + \retval none +*/ +void HardFault_Handler(void) +{ + /* if Hard Fault exception occurs, go to infinite loop */ + while(1) { + } +} + +/*! + \brief this function handles SVC exception + \param[in] none + \param[out] none + \retval none +*/ +void SVC_Handler(void) +{ + /* if SVC exception occurs, go to infinite loop */ + while(1) { + } +} + +/*! + \brief this function handles PendSV exception + \param[in] none + \param[out] none + \retval none +*/ +void PendSV_Handler(void) +{ + /* if PendSV exception occurs, go to infinite loop */ + while(1) { + } +} + +/*! + \brief this function handles SysTick exception + \param[in] none + \param[out] none + \retval none +*/ +void SysTick_Handler(void) { + led_heart_beat(); // LED心跳指示灯 + delay_decrement(); +} + +void USART0_IRQHandler(void) { + // 检查当前配置是否使用USART0，并且函数指针不为空 + if(g_usart_config.usart_periph == USART0 && g_usart_config.irq_handler != 0) { + g_usart_config.irq_handler(); // 通过函数指针调用对应的处理函数 + } +} + +void USART1_IRQHandler(void) { + // 检查当前配置是否使用USART1，并且函数指针不为空 + if(g_usart_config.usart_periph == USART1 && g_usart_config.irq_handler != 0) { + g_usart_config.irq_handler(); // 通过函数指针调用对应的处理函数 + } +} diff --git a/Src/i2c.c b/Src/i2c.c index 44ba655..3507bfb 100644 --- a/Src/i2c.c +++ b/Src/i2c.c @@ -1,1158 +1,677 @@ -// -// Created by dell on 24-12-20. -// - -#include "i2c.h" - -/*! - \brief configure the GPIO ports - \param[in] none - \param[out] none - \retval none -*/ -void i2c_gpio_config(void) { - /* enable IIC GPIO clock */ - rcu_periph_clock_enable(RCU_GPIO_I2C); - - /* connect I2C_SCL_PIN to I2C_SCL */ - gpio_af_set(I2C_SCL_PORT, I2C_GPIO_AF, I2C_SCL_PIN); - /* connect I2C_SDA_PIN to I2C_SDA */ - gpio_af_set(I2C_SDA_PORT, I2C_GPIO_AF, I2C_SDA_PIN); - /* configure GPIO pins of I2C */ - gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SCL_PIN); - gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); - gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SDA_PIN); - gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); -} - -/*! - \brief configure the I2CX interface - \param[in] none - \param[out] none - \retval none -*/ -i2c_result_t i2c_config(void) { - /* configure I2C GPIO */ - i2c_gpio_config(); - /* enable I2C clock */ - rcu_periph_clock_enable(RCU_I2C); - /* configure I2C clock */ - i2c_clock_config(I2C0, I2C_SPEED, I2C_DTCY_2); - /* configure I2C address */ - i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0xA0); - /* enable I2CX */ - i2c_enable(I2C0); - /* enable acknowledge */ - i2c_ack_config(I2C0, I2C_ACK_ENABLE); - - return I2C_RESULT_SUCCESS; -} - -/* wait for SCL to go high, return true if successful, false if timeout */ -static bool i2c_wait_scl_high(uint16_t max_wait_time) { - while (max_wait_time--) { - if (gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN)) { - return true; - } - delay_10us(1); - } - return false; -} - -/* generate one manual SCL pulse; return true if SCL observed high (no stuck/overstretch) */ -static bool i2c_generate_scl_pulse(void) { - GPIO_BC(I2C_SCL_PORT) = I2C_SCL_PIN; /* drive SCL low */ - delay_10us(1); - GPIO_BOP(I2C_SCL_PORT) = I2C_SCL_PIN; /* release SCL (open-drain -> high via pull-up) */ - return i2c_wait_scl_high(200); /* wait up to ~2ms for clock stretching release */ -} - -/*! - \brief reset I2C bus - \param[in] none - \param[out] none - \retval none -*/ -i2c_result_t i2c_bus_reset(void) { - /* 1. Disable & deinit peripheral so pins can be fully controlled */ - i2c_disable(I2C0); - i2c_deinit(I2C0); - -#ifdef DEBUG_VERBOSE - printf("I2C bus reset\r\n"); -#endif - - /* 2. Configure SCL/SDA as GPIO open-drain outputs with pull-up and release them */ - gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SCL_PIN); - gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SDA_PIN); - gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); - gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); - gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN); /* release SCL */ - gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN); /* release SDA */ - -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: SCL = %d, SDA = %d\r\n", gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN), gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN)); -#endif - - /* 3. Double sample to confirm bus state */ - delay_10us(1); - bool scl_value1 = gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN); - bool sda_value1 = gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN); - delay_10us(1); - bool scl_value2 = gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN); - bool sda_value2 = gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN); - - /* 4. If SCL low -> stuck (cannot proceed) */ - if (!scl_value2) { -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: SCL stuck low\r\n"); -#endif - return I2C_RECOVERY_SCL_STUCK_LOW; - } - - /* 5. Fast path: bus idle */ - if (scl_value1 && sda_value1 && scl_value2 && sda_value2) { - i2c_config(); -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: bus idle\r\n"); -#endif - return I2C_RECOVERY_OK; - } - - /* 6. SDA low: attempt to free by generating up to I2C_RECOVERY_CLOCKS pulses */ - if (scl_value2 && !sda_value2) { - bool sda_released = false; -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: SCL will try to free SDA\r\n"); -#endif - for (uint8_t i = 0; i < I2C_RECOVERY_CLOCKS && !sda_released; i++) { - if (!i2c_generate_scl_pulse()) { - return I2C_RECOVERY_SCL_STUCK_LOW; /* SCL failed to go high */ - } - if (gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN)) { - sda_released = true; - } - } - if (!sda_released) { - return I2C_RECOVERY_SDA_STUCK_LOW; - } - /* 7. Generate a STOP condition to leave bus in idle state */ -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: generating STOP condition\r\n"); -#endif - gpio_bit_reset(I2C_SDA_PORT, I2C_SDA_PIN); /* SDA low */ - delay_10us(1); - gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN); /* ensure SCL high */ - delay_10us(1); - gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN); /* SDA rising while SCL high -> STOP */ - delay_10us(1); - } - -#ifdef DEBUG_VERBOSE - printf("I2C bus reset: bus recovered\r\n"); -#endif - /* 8. Reconfigure & enable peripheral */ - i2c_config(); - return I2C_RECOVERY_OK; -} - -/** - * @brief 扫描I2C总线，查找连接的设备 - * - * 该函数会扫描I2C总线上的所有地址（1到126），并尝试与每个地址进行通信。 - * 如果在某个地址上发现了设备，则会打印出该设备的地址。 - * 最后会打印出找到的设备总数。 - */ -void i2c_scan(void) { - uint32_t timeout; - uint8_t address; - int found_devices = 0; - - // printf("Scanning I2C bus...\r\n"); - const char* msg1 = "Scanning I2C bus...\r\n"; - for (uint8_t i = 0; msg1[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg1[i]); - } - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} - - for (address = 1; address < 127; address++) { - timeout = 0; - - // 生成起始条件 - while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) - timeout++; - if (timeout >= I2C_TIME_OUT) { - continue; // 超时，跳过该地址 - } - i2c_start_on_bus(I2C0); - timeout = 0; - - // 等待起始条件发送完成 - while (!i2c_flag_get(I2C0, I2C_FLAG_SBSEND) && (timeout < I2C_TIME_OUT)) - timeout++; - if (timeout >= I2C_TIME_OUT) { - continue; // 超时，跳过该地址 - } - i2c_master_addressing(I2C0, (address << 1), I2C_TRANSMITTER); - timeout = 0; - - // 等待地址发送完成 - while (!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND) && (timeout < I2C_TIME_OUT)) - timeout++; - if (timeout < I2C_TIME_OUT) { - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - // printf("Found device at 0x%02X\r\n", address); - const char* msg2_prefix = "Found device at 0x"; - for (uint8_t i = 0; msg2_prefix[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg2_prefix[i]); - } - // 发送地址的十六进制表示 - uint8_t hex_chars[] = "0123456789ABCDEF"; - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, hex_chars[(address >> 4) & 0x0F]); - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, hex_chars[address & 0x0F]); - const char* msg2_suffix = "\r\n"; - for (uint8_t i = 0; msg2_suffix[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg2_suffix[i]); - } - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} - found_devices++; - } - - // 生成停止条件 - i2c_stop_on_bus(I2C0); - - timeout = 0; - - while (i2c_flag_get(I2C0, I2C_FLAG_STPDET) && (timeout < I2C_TIME_OUT)) - timeout++; - } - - if (found_devices == 0) { - // printf("No I2C devices found.\r\n"); - const char* msg3 = "No I2C devices found.\r\n"; - for (uint8_t i = 0; msg3[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg3[i]); - } - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} - } else { - // printf("Total %d I2C devices found.\r\n", found_devices); - const char* msg4_prefix = "Total "; - for (uint8_t i = 0; msg4_prefix[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg4_prefix[i]); - } - // 发送设备数量 - if (found_devices >= 10) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, '0' + (found_devices / 10)); - } - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, '0' + (found_devices % 10)); - const char* msg4_suffix = " I2C devices found.\r\n"; - for (uint8_t i = 0; msg4_suffix[i] != '\0'; i++) { - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(I2C_DEBUG_UART, msg4_suffix[i]); - } - while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} - } -} - -i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) { - i2c_state_t state = I2C_STATE_START; - uint16_t timeout = 0; - uint8_t retry_count = 0; - - /* parameter validation */ - if (data == NULL || slave_addr > 0x7F) { - return I2C_RESULT_INVALID_PARAM; - } - - while (retry_count < I2C_MAX_RETRY) { - switch (state) { - case I2C_STATE_START: - timeout = 0; - - /* wait for bus to be idle */ - while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - i2c_start_on_bus(I2C0); - timeout = 0; - state = I2C_STATE_SEND_ADDRESS; - break; - - case I2C_STATE_SEND_ADDRESS: - /* wait for start condition to be sent. SBSEND flag */ - while((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send slave address */ - i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER); - timeout = 0; - state = I2C_STATE_CLEAR_ADDRESS; - break; - - case I2C_STATE_CLEAR_ADDRESS: - /* wait for address to be acknowledged.ADDSEND set means i2c slave sends ACK */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (!i2c_flag_get(I2C0, I2C_FLAG_AERR)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } else if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) - { - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - timeout =0; - state = I2C_STATE_TRANSMIT_REG; - break; - } else { - i2c_flag_clear(I2C0, I2C_FLAG_AERR); - timeout =0; -#ifdef DEBUG_VERBOES - printf("IIC write failed for Error Slave Address. \n"); -#endif - return I2C_RESULT_NACK; - } - - case I2C_STATE_TRANSMIT_REG: - /* wait until the transmit data buffer is empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send register address */ - i2c_data_transmit(I2C0, reg_addr); - timeout = 0; - state = I2C_STATE_TRANSMIT_DATA; - break; - - case I2C_STATE_TRANSMIT_DATA: - /* wait until the transmit data buffer is empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send register MSB value */ - i2c_data_transmit(I2C0, data[0]); - timeout = 0; - - /* wait until the transmit data buffer is empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { - i2c_stop_on_bus(I2C0); - return I2C_RESULT_NACK; - } else if (i2c_flag_get(I2C0, I2C_FLAG_BERR) || i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) { - // 可按需清标志 - i2c_stop_on_bus(I2C0); - return I2C_RESULT_ERROR; - } - - /* send register LSB value */ - i2c_data_transmit(I2C0, data[1]); - timeout = 0; - - /* wait until BTC bit is set */ - while (!i2c_flag_get(I2C0, I2C_FLAG_BTC) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - state = I2C_STATE_STOP; - break; - - case I2C_STATE_STOP: - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(I2C0); - - timeout = 0; - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* i2c master sends STOP signal successfully */ - /* success */ - return I2C_RESULT_SUCCESS; - - case I2C_STATE_ERROR: - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(I2C0); - - timeout = 0; - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - return I2C_RESULT_ERROR; - } - - i2c_flag_clear(I2C0, I2C_FLAG_AERR); - i2c_flag_clear(I2C0, I2C_FLAG_BERR); - i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB); - - retry_count ++; - if (retry_count >= I2C_MAX_RETRY) - { -#ifdef DEBUG_VERBOES - printf("IIC write failed after %d retries\n", I2C_MAX_RETRY); -#endif - return I2C_RESULT_ERROR; - } - - /* reset state machine for retry */ - state = I2C_STATE_START; - timeout = 0; - - /* small delay before retry */ - delay_10us(10); - break; - - default: - state = I2C_STATE_START; - break; - } - } - return I2C_RESULT_TIMEOUT; -} - -i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) { - i2c_state_t state = I2C_STATE_START; - uint16_t timeout = 0; - uint8_t retry_count = 0; - bool write_phase = true; - - // 参数检查：防止空指针和非法地址 - if (data == NULL || slave_addr > 0x7F) { - return I2C_RESULT_INVALID_PARAM; - } - - /* enable acknowledge */ - i2c_ack_config(I2C0, I2C_ACK_ENABLE); - - while (retry_count < (uint8_t)I2C_MAX_RETRY) { - switch (state) { - case I2C_STATE_START: - timeout = 0; - - // wait for bus to be idle - while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - // send start condition - i2c_start_on_bus(I2C0); - state = I2C_STATE_SEND_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_SEND_ADDRESS: - /* wait for start condition to be sent */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - // send slave address - if (write_phase) { - /* write phase: send address with write bit */ - i2c_master_addressing(I2C0, (slave_addr << 1), I2C_TRANSMITTER); - } else { - /* read phase: send address with read bit */ - i2c_master_addressing(I2C0, (slave_addr << 1) | 0x01, I2C_RECEIVER); - } - - state = I2C_STATE_CLEAR_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_CLEAR_ADDRESS: - /* wait for address to be acknowledged */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - if (write_phase) { - /* clear address flag (write phase) */ - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - state = I2C_STATE_TRANSMIT_DATA; - } else { - /* READ phase for 2 bytes: set POS=NEXT and disable ACK BEFORE clearing ADDR */ - i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT); - i2c_ack_config(I2C0, I2C_ACK_DISABLE); - - /* now clear address flag to release SCL and enter data phase */ - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - - state = I2C_STATE_RECEIVE_DATA; - } - - timeout = 0; - break; - - case I2C_STATE_TRANSMIT_DATA: - /* wait for transmit buffer to be empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send register address */ - i2c_data_transmit(I2C0, reg_addr); - state = I2C_STATE_RESTART; - timeout = 0; - break; - - case I2C_STATE_RESTART: - /* wait for byte transfer complete BTC: Bit Transfer Complete */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* generate repeated start condition */ - i2c_start_on_bus(I2C0); - - /* wait for repeated start condition to be sent */ - timeout = 0; - while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send slave address with read bit (R/W bit is set by library) */ - i2c_master_addressing(I2C0, (slave_addr << 1), I2C_RECEIVER); - - /* switch to read phase */ - write_phase = false; - state = I2C_STATE_CLEAR_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_RECEIVE_DATA: - /* Wait for BTC (both bytes received) */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* Send STOP before reading the last two bytes */ - i2c_stop_on_bus(I2C0); - - /* Read the two bytes back-to-back */ - data[0] = i2c_data_receive(I2C0); - data[1] = i2c_data_receive(I2C0); - - state = I2C_STATE_STOP; - break; - - case I2C_STATE_STOP: - /* wait for stop condition to complete */ - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* i2c master sends STOP signal successfully */ - /* success */ - return I2C_RESULT_SUCCESS; - - case I2C_STATE_ERROR: - /* send stop condition to release bus */ - i2c_stop_on_bus(I2C0); - - retry_count++; - if (retry_count >= I2C_MAX_RETRY) { -#ifdef DEBUG_VERBOES - printf("IIC read failed after %d retries\n", I2C_RETRY_MAX); -#endif - return I2C_RESULT_ERROR; - } - - /* reset state machine for retry */ - state = I2C_STATE_START; - write_phase = true; - timeout = 0; - - /* small delay before retry */ - delay_10us(10); - break; - - default: - state = I2C_STATE_START; - break; - } - } - return I2C_RESULT_TIMEOUT; -} - -/*! - \brief write data to I2C device with configurable length - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[in] data: pointer to data buffer - \param[in] length: number of bytes to write (1-255) - \param[out] none - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_write(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length) { - i2c_state_t state = I2C_STATE_START; - uint16_t timeout = 0; - uint8_t retry_count = 0; - uint8_t data_index = 0; - - /* parameter validation */ - if (data == NULL || slave_addr > 0x7F || length == 0) { - return I2C_RESULT_INVALID_PARAM; - } - - while (retry_count < I2C_MAX_RETRY) { - switch (state) { - case I2C_STATE_START: - timeout = 0; - data_index = 0; - - /* wait for bus to be idle */ - while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - i2c_start_on_bus(I2C0); - timeout = 0; - state = I2C_STATE_SEND_ADDRESS; - break; - - case I2C_STATE_SEND_ADDRESS: - /* wait for start condition to be sent. SBSEND flag */ - while((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send slave address */ - i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER); - timeout = 0; - state = I2C_STATE_CLEAR_ADDRESS; - break; - - case I2C_STATE_CLEAR_ADDRESS: - /* wait for address to be acknowledged.ADDSEND set means i2c slave sends ACK */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (!i2c_flag_get(I2C0, I2C_FLAG_AERR)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } else if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) { - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - timeout = 0; - state = I2C_STATE_TRANSMIT_REG; - break; - } else { - i2c_flag_clear(I2C0, I2C_FLAG_AERR); - timeout = 0; -#ifdef DEBUG_VERBOSE - printf("IIC write failed for Error Slave Address. \n"); -#endif - return I2C_RESULT_NACK; - } - - case I2C_STATE_TRANSMIT_REG: - /* wait until the transmit data buffer is empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send register address */ - i2c_data_transmit(I2C0, reg_addr); - timeout = 0; - state = I2C_STATE_TRANSMIT_DATA; - break; - - case I2C_STATE_TRANSMIT_DATA: - /* wait until the transmit data buffer is empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send data byte */ - i2c_data_transmit(I2C0, data[data_index]); - data_index++; - - /* check for errors */ - if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { - i2c_stop_on_bus(I2C0); - return I2C_RESULT_NACK; - } else if (i2c_flag_get(I2C0, I2C_FLAG_BERR) || i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) { - i2c_stop_on_bus(I2C0); - return I2C_RESULT_ERROR; - } - - /* check if all data has been sent */ - if (data_index >= length) { - /* wait until BTC bit is set for last byte */ - timeout = 0; - while (!i2c_flag_get(I2C0, I2C_FLAG_BTC) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - state = I2C_STATE_STOP; - } - timeout = 0; - break; - - case I2C_STATE_STOP: - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(I2C0); - - timeout = 0; - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* success */ - return I2C_RESULT_SUCCESS; - - case I2C_STATE_ERROR: - /* send a stop condition to I2C bus */ - i2c_stop_on_bus(I2C0); - - timeout = 0; - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - - i2c_flag_clear(I2C0, I2C_FLAG_AERR); - i2c_flag_clear(I2C0, I2C_FLAG_BERR); - i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB); - - retry_count++; - if (retry_count >= I2C_MAX_RETRY) { -#ifdef DEBUG_VERBOSE - printf("IIC write failed after %d retries\n", I2C_MAX_RETRY); -#endif - return I2C_RESULT_ERROR; - } - - /* reset state machine for retry */ - state = I2C_STATE_START; - timeout = 0; - - /* small delay before retry */ - delay_10us(10); - break; - - default: - state = I2C_STATE_START; - break; - } - } - return I2C_RESULT_TIMEOUT; -} - -/*! - \brief read data from I2C device with configurable length - \param[in] slave_addr: slave device address (7-bit) - \param[in] reg_addr: register address - \param[out] data: pointer to data buffer - \param[in] length: number of bytes to read (1-255) - \retval i2c_result_t: operation result -*/ -i2c_result_t i2c_read(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length) { - i2c_state_t state = I2C_STATE_START; - uint16_t timeout = 0; - uint8_t retry_count = 0; - bool write_phase = true; - uint8_t data_index = 0; - - /* parameter validation */ - if (data == NULL || slave_addr > 0x7F || length == 0) { - return I2C_RESULT_INVALID_PARAM; - } - - /* enable acknowledge */ - i2c_ack_config(I2C0, I2C_ACK_ENABLE); - - while (retry_count < (uint8_t)I2C_MAX_RETRY) { - switch (state) { - case I2C_STATE_START: - timeout = 0; - data_index = 0; - - /* wait for bus to be idle */ - while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send start condition */ - i2c_start_on_bus(I2C0); - state = I2C_STATE_SEND_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_SEND_ADDRESS: - /* wait for start condition to be sent */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send slave address */ - if (write_phase) { - /* write phase: send address with write bit */ - i2c_master_addressing(I2C0, (slave_addr << 1), I2C_TRANSMITTER); - } else { - /* read phase: send address with read bit */ - i2c_master_addressing(I2C0, (slave_addr << 1) | 0x01, I2C_RECEIVER); - } - - state = I2C_STATE_CLEAR_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_CLEAR_ADDRESS: - /* wait for address to be acknowledged */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - if (write_phase) { - /* clear address flag (write phase) */ - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - state = I2C_STATE_TRANSMIT_DATA; - } else { - /* read phase setup based on length */ - if (length == 1) { - /* single byte read: disable ACK before clearing ADDR */ - i2c_ack_config(I2C0, I2C_ACK_DISABLE); - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - /* send STOP immediately after clearing ADDR for single byte */ - i2c_stop_on_bus(I2C0); - } else if (length == 2) { - /* two bytes read: set POS=NEXT and disable ACK before clearing ADDR */ - i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT); - i2c_ack_config(I2C0, I2C_ACK_DISABLE); - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - } else { - /* multi-byte read: clear ADDR with ACK enabled */ - i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); - } - state = I2C_STATE_RECEIVE_DATA; - } - timeout = 0; - break; - - case I2C_STATE_TRANSMIT_DATA: - /* wait for transmit buffer to be empty */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send register address */ - i2c_data_transmit(I2C0, reg_addr); - state = I2C_STATE_RESTART; - timeout = 0; - break; - - case I2C_STATE_RESTART: - /* wait for byte transfer complete */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* generate repeated start condition */ - i2c_start_on_bus(I2C0); - - /* wait for repeated start condition to be sent */ - timeout = 0; - while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* send slave address with read bit */ - i2c_master_addressing(I2C0, (slave_addr << 1), I2C_RECEIVER); - - /* switch to read phase */ - write_phase = false; - state = I2C_STATE_CLEAR_ADDRESS; - timeout = 0; - break; - - case I2C_STATE_RECEIVE_DATA: - if (length == 1) { - /* single byte read */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - data[0] = i2c_data_receive(I2C0); - state = I2C_STATE_STOP; - } else if (length == 2) { - /* two bytes read */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - /* send STOP before reading the last two bytes */ - i2c_stop_on_bus(I2C0); - /* read the two bytes back-to-back */ - data[0] = i2c_data_receive(I2C0); - data[1] = i2c_data_receive(I2C0); - state = I2C_STATE_STOP; - } else { - /* multi-byte read (length > 2) */ - while (data_index < length) { - /* wait for RBNE (receive buffer not empty) */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_RBNE)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* special handling for last 3 bytes */ - if (data_index == length - 3) { - /* wait for BTF (byte transfer finished) before reading N-2 */ - while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - /* disable ACK for last 2 bytes */ - i2c_ack_config(I2C0, I2C_ACK_DISABLE); - } - - /* read data byte */ - data[data_index] = i2c_data_receive(I2C0); - data_index++; - - /* send STOP after reading N-1 byte */ - if (data_index == length - 1) { - i2c_stop_on_bus(I2C0); - } - - timeout = 0; - } - state = I2C_STATE_STOP; - } - break; - - case I2C_STATE_STOP: - /* wait for stop condition to complete */ - while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { - timeout++; - } - if (timeout >= I2C_TIME_OUT) { - state = I2C_STATE_ERROR; - break; - } - - /* reset ACK configuration for next operation */ - i2c_ack_config(I2C0, I2C_ACK_ENABLE); - i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); - - /* success */ - return I2C_RESULT_SUCCESS; - - case I2C_STATE_ERROR: - /* send stop condition to release bus */ - i2c_stop_on_bus(I2C0); - - /* reset ACK configuration */ - i2c_ack_config(I2C0, I2C_ACK_ENABLE); - i2c_ackpos_config(I2C0, I2C_ACKPOS_CURRENT); - - retry_count++; - if (retry_count >= I2C_MAX_RETRY) { -#ifdef DEBUG_VERBOSE - printf("I2C read failed after %d retries\n", I2C_MAX_RETRY); -#endif - return I2C_RESULT_ERROR; - } - - /* reset state machine for retry */ - state = I2C_STATE_START; - write_phase = true; - timeout = 0; - - /* small delay before retry */ - delay_10us(10); - break; - - default: - state = I2C_STATE_START; - break; - } - } - return I2C_RESULT_TIMEOUT; -} - -/* convenience functions for common operations */ -i2c_result_t i2c_write_8bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data) { - return i2c_write(slave_addr, reg_addr, &data, 1); -} - -i2c_result_t i2c_read_8bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) { - return i2c_read(slave_addr, reg_addr, data, 1); -} - -i2c_result_t i2c_write_32bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[4]) { - return i2c_write(slave_addr, reg_addr, data, 4); -} - -i2c_result_t i2c_read_32bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) { - return i2c_read(slave_addr, reg_addr, data, 4); -} - -/* 显示面板专用函数 - 支持读取显示界面参数 */ -i2c_result_t i2c_read_display_params(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data, uint8_t length) { - /* 针对显示面板的多字节读取，支持13字节的完整参数读取 */ - if (length > 13) { - return I2C_RESULT_INVALID_PARAM; - } - return i2c_read(slave_addr, reg_addr, data, length); -} - -#ifdef DEBUG_VERBOSE -/*! - \brief get status string for debugging - \param[in] status: i2c_status_t value - \param[out] none - \retval const char* status string -*/ -const char* i2c_get_status_string(i2c_result_t status) { - switch (status) { - case I2C_RESULT_SUCCESS: - return "SUCCESS"; - case I2C_RESULT_TIMEOUT: - return "TIMEOUT"; - case I2C_RESULT_NACK: - return "NACK"; - case I2C_RESULT_BUS_BUSY: - return "BUS_BUSY"; - case I2C_RESULT_ERROR: - return "ERROR"; - case I2C_RESULT_INVALID_PARAM: - return "INVALID_PARAM"; - default: - return "UNKNOWN"; - } -} -#endif +// +// Created by dell on 24-12-20. +// + +#include "i2c.h" + +/*! + \brief configure the GPIO ports + \param[in] none + \param[out] none + \retval none +*/ +void i2c_gpio_config(void) { + /* enable IIC GPIO clock */ + rcu_periph_clock_enable(RCU_GPIO_I2C); + + /* connect I2C_SCL_PIN to I2C_SCL */ + gpio_af_set(I2C_SCL_PORT, I2C_GPIO_AF, I2C_SCL_PIN); + /* connect I2C_SDA_PIN to I2C_SDA */ + gpio_af_set(I2C_SDA_PORT, I2C_GPIO_AF, I2C_SDA_PIN); + /* configure GPIO pins of I2C */ + gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SCL_PIN); + gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); + gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, I2C_SDA_PIN); + gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); +} + +/*! + \brief configure the I2CX interface + \param[in] none + \param[out] none + \retval none +*/ +i2c_result_t i2c_config(void) { + /* configure I2C GPIO */ + i2c_gpio_config(); + /* enable I2C clock */ + rcu_periph_clock_enable(RCU_I2C); + /* configure I2C clock */ + i2c_clock_config(I2C0, I2C_SPEED, I2C_DTCY_2); + /* configure I2C address */ + i2c_mode_addr_config(I2C0, I2C_I2CMODE_ENABLE, I2C_ADDFORMAT_7BITS, 0xA0); + /* enable I2CX */ + i2c_enable(I2C0); + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + + return I2C_RESULT_SUCCESS; +} + +/* wait for SCL to go high, return true if successful, false if timeout */ +static bool i2c_wait_scl_high(uint16_t max_wait_time) { + while (max_wait_time--) { + if (gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN)) { + return true; + } + delay_10us(1); + } + return false; +} + +/* generate one manual SCL pulse; return true if SCL observed high (no stuck/overstretch) */ +static bool i2c_generate_scl_pulse(void) { + GPIO_BC(I2C_SCL_PORT) = I2C_SCL_PIN; /* drive SCL low */ + delay_10us(1); + GPIO_BOP(I2C_SCL_PORT) = I2C_SCL_PIN; /* release SCL (open-drain -> high via pull-up) */ + return i2c_wait_scl_high(200); /* wait up to ~2ms for clock stretching release */ +} + +/*! + \brief reset I2C bus + \param[in] none + \param[out] none + \retval none +*/ +i2c_result_t i2c_bus_reset(void) { + /* 1. Disable & deinit peripheral so pins can be fully controlled */ + i2c_disable(I2C0); + i2c_deinit(I2C0); + +#ifdef DEBUG_VERBOSE + printf("I2C bus reset\r\n"); +#endif + + /* 2. Configure SCL/SDA as GPIO open-drain outputs with pull-up and release them */ + gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SCL_PIN); + gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SDA_PIN); + gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); + gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); + gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN); /* release SCL */ + gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN); /* release SDA */ + +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: SCL = %d, SDA = %d\r\n", gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN), gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN)); +#endif + + /* 3. Double sample to confirm bus state */ + delay_10us(1); + bool scl_value1 = gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN); + bool sda_value1 = gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN); + delay_10us(1); + bool scl_value2 = gpio_input_bit_get(I2C_SCL_PORT, I2C_SCL_PIN); + bool sda_value2 = gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN); + + /* 4. If SCL low -> stuck (cannot proceed) */ + if (!scl_value2) { +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: SCL stuck low\r\n"); +#endif + return I2C_RECOVERY_SCL_STUCK_LOW; + } + + /* 5. Fast path: bus idle */ + if (scl_value1 && sda_value1 && scl_value2 && sda_value2) { + i2c_config(); +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: bus idle\r\n"); +#endif + return I2C_RECOVERY_OK; + } + + /* 6. SDA low: attempt to free by generating up to I2C_RECOVERY_CLOCKS pulses */ + if (scl_value2 && !sda_value2) { + bool sda_released = false; +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: SCL will try to free SDA\r\n"); +#endif + for (uint8_t i = 0; i < I2C_RECOVERY_CLOCKS && !sda_released; i++) { + if (!i2c_generate_scl_pulse()) { + return I2C_RECOVERY_SCL_STUCK_LOW; /* SCL failed to go high */ + } + if (gpio_input_bit_get(I2C_SDA_PORT, I2C_SDA_PIN)) { + sda_released = true; + } + } + if (!sda_released) { + return I2C_RECOVERY_SDA_STUCK_LOW; + } + /* 7. Generate a STOP condition to leave bus in idle state */ +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: generating STOP condition\r\n"); +#endif + gpio_bit_reset(I2C_SDA_PORT, I2C_SDA_PIN); /* SDA low */ + delay_10us(1); + gpio_bit_set(I2C_SCL_PORT, I2C_SCL_PIN); /* ensure SCL high */ + delay_10us(1); + gpio_bit_set(I2C_SDA_PORT, I2C_SDA_PIN); /* SDA rising while SCL high -> STOP */ + delay_10us(1); + } + +#ifdef DEBUG_VERBOSE + printf("I2C bus reset: bus recovered\r\n"); +#endif + /* 8. Reconfigure & enable peripheral */ + i2c_config(); + return I2C_RECOVERY_OK; +} + +/** + * @brief 扫描I2C总线，查找连接的设备 + * + * 该函数会扫描I2C总线上的所有地址（1到126），并尝试与每个地址进行通信。 + * 如果在某个地址上发现了设备，则会打印出该设备的地址。 + * 最后会打印出找到的设备总数。 + */ +void i2c_scan(void) { + uint32_t timeout; + uint8_t address; + int found_devices = 0; + + // printf("Scanning I2C bus...\r\n"); + const char* msg1 = "Scanning I2C bus...\r\n"; + for (uint8_t i = 0; msg1[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg1[i]); + } + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} + + for (address = 1; address < 127; address++) { + timeout = 0; + + // 生成起始条件 + while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) + timeout++; + if (timeout >= I2C_TIME_OUT) { + continue; // 超时，跳过该地址 + } + i2c_start_on_bus(I2C0); + timeout = 0; + + // 等待起始条件发送完成 + while (!i2c_flag_get(I2C0, I2C_FLAG_SBSEND) && (timeout < I2C_TIME_OUT)) + timeout++; + if (timeout >= I2C_TIME_OUT) { + continue; // 超时，跳过该地址 + } + i2c_master_addressing(I2C0, (address << 1), I2C_TRANSMITTER); + timeout = 0; + + // 等待地址发送完成 + while (!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND) && (timeout < I2C_TIME_OUT)) + timeout++; + if (timeout < I2C_TIME_OUT) { + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + // printf("Found device at 0x%02X\r\n", address); + const char* msg2_prefix = "Found device at 0x"; + for (uint8_t i = 0; msg2_prefix[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg2_prefix[i]); + } + // 发送地址的十六进制表示 + uint8_t hex_chars[] = "0123456789ABCDEF"; + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, hex_chars[(address >> 4) & 0x0F]); + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, hex_chars[address & 0x0F]); + const char* msg2_suffix = "\r\n"; + for (uint8_t i = 0; msg2_suffix[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg2_suffix[i]); + } + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} + found_devices++; + } + + // 生成停止条件 + i2c_stop_on_bus(I2C0); + + timeout = 0; + + while (i2c_flag_get(I2C0, I2C_FLAG_STPDET) && (timeout < I2C_TIME_OUT)) + timeout++; + } + + if (found_devices == 0) { + // printf("No I2C devices found.\r\n"); + const char* msg3 = "No I2C devices found.\r\n"; + for (uint8_t i = 0; msg3[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg3[i]); + } + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} + } else { + // printf("Total %d I2C devices found.\r\n", found_devices); + const char* msg4_prefix = "Total "; + for (uint8_t i = 0; msg4_prefix[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg4_prefix[i]); + } + // 发送设备数量 + if (found_devices >= 10) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, '0' + (found_devices / 10)); + } + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, '0' + (found_devices % 10)); + const char* msg4_suffix = " I2C devices found.\r\n"; + for (uint8_t i = 0; msg4_suffix[i] != '\0'; i++) { + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(I2C_DEBUG_UART, msg4_suffix[i]); + } + while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} + } +} + +i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) { + i2c_state_t state = I2C_STATE_START; + uint16_t timeout = 0; + uint8_t retry_count = 0; + + /* parameter validation */ + if (data == NULL || slave_addr > 0x7F) { + return I2C_RESULT_INVALID_PARAM; + } + + while (retry_count < I2C_MAX_RETRY) { + switch (state) { + case I2C_STATE_START: + timeout = 0; + + /* wait for bus to be idle */ + while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + i2c_start_on_bus(I2C0); + timeout = 0; + state = I2C_STATE_SEND_ADDRESS; + break; + + case I2C_STATE_SEND_ADDRESS: + /* wait for start condition to be sent. SBSEND flag */ + while((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* send slave address */ + i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER); + timeout = 0; + state = I2C_STATE_CLEAR_ADDRESS; + break; + + case I2C_STATE_CLEAR_ADDRESS: + /* wait for address to be acknowledged.ADDSEND set means i2c slave sends ACK */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (!i2c_flag_get(I2C0, I2C_FLAG_AERR)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } else if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) + { + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + timeout =0; + state = I2C_STATE_TRANSMIT_REG; + break; + } else { + i2c_flag_clear(I2C0, I2C_FLAG_AERR); + timeout =0; +#ifdef DEBUG_VERBOES + printf("IIC write failed for Error Slave Address. \n"); +#endif + return I2C_RESULT_NACK; + } + + case I2C_STATE_TRANSMIT_REG: + /* wait until the transmit data buffer is empty */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* send register address */ + i2c_data_transmit(I2C0, reg_addr); + timeout = 0; + state = I2C_STATE_TRANSMIT_DATA; + break; + + case I2C_STATE_TRANSMIT_DATA: + /* wait until the transmit data buffer is empty */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* send register MSB value */ + i2c_data_transmit(I2C0, data[0]); + timeout = 0; + + /* wait until the transmit data buffer is empty */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { + i2c_stop_on_bus(I2C0); + return I2C_RESULT_NACK; + } else if (i2c_flag_get(I2C0, I2C_FLAG_BERR) || i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) { + // 可按需清标志 + i2c_stop_on_bus(I2C0); + return I2C_RESULT_ERROR; + } + + /* send register LSB value */ + i2c_data_transmit(I2C0, data[1]); + timeout = 0; + + /* wait until BTC bit is set */ + while (!i2c_flag_get(I2C0, I2C_FLAG_BTC) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + state = I2C_STATE_STOP; + break; + + case I2C_STATE_STOP: + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + + timeout = 0; + while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* i2c master sends STOP signal successfully */ + /* success */ + return I2C_RESULT_SUCCESS; + + case I2C_STATE_ERROR: + /* send a stop condition to I2C bus */ + i2c_stop_on_bus(I2C0); + + timeout = 0; + while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + return I2C_RESULT_ERROR; + } + + i2c_flag_clear(I2C0, I2C_FLAG_AERR); + i2c_flag_clear(I2C0, I2C_FLAG_BERR); + i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB); + + retry_count ++; + if (retry_count >= I2C_MAX_RETRY) + { +#ifdef DEBUG_VERBOES + printf("IIC write failed after %d retries\n", I2C_MAX_RETRY); +#endif + return I2C_RESULT_ERROR; + } + + /* reset state machine for retry */ + state = I2C_STATE_START; + timeout = 0; + + /* small delay before retry */ + delay_10us(10); + break; + + default: + state = I2C_STATE_START; + break; + } + } + return I2C_RESULT_TIMEOUT; +} + +i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) { + i2c_state_t state = I2C_STATE_START; + uint16_t timeout = 0; + uint8_t retry_count = 0; + bool write_phase = true; + + // 参数检查：防止空指针和非法地址 + if (data == NULL || slave_addr > 0x7F) { + return I2C_RESULT_INVALID_PARAM; + } + + /* enable acknowledge */ + i2c_ack_config(I2C0, I2C_ACK_ENABLE); + + while (retry_count < (uint8_t)I2C_MAX_RETRY) { + switch (state) { + case I2C_STATE_START: + timeout = 0; + + // wait for bus to be idle + while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + // send start condition + i2c_start_on_bus(I2C0); + state = I2C_STATE_SEND_ADDRESS; + timeout = 0; + break; + + case I2C_STATE_SEND_ADDRESS: + /* wait for start condition to be sent */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + // send slave address + if (write_phase) { + /* write phase: send address with write bit */ + i2c_master_addressing(I2C0, (slave_addr << 1), I2C_TRANSMITTER); + } else { + /* read phase: send address with read bit */ + i2c_master_addressing(I2C0, (slave_addr << 1) | 0x01, I2C_RECEIVER); + } + + state = I2C_STATE_CLEAR_ADDRESS; + timeout = 0; + break; + + case I2C_STATE_CLEAR_ADDRESS: + /* wait for address to be acknowledged */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + if (write_phase) { + /* clear address flag (write phase) */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + state = I2C_STATE_TRANSMIT_DATA; + } else { + /* READ phase for 2 bytes: set POS=NEXT and disable ACK BEFORE clearing ADDR */ + i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT); + i2c_ack_config(I2C0, I2C_ACK_DISABLE); + + /* now clear address flag to release SCL and enter data phase */ + i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); + + state = I2C_STATE_RECEIVE_DATA; + } + + timeout = 0; + break; + + case I2C_STATE_TRANSMIT_DATA: + /* wait for transmit buffer to be empty */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* send register address */ + i2c_data_transmit(I2C0, reg_addr); + state = I2C_STATE_RESTART; + timeout = 0; + break; + + case I2C_STATE_RESTART: + /* wait for byte transfer complete BTC: Bit Transfer Complete */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* generate repeated start condition */ + i2c_start_on_bus(I2C0); + + /* wait for repeated start condition to be sent */ + timeout = 0; + while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* send slave address with read bit (R/W bit is set by library) */ + i2c_master_addressing(I2C0, (slave_addr << 1), I2C_RECEIVER); + + /* switch to read phase */ + write_phase = false; + state = I2C_STATE_CLEAR_ADDRESS; + timeout = 0; + break; + + case I2C_STATE_RECEIVE_DATA: + /* Wait for BTC (both bytes received) */ + while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* Send STOP before reading the last two bytes */ + i2c_stop_on_bus(I2C0); + + /* Read the two bytes back-to-back */ + data[0] = i2c_data_receive(I2C0); + data[1] = i2c_data_receive(I2C0); + + state = I2C_STATE_STOP; + break; + + case I2C_STATE_STOP: + /* wait for stop condition to complete */ + while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { + timeout++; + } + if (timeout >= I2C_TIME_OUT) { + state = I2C_STATE_ERROR; + break; + } + + /* i2c master sends STOP signal successfully */ + /* success */ + return I2C_RESULT_SUCCESS; + + case I2C_STATE_ERROR: + /* send stop condition to release bus */ + i2c_stop_on_bus(I2C0); + + retry_count++; + if (retry_count >= I2C_MAX_RETRY) { +#ifdef DEBUG_VERBOES + printf("IIC read failed after %d retries\n", I2C_RETRY_MAX); +#endif + return I2C_RESULT_ERROR; + } + + /* reset state machine for retry */ + state = I2C_STATE_START; + write_phase = true; + timeout = 0; + + /* small delay before retry */ + delay_10us(10); + break; + + default: + state = I2C_STATE_START; + break; + } + } + return I2C_RESULT_TIMEOUT; +} + +#ifdef DEBUG_VERBOSE +/*! + \brief get status string for debugging + \param[in] status: i2c_status_t value + \param[out] none + \retval const char* status string +*/ +const char* i2c_get_status_string(i2c_result_t status) { + switch (status) { + case I2C_RESULT_SUCCESS: + return "SUCCESS"; + case I2C_RESULT_TIMEOUT: + return "TIMEOUT"; + case I2C_RESULT_NACK: + return "NACK"; + case I2C_RESULT_BUS_BUSY: + return "BUS_BUSY"; + case I2C_RESULT_ERROR: + return "ERROR"; + case I2C_RESULT_INVALID_PARAM: + return "INVALID_PARAM"; + default: + return "UNKNOWN"; + } +} +#endif diff --git a/Src/ldc1612.c b/Src/ldc1612.c index f671e75..9042ef8 100644 --- a/Src/ldc1612.c +++ b/Src/ldc1612.c @@ -1,335 +1,246 @@ -// -// Created by dell on 24-12-3. -// - -#include "ldc1612.h" - -#ifdef LDC_DEBUG - #include - #define LDC1612_DEBUG(fmt, ...) printf("[LDC1612] " fmt "\n", ##__VA_ARGS__) -#else - #define LDC1612_DEBUG(fmt, ...) -#endif - -/*! - \brief 写入寄存器 - \param[in] reg_addr: 寄存器地址 - \param[in] value: 写入值 - \param[out] none - \retval i2c_result_t -*/ -static i2c_result_t ldc1612_write_register(uint8_t reg_addr, uint16_t value) { - uint8_t data[2]; - data[0] = (value >> 8) & 0xFF; - data[1] = value & 0xFF; - - return LDC1612_IIC_WRITE_16BITS(LDC1612_ADDR, reg_addr, data); -} - -/*! - \brief 读取寄存器 - \param[in] reg_addr: 寄存器地址 - \param[out] value: 读取值指针 - \retval i2c_status_t -*/ -static i2c_result_t ldc1612_read_register(uint8_t reg_addr, uint16_t *value) { - uint8_t data[2]; - i2c_result_t status; - - if (value == NULL) { - return I2C_RESULT_INVALID_PARAM; - } - - status = LDC1612_IIC_READ_16BITS(LDC1612_ADDR, reg_addr, data); - if (status == I2C_RESULT_SUCCESS) { - *value = ((uint16_t)data[0] << 8) | data[1]; - } - - return status; -} - -/*! - \brief 计算并获取频率分频值 - \param[in] channel: 通道号 - \param[out] none - \retval 计算得到的频率分频值 -*/ -static uint16_t ldc1612_calculate_freq_divider(uint8_t channel) { - uint16_t value; - uint16_t fin_div, freq_div; - float sensor_freq; - - sensor_freq = 1 / (2 * 3.14 * sqrt(COIL_L_UH * COIL_C_PF * pow(10, -18))) * pow(10, -6); - if (sensor_freq <= 8.75) { - fin_div = LDC1612_FIN_DIV_1; - } else if (sensor_freq <= 17.5) { - fin_div = LDC1612_FIN_DIV_2; - } else if (sensor_freq <= 35.0) { - fin_div = LDC1612_FIN_DIV_4; - } else { - LDC1612_DEBUG("Error: Sensor frequency (%.2f MHz) exceeds maximum limit!", sensor_freq); - return 0; - - } - -/* - Fref为参考时钟频率，单位MHz，必须小于35MHz，如果输入时钟为外部时钟40MHz，则需要分频 - LDC1612_EXT_CLK_MHZ为外部时钟频率，单位MHz - Fin为传感器谐振频率，单位MHz。 - 必须满足：Fin < Fref / 4 - 通常高精度应用，采用外部40MHz，2分频，Fin不应超5MHz。 -*/ - if (LDC1612_EXT_CLK_MHZ >= 35) - { - freq_div = LDC1612_FREF_DIV_2; - } else { - freq_div = LDC1612_FREF_DIV_1; - } - - if (sensor_freq >= (LDC1612_EXT_CLK_MHZ / freq_div) / 4) - { - LDC1612_DEBUG("Warning: Sensor frequency (%.2f MHz) is too high for the given reference clock (%.2f MHz)!\n", sensor_freq, (float)(LDC1612_EXT_CLK_MHZ / freq_div)); - } - - value = LDC1612_CLOCK_DIVIDER_GEN(fin_div, freq_div); - - return value; -} - -uint16_t ldc1612_get_manufacturer_id(void) { - uint8_t data[2] = {0}; - - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, READ_MANUFACTURER_ID, data); - return (data[0] << 8) | data[1]; -} - -uint16_t ldc1612_get_deveice_id(void) { - uint8_t data[2] = {0}; - - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, READ_DEVICE_ID, data); - return (data[0] << 8) | data[1]; -} - -/** @brief reset sensor. - - * */ -ldc1612_status_t ldc1612_reset_sensor(void) { - i2c_result_t state = ldc1612_write_register(SENSOR_RESET_REG, LDC1612_RESET_DEV); - return (state == I2C_RESULT_SUCCESS) ? LDC1612_STATUS_SUCCESS : LDC1612_STATUS_ERROR; -} - -ldc1612_status_t ldc1612_init(void) { - i2c_result_t i2c_status; - uint16_t manufacturer_id, device_id; - - /* reset LDC1612 sensor */ - i2c_status = ldc1612_reset_sensor(); - if (i2c_status != I2C_RESULT_SUCCESS) { - return LDC1612_STATUS_ERROR; - } - - delay_ms(100); - - manufacturer_id = ldc1612_get_manufacturer_id(); - device_id = ldc1612_get_deveice_id(); - - if (manufacturer_id != 0x5449 || device_id != 0x3055) { - return LDC1612_STATUS_ERROR; - } - - return LDC1612_STATUS_SUCCESS; -} - -/*! - \brief 配置单通道模式 - \param[in] channel: 通道号 (0或1) - \param[out] none - \retval ldc1612_status_t -*/ -ldc1612_status_t ldc1612_config_single_channel(uint8_t channel) { - i2c_result_t status; - - if (channel > 1) { - return LDC1612_STATUS_INVALID_PARAM; - } - - /* 配置顺序严格按照TI官方文档要求 */ - - /* Step 1: 确保传感器处于睡眠模式 - 配置前必须 */ - status = ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); - if (status != I2C_RESULT_SUCCESS) return LDC1612_STATUS_ERROR; - delay_ms(10); - - /* Step 2: 配置频率分频 - 必须在其他配置之前 */ - uint16_t freq_divider = ldc1612_calculate_freq_divider(channel); - ldc1612_write_register(SET_FREQ_REG_START + channel, freq_divider); - delay_ms(5); - - /* Step 3: 配置LC稳定时间 - 影响测量精度 */ - ldc1612_write_register(SET_SETTLECOUNT_REG_START + channel, LDC1612_SETTLECOUNT_CH0); - - /* Step 4: 配置转换时间 - 影响测量速度和精度 */ - ldc1612_write_register(SET_CONVERSION_TIME_REG_START + channel, LDC1612_RCOUNT_TIME_CH0); - - /* Step 5: 配置转换偏移 */ - ldc1612_write_register(SET_CONVERSION_OFFSET_REG_START + channel, SET_CONVERSION_OFFSET_CH0); - - /* Step 6: 配置驱动电流 - 影响传感器灵敏度 */ - ldc1612_write_register(SET_DRIVER_CURRENT_REG + channel, LDC1612_DRIVE_CURRENT); - - /* Step 7: 配置多路复用器 - 设置通道选择和滤波 */ - // ldc1612_configure_mux_register(LDC1612_MUX_AUTOSCAN_DISABLE, LDC1612_MUX_RR_SEQUENCE_0, LDC1612_MUX_FILTER_ALL_LOW, LDC1612_MUX_FILTER_NONE); - ldc1612_write_register(MUX_CONFIG_REG, LDC1612_MUX_CONFIG); - - /* Step 8: 配置错误输出 */ - ldc1612_write_register(ERROR_CONFIG_REG, LDC1612_ERROR_CONFIG_DEFAULT); - - /* Step 9: 最后启动传感器 - 必须最后一步 */ - status = ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SENSOR_CONFIG_CH0); - if (status != I2C_RESULT_SUCCESS) return LDC1612_STATUS_ERROR; - - /* Step 10: 等待传感器稳定 */ - delay_ms(50); - - return LDC1612_STATUS_SUCCESS; -} - -/** @brief read the raw channel result from register. - @param channel LDC1612 has total two channels. - @param result raw data - * */ -uint32_t ldc1612_get_raw_channel_result(uint8_t channel) { - uint32_t raw_value = 0; - uint8_t value[2] = {0}; - - /* Read MSW */ - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, CONVERSION_RESULT_REG_START + (channel * 2), value); - raw_value |= (uint32_t)(((uint16_t)value[0] << 8) | value[1]) << 16; - - /* Read LSW */ - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, CONVERSION_RESULT_REG_START + 1 + (channel * 2), value); - raw_value |= (uint32_t)(((uint16_t)value[0] << 8) | value[1]); - - - uint32_t calibration_value = raw_value & 0x0FFFFFFF; - if (calibration_value == 0x0FFFFFFF) { - return 0xF0000000; /* No coil */ - } - if (LDC1612_ERROR_CONFIG_DEFAULT & 0xF800) { - uint8_t error_code = (uint8_t)(raw_value >> 24); - if (error_code & 0x80) return 0x80000000; /* Under range */ - if (error_code & 0x40) return 0x40000000; /* Over range */ - if (error_code & 0x20) return 0x20000000; /* Watchdog */ - if (error_code & 0x10) return 0x10000000; /* Amplitude error */ - } - - return raw_value; -} - - -void ldc1612_drvie_current_detect(uint8_t channel) { - uint8_t data[2] = {0}; - uint16_t init_value = 0 , drive_current = 0; - - ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); - delay_ms(10); - - uint16_t freq_divider = ldc1612_calculate_freq_divider(channel); - ldc1612_write_register(SET_FREQ_REG_START + channel, freq_divider); - delay_ms(5); - - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SENSOR_CONFIG_REG, data); - // ldc1612_set_sensor_config(LDC1612_SLEEP_MODE); - ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); - delay_ms(10); - ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SENSOR_CONFIG_CH0); - delay_ms(10); - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SET_DRIVER_CURRENT_REG, data); - - init_value = (((data[0] << 8) | data[1]) >> 6) & 0x1F; - drive_current = (init_value << 11) | 0x0000; - LDC1612_DEBUG("init value: 0x%x\tdrive current: 0x%x\n", init_value, drive_current); -} - -/** @brief Get sensor status register - @return Status register value - * */ -uint16_t ldc1612_get_sensor_status(void) { - uint8_t data[2] = {0}; - LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SENSOR_STATUS_REG, data); - return (data[0] << 8) | data[1]; -} - -/** @brief Check if data is ready for specific channel - @param channel Channel to check (0 or 1) - @return true if data is ready, false otherwise - * */ -bool ldc1612_is_data_ready(uint8_t channel) { - uint16_t status = ldc1612_get_sensor_status(); - if (channel == 0) { - return (status & 0x0040) != 0; // DRDY_0 bit - } else if (channel == 1) { - return (status & 0x0080) != 0; // DRDY_1 bit - } - return false; -} - -/*! - \brief 检查并记录LDC1612的状态和错误 - \param[in] none - \param[out] none - \retval 读取到的原始状态寄存器值 -*/ -uint16_t ldc1612_check_status_and_log_errors(void) { - uint16_t status; - i2c_result_t i2c_status = ldc1612_read_register(SENSOR_STATUS_REG, &status); - - if (i2c_status != I2C_RESULT_SUCCESS) { - LDC1612_DEBUG("Failed to read STATUS register!"); - return 0; - } - - LDC1612_DEBUG("--- LDC1612 Status Check (Value: 0x%04X) ---", status); - - // 检查数据就绪状态 - if (status & LDC1612_STATUS_DRDY) { - LDC1612_DEBUG(" [OK] Data is ready."); - } - if (status & LDC1612_STATUS_UNREAD_CH0) { - LDC1612_DEBUG(" [INFO] Channel 0 has unread data."); - } - if (status & LDC1612_STATUS_UNREAD_CH1) { - LDC1612_DEBUG(" [INFO] Channel 1 has unread data."); - } - - // 检查是否有任何错误标志 - if ((status & 0x3F00) == 0) { // 检查所有错误位的掩码 - LDC1612_DEBUG(" [OK] No errors detected."); - } else { - uint8_t err_chan = (status & LDC1612_STATUS_ERR_CHAN_MASK) >> 14; - LDC1612_DEBUG(" [ERROR] An error occurred on Channel %d.", err_chan); - - if (status & LDC1612_STATUS_ERR_UR) { - LDC1612_DEBUG(" - Underflow Error: Conversion result is less than OFFSET."); - } - if (status & LDC1612_STATUS_ERR_OR) { - LDC1612_DEBUG(" - Overflow Error: Conversion result is at maximum."); - } - if (status & LDC1612_STATUS_ERR_WD) { - LDC1612_DEBUG(" - Watchdog Timeout: Sensor failed to complete conversion in time."); - } - if (status & LDC1612_STATUS_ERR_AHE) { - LDC1612_DEBUG(" - Amplitude High Error: Sensor oscillation amplitude > 1.8V."); - } - if (status & LDC1612_STATUS_ERR_ALE) { - LDC1612_DEBUG(" - Amplitude Low Error: Sensor oscillation amplitude < 1.2V."); - } - if (status & LDC1612_STATUS_ERR_ZC) { - LDC1612_DEBUG(" - Zero-Count Error: Reference count is zero, check clock."); - } - } - LDC1612_DEBUG("-------------------------------------------------"); - - // 读取STATUS寄存器会自动清除错误标志，但不会清除DRDY和UNREADCONV标志 - return status; +// +// Created by dell on 24-12-3. +// + +#include "ldc1612.h" + +/*! + \brief 写入寄存器 + \param[in] reg_addr: 寄存器地址 + \param[in] value: 写入值 + \param[out] none + \retval i2c_result_t +*/ +static i2c_result_t ldc1612_write_register(uint8_t reg_addr, uint16_t value) { + uint8_t data[2]; + data[0] = (value >> 8) & 0xFF; + data[1] = value & 0xFF; + + return LDC1612_IIC_WRITE_16BITS(LDC1612_ADDR, reg_addr, data); +} + +/*! + \brief 读取寄存器 + \param[in] reg_addr: 寄存器地址 + \param[out] value: 读取值指针 + \retval i2c_status_t +*/ +static i2c_result_t ldc1612_read_register(uint8_t reg_addr, uint16_t *value) { + uint8_t data[2]; + i2c_result_t status; + + if (value == NULL) { + return I2C_RESULT_INVALID_PARAM; + } + + status = LDC1612_IIC_READ_16BITS(LDC1612_ADDR, reg_addr, data); + if (status == I2C_RESULT_SUCCESS) { + *value = ((uint16_t)data[0] << 8) | data[1]; + } + + return status; +} + +/*! + \brief 计算并获取频率分频值 + \param[in] channel: 通道号 + \param[out] none + \retval 计算得到的频率分频值 +*/ +static uint16_t ldc1612_calculate_freq_divider(uint8_t channel) { + uint16_t value; + uint16_t fin_div, freq_div; + float sensor_freq; + + sensor_freq = 1 / (2 * 3.14 * sqrt(COIL_L_UH * COIL_C_PF * pow(10, -18))) * pow(10, -6); + fin_div = (uint16_t) (sensor_freq / 8.75 + 1); + + if (fin_div * 4 < 40) { + freq_div = 2; + } else { + freq_div = 4; + } + + value = fin_div << 12; + value |= freq_div; + + return value; +} + +uint16_t ldc1612_get_manufacturer_id(void) { + uint8_t data[2] = {0}; + + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, READ_MANUFACTURER_ID, data); + return (data[0] << 8) | data[1]; +} + +uint16_t ldc1612_get_deveice_id(void) { + uint8_t data[2] = {0}; + + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, READ_DEVICE_ID, data); + return (data[0] << 8) | data[1]; +} + +/** @brief reset sensor. + + * */ +ldc1612_status_t ldc1612_reset_sensor(void) { + i2c_result_t state = ldc1612_write_register(SENSOR_RESET_REG, LDC1612_RESET_DEV); + return (state == I2C_RESULT_SUCCESS) ? LDC1612_STATUS_SUCCESS : LDC1612_STATUS_ERROR; +} + +ldc1612_status_t ldc1612_init(void) { + i2c_result_t i2c_status; + uint16_t manufacturer_id, device_id; + + /* reset LDC1612 sensor */ + i2c_status = ldc1612_reset_sensor(); + if (i2c_status != I2C_RESULT_SUCCESS) { + return LDC1612_STATUS_ERROR; + } + + delay_ms(100); + + manufacturer_id = ldc1612_get_manufacturer_id(); + device_id = ldc1612_get_deveice_id(); + + if (manufacturer_id != 0x5449 || device_id != 0x3055) { + return LDC1612_STATUS_ERROR; + } + + return LDC1612_STATUS_SUCCESS; +} + +/*! + \brief 配置单通道模式 + \param[in] channel: 通道号 (0或1) + \param[out] none + \retval ldc1612_status_t +*/ +ldc1612_status_t ldc1612_config_single_channel(uint8_t channel) { + i2c_result_t status; + + if (channel > 1) { + return LDC1612_STATUS_INVALID_PARAM; + } + + /* 配置顺序严格按照TI官方文档要求 */ + + /* Step 1: 确保传感器处于睡眠模式 - 配置前必须 */ + status = ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); + if (status != I2C_RESULT_SUCCESS) return LDC1612_STATUS_ERROR; + delay_ms(10); + + /* Step 2: 配置频率分频 - 必须在其他配置之前 */ + uint16_t freq_divider = ldc1612_calculate_freq_divider(channel); + ldc1612_write_register(SET_FREQ_REG_START + channel, freq_divider); + delay_ms(5); + + /* Step 3: 配置LC稳定时间 - 影响测量精度 */ + ldc1612_write_register(SET_SETTLECOUNT_REG_START + channel, LDC1612_SETTLECOUNT_CH0); + + /* Step 4: 配置转换时间 - 影响测量速度和精度 */ + ldc1612_write_register(SET_CONVERSION_TIME_REG_START + channel, LDC1612_RCOUNT_TIME_CH0); + + /* Step 5: 配置转换偏移 */ + ldc1612_write_register(SET_CONVERSION_OFFSET_REG_START + channel, SET_CONVERSION_OFFSET_CH0); + + /* Step 6: 配置驱动电流 - 影响传感器灵敏度 */ + ldc1612_write_register(SET_DRIVER_CURRENT_REG + channel, LDC1612_DRIVE_CURRENT); + + /* Step 7: 配置多路复用器 - 设置通道选择和滤波 */ + // ldc1612_configure_mux_register(LDC1612_MUX_AUTOSCAN_DISABLE, LDC1612_MUX_RR_SEQUENCE_0, LDC1612_MUX_FILTER_ALL_LOW, LDC1612_MUX_FILTER_NONE); + ldc1612_write_register(MUX_CONFIG_REG, LDC1612_MUX_CONFIG); + + /* Step 8: 配置错误输出 */ + ldc1612_write_register(ERROR_CONFIG_REG, LDC1612_ERROR_CONFIG); + + /* Step 9: 最后启动传感器 - 必须最后一步 */ + status = ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SENSOR_CONFIG_CH0); + if (status != I2C_RESULT_SUCCESS) return LDC1612_STATUS_ERROR; + + /* Step 10: 等待传感器稳定 */ + delay_ms(50); + + return LDC1612_STATUS_SUCCESS; +} + +/** @brief read the raw channel result from register. + @param channel LDC1612 has total two channels. + @param result raw data + * */ +uint32_t ldc1612_get_raw_channel_result(uint8_t channel) { + uint32_t raw_value = 0; + uint8_t value[2] = {0}; + + /* Read MSW */ + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, CONVERTION_RESULT_REG_START + (channel * 2), value); + raw_value |= (uint32_t)(((uint16_t)value[0] << 8) | value[1]) << 16; + + /* Read LSW */ + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, CONVERTION_RESULT_REG_START + 1 + (channel * 2), value); + raw_value |= (uint32_t)(((uint16_t)value[0] << 8) | value[1]); + + + uint32_t calibration_value = raw_value & 0x0FFFFFFF; + if (calibration_value == 0x0FFFFFFF) { + return 0xF0000000; /* No coil */ + } + if (LDC1612_ERROR_CONFIG & 0xF800) { + uint8_t error_code = (uint8_t)(raw_value >> 24); + if (error_code & 0x80) return 0x80000000; /* Under range */ + if (error_code & 0x40) return 0x40000000; /* Over range */ + if (error_code & 0x20) return 0x20000000; /* Watchdog */ + if (error_code & 0x10) return 0x10000000; /* Amplitude error */ + } + + return raw_value; +} + + +void ldc1612_drvie_current_detect(uint8_t channel) { + uint8_t data[2] = {0}; + uint16_t init_value = 0 , drive_current = 0; + + ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); + delay_ms(10); + + uint16_t freq_divider = ldc1612_calculate_freq_divider(channel); + ldc1612_write_register(SET_FREQ_REG_START + channel, freq_divider); + delay_ms(5); + + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SENSOR_CONFIG_REG, data); + // ldc1612_set_sensor_config(LDC1612_SLEEP_MODE); + ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SLEEP_MODE); + delay_ms(10); + ldc1612_write_register(SENSOR_CONFIG_REG, LDC1612_SENSOR_CONFIG_CH0); + delay_ms(10); + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SET_DRIVER_CURRENT_REG, data); + + init_value = (((data[0] << 8) | data[1]) >> 6) & 0x1F; + drive_current = (init_value << 11) | 0x0000; + printf("init value: 0x%x\tdrive current: 0x%x\n", init_value, drive_current); +} + +/** @brief Get sensor status register + @return Status register value + * */ +uint16_t ldc1612_get_sensor_status(void) { + uint8_t data[2] = {0}; + LDC1612_IIC_READ_16BITS(LDC1612_ADDR, SENSOR_STATUS_REG, data); + return (data[0] << 8) | data[1]; +} + +/** @brief Check if data is ready for specific channel + @param channel Channel to check (0 or 1) + @return true if data is ready, false otherwise + * */ +bool ldc1612_is_data_ready(uint8_t channel) { + uint16_t status = ldc1612_get_sensor_status(); + if (channel == 0) { + return (status & 0x0040) != 0; // DRDY_0 bit + } else if (channel == 1) { + return (status & 0x0080) != 0; // DRDY_1 bit + } + return false; } \ No newline at end of file diff --git a/Src/led.c b/Src/led.c index 1661867..cafed33 100644 --- a/Src/led.c +++ b/Src/led.c @@ -1,57 +1,57 @@ -#include "led.h" - -/** - * @brief LED心跳指示灯功能 - * @details 实现类似心跳的LED闪烁模式：快闪两次然后暂停 - * 适合在SysTick中断中调用，通过计数器控制闪烁节拍 - * @note 假设SysTick中断频率为1ms，心跳周期约为2秒 - * 心跳模式：亮200ms->灭200ms->亮200ms->灭1400ms（循环） - */ -void led_heart_beat(void) -{ - static uint16_t heart_beat_counter = 0; - - // 心跳周期：2000ms (假设SysTick为1ms中断) - // 模式：亮200ms -> 灭200ms -> 亮200ms -> 灭1400ms - heart_beat_counter++; - - if (heart_beat_counter <= 200) { - // 第一次亮：0-200ms - led_on(); - } - else if (heart_beat_counter <= 400) { - // 第一次灭：200-400ms - led_off(); - } - else if (heart_beat_counter <= 600) { - // 第二次亮：400-600ms - led_on(); - } - else if (heart_beat_counter <= 2000) { - // 长时间灭：600-2000ms - led_off(); - } - else { - // 重置计数器，开始新的心跳周期 - heart_beat_counter = 0; - } -} - -void led_init(void) { - rcu_periph_clock_enable(LED_RCU); - gpio_mode_set(LED_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_PIN); - gpio_output_options_set(LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LED_PIN); - gpio_bit_set(LED_PORT, LED_PIN); -} - -void led_on(void) { - gpio_bit_reset(LED_PORT, LED_PIN); -} - -void led_off(void) { - gpio_bit_set(LED_PORT, LED_PIN); -} - -void led_toggle(void) { - gpio_bit_toggle(LED_PORT, LED_PIN); -} +#include "led.h" + +/** + * @brief LED心跳指示灯功能 + * @details 实现类似心跳的LED闪烁模式：快闪两次然后暂停 + * 适合在SysTick中断中调用，通过计数器控制闪烁节拍 + * @note 假设SysTick中断频率为1ms，心跳周期约为2秒 + * 心跳模式：亮200ms->灭200ms->亮200ms->灭1400ms（循环） + */ +void led_heart_beat(void) +{ + static uint16_t heart_beat_counter = 0; + + // 心跳周期：2000ms (假设SysTick为1ms中断) + // 模式：亮200ms -> 灭200ms -> 亮200ms -> 灭1400ms + heart_beat_counter++; + + if (heart_beat_counter <= 200) { + // 第一次亮：0-200ms + led_on(); + } + else if (heart_beat_counter <= 400) { + // 第一次灭：200-400ms + led_off(); + } + else if (heart_beat_counter <= 600) { + // 第二次亮：400-600ms + led_on(); + } + else if (heart_beat_counter <= 2000) { + // 长时间灭：600-2000ms + led_off(); + } + else { + // 重置计数器，开始新的心跳周期 + heart_beat_counter = 0; + } +} + +void led_init(void) { + rcu_periph_clock_enable(LED_RCU); + gpio_mode_set(LED_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED_PIN); + gpio_output_options_set(LED_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, LED_PIN); + gpio_bit_set(LED_PORT, LED_PIN); +} + +void led_on(void) { + gpio_bit_reset(LED_PORT, LED_PIN); +} + +void led_off(void) { + gpio_bit_set(LED_PORT, LED_PIN); +} + +void led_toggle(void) { + gpio_bit_toggle(LED_PORT, LED_PIN); +} diff --git a/Src/main.c b/Src/main.c index d4b9476..04bf7fb 100644 --- a/Src/main.c +++ b/Src/main.c @@ -1,111 +1,111 @@ -/*! - \file main.c - \brief running LED - - \version 2025-02-10, V2.4.0, demo for GD32E23x -*/ - -/* - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its contributors - may be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. -IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, -INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT -NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY -OF SUCH DAMAGE. -*/ - -#include "gd32e23x.h" -#include "systick.h" -#include "uart.h" -#include "led.h" -#include "command.h" -#include -#include "i2c.h" -#include "board_config.h" -#include "ldc1612.h" -#include "tmp112.h" - -/*! - \brief main function - \param[in] none - \param[out] none - \retval none -*/ -int main(void) -{ - // nvic_vector_table_set(NVIC_VECTTAB_FLASH, 0x2000); - - led_init(); - mcu_detect_and_config(); - - setbuf(stdout, NULL); - systick_config(); - rs485_init(); - - // led_init(); - - // printf("Flash size: %d Kbytes\n", get_flash_size()); - -#ifdef DEBUG_VERBOSE - char hello_world[] = {"Hello World!\r\n"}; - - for (uint8_t i = 0; i < sizeof(hello_world); i++) - { - while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(RS485_PHY, hello_world[i]); - } - - while (usart_flag_get(RS485_PHY, USART_FLAG_TC) == RESET) {} -#endif - - i2c_config(); - -#ifdef DEBUG_VERBOSE - i2c_scan(); - - i2c_bus_reset(); -#endif - - ldc1612_init(); - ldc1612_config_single_channel(CHANNEL_0); - - tmp112a_init(); - -#ifdef EDDY_DRIVE_CURRENT_DETECTION - ldc1612_drvie_current_detect(CHANNEL_0); -#endif - - while(1){ -#ifndef EDDY_DRIVE_CURRENT_DETECTION - command_process(); - delay_ms(10); - if (g_eddy_current_sensor_report_enabled) - eddy_current_report(); - -#else - ldc1612_drvie_current_detect(CHANNEL_0); - delay_ms(1000); -#endif - - - - } -} +/*! + \file main.c + \brief running LED + + \version 2025-02-10, V2.4.0, demo for GD32E23x +*/ + +/* + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its contributors + may be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. +*/ + +#include "gd32e23x.h" +#include "systick.h" +#include "uart.h" +#include "led.h" +#include "command.h" +#include +#include "i2c.h" +#include "board_config.h" +#include "ldc1612.h" +#include "tmp112.h" + +/*! + \brief main function + \param[in] none + \param[out] none + \retval none +*/ +int main(void) +{ + nvic_vector_table_set(NVIC_VECTTAB_FLASH, 0x2000); + + led_init(); + mcu_detect_and_config(); + + setbuf(stdout, NULL); + systick_config(); + rs485_init(); + + // led_init(); + + // printf("Flash size: %d Kbytes\n", get_flash_size()); + +#ifdef DEBUG_VERBOSE + char hello_world[] = {"Hello World!\r\n"}; + + for (uint8_t i = 0; i < sizeof(hello_world); i++) + { + while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(RS485_PHY, hello_world[i]); + } + + while (usart_flag_get(RS485_PHY, USART_FLAG_TC) == RESET) {} +#endif + + i2c_config(); + +#ifdef DEBUG_VERBOSE + i2c_scan(); + + i2c_bus_reset(); +#endif + + ldc1612_init(); + ldc1612_config_single_channel(CHANNEL_0); + + tmp112a_init(); + +#ifdef EDDY_DRIVE_CURRENT_DETECTION + ldc1612_drvie_current_detect(CHANNEL_0); +#endif + + while(1){ +#ifndef EDDY_DRIVE_CURRENT_DETECTION + command_process(); + delay_ms(10); + if (g_eddy_current_sensor_report_enabled) + eddy_current_report(); + +#else + ldc1612_drvie_current_detect(CHANNEL_0); + delay_ms(1000); +#endif + + + + } +} diff --git a/Src/soft_i2c.c b/Src/soft_i2c.c index 05544c2..d5905d4 100644 --- a/Src/soft_i2c.c +++ b/Src/soft_i2c.c @@ -1,234 +1,234 @@ -// -// Created by dell on 24-12-28. -// - -#include "soft_i2c.h" - -/*! - \brief delay - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_delay(void) { - delay_10us(2); // Adjust delay as needed - /* delay to freq - * 15KHz: delay_us(20); - * 65KHz: delay_us(1); - */ -} - -/*! - \brief configure the software IIC GPIO - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_config(void) { - rcu_periph_clock_enable(RCU_GPIO_I2C); - - gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SCL_PIN); - gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); - - gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SDA_PIN); - gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); - - I2C_SCL_HIGH(); - I2C_SDA_HIGH(); -} - -/*! - \brief generate I2C start signal - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_start(void) { - I2C_SDA_HIGH(); - I2C_SCL_HIGH(); - soft_i2c_delay(); - I2C_SDA_LOW(); - soft_i2c_delay(); - I2C_SCL_LOW(); -} - -/*! - \brief generate I2C stop signal - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_stop(void) { - I2C_SCL_LOW(); // 确保时钟为低 - I2C_SDA_LOW(); // 拉低数据线 - soft_i2c_delay(); - I2C_SCL_HIGH(); // 拉高时钟 - soft_i2c_delay(); - I2C_SDA_HIGH(); // 在时钟高电平时拉高数据线产生停止条件 - soft_i2c_delay(); // 添加缺失的延时 -} - -/*! - \brief send I2C ACK signal - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_send_ack(void) { - // sda_out(); - I2C_SDA_LOW(); - soft_i2c_delay(); - I2C_SCL_HIGH(); - soft_i2c_delay(); - I2C_SCL_LOW(); - soft_i2c_delay(); - I2C_SDA_HIGH(); -} - -/*! - \brief send I2C NACK signal - \param[in] none - \param[out] none - \retval none -*/ -void soft_i2c_send_nack(void) { - I2C_SDA_HIGH(); - soft_i2c_delay(); - I2C_SCL_HIGH(); - soft_i2c_delay(); - I2C_SCL_LOW(); - soft_i2c_delay(); - I2C_SDA_HIGH(); -} - -/*! - \brief wait I2C ACK signal - \param[in] none - \param[out] none - \retval 0: ACK received, 1: ACK not received -*/ -uint8_t soft_i2c_wait_ack(void) { - I2C_SDA_HIGH(); // 释放SDA线，让从设备控制 - soft_i2c_delay(); - I2C_SCL_HIGH(); // 拉高时钟 - soft_i2c_delay(); - uint8_t ack = !I2C_SDA_READ(); // 读取ACK信号（低电平为ACK） - I2C_SCL_LOW(); // 拉低时钟 - soft_i2c_delay(); // 添加缺失的延时 - return ack; -} - -/*! - \brief send a byte via I2C - \param[in] byte: byte to be sent - \param[out] none - \retval none -*/ -void soft_i2c_send_byte(uint8_t byte) { - // sda_out(); - for (int i = 0; i < 8; i++) { - if (byte & 0x80) { - I2C_SDA_HIGH(); - } else { - I2C_SDA_LOW(); - } - byte <<= 1; - soft_i2c_delay(); - I2C_SCL_HIGH(); - soft_i2c_delay(); - I2C_SCL_LOW(); - soft_i2c_delay(); - } -} - -/*! - \brief receive a byte via I2C - \param[in] ack: 1: send ACK, 0: send NACK - \param[out] none - \retval received byte -*/ -uint8_t soft_i2c_receive_byte(uint8_t ack) { - uint8_t byte = 0; - I2C_SDA_HIGH(); - for (int i = 0; i < 8; i++) { - byte <<= 1; - I2C_SCL_HIGH(); - soft_i2c_delay(); - if (I2C_SDA_READ()) { - byte |= 0x01; - } - I2C_SCL_LOW(); - soft_i2c_delay(); - } - if (ack) { - soft_i2c_send_ack(); - } else { - soft_i2c_send_nack(); - } - return byte; -} - -uint8_t soft_i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) { - /* 参数验证 */ - if (data == NULL || slave_addr > 0x7F) { - return SOFT_I2C_FAIL; - } - - soft_i2c_start(); - soft_i2c_send_byte(slave_addr << 1); // 修复：左移1位，添加写位 - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_send_byte(reg_addr); - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_send_byte(data[0]); - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_send_byte(data[1]); - if (!soft_i2c_wait_ack()) { // 修复：添加错误处理 - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_stop(); - return SOFT_I2C_OK; -} - -uint8_t soft_i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) -{ - /* 参数验证 */ - if (data == NULL || slave_addr > 0x7F) { - return SOFT_I2C_FAIL; - } - - /* 写阶段：发送寄存器地址 */ - soft_i2c_start(); - soft_i2c_send_byte(slave_addr << 1); // 修复：左移1位，写操作 - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_send_byte(reg_addr); - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - - /* 读阶段：重新开始并读取数据 */ - soft_i2c_start(); // 重新开始 - soft_i2c_send_byte((slave_addr << 1) | 0x01); // 修复：正确的读地址 - if (!soft_i2c_wait_ack()) { - soft_i2c_stop(); - return SOFT_I2C_FAIL; - } - soft_i2c_delay(); - data[0] = soft_i2c_receive_byte(1); // 第一个字节发送ACK - data[1] = soft_i2c_receive_byte(0); // 最后一个字节发送NACK - soft_i2c_stop(); - return SOFT_I2C_OK; +// +// Created by dell on 24-12-28. +// + +#include "soft_i2c.h" + +/*! + \brief delay + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_delay(void) { + delay_10us(2); // Adjust delay as needed + /* delay to freq + * 15KHz: delay_us(20); + * 65KHz: delay_us(1); + */ +} + +/*! + \brief configure the software IIC GPIO + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_config(void) { + rcu_periph_clock_enable(RCU_GPIO_I2C); + + gpio_mode_set(I2C_SCL_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SCL_PIN); + gpio_output_options_set(I2C_SCL_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SCL_PIN); + + gpio_mode_set(I2C_SDA_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, I2C_SDA_PIN); + gpio_output_options_set(I2C_SDA_PORT, GPIO_OTYPE_OD, GPIO_OSPEED_50MHZ, I2C_SDA_PIN); + + I2C_SCL_HIGH(); + I2C_SDA_HIGH(); +} + +/*! + \brief generate I2C start signal + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_start(void) { + I2C_SDA_HIGH(); + I2C_SCL_HIGH(); + soft_i2c_delay(); + I2C_SDA_LOW(); + soft_i2c_delay(); + I2C_SCL_LOW(); +} + +/*! + \brief generate I2C stop signal + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_stop(void) { + I2C_SCL_LOW(); // 确保时钟为低 + I2C_SDA_LOW(); // 拉低数据线 + soft_i2c_delay(); + I2C_SCL_HIGH(); // 拉高时钟 + soft_i2c_delay(); + I2C_SDA_HIGH(); // 在时钟高电平时拉高数据线产生停止条件 + soft_i2c_delay(); // 添加缺失的延时 +} + +/*! + \brief send I2C ACK signal + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_send_ack(void) { + // sda_out(); + I2C_SDA_LOW(); + soft_i2c_delay(); + I2C_SCL_HIGH(); + soft_i2c_delay(); + I2C_SCL_LOW(); + soft_i2c_delay(); + I2C_SDA_HIGH(); +} + +/*! + \brief send I2C NACK signal + \param[in] none + \param[out] none + \retval none +*/ +void soft_i2c_send_nack(void) { + I2C_SDA_HIGH(); + soft_i2c_delay(); + I2C_SCL_HIGH(); + soft_i2c_delay(); + I2C_SCL_LOW(); + soft_i2c_delay(); + I2C_SDA_HIGH(); +} + +/*! + \brief wait I2C ACK signal + \param[in] none + \param[out] none + \retval 0: ACK received, 1: ACK not received +*/ +uint8_t soft_i2c_wait_ack(void) { + I2C_SDA_HIGH(); // 释放SDA线，让从设备控制 + soft_i2c_delay(); + I2C_SCL_HIGH(); // 拉高时钟 + soft_i2c_delay(); + uint8_t ack = !I2C_SDA_READ(); // 读取ACK信号（低电平为ACK） + I2C_SCL_LOW(); // 拉低时钟 + soft_i2c_delay(); // 添加缺失的延时 + return ack; +} + +/*! + \brief send a byte via I2C + \param[in] byte: byte to be sent + \param[out] none + \retval none +*/ +void soft_i2c_send_byte(uint8_t byte) { + // sda_out(); + for (int i = 0; i < 8; i++) { + if (byte & 0x80) { + I2C_SDA_HIGH(); + } else { + I2C_SDA_LOW(); + } + byte <<= 1; + soft_i2c_delay(); + I2C_SCL_HIGH(); + soft_i2c_delay(); + I2C_SCL_LOW(); + soft_i2c_delay(); + } +} + +/*! + \brief receive a byte via I2C + \param[in] ack: 1: send ACK, 0: send NACK + \param[out] none + \retval received byte +*/ +uint8_t soft_i2c_receive_byte(uint8_t ack) { + uint8_t byte = 0; + I2C_SDA_HIGH(); + for (int i = 0; i < 8; i++) { + byte <<= 1; + I2C_SCL_HIGH(); + soft_i2c_delay(); + if (I2C_SDA_READ()) { + byte |= 0x01; + } + I2C_SCL_LOW(); + soft_i2c_delay(); + } + if (ack) { + soft_i2c_send_ack(); + } else { + soft_i2c_send_nack(); + } + return byte; +} + +uint8_t soft_i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) { + /* 参数验证 */ + if (data == NULL || slave_addr > 0x7F) { + return SOFT_I2C_FAIL; + } + + soft_i2c_start(); + soft_i2c_send_byte(slave_addr << 1); // 修复：左移1位，添加写位 + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_send_byte(reg_addr); + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_send_byte(data[0]); + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_send_byte(data[1]); + if (!soft_i2c_wait_ack()) { // 修复：添加错误处理 + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_stop(); + return SOFT_I2C_OK; +} + +uint8_t soft_i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) +{ + /* 参数验证 */ + if (data == NULL || slave_addr > 0x7F) { + return SOFT_I2C_FAIL; + } + + /* 写阶段：发送寄存器地址 */ + soft_i2c_start(); + soft_i2c_send_byte(slave_addr << 1); // 修复：左移1位，写操作 + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_send_byte(reg_addr); + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + + /* 读阶段：重新开始并读取数据 */ + soft_i2c_start(); // 重新开始 + soft_i2c_send_byte((slave_addr << 1) | 0x01); // 修复：正确的读地址 + if (!soft_i2c_wait_ack()) { + soft_i2c_stop(); + return SOFT_I2C_FAIL; + } + soft_i2c_delay(); + data[0] = soft_i2c_receive_byte(1); // 第一个字节发送ACK + data[1] = soft_i2c_receive_byte(0); // 最后一个字节发送NACK + soft_i2c_stop(); + return SOFT_I2C_OK; } \ No newline at end of file diff --git a/Src/syscalls.c b/Src/syscalls.c index c1a1d8c..d00b3fd 100644 --- a/Src/syscalls.c +++ b/Src/syscalls.c @@ -1,171 +1,171 @@ -/* Support files for GNU libc. Files in the system namespace go here. - Files in the C namespace (ie those that do not start with an - underscore) go in .c. */ - -#include <_ansi.h> -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gd32e23x_usart.h" -#include "board_config.h" - -#undef errno -extern int errno; - -extern int __io_putchar(int ch) __attribute__((weak)); -extern int __io_getchar(void) __attribute__((weak)); - -caddr_t _sbrk(int incr) -{ - extern char _end[]; - static char *curbrk = _end; - - if ((curbrk + incr < _end)) - return NULL - 1; - - curbrk += incr; - return curbrk - incr; -} - -/* - * _gettimeofday primitive (Stub function) - * */ -int _gettimeofday (struct timeval * tp, struct timezone * tzp) -{ - /* Return fixed data for the timezone. */ - if (tzp) - { - tzp->tz_minuteswest = 0; - tzp->tz_dsttime = 0; - } - - return 0; -} -void initialise_monitor_handles() -{ -} - -int _getpid(void) -{ - return 1; -} - -int _kill(int pid, int sig) -{ - errno = EINVAL; - return -1; -} - -void _exit (int status) -{ - _kill(status, -1); - while (1) {} -} - -int _write(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - __io_putchar( *ptr++ ); - } - return len; -} - -int _close(int file) -{ - return -1; -} - -int _fstat(int file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _isatty(int file) -{ - return 1; -} - -int _lseek(int file, int ptr, int dir) -{ - return 0; -} - -int _read(int file, char *ptr, int len) -{ - int DataIdx; - - for (DataIdx = 0; DataIdx < len; DataIdx++) - { - *ptr++ = __io_getchar(); - } - - return len; -} - -int _open(char *path, int flags, ...) -{ - /* Pretend like we always fail */ - return -1; -} - -int _wait(int *status) -{ - errno = ECHILD; - return -1; -} - -int _unlink(char *name) -{ - errno = ENOENT; - return -1; -} - -int _times(struct tms *buf) -{ - return -1; -} - -int _stat(char *file, struct stat *st) -{ - st->st_mode = S_IFCHR; - return 0; -} - -int _link(char *old, char *new) -{ - errno = EMLINK; - return -1; -} - -int _fork(void) -{ - errno = EAGAIN; - return -1; -} - -int _execve(char *name, char **argv, char **env) -{ - errno = ENOMEM; - return -1; -} - -// USART0 printf重定向实现 -int __io_putchar(int ch) { - // 等待发送缓冲区空 - while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} - usart_data_transmit(RS485_PHY, (uint8_t)ch); - return ch; -} +/* Support files for GNU libc. Files in the system namespace go here. + Files in the C namespace (ie those that do not start with an + underscore) go in .c. */ + +#include <_ansi.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gd32e23x_usart.h" +#include "board_config.h" + +#undef errno +extern int errno; + +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + +caddr_t _sbrk(int incr) +{ + extern char _end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + +/* + * _gettimeofday primitive (Stub function) + * */ +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} +} + +int _write(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar( *ptr++ ); + } + return len; +} + +int _close(int file) +{ + return -1; +} + +int _fstat(int file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + return 0; +} + +int _read(int file, char *ptr, int len) +{ + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +int _open(char *path, int flags, ...) +{ + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + errno = ENOENT; + return -1; +} + +int _times(struct tms *buf) +{ + return -1; +} + +int _stat(char *file, struct stat *st) +{ + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + errno = ENOMEM; + return -1; +} + +// USART0 printf重定向实现 +int __io_putchar(int ch) { + // 等待发送缓冲区空 + while (usart_flag_get(RS485_PHY, USART_FLAG_TBE) == RESET) {} + usart_data_transmit(RS485_PHY, (uint8_t)ch); + return ch; +} diff --git a/Src/system_gd32e23x.c b/Src/system_gd32e23x.c index 480e817..fc9865a 100644 --- a/Src/system_gd32e23x.c +++ b/Src/system_gd32e23x.c @@ -1,451 +1,451 @@ -/*! - \file system_gd32e23x.c - \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for - GD32E23x Device Series -*/ - -/* Copyright (c) 2012 ARM LIMITED - Copyright (c) 2025, GigaDevice Semiconductor Inc. - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - -/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ - -#include "gd32e23x.h" - -/* system frequency define */ -#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ -#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ -#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ - -#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ - -/* select a system clock by uncommenting the following line */ -//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) -//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) -// #define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) -#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) - -/* The following is to prevent Vcore fluctuations caused by frequency switching. - It is strongly recommended to include it to avoid issues caused by self-removal. -*/ -#define RCU_MODIFY(__delay) do{ \ - volatile uint32_t i,reg; \ - if(0 != __delay){ \ - reg = RCU_CFG0; \ - reg &= ~(RCU_CFG0_AHBPSC); \ - /* CK_AHB = SYSCLK/2 */ \ - reg |= RCU_AHB_CKSYS_DIV2; \ - RCU_CFG0 = reg; \ - for(i=0; i<__delay; i++){ \ - } \ - reg = RCU_CFG0; \ - reg &= ~(RCU_CFG0_AHBPSC); \ - reg |= RCU_AHB_CKSYS_DIV4; \ - /* CK_AHB = SYSCLK/4 */ \ - RCU_CFG0 = reg; \ - for(i=0; i<__delay; i++){ \ - } \ - } \ - }while(0) - -#define SEL_IRC8M 0x00 -#define SEL_HXTAL 0x01 -#define SEL_PLL 0x02 - -/* set the system clock frequency and declare the system clock configuration function */ -#ifdef __SYSTEM_CLOCK_8M_HXTAL -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; -static void system_clock_8m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; -static void system_clock_72m_hxtal(void); - -#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) -uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; -static void system_clock_72m_irc8m(void); - -#else -uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; -static void system_clock_8m_irc8m(void); -#endif /* __SYSTEM_CLOCK_8M_HXTAL */ - -/* configure the system clock */ -static void system_clock_config(void); - -/* software delay to prevent the impact of Vcore fluctuations. - It is strongly recommended to include it to avoid issues caused by self-removal. */ -static void _soft_delay_(uint32_t time) -{ - __IO uint32_t i; - for(i=0; i> 1) * pllmf; - } - break; - /* IRC8M is selected as CK_SYS */ - default: - SystemCoreClock = IRC8M_VALUE; - break; - } - /* calculate AHB clock frequency */ - idx = GET_BITS(RCU_CFG0, 4, 7); - clk_exp = ahb_exp[idx]; - SystemCoreClock >>= clk_exp; -} - -#ifdef __FIRMWARE_VERSION_DEFINE -/*! - \brief get firmware version - \param[in] none - \param[out] none - \retval firmware version -*/ -uint32_t gd32e23x_firmware_version_get(void) -{ - return __GD32E23x_STDPERIPH_VERSION; -} -#endif /* __FIRMWARE_VERSION_DEFINE */ +/*! + \file system_gd32e23x.c + \brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for + GD32E23x Device Series +*/ + +/* Copyright (c) 2012 ARM LIMITED + Copyright (c) 2025, GigaDevice Semiconductor Inc. + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */ + +#include "gd32e23x.h" + +/* system frequency define */ +#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */ +#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */ +#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */ + +#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */ + +/* select a system clock by uncommenting the following line */ +//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL) +//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M) +// #define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000) +#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000) + +/* The following is to prevent Vcore fluctuations caused by frequency switching. + It is strongly recommended to include it to avoid issues caused by self-removal. +*/ +#define RCU_MODIFY(__delay) do{ \ + volatile uint32_t i,reg; \ + if(0 != __delay){ \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + /* CK_AHB = SYSCLK/2 */ \ + reg |= RCU_AHB_CKSYS_DIV2; \ + RCU_CFG0 = reg; \ + for(i=0; i<__delay; i++){ \ + } \ + reg = RCU_CFG0; \ + reg &= ~(RCU_CFG0_AHBPSC); \ + reg |= RCU_AHB_CKSYS_DIV4; \ + /* CK_AHB = SYSCLK/4 */ \ + RCU_CFG0 = reg; \ + for(i=0; i<__delay; i++){ \ + } \ + } \ + }while(0) + +#define SEL_IRC8M 0x00 +#define SEL_HXTAL 0x01 +#define SEL_PLL 0x02 + +/* set the system clock frequency and declare the system clock configuration function */ +#ifdef __SYSTEM_CLOCK_8M_HXTAL +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL; +static void system_clock_8m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL; +static void system_clock_72m_hxtal(void); + +#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2) +uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2; +static void system_clock_72m_irc8m(void); + +#else +uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M; +static void system_clock_8m_irc8m(void); +#endif /* __SYSTEM_CLOCK_8M_HXTAL */ + +/* configure the system clock */ +static void system_clock_config(void); + +/* software delay to prevent the impact of Vcore fluctuations. + It is strongly recommended to include it to avoid issues caused by self-removal. */ +static void _soft_delay_(uint32_t time) +{ + __IO uint32_t i; + for(i=0; i> 1) * pllmf; + } + break; + /* IRC8M is selected as CK_SYS */ + default: + SystemCoreClock = IRC8M_VALUE; + break; + } + /* calculate AHB clock frequency */ + idx = GET_BITS(RCU_CFG0, 4, 7); + clk_exp = ahb_exp[idx]; + SystemCoreClock >>= clk_exp; +} + +#ifdef __FIRMWARE_VERSION_DEFINE +/*! + \brief get firmware version + \param[in] none + \param[out] none + \retval firmware version +*/ +uint32_t gd32e23x_firmware_version_get(void) +{ + return __GD32E23x_STDPERIPH_VERSION; +} +#endif /* __FIRMWARE_VERSION_DEFINE */ diff --git a/Src/systick.c b/Src/systick.c index fd3d707..47c202a 100644 --- a/Src/systick.c +++ b/Src/systick.c @@ -1,118 +1,118 @@ -/** - * ************************************************************************ - * - * @file systick.c - * @author GD32 - * @brief 通过 SysTick 定时器进行微秒级别和毫秒级别的延时函数 - * - * ************************************************************************ - * @copyright Copyright (c) 2024 GD32 - * ************************************************************************ - */ -#include "gd32e23x.h" -#include "systick.h" - -volatile static uint32_t delay_count = 0; - -/** - * ************************************************************************ - * @brief 配置 SysTick 定时器 - * - * - * ************************************************************************ - */ -void systick_config(void) -{ - //设置了 SysTick 定时器的时钟源为 HCLK - systick_clksource_set(SYSTICK_CLKSOURCE_HCLK); - - // 配置SysTick为1ms周期中断 - // 注意：SysTick_Config会自动设置时钟源为HCLK，所以需要使用SystemCoreClock/1000 - SysTick_Config(SystemCoreClock / 1000U); // 1ms中断 - NVIC_SetPriority(SysTick_IRQn, 0x00U); -} - -/** - * ************************************************************************ - * @brief delay_ms 毫秒延时函数 - * - * @param[in] count 毫秒值 - * - * ************************************************************************ - */ -void delay_10us(uint32_t count) -{ - // 基于系统时钟的简单循环延时 - // 这是一个粗略的估计，实际延时可能有偏差 实测10.2us - uint32_t loops_per_10us = SystemCoreClock / 1700000; // 粗略估计，每10微秒的循环次数 - - for(uint32_t i = 0; i < count; i++) { - for(volatile uint32_t j = 0; j < loops_per_10us; j++); - } -} - -/** - * ************************************************************************ - * @brief delay_ms 毫秒延时函数 - * - * @param[in] count 毫秒值 - * - * ************************************************************************ - */ -void delay_ms(uint32_t count) -{ - delay_count = count; // 设置延时计数 - while (delay_count != 0U); -} - -/** - * ************************************************************************ - * @brief 每个 SysTick 中断调用时，减少延时计数 - * - * @param[in] void - * - * ************************************************************************ - */ -void delay_decrement(void) -{ - if (delay_count != 0U) - { - delay_count--; - } -} - -// /** -// * ************************************************************************ -// * @brief delay_ms_safe 毫秒延时函数（不干扰SysTick中断） -// * @details 使用简单循环实现延时，不会重新配置SysTick -// * @param[in] count 毫秒值 -// * ************************************************************************ -// */ -// void delay_ms_safe(uint32_t count) -// { -// // 基于系统时钟的简单循环延时 -// // 这是一个粗略的估计，实际延时可能有偏差 -// uint32_t loops_per_ms = SystemCoreClock / 14000; // 粗略估计 - -// for(uint32_t i = 0; i < count; i++) { -// for(volatile uint32_t j = 0; j < loops_per_ms; j++); -// } -// } - -// /** -// * ************************************************************************ -// * @brief delay_us_safe 微秒延时函数（不干扰SysTick中断） -// * @details 使用简单循环实现延时，不会重新配置SysTick -// * @param[in] count 微秒值 -// * ************************************************************************ -// */ -// void delay_us_safe(uint32_t count) -// { -// // 基于系统时钟的简单循环延时 -// // 这是一个粗略的估计，实际延时可能有偏差 -// uint32_t loops_per_us = SystemCoreClock / 22000000; // 粗略估计，每微秒的循环次数 - -// for(uint32_t i = 0; i < count; i++) { -// for(volatile uint32_t j = 0; j < loops_per_us; j++); -// } +/** + * ************************************************************************ + * + * @file systick.c + * @author GD32 + * @brief 通过 SysTick 定时器进行微秒级别和毫秒级别的延时函数 + * + * ************************************************************************ + * @copyright Copyright (c) 2024 GD32 + * ************************************************************************ + */ +#include "gd32e23x.h" +#include "systick.h" + +volatile static uint32_t delay_count = 0; + +/** + * ************************************************************************ + * @brief 配置 SysTick 定时器 + * + * + * ************************************************************************ + */ +void systick_config(void) +{ + //设置了 SysTick 定时器的时钟源为 HCLK + systick_clksource_set(SYSTICK_CLKSOURCE_HCLK); + + // 配置SysTick为1ms周期中断 + // 注意：SysTick_Config会自动设置时钟源为HCLK，所以需要使用SystemCoreClock/1000 + SysTick_Config(SystemCoreClock / 1000U); // 1ms中断 + NVIC_SetPriority(SysTick_IRQn, 0x00U); +} + +/** + * ************************************************************************ + * @brief delay_ms 毫秒延时函数 + * + * @param[in] count 毫秒值 + * + * ************************************************************************ + */ +void delay_10us(uint32_t count) +{ + // 基于系统时钟的简单循环延时 + // 这是一个粗略的估计，实际延时可能有偏差 实测10.2us + uint32_t loops_per_10us = SystemCoreClock / 1700000; // 粗略估计，每10微秒的循环次数 + + for(uint32_t i = 0; i < count; i++) { + for(volatile uint32_t j = 0; j < loops_per_10us; j++); + } +} + +/** + * ************************************************************************ + * @brief delay_ms 毫秒延时函数 + * + * @param[in] count 毫秒值 + * + * ************************************************************************ + */ +void delay_ms(uint32_t count) +{ + delay_count = count; // 设置延时计数 + while (delay_count != 0U); +} + +/** + * ************************************************************************ + * @brief 每个 SysTick 中断调用时，减少延时计数 + * + * @param[in] void + * + * ************************************************************************ + */ +void delay_decrement(void) +{ + if (delay_count != 0U) + { + delay_count--; + } +} + +// /** +// * ************************************************************************ +// * @brief delay_ms_safe 毫秒延时函数（不干扰SysTick中断） +// * @details 使用简单循环实现延时，不会重新配置SysTick +// * @param[in] count 毫秒值 +// * ************************************************************************ +// */ +// void delay_ms_safe(uint32_t count) +// { +// // 基于系统时钟的简单循环延时 +// // 这是一个粗略的估计，实际延时可能有偏差 +// uint32_t loops_per_ms = SystemCoreClock / 14000; // 粗略估计 + +// for(uint32_t i = 0; i < count; i++) { +// for(volatile uint32_t j = 0; j < loops_per_ms; j++); +// } +// } + +// /** +// * ************************************************************************ +// * @brief delay_us_safe 微秒延时函数（不干扰SysTick中断） +// * @details 使用简单循环实现延时，不会重新配置SysTick +// * @param[in] count 微秒值 +// * ************************************************************************ +// */ +// void delay_us_safe(uint32_t count) +// { +// // 基于系统时钟的简单循环延时 +// // 这是一个粗略的估计，实际延时可能有偏差 +// uint32_t loops_per_us = SystemCoreClock / 22000000; // 粗略估计，每微秒的循环次数 + +// for(uint32_t i = 0; i < count; i++) { +// for(volatile uint32_t j = 0; j < loops_per_us; j++); +// } // } \ No newline at end of file diff --git a/Src/tmp112.c b/Src/tmp112.c index 7f5c71f..bc68693 100644 --- a/Src/tmp112.c +++ b/Src/tmp112.c @@ -1,329 +1,328 @@ -// -// Created by dell on 24-12-20. -// TMP112A Temperature Sensor Driver Implementation -// - -#include "tmp112.h" - -/* Private function prototypes */ -static i2c_result_t tmp112a_write_register(uint8_t reg_addr, uint16_t value); -static i2c_result_t tmp112a_read_register(uint8_t reg_addr, uint16_t *value); -static float tmp112a_raw_to_celsius(uint16_t raw_data); -static uint16_t tmp112a_celsius_to_raw(float temperature); - -/*! - \brief 初始化TMP112A传感器 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_init(void) { - i2c_result_t i2c_status; - - /* 配置传感器为默认设置 */ - i2c_status = tmp112a_config(TMP112A_CONFIG_DEFAULT); - if (i2c_status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 等待配置生效 */ - delay_ms(1); - - return TMP112A_STATUS_SUCCESS; -} - -/*! - \brief 配置TMP112A传感器 - \param[in] config: 配置值 - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_config(uint16_t config) { - i2c_result_t status = tmp112a_write_register(TMP112A_CONFIG_REG, config); - return (status == I2C_RESULT_SUCCESS) ? TMP112A_STATUS_SUCCESS : TMP112A_STATUS_ERROR; -} - -/*! - \brief 读取温度 - \param[in] none - \param[out] result: 结果结构体指针 - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_read_temperature(tmp112a_result_t *result) { - uint16_t raw_data; - i2c_result_t status; - - if (result == NULL) { - return TMP112A_STATUS_INVALID_PARAM; - } - - /* 读取温度寄存器 */ - status = tmp112a_read_register(TMP112A_TEMP_REG, &raw_data); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 解析温度数据 */ - result->raw_data = raw_data; - result->temperature_c = tmp112a_raw_to_celsius(raw_data); - result->temperature_f = result->temperature_c * 9.0f / 5.0f + 32.0f; - - /* 检查温度范围 */ - if (result->temperature_c < TMP112A_TEMP_MIN || result->temperature_c > TMP112A_TEMP_MAX) { - return TMP112A_STATUS_OUT_OF_RANGE; - } - - /* 检查报警标志 */ - uint16_t config_reg; - status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); - if (status == I2C_RESULT_SUCCESS) { - result->alert_flag = (config_reg & TMP112A_CONFIG_AL) ? true : false; - } else { - result->alert_flag = false; - } - - return TMP112A_STATUS_SUCCESS; -} - -void tmp112a_get_raw_temperature_value(uint8_t *value) { - // i2c_read_16bits(TMP112A_ADDR, TMP112A_TEMP_REG, value); - i2c_read(TMP112A_ADDR, TMP112A_TEMP_REG, value, 2); - return; -} - -/*! - \brief 设置温度阈值 - \param[in] low_temp: 低温阈值 (°C) - \param[in] high_temp: 高温阈值 (°C) - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_set_thresholds(float low_temp, float high_temp) { - uint16_t low_raw, high_raw; - i2c_result_t status; - - /* 参数验证 */ - if (low_temp < TMP112A_TEMP_MIN || low_temp > TMP112A_TEMP_MAX || - high_temp < TMP112A_TEMP_MIN || high_temp > TMP112A_TEMP_MAX || - low_temp >= high_temp) { - return TMP112A_STATUS_INVALID_PARAM; - } - - /* 转换温度为原始值 */ - low_raw = tmp112a_celsius_to_raw(low_temp); - high_raw = tmp112a_celsius_to_raw(high_temp); - - /* 写入低温阈值 */ - status = tmp112a_write_register(TMP112A_TLOW_REG, low_raw); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 写入高温阈值 */ - status = tmp112a_write_register(TMP112A_THIGH_REG, high_raw); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - return TMP112A_STATUS_SUCCESS; -} - -/*! - \brief 进入关机模式 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_shutdown(void) { - uint16_t config_reg; - i2c_result_t status; - - /* 读取当前配置 */ - status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 设置关机位 */ - config_reg |= TMP112A_CONFIG_SD; - - /* 写回配置 */ - status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); - return (status == I2C_RESULT_SUCCESS) ? TMP112A_STATUS_SUCCESS : TMP112A_STATUS_ERROR; -} - -/*! - \brief 退出关机模式 - \param[in] none - \param[out] none - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_wakeup(void) { - uint16_t config_reg; - i2c_result_t status; - - /* 读取当前配置 */ - status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 清除关机位 */ - config_reg &= ~TMP112A_CONFIG_SD; - - /* 写回配置 */ - status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 等待传感器启动 */ - delay_ms(1); - - return TMP112A_STATUS_SUCCESS; -} - -/*! - \brief 单次转换 - \param[in] none - \param[out] result: 结果结构体指针 - \retval tmp112a_status_t -*/ -tmp112a_status_t tmp112a_one_shot(tmp112a_result_t *result) { - uint16_t config_reg; - i2c_result_t status; - uint8_t timeout = 100; // 100ms超时 - - if (result == NULL) { - return TMP112A_STATUS_INVALID_PARAM; - } - - /* 读取当前配置 */ - status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 启动单次转换 */ - config_reg |= TMP112A_CONFIG_OS; - status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - - /* 等待转换完成 */ - do { - delay_ms(1); - status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); - if (status != I2C_RESULT_SUCCESS) { - return TMP112A_STATUS_ERROR; - } - timeout--; - } while ((config_reg & TMP112A_CONFIG_OS) && timeout > 0); - - if (timeout == 0) { - return TMP112A_STATUS_TIMEOUT; - } - - /* 读取转换结果 */ - return tmp112a_read_temperature(result); -} - -/*! - \brief 获取状态字符串 - \param[in] status: 状态码 - \param[out] none - \retval const char* 状态字符串 -*/ -const char* tmp112a_get_status_string(tmp112a_status_t status) { - switch (status) { - case TMP112A_STATUS_SUCCESS: - return "SUCCESS"; - case TMP112A_STATUS_ERROR: - return "ERROR"; - case TMP112A_STATUS_TIMEOUT: - return "TIMEOUT"; - case TMP112A_STATUS_INVALID_PARAM: - return "INVALID_PARAM"; - case TMP112A_STATUS_OUT_OF_RANGE: - return "OUT_OF_RANGE"; - default: - return "UNKNOWN"; - } -} - -/* Private Functions Implementation */ - -/*! - \brief 写入寄存器 - \param[in] reg_addr: 寄存器地址 - \param[in] value: 写入值 - \param[out] none - \retval i2c_result_t -*/ -static i2c_result_t tmp112a_write_register(uint8_t reg_addr, uint16_t value) { - uint8_t data[2]; - data[0] = (value >> 8) & 0xFF; - data[1] = value & 0xFF; - - return i2c_write_16bits(TMP112A_ADDR, reg_addr, data); -} - -/*! - \brief 读取寄存器 - \param[in] reg_addr: 寄存器地址 - \param[out] value: 读取值指针 - \retval i2c_result_t -*/ -static i2c_result_t tmp112a_read_register(uint8_t reg_addr, uint16_t *value) { - uint8_t data[2]; - i2c_result_t status; - - if (value == NULL) { - return I2C_RESULT_INVALID_PARAM; - } - - status = i2c_read_16bits(TMP112A_ADDR, reg_addr, data); - if (status == I2C_RESULT_SUCCESS) { - *value = ((uint16_t)data[0] << 8) | data[1]; - } - - return status; -} - -/*! - \brief 将原始数据转换为摄氏度 - \param[in] raw_data: 原始数据 - \param[out] none - \retval float 温度值(°C) -*/ -static float tmp112a_raw_to_celsius(uint16_t raw_data) { - int16_t temp_raw; - - /* TMP112A使用12位分辨率，数据在高12位 */ - temp_raw = (int16_t)(raw_data >> 4); - - /* 处理负数 */ - if (temp_raw & 0x800) { - temp_raw |= 0xF000; // 符号扩展 - } - - /* 转换为摄氏度 */ - return (float)temp_raw * TMP112A_TEMP_RESOLUTION; -} - -/*! - \brief 将摄氏度转换为原始数据 - \param[in] temperature: 温度值(°C) - \param[out] none - \retval uint16_t 原始数据 -*/ -static uint16_t tmp112a_celsius_to_raw(float temperature) { - int16_t temp_raw; - - /* 转换为原始值 */ - temp_raw = (int16_t)(temperature / TMP112A_TEMP_RESOLUTION); - - /* 移位到高12位 */ - return (uint16_t)(temp_raw << 4); -} +// +// Created by dell on 24-12-20. +// TMP112A Temperature Sensor Driver Implementation +// + +#include "tmp112.h" + +/* Private function prototypes */ +static i2c_result_t tmp112a_write_register(uint8_t reg_addr, uint16_t value); +static i2c_result_t tmp112a_read_register(uint8_t reg_addr, uint16_t *value); +static float tmp112a_raw_to_celsius(uint16_t raw_data); +static uint16_t tmp112a_celsius_to_raw(float temperature); + +/*! + \brief 初始化TMP112A传感器 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_init(void) { + i2c_result_t i2c_status; + + /* 配置传感器为默认设置 */ + i2c_status = tmp112a_config(TMP112A_CONFIG_DEFAULT); + if (i2c_status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 等待配置生效 */ + delay_ms(1); + + return TMP112A_STATUS_SUCCESS; +} + +/*! + \brief 配置TMP112A传感器 + \param[in] config: 配置值 + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_config(uint16_t config) { + i2c_result_t status = tmp112a_write_register(TMP112A_CONFIG_REG, config); + return (status == I2C_RESULT_SUCCESS) ? TMP112A_STATUS_SUCCESS : TMP112A_STATUS_ERROR; +} + +/*! + \brief 读取温度 + \param[in] none + \param[out] result: 结果结构体指针 + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_read_temperature(tmp112a_result_t *result) { + uint16_t raw_data; + i2c_result_t status; + + if (result == NULL) { + return TMP112A_STATUS_INVALID_PARAM; + } + + /* 读取温度寄存器 */ + status = tmp112a_read_register(TMP112A_TEMP_REG, &raw_data); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 解析温度数据 */ + result->raw_data = raw_data; + result->temperature_c = tmp112a_raw_to_celsius(raw_data); + result->temperature_f = result->temperature_c * 9.0f / 5.0f + 32.0f; + + /* 检查温度范围 */ + if (result->temperature_c < TMP112A_TEMP_MIN || result->temperature_c > TMP112A_TEMP_MAX) { + return TMP112A_STATUS_OUT_OF_RANGE; + } + + /* 检查报警标志 */ + uint16_t config_reg; + status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); + if (status == I2C_RESULT_SUCCESS) { + result->alert_flag = (config_reg & TMP112A_CONFIG_AL) ? true : false; + } else { + result->alert_flag = false; + } + + return TMP112A_STATUS_SUCCESS; +} + +void tmp112a_get_raw_temperature_value(uint8_t *value) { + i2c_read_16bits(TMP112A_ADDR, TMP112A_TEMP_REG, value); + return; +} + +/*! + \brief 设置温度阈值 + \param[in] low_temp: 低温阈值 (°C) + \param[in] high_temp: 高温阈值 (°C) + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_set_thresholds(float low_temp, float high_temp) { + uint16_t low_raw, high_raw; + i2c_result_t status; + + /* 参数验证 */ + if (low_temp < TMP112A_TEMP_MIN || low_temp > TMP112A_TEMP_MAX || + high_temp < TMP112A_TEMP_MIN || high_temp > TMP112A_TEMP_MAX || + low_temp >= high_temp) { + return TMP112A_STATUS_INVALID_PARAM; + } + + /* 转换温度为原始值 */ + low_raw = tmp112a_celsius_to_raw(low_temp); + high_raw = tmp112a_celsius_to_raw(high_temp); + + /* 写入低温阈值 */ + status = tmp112a_write_register(TMP112A_TLOW_REG, low_raw); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 写入高温阈值 */ + status = tmp112a_write_register(TMP112A_THIGH_REG, high_raw); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + return TMP112A_STATUS_SUCCESS; +} + +/*! + \brief 进入关机模式 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_shutdown(void) { + uint16_t config_reg; + i2c_result_t status; + + /* 读取当前配置 */ + status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 设置关机位 */ + config_reg |= TMP112A_CONFIG_SD; + + /* 写回配置 */ + status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); + return (status == I2C_RESULT_SUCCESS) ? TMP112A_STATUS_SUCCESS : TMP112A_STATUS_ERROR; +} + +/*! + \brief 退出关机模式 + \param[in] none + \param[out] none + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_wakeup(void) { + uint16_t config_reg; + i2c_result_t status; + + /* 读取当前配置 */ + status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 清除关机位 */ + config_reg &= ~TMP112A_CONFIG_SD; + + /* 写回配置 */ + status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 等待传感器启动 */ + delay_ms(1); + + return TMP112A_STATUS_SUCCESS; +} + +/*! + \brief 单次转换 + \param[in] none + \param[out] result: 结果结构体指针 + \retval tmp112a_status_t +*/ +tmp112a_status_t tmp112a_one_shot(tmp112a_result_t *result) { + uint16_t config_reg; + i2c_result_t status; + uint8_t timeout = 100; // 100ms超时 + + if (result == NULL) { + return TMP112A_STATUS_INVALID_PARAM; + } + + /* 读取当前配置 */ + status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 启动单次转换 */ + config_reg |= TMP112A_CONFIG_OS; + status = tmp112a_write_register(TMP112A_CONFIG_REG, config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + + /* 等待转换完成 */ + do { + delay_ms(1); + status = tmp112a_read_register(TMP112A_CONFIG_REG, &config_reg); + if (status != I2C_RESULT_SUCCESS) { + return TMP112A_STATUS_ERROR; + } + timeout--; + } while ((config_reg & TMP112A_CONFIG_OS) && timeout > 0); + + if (timeout == 0) { + return TMP112A_STATUS_TIMEOUT; + } + + /* 读取转换结果 */ + return tmp112a_read_temperature(result); +} + +/*! + \brief 获取状态字符串 + \param[in] status: 状态码 + \param[out] none + \retval const char* 状态字符串 +*/ +const char* tmp112a_get_status_string(tmp112a_status_t status) { + switch (status) { + case TMP112A_STATUS_SUCCESS: + return "SUCCESS"; + case TMP112A_STATUS_ERROR: + return "ERROR"; + case TMP112A_STATUS_TIMEOUT: + return "TIMEOUT"; + case TMP112A_STATUS_INVALID_PARAM: + return "INVALID_PARAM"; + case TMP112A_STATUS_OUT_OF_RANGE: + return "OUT_OF_RANGE"; + default: + return "UNKNOWN"; + } +} + +/* Private Functions Implementation */ + +/*! + \brief 写入寄存器 + \param[in] reg_addr: 寄存器地址 + \param[in] value: 写入值 + \param[out] none + \retval i2c_result_t +*/ +static i2c_result_t tmp112a_write_register(uint8_t reg_addr, uint16_t value) { + uint8_t data[2]; + data[0] = (value >> 8) & 0xFF; + data[1] = value & 0xFF; + + return i2c_write_16bits(TMP112A_ADDR, reg_addr, data); +} + +/*! + \brief 读取寄存器 + \param[in] reg_addr: 寄存器地址 + \param[out] value: 读取值指针 + \retval i2c_result_t +*/ +static i2c_result_t tmp112a_read_register(uint8_t reg_addr, uint16_t *value) { + uint8_t data[2]; + i2c_result_t status; + + if (value == NULL) { + return I2C_RESULT_INVALID_PARAM; + } + + status = i2c_read_16bits(TMP112A_ADDR, reg_addr, data); + if (status == I2C_RESULT_SUCCESS) { + *value = ((uint16_t)data[0] << 8) | data[1]; + } + + return status; +} + +/*! + \brief 将原始数据转换为摄氏度 + \param[in] raw_data: 原始数据 + \param[out] none + \retval float 温度值(°C) +*/ +static float tmp112a_raw_to_celsius(uint16_t raw_data) { + int16_t temp_raw; + + /* TMP112A使用12位分辨率，数据在高12位 */ + temp_raw = (int16_t)(raw_data >> 4); + + /* 处理负数 */ + if (temp_raw & 0x800) { + temp_raw |= 0xF000; // 符号扩展 + } + + /* 转换为摄氏度 */ + return (float)temp_raw * TMP112A_TEMP_RESOLUTION; +} + +/*! + \brief 将摄氏度转换为原始数据 + \param[in] temperature: 温度值(°C) + \param[out] none + \retval uint16_t 原始数据 +*/ +static uint16_t tmp112a_celsius_to_raw(float temperature) { + int16_t temp_raw; + + /* 转换为原始值 */ + temp_raw = (int16_t)(temperature / TMP112A_TEMP_RESOLUTION); + + /* 移位到高12位 */ + return (uint16_t)(temp_raw << 4); +} diff --git a/Src/uart.c b/Src/uart.c index 10f27ee..d73cd75 100644 --- a/Src/uart.c +++ b/Src/uart.c @@ -1,107 +1,107 @@ -#include "uart.h" -#include "gd32e23x_usart.h" -#include "gd32e23x_rcu.h" -#include "gd32e23x_gpio.h" -#include "board_config.h" -#include "uart_ring_buffer.h" - - -void rs485_init(void) { - - #ifndef RS485_MAX13487 - /* 使能 GPIOA 和 USART0 时钟 */ - rcu_periph_clock_enable(RS485_GPIO_RCU); - rcu_periph_clock_enable(RS485_RCU); - - /* 配置 PA2 为 USART0_TX，PA3 为 USART0_RX */ - gpio_af_set(RS485_GPIO_PORT, GPIO_AF_1, RS485_TX_PIN | RS485_RX_PIN | RS485_EN_PIN); - - gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, RS485_TX_PIN | RS485_RX_PIN); - gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_TX_PIN | RS485_RX_PIN); - - gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, RS485_EN_PIN); - gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_EN_PIN); - - /* 配置波特率、数据位、停止位等 */ - usart_deinit(RS485_PHY); - usart_word_length_set(RS485_PHY, USART_WL_8BIT); - usart_stop_bit_set(RS485_PHY, USART_STB_1BIT); - usart_parity_config(RS485_PHY, USART_PM_NONE); - usart_baudrate_set(RS485_PHY, RS485_BAUDRATE); - usart_receive_config(RS485_PHY, USART_RECEIVE_ENABLE); - usart_transmit_config(RS485_PHY, USART_TRANSMIT_ENABLE); - - usart_driver_assertime_config(RS485_PHY, 0x01); - usart_driver_deassertime_config(RS485_PHY, 0x10); - - usart_rs485_driver_enable(RS485_PHY); - - usart_enable(RS485_PHY); - - nvic_irq_enable(RS485_IRQ, 0); - usart_interrupt_enable(RS485_PHY, USART_INT_RBNE); - // usart_interrupt_enable(RS485_PHY, USART_INT_IDLE); - - #else - rcu_periph_clock_enable(RS485_GPIO_RCU); - rcu_periph_clock_enable(RS485_RCU); - - gpio_af_set(RS485_GPIO_PORT, GPIO_AF_1, GPIO_PIN_2 | GPIO_PIN_3); - - /* configure USART Tx&Rx as alternate function push-pull */ - gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, RS485_TX_PIN | RS485_RX_PIN); - gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, RS485_TX_PIN | RS485_RX_PIN); - - /* configure RS485 EN Pin */ - gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, RS485_EN_PIN); - gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_EN_PIN); - gpio_bit_write(RS485_GPIO_PORT, RS485_EN_PIN, SET); - - /* USART configure */ - usart_deinit(RS485_PHY); - usart_baudrate_set(RS485_PHY, RS485_BAUDRATE); - usart_receive_config(RS485_PHY, USART_RECEIVE_ENABLE); - usart_transmit_config(RS485_PHY, USART_TRANSMIT_ENABLE); - - usart_enable(RS485_PHY); - - nvic_irq_enable(USART0_IRQn, 0); - usart_interrupt_enable(RS485_PHY, USART_INT_RBNE); - usart_interrupt_enable(RS485_PHY, USART_INT_IDLE); - - #endif // RS485_MAX13487 - } - -/******************************************************************************/ -/* 具体的中断处理函数实现 */ -/******************************************************************************/ - -void usart0_irq_handler(void) { - // 处理USART0的接收中断 - if(usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) { - uint8_t data = usart_data_receive(USART0); - // 使用原有的环形缓冲区处理逻辑 - (void)uart_ring_buffer_put(data); // 缓冲满时丢弃，返回值可用于统计 - } - - // 处理USART0的空闲中断 - if(usart_interrupt_flag_get(USART0, USART_INT_FLAG_IDLE)) { - usart_interrupt_flag_clear(USART0, USART_INT_FLAG_IDLE); - // 在这里添加空闲中断处理逻辑 - } -} - -void usart1_irq_handler(void) { - // 处理USART1的接收中断 - if(usart_interrupt_flag_get(USART1, USART_INT_FLAG_RBNE)) { - uint8_t data = usart_data_receive(USART1); - // 使用原有的环形缓冲区处理逻辑 - (void)uart_ring_buffer_put(data); // 缓冲满时丢弃，返回值可用于统计 - } - - // 处理USART1的空闲中断 - if(usart_interrupt_flag_get(USART1, USART_INT_FLAG_IDLE)) { - usart_interrupt_flag_clear(USART1, USART_INT_FLAG_IDLE); - // 在这里添加空闲中断处理逻辑 - } -} +#include "uart.h" +#include "gd32e23x_usart.h" +#include "gd32e23x_rcu.h" +#include "gd32e23x_gpio.h" +#include "board_config.h" +#include "uart_ring_buffer.h" + + +void rs485_init(void) { + + #ifndef RS485_MAX13487 + /* 使能 GPIOA 和 USART0 时钟 */ + rcu_periph_clock_enable(RS485_GPIO_RCU); + rcu_periph_clock_enable(RS485_RCU); + + /* 配置 PA2 为 USART0_TX，PA3 为 USART0_RX */ + gpio_af_set(RS485_GPIO_PORT, GPIO_AF_1, RS485_TX_PIN | RS485_RX_PIN | RS485_EN_PIN); + + gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, RS485_TX_PIN | RS485_RX_PIN); + gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_TX_PIN | RS485_RX_PIN); + + gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE, RS485_EN_PIN); + gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_EN_PIN); + + /* 配置波特率、数据位、停止位等 */ + usart_deinit(RS485_PHY); + usart_word_length_set(RS485_PHY, USART_WL_8BIT); + usart_stop_bit_set(RS485_PHY, USART_STB_1BIT); + usart_parity_config(RS485_PHY, USART_PM_NONE); + usart_baudrate_set(RS485_PHY, RS485_BAUDRATE); + usart_receive_config(RS485_PHY, USART_RECEIVE_ENABLE); + usart_transmit_config(RS485_PHY, USART_TRANSMIT_ENABLE); + + usart_driver_assertime_config(RS485_PHY, 0x01); + usart_driver_deassertime_config(RS485_PHY, 0x10); + + usart_rs485_driver_enable(RS485_PHY); + + usart_enable(RS485_PHY); + + nvic_irq_enable(RS485_IRQ, 0); + usart_interrupt_enable(RS485_PHY, USART_INT_RBNE); + // usart_interrupt_enable(RS485_PHY, USART_INT_IDLE); + + #else + rcu_periph_clock_enable(RS485_GPIO_RCU); + rcu_periph_clock_enable(RS485_RCU); + + gpio_af_set(RS485_GPIO_PORT, GPIO_AF_1, GPIO_PIN_2 | GPIO_PIN_3); + + /* configure USART Tx&Rx as alternate function push-pull */ + gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_AF, GPIO_PUPD_PULLUP, RS485_TX_PIN | RS485_RX_PIN); + gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_10MHZ, RS485_TX_PIN | RS485_RX_PIN); + + /* configure RS485 EN Pin */ + gpio_mode_set(RS485_GPIO_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, RS485_EN_PIN); + gpio_output_options_set(RS485_GPIO_PORT, GPIO_OTYPE_PP, GPIO_OSPEED_50MHZ, RS485_EN_PIN); + gpio_bit_write(RS485_GPIO_PORT, RS485_EN_PIN, SET); + + /* USART configure */ + usart_deinit(RS485_PHY); + usart_baudrate_set(RS485_PHY, RS485_BAUDRATE); + usart_receive_config(RS485_PHY, USART_RECEIVE_ENABLE); + usart_transmit_config(RS485_PHY, USART_TRANSMIT_ENABLE); + + usart_enable(RS485_PHY); + + nvic_irq_enable(USART0_IRQn, 0); + usart_interrupt_enable(RS485_PHY, USART_INT_RBNE); + usart_interrupt_enable(RS485_PHY, USART_INT_IDLE); + + #endif // RS485_MAX13487 + } + +/******************************************************************************/ +/* 具体的中断处理函数实现 */ +/******************************************************************************/ + +void usart0_irq_handler(void) { + // 处理USART0的接收中断 + if(usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) { + uint8_t data = usart_data_receive(USART0); + // 使用原有的环形缓冲区处理逻辑 + (void)uart_ring_buffer_put(data); // 缓冲满时丢弃，返回值可用于统计 + } + + // 处理USART0的空闲中断 + if(usart_interrupt_flag_get(USART0, USART_INT_FLAG_IDLE)) { + usart_interrupt_flag_clear(USART0, USART_INT_FLAG_IDLE); + // 在这里添加空闲中断处理逻辑 + } +} + +void usart1_irq_handler(void) { + // 处理USART1的接收中断 + if(usart_interrupt_flag_get(USART1, USART_INT_FLAG_RBNE)) { + uint8_t data = usart_data_receive(USART1); + // 使用原有的环形缓冲区处理逻辑 + (void)uart_ring_buffer_put(data); // 缓冲满时丢弃，返回值可用于统计 + } + + // 处理USART1的空闲中断 + if(usart_interrupt_flag_get(USART1, USART_INT_FLAG_IDLE)) { + usart_interrupt_flag_clear(USART1, USART_INT_FLAG_IDLE); + // 在这里添加空闲中断处理逻辑 + } +} diff --git a/Src/uart_ring_buffer.c b/Src/uart_ring_buffer.c index 73554f0..12a7efc 100644 --- a/Src/uart_ring_buffer.c +++ b/Src/uart_ring_buffer.c @@ -1,104 +1,104 @@ -/** - * @file uart_ring_buffer.c - * @brief 字节环形接收缓冲区的实现。 - * @details 适用于中断接收（写）与主循环解析（读）的典型串口场景； - * 采用“预留一格”区分空/满，最大可用容量为 UART_RX_BUFFER_SIZE-1。 - * @ingroup RingBuffer - */ -#include "uart_ring_buffer.h" - -static volatile uint8_t uart_rx_buffer[UART_RX_BUFFER_SIZE]; -static volatile uint8_t write_index = 0; -static volatile uint8_t read_index = 0; -static volatile uint32_t dropped_bytes = 0; - -/** - * @brief 重置环形缓冲区状态。 - * @details 将读指针、写指针与丢弃计数清零，不清空数据区内容。 - * @note 内部工具函数；对外请优先使用 uart_ring_buffer_init()/uart_ring_buffer_clear()。 - * @ingroup RingBuffer - */ -static void uart_ring_buffer_reset_state(void) { - write_index = 0; - read_index = 0; - dropped_bytes = 0; -} - -/** - * @brief 初始化环形缓冲区。 - * @details 调用内部重置逻辑，复位读写索引与丢弃计数，准备接收数据。 - * @note 若在中断环境使用，初始化前建议关闭相关接收中断以避免并发竞争。 - * @ingroup RingBuffer - */ -void uart_ring_buffer_init(void) { - uart_ring_buffer_reset_state(); -} - -/** - * @brief 获取当前可读的字节数。 - * @details 通过读/写指针的快照计算可读长度，范围为 [0, UART_RX_BUFFER_SIZE-1]。 - * @return uint8_t 可读字节数。 - * @note 预留一个空槽区分“空/满”，因此满时返回 UART_RX_BUFFER_SIZE-1。 - * @ingroup RingBuffer - */ -uint8_t uart_ring_buffer_available(void) { - /* 使用快照减少并发不一致窗口 */ - uint8_t w = write_index; - uint8_t r = read_index; - return (uint8_t)((w + UART_RX_BUFFER_SIZE - r) % UART_RX_BUFFER_SIZE); -} - -/** - * @brief 从环形缓冲区读取一个字节。 - * @details 若缓冲区非空，返回队头字节并推进读指针；若为空，返回 -1。 - * @return int 读取到的字节（0..255），或 -1 表示缓冲区为空。 - * @ingroup RingBuffer - */ -int uart_ring_buffer_get(void) { - if (read_index == write_index) return -1; // 空 - uint8_t data = uart_rx_buffer[read_index]; - read_index = (read_index + 1) % UART_RX_BUFFER_SIZE; - return data; -} - -/** - * @brief 向环形缓冲区写入一个字节。 - * @details 尝试写入一个新字节；若缓冲区已满则丢弃并计数。 - * @param data 待写入的字节。 - * @return bool 是否写入成功。 - * @retval true 写入成功。 - * @retval false 写入失败（缓冲区已满，数据被丢弃并计数）。 - * @note 如需“覆盖写入”策略，可在满时先推进读指针再写入。 - * @ingroup RingBuffer - */ -bool uart_ring_buffer_put(uint8_t data) { - uint8_t next = (write_index + 1) % UART_RX_BUFFER_SIZE; - if (next != read_index) { // 缓冲区未满 - uart_rx_buffer[write_index] = data; - write_index = next; - return true; - } else { - /* 缓冲区已满，丢弃新字节并计数 */ - dropped_bytes++; - return false; - } -} - -/** - * @brief 清空环形缓冲区。 - * @details 复位读写索引与丢弃计数，相当于逻辑上丢弃所有已接收数据，不擦除数据区内容。 - * @ingroup RingBuffer - */ -void uart_ring_buffer_clear(void) { - uart_ring_buffer_reset_state(); -} - -/** - * @brief 获取因满而被丢弃的字节累计数量。 - * @details 写入时缓冲区满会丢弃新字节并累加计数；该计数在 init/clear 时清零。 - * @return uint32_t 丢弃的累计字节数。 - * @ingroup RingBuffer - */ -uint32_t uart_ring_buffer_drop_count(void) { - return dropped_bytes; -} +/** + * @file uart_ring_buffer.c + * @brief 字节环形接收缓冲区的实现。 + * @details 适用于中断接收（写）与主循环解析（读）的典型串口场景； + * 采用“预留一格”区分空/满，最大可用容量为 UART_RX_BUFFER_SIZE-1。 + * @ingroup RingBuffer + */ +#include "uart_ring_buffer.h" + +static volatile uint8_t uart_rx_buffer[UART_RX_BUFFER_SIZE]; +static volatile uint8_t write_index = 0; +static volatile uint8_t read_index = 0; +static volatile uint32_t dropped_bytes = 0; + +/** + * @brief 重置环形缓冲区状态。 + * @details 将读指针、写指针与丢弃计数清零，不清空数据区内容。 + * @note 内部工具函数；对外请优先使用 uart_ring_buffer_init()/uart_ring_buffer_clear()。 + * @ingroup RingBuffer + */ +static void uart_ring_buffer_reset_state(void) { + write_index = 0; + read_index = 0; + dropped_bytes = 0; +} + +/** + * @brief 初始化环形缓冲区。 + * @details 调用内部重置逻辑，复位读写索引与丢弃计数，准备接收数据。 + * @note 若在中断环境使用，初始化前建议关闭相关接收中断以避免并发竞争。 + * @ingroup RingBuffer + */ +void uart_ring_buffer_init(void) { + uart_ring_buffer_reset_state(); +} + +/** + * @brief 获取当前可读的字节数。 + * @details 通过读/写指针的快照计算可读长度，范围为 [0, UART_RX_BUFFER_SIZE-1]。 + * @return uint8_t 可读字节数。 + * @note 预留一个空槽区分“空/满”，因此满时返回 UART_RX_BUFFER_SIZE-1。 + * @ingroup RingBuffer + */ +uint8_t uart_ring_buffer_available(void) { + /* 使用快照减少并发不一致窗口 */ + uint8_t w = write_index; + uint8_t r = read_index; + return (uint8_t)((w + UART_RX_BUFFER_SIZE - r) % UART_RX_BUFFER_SIZE); +} + +/** + * @brief 从环形缓冲区读取一个字节。 + * @details 若缓冲区非空，返回队头字节并推进读指针；若为空，返回 -1。 + * @return int 读取到的字节（0..255），或 -1 表示缓冲区为空。 + * @ingroup RingBuffer + */ +int uart_ring_buffer_get(void) { + if (read_index == write_index) return -1; // 空 + uint8_t data = uart_rx_buffer[read_index]; + read_index = (read_index + 1) % UART_RX_BUFFER_SIZE; + return data; +} + +/** + * @brief 向环形缓冲区写入一个字节。 + * @details 尝试写入一个新字节；若缓冲区已满则丢弃并计数。 + * @param data 待写入的字节。 + * @return bool 是否写入成功。 + * @retval true 写入成功。 + * @retval false 写入失败（缓冲区已满，数据被丢弃并计数）。 + * @note 如需“覆盖写入”策略，可在满时先推进读指针再写入。 + * @ingroup RingBuffer + */ +bool uart_ring_buffer_put(uint8_t data) { + uint8_t next = (write_index + 1) % UART_RX_BUFFER_SIZE; + if (next != read_index) { // 缓冲区未满 + uart_rx_buffer[write_index] = data; + write_index = next; + return true; + } else { + /* 缓冲区已满，丢弃新字节并计数 */ + dropped_bytes++; + return false; + } +} + +/** + * @brief 清空环形缓冲区。 + * @details 复位读写索引与丢弃计数，相当于逻辑上丢弃所有已接收数据，不擦除数据区内容。 + * @ingroup RingBuffer + */ +void uart_ring_buffer_clear(void) { + uart_ring_buffer_reset_state(); +} + +/** + * @brief 获取因满而被丢弃的字节累计数量。 + * @details 写入时缓冲区满会丢弃新字节并累加计数；该计数在 init/clear 时清零。 + * @return uint32_t 丢弃的累计字节数。 + * @ingroup RingBuffer + */ +uint32_t uart_ring_buffer_drop_count(void) { + return dropped_bytes; +}