Template
55017 lines
1.8 MiB
Plaintext
55017 lines
1.8 MiB
Plaintext
<?xml version="1.0" encoding="utf-8" standalone="no"?>
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<device schemaVersion="1.1"
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xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
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xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>GD32F4xx</name>
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<version>1.0</version>
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<description>GD32F4xx ARM 32-bit Cortex-M4 Microcontroller based device</description>
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<cpu>
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<name>CM4</name>
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<revision>r2p1</revision>
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<endian>little</endian>
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<mpuPresent>1</mpuPresent>
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<fpuPresent>1</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>0</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<!--Bus Interface Properties-->
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<!--the maximum data bit width accessible within a single transfer-->
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<!--Cortex-M3 is byte addressable-->
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<!--Register Default Properties-->
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<size>0x20</size>
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<resetValue>0x0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>ADC0</name>
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<description>Analog to digital converter</description>
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<groupName>ADC</groupName>
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<baseAddress>0x40012000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x100</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>ADC</name>
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<value>18</value>
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</interrupt>
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<registers>
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<register>
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<name>STAT</name>
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<displayName>STAT</displayName>
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<description>status register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ROVF</name>
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<description>Regular data register overflow</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>STRC</name>
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<description>Start flag of regular channel group</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>STIC</name>
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<description>Start flag of inserted channel group</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOIC</name>
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<description>End of inserted group conversion flag</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOC</name>
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<description>End of group conversion flag</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WDE</name>
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<description>Analog watchdog event flag</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CTL0</name>
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<displayName>CTL0</displayName>
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<description>control register 0</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ROVFIE</name>
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<description>Interrupt enable for ROVF</description>
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<bitOffset>26</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DRES</name>
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<description>ADC data resolution</description>
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<bitOffset>24</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>RWDEN</name>
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<description>Regular channel analog watchdog
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enable</description>
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<bitOffset>23</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>IWDEN</name>
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<description>Inserted channel analog watchdog
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enable</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DISNUM</name>
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<description>Number of conversions in
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discontinuous mode</description>
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<bitOffset>13</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>DISIC</name>
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<description>Discontinuous mode on
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inserted channels</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DISRC</name>
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<description>Discontinuous mode on regular
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channels</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ICA</name>
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<description>Inserted channel group convert
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automatically</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WDSC</name>
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<description>When in scan mode, analog watchdog
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is effective on a single channel</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SM</name>
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<description>Scan mode</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOICIE</name>
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<description>Interrupt enable for EOIC</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WDEIE</name>
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<description>Analog watchdog WDE</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOCIE</name>
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<description>Interrupt enable for EOC</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WDCHSEL</name>
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<description>Analog watchdog channel select</description>
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<bitOffset>0</bitOffset>
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<bitWidth>5</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CTL1</name>
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<displayName>CTL1</displayName>
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<description>control register 1</description>
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<addressOffset>0x08</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SWRCST</name>
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<description>Software start on regular channel</description>
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<bitOffset>30</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ETMRC</name>
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<description>External trigger mode for regular
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channel</description>
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<bitOffset>28</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>ETSRC</name>
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<description>External trigger select for regular
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channel</description>
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<bitOffset>24</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>SWICST</name>
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<description>Software start on inserted channel</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ETMIC</name>
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<description>External trigger mode for inserted
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channel</description>
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<bitOffset>20</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>ETSIC</name>
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<description>External trigger select for inserted
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channel</description>
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<bitOffset>16</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>DAL</name>
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<description>Data alignment</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOCM</name>
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<description>End of conversion mode</description>
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<bitOffset>10</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DDM</name>
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<description>DMA disable mode</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DMA</name>
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<description>DMA request enable</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>RSTCLB</name>
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<description>Reset calibration</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CLB</name>
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<description>ADC calibration</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CTN</name>
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<description>Continuous mode</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ADCON</name>
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<description>ADC on</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>SAMPT0</name>
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<displayName>SAMPT0</displayName>
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<description>Sample time register 0</description>
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<addressOffset>0x0C</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SPT10</name>
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<description>Channel 10 sample time
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selection</description>
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<bitOffset>0</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT11</name>
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<description>Channel 11 sample time
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selection</description>
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<bitOffset>3</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT12</name>
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<description>Channel 12 sample time
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selection</description>
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<bitOffset>6</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT13</name>
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<description>Channel 13 sample time
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selection</description>
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<bitOffset>9</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT14</name>
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<description>Channel 14 sample time
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selection</description>
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<bitOffset>12</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT15</name>
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<description>Channel 15 sample time
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selection</description>
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<bitOffset>15</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT16</name>
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<description>Channel 16 sample time
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selection</description>
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<bitOffset>18</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT17</name>
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<description>Channel 17 sample time
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selection</description>
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<bitOffset>21</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT18</name>
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<description>Channel 18 sample time
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selection</description>
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<bitOffset>24</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>SAMPT1</name>
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<displayName>SAMPT1</displayName>
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<description>Sample time register 1</description>
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<addressOffset>0x10</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SPT0</name>
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<description>Channel 0 sample time
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selection</description>
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<bitOffset>0</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT1</name>
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<description>Channel 1 sample time
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selection</description>
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<bitOffset>3</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT2</name>
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<description>Channel 2 sample time
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selection</description>
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<bitOffset>6</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT3</name>
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<description>Channel 3 sample time
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selection</description>
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<bitOffset>9</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT4</name>
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<description>Channel 4 sample time
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selection</description>
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<bitOffset>12</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT5</name>
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<description>Channel 5 sample time
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selection</description>
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<bitOffset>15</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT6</name>
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<description>Channel 6 sample time
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selection</description>
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<bitOffset>18</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT7</name>
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<description>Channel 7 sample time
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selection</description>
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<bitOffset>21</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT8</name>
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<description>Channel 8 sample time
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selection</description>
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<bitOffset>24</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>SPT9</name>
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<description>Channel 9 sample time
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selection</description>
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<bitOffset>27</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>IOFF0</name>
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<displayName>IOFF0</displayName>
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<description>Inserted channel data offset register
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0</description>
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<addressOffset>0x14</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>IOFF</name>
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<description>Data offset for inserted channel
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0</description>
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>IOFF1</name>
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<displayName>IOFF1</displayName>
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<description>Inserted channel data offset register
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1</description>
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<addressOffset>0x18</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
|
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<resetValue>0x00000000</resetValue>
|
|
<fields>
|
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<field>
|
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<name>IOFF</name>
|
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<description>Data offset for inserted channel
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1</description>
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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</fields>
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</register>
|
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<register>
|
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<name>IOFF2</name>
|
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<displayName>IOFF2</displayName>
|
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<description>Inserted channel data offset register
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|
2</description>
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<addressOffset>0x1C</addressOffset>
|
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<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IOFF</name>
|
|
<description>Data offset for inserted channel
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|
2</description>
|
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOFF3</name>
|
|
<displayName>IOFF3</displayName>
|
|
<description>Inserted channel data offset register
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|
3</description>
|
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<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
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<field>
|
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<name>IOFF</name>
|
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<description>Data offset for inserted channel
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3</description>
|
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<bitOffset>0</bitOffset>
|
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<bitWidth>12</bitWidth>
|
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</field>
|
|
</fields>
|
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</register>
|
|
<register>
|
|
<name>WDHT</name>
|
|
<displayName>WDHT</displayName>
|
|
<description>watchdog higher threshold
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDHT</name>
|
|
<description>Analog watchdog higher
|
|
threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDLT</name>
|
|
<displayName>WDLT</displayName>
|
|
<description>watchdog lower threshold
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDLT</name>
|
|
<description>Analog watchdog lower
|
|
threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSQ0</name>
|
|
<displayName>RSQ0</displayName>
|
|
<description>regular sequence register 0</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RL</name>
|
|
<description>Regular channel group
|
|
length</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ15</name>
|
|
<description>16th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ14</name>
|
|
<description>15th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ13</name>
|
|
<description>14th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ12</name>
|
|
<description>13th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSQ1</name>
|
|
<displayName>RSQ1</displayName>
|
|
<description>regular sequence register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSQ11</name>
|
|
<description>12th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ10</name>
|
|
<description>11th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ9</name>
|
|
<description>10th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ8</name>
|
|
<description>9th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ7</name>
|
|
<description>8th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ6</name>
|
|
<description>7th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSQ2</name>
|
|
<displayName>RSQ2</displayName>
|
|
<description>regular sequence register 2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSQ5</name>
|
|
<description>6th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ4</name>
|
|
<description>5th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ3</name>
|
|
<description>4th conversion in regular
|
|
sequence</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ2</name>
|
|
<description>3rd conversion in regular
|
|
sequence</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ1</name>
|
|
<description>2nd conversion in regular
|
|
sequence</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSQ0</name>
|
|
<description>1st conversion in regular
|
|
sequence</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISQ</name>
|
|
<displayName>ISQ</displayName>
|
|
<description>Inserted sequence register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IL</name>
|
|
<description>Inserted channel group length</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISQ3</name>
|
|
<description>4th conversion in inserted
|
|
sequence</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISQ2</name>
|
|
<description>3rd conversion in inserted
|
|
sequence</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISQ1</name>
|
|
<description>2nd conversion in inserted
|
|
sequence</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISQ0</name>
|
|
<description>1st conversion in inserted
|
|
sequence</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDATA0</name>
|
|
<displayName>IDATA0</displayName>
|
|
<description>Inserted data register 0</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDATAn</name>
|
|
<description>Inserted number n conversion data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDATA1</name>
|
|
<displayName>IDATA1</displayName>
|
|
<description>Inserted data register 1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDATAn</name>
|
|
<description>Inserted number n conversion data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDATA2</name>
|
|
<displayName>IDATA2</displayName>
|
|
<description>Inserted data register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDATAn</name>
|
|
<description>Inserted number n conversion data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDATA3</name>
|
|
<displayName>IDATA3</displayName>
|
|
<description>Inserted data register 3</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDATAn</name>
|
|
<description>Inserted number n conversion data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDATA</name>
|
|
<displayName>RDATA</displayName>
|
|
<description>regular data register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Regular channel data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OVSAMPCTL</name>
|
|
<displayName>OVSAMPCTL</displayName>
|
|
<description>Oversample control register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TOVS</name>
|
|
<description>Triggered Oversampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSS</name>
|
|
<description>Oversampling shift</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSR</name>
|
|
<description>Oversampling ratio</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSEN</name>
|
|
<description>Oversampling Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC1</name>
|
|
<baseAddress>0x40012100</baseAddress>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC0">
|
|
<name>ADC2</name>
|
|
<baseAddress>0x40012200</baseAddress>
|
|
<interrupt>
|
|
<name>ADC</name>
|
|
<value>18</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC_Common</name>
|
|
<description>common ADC register</description>
|
|
<baseAddress>0x40012300</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>SSTAT</name>
|
|
<displayName>SSTAT</displayName>
|
|
<description>summary status register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ROVF2</name>
|
|
<description>This bit equals to the ROVF bit of ADC2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STRC2</name>
|
|
<description>This bit equals to the STRC bit of ADC2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STIC2</name>
|
|
<description>This bit equals to the STIC bit of ADC2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOIC2</name>
|
|
<description>This bit equals to the EOIC bit of ADC2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC2</name>
|
|
<description>This bit equals to the EOC bit of ADC2</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDE2</name>
|
|
<description>This bit equals to the WDE bit of ADC2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVF1</name>
|
|
<description>This bit equals to the ROVF bit of ADC1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STRC1</name>
|
|
<description>This bit equals to the STRC bit of ADC1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STIC1</name>
|
|
<description>This bit equals to the STIC bit of ADC1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOIC1</name>
|
|
<description>This bit equals to the EOIC bit of ADC1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC1</name>
|
|
<description>This bit equals to the EOC bit of ADC1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDE1</name>
|
|
<description>This bit equals to the WDE bit of ADC1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVF0</name>
|
|
<description>This bit equals to the ROVF bit of ADC0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STRC0</name>
|
|
<description>This bit equals to the STRC bit of ADC0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STIC0</name>
|
|
<description>This bit equals to the STIC bit of ADC0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOIC0</name>
|
|
<description>This bit equals to the EOIC bit of ADC0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC0</name>
|
|
<description>This bit equals to the EOC bit of ADC0</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDE0</name>
|
|
<description>This bit equals to the WDE bit of ADC0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCCTL</name>
|
|
<displayName>SYNCCTL</displayName>
|
|
<description>sync control register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSVREN</name>
|
|
<description>Channel 16 (temperature sensor) and
|
|
17 (internal reference voltage) enable of ADC0</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBATEN</name>
|
|
<description>Channel 18 (1/4 voltate of external battery) enable
|
|
of ADC0</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCCK</name>
|
|
<description>ADC clock</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDMA</name>
|
|
<description>ADC sync DMA mode selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDDM</name>
|
|
<description>ADC sync DMA disable mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDLY</name>
|
|
<description>ADC sync delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCM</name>
|
|
<description>ADC sync mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNCDATA</name>
|
|
<displayName>SYNCDATA</displayName>
|
|
<description>Sync regular data register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCDATA2</name>
|
|
<description>Regular data2 in ADC sync mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDATA1</name>
|
|
<description>Regular data1 in ADC sync mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN0</name>
|
|
<description>Controller area network</description>
|
|
<groupName>CAN</groupName>
|
|
<baseAddress>0x40006400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CAN0_TX</name>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN0_RX0</name>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN0_RX1</name>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN0_EWMC</name>
|
|
<value>22</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DFZ</name>
|
|
<description>Debug freeze</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TTC</name>
|
|
<description>Time-triggered communication</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABOR</name>
|
|
<description>Automatic bus-off recovery</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWU</name>
|
|
<description>Automatic wakeup</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARD</name>
|
|
<description>Automatic retransmission disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFOD</name>
|
|
<description>Receive FIFO overwrite disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFO</name>
|
|
<description>Transmit FIFO order</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLPWMOD</name>
|
|
<description>Sleep working mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IWMOD</name>
|
|
<description>Initial working mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000C02</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXL</name>
|
|
<description>RX level</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LASTRX</name>
|
|
<description>Last sample value of RX pin</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Receiving state</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Transmitting state</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SLPIF</name>
|
|
<description>Status change interrupt flag of sleep
|
|
working mode entering</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUIF</name>
|
|
<description>Status change interrupt flag of wakeup
|
|
from sleep working mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIF</name>
|
|
<description>Error interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLPWS</name>
|
|
<description>Sleep working state</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IWS</name>
|
|
<description>Initial working state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTAT</name>
|
|
<displayName>TSTAT</displayName>
|
|
<description>Transmit status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x1C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMLS2</name>
|
|
<description>Transmit mailbox 2 last sending
|
|
in transmit FIFO</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TMLS1</name>
|
|
<description>Transmit mailbox 1 last sending
|
|
in transmit FIFO</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TMLS0</name>
|
|
<description>Transmit mailbox 0 last sending
|
|
in transmit FIFO</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TME2</name>
|
|
<description>Transmit mailbox 2 empty</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TME1</name>
|
|
<description>Transmit mailbox 1 empty</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TME0</name>
|
|
<description>Transmit mailbox 0 empty</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NUM</name>
|
|
<description>number of the transmit FIFO mailbox in
|
|
which the frame will be transmitted if at least one mailbox is empty</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MST2</name>
|
|
<description>Mailbox 2 stop transmitting</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTE2</name>
|
|
<description>Mailbox 2 transmit error</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAL2</name>
|
|
<description>Mailbox 2 arbitration lost</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTFNERR2</name>
|
|
<description>Mailbox 2 transmit finished and no error</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTF2</name>
|
|
<description>Mailbox 2 transmit finished</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MST1</name>
|
|
<description>Mailbox 1 stop transmitting</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTE1</name>
|
|
<description>Mailbox 1 transmit error</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAL1</name>
|
|
<description>Mailbox 1 arbitration lost</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTFNERR1</name>
|
|
<description>Mailbox 1 transmit finished and no error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTF1</name>
|
|
<description>Mailbox 1 transmit finished</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MST0</name>
|
|
<description>Mailbox 0 stop transmitting</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTE0</name>
|
|
<description>Mailbox 0 transmit error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAL0</name>
|
|
<description>Mailbox 0 arbitration lost</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTFNERR0</name>
|
|
<description>Mailbox 0 transmit finished and no error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MTF0</name>
|
|
<description>Mailbox 0 transmit finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFO0</name>
|
|
<displayName>RFIFO0</displayName>
|
|
<description>Receive message FIFO0 register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFD0</name>
|
|
<description>Receive FIFO0 dequeue</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFO0</name>
|
|
<description>Receive FIFO0 overfull</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFF0</name>
|
|
<description>Receive FIFO0 full</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFL0</name>
|
|
<description>Receive FIFO0 length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFO1</name>
|
|
<displayName>RFIFO1</displayName>
|
|
<description>Receive message FIFO1 register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFD1</name>
|
|
<description>Receive FIFO1 dequeue</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFO1</name>
|
|
<description>Receive FIFO1 overfull</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFF1</name>
|
|
<description>Receive FIFO1 full</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFL1</name>
|
|
<description>Receive FIFO1 length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<displayName>INTEN</displayName>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLPWIE</name>
|
|
<description>Sleep working interrupt enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIE</name>
|
|
<description>Wakeup interrupt enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRNIE</name>
|
|
<description>Error number interrupt enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOIE</name>
|
|
<description>Bus-off interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERRIE</name>
|
|
<description>Passive error interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WERRIE</name>
|
|
<description>Warning error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFOIE1</name>
|
|
<description>Receive FIFO1 overfull interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFFIE1</name>
|
|
<description>Receive FIFO1 full interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFNEIE1</name>
|
|
<description>Receive FIFO1 not empty interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFOIE0</name>
|
|
<description>Receive FIFO0 overfull interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFFIE0</name>
|
|
<description>Receive FIFO0 full interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFNEIE0</name>
|
|
<description>Receive FIFO0 not empty interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMEIE</name>
|
|
<description>Transmit mailbox empty interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ERR</name>
|
|
<displayName>ERR</displayName>
|
|
<description>Error register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RECNT</name>
|
|
<description>Receive Error Count defined
|
|
by the CAN standard</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TECNT</name>
|
|
<description>Transmit Error Count defined
|
|
by the CAN standard</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRN</name>
|
|
<description>Error number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOERR</name>
|
|
<description>Bus-off error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Passive error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WERR</name>
|
|
<description>Warning error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BT</name>
|
|
<displayName>BT</displayName>
|
|
<description>Bit timing register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x01230000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCMOD</name>
|
|
<description>Silent communication mode</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCMOD</name>
|
|
<description>Loopback communication mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SJW</name>
|
|
<description>Resynchronization jump width</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Bit segment 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Bit segment 1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUADPSC</name>
|
|
<description>Baud rate prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMI0</name>
|
|
<displayName>TMI0</displayName>
|
|
<description>Transmit mailbox identifier register 0</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFID_EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT</name>
|
|
<description>Frame type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmit enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMP0</name>
|
|
<displayName>TMP0</displayName>
|
|
<description>Transmit mailbox property register 0</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Time stamp enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLENC</name>
|
|
<description>Data length code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA00</name>
|
|
<displayName>TMDATA00</displayName>
|
|
<description>Transmit mailbox data0 register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB3</name>
|
|
<description>Data byte 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB2</name>
|
|
<description>Data byte 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB1</name>
|
|
<description>Data byte 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB0</name>
|
|
<description>Data byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA10</name>
|
|
<displayName>TMDATA10</displayName>
|
|
<description>Transmit mailbox data1 register</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB7</name>
|
|
<description>Data byte 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB6</name>
|
|
<description>Data byte 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB5</name>
|
|
<description>Data byte 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB4</name>
|
|
<description>Data byte 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMI1</name>
|
|
<displayName>TMI1</displayName>
|
|
<description>Transmit mailbox identifier register 1</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFID_EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT</name>
|
|
<description>Frame type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmit enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMP1</name>
|
|
<displayName>TMP1</displayName>
|
|
<description>Transmit mailbox property register 1</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Time stamp enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLENC</name>
|
|
<description>Data length code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA01</name>
|
|
<displayName>TMDATA01</displayName>
|
|
<description>Transmit mailbox data0 register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB3</name>
|
|
<description>Data byte 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB2</name>
|
|
<description>Data byte 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB1</name>
|
|
<description>Data byte 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB0</name>
|
|
<description>Data byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA11</name>
|
|
<displayName>TMDATA11</displayName>
|
|
<description>Transmit mailbox data1 register</description>
|
|
<addressOffset>0x19C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB7</name>
|
|
<description>Data byte 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB6</name>
|
|
<description>Data byte 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB5</name>
|
|
<description>Data byte 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB4</name>
|
|
<description>Data byte 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMI2</name>
|
|
<displayName>TMI2</displayName>
|
|
<description>Transmit mailbox identifier register 2</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFID_EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT</name>
|
|
<description>Frame type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmit enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMP2</name>
|
|
<displayName>TMP2</displayName>
|
|
<description>Transmit mailbox property register 2</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Time stamp enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLENC</name>
|
|
<description>Data length code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA02</name>
|
|
<displayName>TMDATA02</displayName>
|
|
<description>Transmit mailbox data0 register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB3</name>
|
|
<description>Data byte 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB2</name>
|
|
<description>Data byte 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB1</name>
|
|
<description>Data byte 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB0</name>
|
|
<description>Data byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMDATA12</name>
|
|
<displayName>TMDATA12</displayName>
|
|
<description>Transmit mailbox data1 register</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB7</name>
|
|
<description>Data byte 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB6</name>
|
|
<description>Data byte 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB5</name>
|
|
<description>Data byte 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB4</name>
|
|
<description>Data byte 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMI0</name>
|
|
<displayName>RFIFOMI0</displayName>
|
|
<description>Receive FIFO mailbox identifier register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFID_EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT</name>
|
|
<description>Frame type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMP0</name>
|
|
<displayName>RFIFOMP0</displayName>
|
|
<description>Receive FIFO0 mailbox property register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FI</name>
|
|
<description>Filtering index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLENC</name>
|
|
<description>Data length code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMDATA00</name>
|
|
<displayName>RFIFOMDATA00</displayName>
|
|
<description>Receive FIFO0 mailbox data0 register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB3</name>
|
|
<description>Data byte 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB2</name>
|
|
<description>Data byte 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB1</name>
|
|
<description>Data byte 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB0</name>
|
|
<description>Data byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMDATA10</name>
|
|
<displayName>RFIFOMDATA10</displayName>
|
|
<description>Receive FIFO0 mailbox data1 register</description>
|
|
<addressOffset>0x1BC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB7</name>
|
|
<description>Data byte 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB6</name>
|
|
<description>Data byte 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB5</name>
|
|
<description>Data byte 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB4</name>
|
|
<description>Data byte 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMI1</name>
|
|
<displayName>RFIFOMI1</displayName>
|
|
<description>Receive FIFO1 mailbox identifier register</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SFID_EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFID</name>
|
|
<description>The frame identifier</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT</name>
|
|
<description>Frame type</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMP1</name>
|
|
<displayName>RFIFOMP1</displayName>
|
|
<description>Receive FIFO1 mailbox property register</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FI</name>
|
|
<description>Filtering index</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLENC</name>
|
|
<description>Data length code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMDATA01</name>
|
|
<displayName>RFIFOMDATA01</displayName>
|
|
<description>Receive FIFO1 mailbox data0 register</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB3</name>
|
|
<description>Data byte 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB2</name>
|
|
<description>Data byte 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB1</name>
|
|
<description>Data byte 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB0</name>
|
|
<description>Data byte 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RFIFOMDATA11</name>
|
|
<displayName>RFIFOMDATA11</displayName>
|
|
<description>Receive FIFO1 mailbox data1 register</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DB7</name>
|
|
<description>Data byte 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB6</name>
|
|
<description>Data byte 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB5</name>
|
|
<description>Data byte 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DB4</name>
|
|
<description>Data byte 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTL</name>
|
|
<displayName>FCTL</displayName>
|
|
<description>Filter control register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2A1C0E01</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HBC1F</name>
|
|
<description>Header bank of CAN1 filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLD</name>
|
|
<description>Filter lock disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMCFG</name>
|
|
<displayName>FMCFG</displayName>
|
|
<description>Filter mode configuration register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FMOD27</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD26</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD25</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD24</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD23</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD22</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD21</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD20</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD19</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD18</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD17</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD16</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD15</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD14</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD13</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD12</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD11</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD10</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD9</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD8</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD7</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD6</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD5</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD4</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD3</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD2</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD1</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMOD0</name>
|
|
<description>Filter mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FSCFG</name>
|
|
<displayName>FSCFG</displayName>
|
|
<description>Filter scale configuration register</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FS0</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS1</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS2</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS3</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS4</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS5</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS6</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS7</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS8</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS9</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS10</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS11</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS12</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS13</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS14</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS15</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS16</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS17</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS18</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS19</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS20</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS21</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS22</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS23</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS24</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS25</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS26</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS27</name>
|
|
<description>Filter scale configuration</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAFIFO</name>
|
|
<displayName>FAFIFO</displayName>
|
|
<description>Filter associated FIFO register</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FAF0</name>
|
|
<description>Filter 0 associated with FIFO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF1</name>
|
|
<description>Filter 1 associated with FIFO</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF2</name>
|
|
<description>Filter 2 associated with FIFO</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF3</name>
|
|
<description>Filter 3 associated with FIFO</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF4</name>
|
|
<description>Filter 4 associated with FIFO</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF5</name>
|
|
<description>Filter 5 associated with FIFO</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF6</name>
|
|
<description>Filter 6 associated with FIFO</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF7</name>
|
|
<description>Filter 7 associated with FIFO</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF8</name>
|
|
<description>Filter 8 associated with FIFO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF9</name>
|
|
<description>Filter 9 associated with FIFO</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF10</name>
|
|
<description>Filter 10 associated with FIFO</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF11</name>
|
|
<description>Filter 11 associated with FIFO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF12</name>
|
|
<description>Filter 12 associated with FIFO</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF13</name>
|
|
<description>Filter 13 associated with FIFO</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF14</name>
|
|
<description>Filter 14 associated with FIFO</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF15</name>
|
|
<description>Filter 15 associated with FIFO</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF16</name>
|
|
<description>Filter 16 associated with FIFO</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF17</name>
|
|
<description>Filter 17 associated with FIFO</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF18</name>
|
|
<description>Filter 18 associated with FIFO</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF19</name>
|
|
<description>Filter 19 associated with FIFO</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF20</name>
|
|
<description>Filter 20 associated with FIFO</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF21</name>
|
|
<description>Filter 21 associated with FIFO</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF22</name>
|
|
<description>Filter 22 associated with FIFO</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF23</name>
|
|
<description>Filter 23 associated with FIFO</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF24</name>
|
|
<description>Filter 24 associated with FIFO</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF25</name>
|
|
<description>Filter 25 associated with FIFO</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF26</name>
|
|
<description>Filter 26 associated with FIFO</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAF27</name>
|
|
<description>Filter 27 associated with FIFO</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FW</name>
|
|
<displayName>FW</displayName>
|
|
<description>Filter working register</description>
|
|
<addressOffset>0x21C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FW0</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW1</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW2</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW3</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW4</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW5</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW6</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW7</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW8</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW9</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW10</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW11</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW12</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW13</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW14</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW15</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW16</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW17</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW18</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW19</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW20</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW21</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW22</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW23</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW24</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW25</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW26</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FW27</name>
|
|
<description>Filter working</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F0DATA0</name>
|
|
<displayName>F0DATA0</displayName>
|
|
<description>Filter 0 data 0 register</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F0DATA1</name>
|
|
<displayName>F0DATA1</displayName>
|
|
<description>Filter 0 data 1 register</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F1DATA0</name>
|
|
<displayName>F1DATA0</displayName>
|
|
<description>Filter 1 data 0 register</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F1DATA1</name>
|
|
<displayName>F1DATA1</displayName>
|
|
<description>Filter 1 data 1 register</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F2DATA0</name>
|
|
<displayName>F2DATA0</displayName>
|
|
<description>Filter 2 data 0 register</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F2DATA1</name>
|
|
<displayName>F2DATA1</displayName>
|
|
<description>Filter 2 data 1 register</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F3DATA0</name>
|
|
<displayName>F3DATA0</displayName>
|
|
<description>Filter 3 data 0 register</description>
|
|
<addressOffset>0x258</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F3DATA1</name>
|
|
<displayName>F3DATA1</displayName>
|
|
<description>Filter 3 data 1 register</description>
|
|
<addressOffset>0x25C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F4DATA0</name>
|
|
<displayName>F4DATA0</displayName>
|
|
<description>Filter 4 data 0 register</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F4DATA1</name>
|
|
<displayName>F4DATA1</displayName>
|
|
<description>Filter 4 data 1 register</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F5DATA0</name>
|
|
<displayName>F5DATA0</displayName>
|
|
<description>Filter 5 data 0 register</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F5DATA1</name>
|
|
<displayName>F5DATA1</displayName>
|
|
<description>Filter 5 data 1 register</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F6DATA0</name>
|
|
<displayName>F6DATA0</displayName>
|
|
<description>Filter 6 data 0 register</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F6DATA1</name>
|
|
<displayName>F6DATA1</displayName>
|
|
<description>Filter 6 data 1 register</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F7DATA0</name>
|
|
<displayName>F7DATA0</displayName>
|
|
<description>Filter 7 data 0 register</description>
|
|
<addressOffset>0x278</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F7DATA1</name>
|
|
<displayName>F7DATA1</displayName>
|
|
<description>Filter 7 data 1 register</description>
|
|
<addressOffset>0x27C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F8DATA0</name>
|
|
<displayName>F8DATA0</displayName>
|
|
<description>Filter 8 data 0 register</description>
|
|
<addressOffset>0x280</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F8DATA1</name>
|
|
<displayName>F8DATA1</displayName>
|
|
<description>Filter 8 data 1 register</description>
|
|
<addressOffset>0x284</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F9DATA0</name>
|
|
<displayName>F9DATA0</displayName>
|
|
<description>Filter 9 data 0 register</description>
|
|
<addressOffset>0x288</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F9DATA1</name>
|
|
<displayName>F9DATA1</displayName>
|
|
<description>Filter 9 data 1 register</description>
|
|
<addressOffset>0x28C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F10DATA0</name>
|
|
<displayName>F10DATA0</displayName>
|
|
<description>Filter 10 data 0 register</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F10DATA1</name>
|
|
<displayName>F10DATA1</displayName>
|
|
<description>Filter 10 data 1 register</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F11DATA0</name>
|
|
<displayName>F11DATA0</displayName>
|
|
<description>Filter 11 data 0 register</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F11DATA1</name>
|
|
<displayName>F11DATA1</displayName>
|
|
<description>Filter 11 data 1 register</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F12DATA0</name>
|
|
<displayName>F12DATA0</displayName>
|
|
<description>Filter 12 data 0 register</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F12DATA1</name>
|
|
<displayName>F12DATA1</displayName>
|
|
<description>Filter 12 data 1 register</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F13DATA0</name>
|
|
<displayName>F13DATA0</displayName>
|
|
<description>Filter 13 data 0 register</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F13DATA1</name>
|
|
<displayName>F13DATA1</displayName>
|
|
<description>Filter 13 data 1 register</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F14DATA0</name>
|
|
<displayName>F14DATA0</displayName>
|
|
<description>Filter 14 data 0 register</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F14DATA1</name>
|
|
<displayName>F14DATA1</displayName>
|
|
<description>Filter 14 data 1 register</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F15DATA0</name>
|
|
<displayName>F15DATA0</displayName>
|
|
<description>Filter 15 data 0 register</description>
|
|
<addressOffset>0x2B8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F15DATA1</name>
|
|
<displayName>F15DATA1</displayName>
|
|
<description>Filter 15 data 1 register</description>
|
|
<addressOffset>0x2BC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F16DATA0</name>
|
|
<displayName>F16DATA0</displayName>
|
|
<description>Filter 16 data 0 register</description>
|
|
<addressOffset>0x2C0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F16DATA1</name>
|
|
<displayName>F16DATA1</displayName>
|
|
<description>Filter 16 data 1 register</description>
|
|
<addressOffset>0x2C4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F17DATA0</name>
|
|
<displayName>F17DATA0</displayName>
|
|
<description>Filter 17 data 0 register</description>
|
|
<addressOffset>0x2C8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F17DATA1</name>
|
|
<displayName>F17DATA1</displayName>
|
|
<description>Filter 17 data 1 register</description>
|
|
<addressOffset>0x2CC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F18DATA0</name>
|
|
<displayName>F18DATA0</displayName>
|
|
<description>Filter 18 data 0 register</description>
|
|
<addressOffset>0x2D0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F18DATA1</name>
|
|
<displayName>F18DATA1</displayName>
|
|
<description>Filter 18 data 1 register</description>
|
|
<addressOffset>0x2D4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F19DATA0</name>
|
|
<displayName>F19DATA0</displayName>
|
|
<description>Filter 19 data 0 register</description>
|
|
<addressOffset>0x2D8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F19DATA1</name>
|
|
<displayName>F19DATA1</displayName>
|
|
<description>Filter 19 data 1 register</description>
|
|
<addressOffset>0x2DC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F20DATA0</name>
|
|
<displayName>F20DATA0</displayName>
|
|
<description>Filter 20 data 0 register</description>
|
|
<addressOffset>0x2E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F20DATA1</name>
|
|
<displayName>F20DATA1</displayName>
|
|
<description>Filter 20 data 1 register</description>
|
|
<addressOffset>0x2E4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F21DATA0</name>
|
|
<displayName>F21DATA0</displayName>
|
|
<description>Filter 21 data 0 register</description>
|
|
<addressOffset>0x2E8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F21DATA1</name>
|
|
<displayName>F21DATA1</displayName>
|
|
<description>Filter 21 data 1 register</description>
|
|
<addressOffset>0x2EC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F22DATA0</name>
|
|
<displayName>F22DATA0</displayName>
|
|
<description>Filter 22 data 0 register</description>
|
|
<addressOffset>0x2F0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F22DATA1</name>
|
|
<displayName>F22DATA1</displayName>
|
|
<description>Filter 22 data 1 register</description>
|
|
<addressOffset>0x2F4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F23DATA0</name>
|
|
<displayName>F23DATA0</displayName>
|
|
<description>Filter 23 data 0 register</description>
|
|
<addressOffset>0x2F8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F23DATA1</name>
|
|
<displayName>F23DATA1</displayName>
|
|
<description>Filter 23 data 1 register</description>
|
|
<addressOffset>0x2FC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F24DATA0</name>
|
|
<displayName>F24DATA0</displayName>
|
|
<description>Filter 24 data 0 register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F24DATA1</name>
|
|
<displayName>F24DATA1</displayName>
|
|
<description>Filter 24 data 1 register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F25DATA0</name>
|
|
<displayName>F25DATA0</displayName>
|
|
<description>Filter 25 data 0 register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F25DATA1</name>
|
|
<displayName>F25DATA1</displayName>
|
|
<description>Filter 25 data 1 register</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F26DATA0</name>
|
|
<displayName>F26DATA0</displayName>
|
|
<description>Filter 26 data 0 register</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F26DATA1</name>
|
|
<displayName>F26DATA1</displayName>
|
|
<description>Filter 26 data 1 register</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F27DATA0</name>
|
|
<displayName>F27DATA0</displayName>
|
|
<description>Filter 27 data 0 register</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>F27DATA1</name>
|
|
<displayName>F27DATA1</displayName>
|
|
<description>Filter 27 data 1 register</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD0</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD1</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD2</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD3</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD4</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD5</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD6</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD7</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD8</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD9</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD10</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD11</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD12</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD13</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD14</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD15</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD16</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD17</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD18</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD19</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD20</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD21</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD22</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD23</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD24</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD25</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD26</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD27</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD28</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD29</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD30</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FD31</name>
|
|
<description>Filter bits</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="CAN0">
|
|
<name>CAN1</name>
|
|
<baseAddress>0x40006800</baseAddress>
|
|
<interrupt>
|
|
<name>CAN1_TX</name>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN1_RX0</name>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN1_RX1</name>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CAN1_EWMC</name>
|
|
<value>66</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>cyclic redundancy check calculation unit</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>CRC calculation result bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDATA</name>
|
|
<displayName>FDATA</displayName>
|
|
<description>Free data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FDATA</name>
|
|
<description>Free Data Register bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CTC</name>
|
|
<description>Clock trim controller</description>
|
|
<groupName>CTC</groupName>
|
|
<baseAddress>0x40006C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCU_CTC</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIE</name>
|
|
<description>Clock trim ok interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIE</name>
|
|
<description>Clock trim warning interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EREFIE</name>
|
|
<description>EREFIF interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTEN</name>
|
|
<description>CTC counter enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRIM</name>
|
|
<description>Hardware automatically trim mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWREFPUL</name>
|
|
<description>Software reference source sync pulse</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMVALUE</name>
|
|
<description>IRC48M trim value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2022BB7F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REFPOL</name>
|
|
<description>Reference signal source polarity</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBSOFSEL</name>
|
|
<description>SOF signal selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>Reference signal source selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFPSC</name>
|
|
<description>Reference signal source prescaler</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKLIM</name>
|
|
<description>Clock trim base limit value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RLVALUE</name>
|
|
<description>CTC counter reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIF</name>
|
|
<description>Clock trim OK interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIF</name>
|
|
<description>Clock trim warning interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIF</name>
|
|
<description>Error interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EREFIF</name>
|
|
<description>Expect reference interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKERR</name>
|
|
<description>Clock trim error bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFMISS</name>
|
|
<description>Reference sync pulse miss</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMERR</name>
|
|
<description>Trim value error bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFDIR</name>
|
|
<description>CTC trim counter direction when reference sync pulse</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCAP</name>
|
|
<description>CTC counter capture when reference sync pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC</name>
|
|
<displayName>INTC</displayName>
|
|
<description>Interrupt clear register </description>
|
|
<addressOffset>0x0c</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIC</name>
|
|
<description>CKOKIF interrupt clear bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIC</name>
|
|
<description>CKWARNIF interrupt clear bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIC</name>
|
|
<description>ERRIF interrupt clear bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EREFIC</name>
|
|
<description>EREFIF interrupt clear bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>Digital-to-analog converter</description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x40007400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER5_DAC</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEN0</name>
|
|
<description>DAC0 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBOFF0</name>
|
|
<description>DAC0 output buffer turn off</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN0</name>
|
|
<description>DAC0 trigger enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTSEL0</name>
|
|
<description>DAC0 trigger selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWM0</name>
|
|
<description>DAC0 noise wave mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWBW0</name>
|
|
<description>DAC0 noise wave bit width</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDMAEN0</name>
|
|
<description>DAC0 DMA enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDUDRIE0</name>
|
|
<description>DAC0 DMA Underrun Interrupt
|
|
enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEN1</name>
|
|
<description>DAC1 enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBOFF1</name>
|
|
<description>DAC1 output buffer turn off</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN1</name>
|
|
<description>DAC1 trigger enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTSEL1</name>
|
|
<description>DAC1 trigger selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWM1</name>
|
|
<description>DAC1 noise wave mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DWBW1</name>
|
|
<description>DAC1 noise wave bit width</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDMAEN1</name>
|
|
<description>DAC1 DMA enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDUDRIE1</name>
|
|
<description>DAC1 DMA Underrun Interrupt enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWT</name>
|
|
<displayName>SWT</displayName>
|
|
<description>software trigger register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTR0</name>
|
|
<description>DAC0 software trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTR1</name>
|
|
<description>DAC1 software trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC0_R12DH</name>
|
|
<displayName>DAC0_R12DH</displayName>
|
|
<description>DAC0 12-bit right-aligned data holding register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 12-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC0_L12DH</name>
|
|
<displayName>DAC0_L12DH</displayName>
|
|
<description>DAC0 12-bit left-aligned data holding register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 12-bit left-aligned
|
|
data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC0_R8DH</name>
|
|
<displayName>DAC0_R8DH</displayName>
|
|
<description>DAC0 8-bit right aligned data holding
|
|
register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 8-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC1_R12DH</name>
|
|
<displayName>DAC1_R12DH</displayName>
|
|
<description>DAC1 12-bit right-aligned data holding
|
|
register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 12-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC1_L12DH</name>
|
|
<displayName>DAC1_L12DH</displayName>
|
|
<description>DAC1 12-bit left aligned data holding
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 12-bit left-aligned
|
|
data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC1_R8DH</name>
|
|
<displayName>DAC1_R8DH</displayName>
|
|
<description>DAC1 8-bit right aligned data holding
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 8-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACC_R12DH</name>
|
|
<displayName>DACC_R12DH</displayName>
|
|
<description>DAC concurrent mode 12-bit right-aligned data holding
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 12-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 12-bit right-aligned
|
|
data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACC_L12DH</name>
|
|
<displayName>DACC_L12DH</displayName>
|
|
<description>DAC concurrent mode 12-bit left aligned data holding
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 12-bit left-aligned
|
|
data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 12-bit left-aligned
|
|
data</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DACC_R8DH</name>
|
|
<displayName>DACC_R8DH</displayName>
|
|
<description>DAC concurrent mode 8-bit right aligned data holding
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DH</name>
|
|
<description>DAC0 8-bit right-aligned
|
|
data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1_DH</name>
|
|
<description>DAC1 8-bit right-aligned
|
|
data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC0_DO</name>
|
|
<displayName>DAC0_DO</displayName>
|
|
<description>DAC0 data output register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC0_DO</name>
|
|
<description>DAC0 data output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC1_DO</name>
|
|
<displayName>DAC1_DO</displayName>
|
|
<description>DAC1 data output register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1_DO</name>
|
|
<description>DAC1 data output</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DDUDR0</name>
|
|
<description>DAC0 DMA underrun
|
|
flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDUDR1</name>
|
|
<description>DAC1 DMA underrun
|
|
flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DBG</name>
|
|
<description>Debug support</description>
|
|
<groupName>DBG</groupName>
|
|
<baseAddress>0xE0042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ID</name>
|
|
<displayName>ID</displayName>
|
|
<description>ID code register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID_CODE</name>
|
|
<description>DBG ID code register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control register 0</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLP_HOLD</name>
|
|
<description>Sleep mode hold register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSLP_HOLD</name>
|
|
<description>Deep-sleep mode hold register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STB_HOLD</name>
|
|
<description>Standby mode hold register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_IOEN</name>
|
|
<description>Trace pin allocation enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_MODE</name>
|
|
<description>Trace pin allocation mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER1_HOLD</name>
|
|
<description>TIMER 1 hold register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2_HOLD</name>
|
|
<description>TIMER 2 hold register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3_HOLD</name>
|
|
<description>TIMER 3 hold register</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER4_HOLD</name>
|
|
<description>TIMER 4 hold register</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER5_HOLD</name>
|
|
<description>TIMER 5 hold register</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER6_HOLD</name>
|
|
<description>TIMER 6 hold register</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER11_HOLD</name>
|
|
<description>TIMER 11 hold register</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER12_HOLD</name>
|
|
<description>TIMER 12 hold register</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER13_HOLD</name>
|
|
<description>TIMER 13 hold register</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTC_HOLD</name>
|
|
<description>RTC hold register</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGT_HOLD</name>
|
|
<description>WWDGT hold register</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FWDGT_HOLD</name>
|
|
<description>FWDGT hold register</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C0_HOLD</name>
|
|
<description>I2C0 hold register</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1_HOLD</name>
|
|
<description>I2C1 hold register</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2_HOLD</name>
|
|
<description>I2C2 hold register</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN0_HOLD</name>
|
|
<description>CAN0 hold register</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN1_HOLD</name>
|
|
<description>CAN1 hold register</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0_HOLD</name>
|
|
<description>TIMER 0 hold register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER7_HOLD</name>
|
|
<description>TIMER 7 hold register</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER8_HOLD</name>
|
|
<description>TIMER 8 hold register</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER9_HOLD</name>
|
|
<description>TIMER 9 hold register</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER10_HOLD</name>
|
|
<description>TIMER 10 hold register</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DCI</name>
|
|
<description>Digital Camera Interface</description>
|
|
<groupName>DCI</groupName>
|
|
<baseAddress>0x50050000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DCI</name>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCIEN</name>
|
|
<description>DCI Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCIF</name>
|
|
<description>Digital camera interface format</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FR</name>
|
|
<description>Frame rate</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS</name>
|
|
<description>Vertical Polarity Selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPS</name>
|
|
<description>Horizontal Polarity Selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKS</name>
|
|
<description>Clock Polarity Selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESM</name>
|
|
<description>Embedded Synchronous Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JM</name>
|
|
<description>JPEG mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDEN</name>
|
|
<description>Window Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SNAP</name>
|
|
<description>Snapshot mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAP</name>
|
|
<description>Capture Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT0</name>
|
|
<displayName>STAT0</displayName>
|
|
<description>Status register 0</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FV</name>
|
|
<description>FIFO Valid</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VS</name>
|
|
<description>VS line status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>HS line status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT1</name>
|
|
<displayName>STAT1</displayName>
|
|
<description>Status register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ELF</name>
|
|
<description>End of Line Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSF</name>
|
|
<description>Vsync Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESEF</name>
|
|
<description>Embedded Synchronous Error Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRF</name>
|
|
<description>FIFO Overrun Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFF</name>
|
|
<description>End of Frame Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<displayName>INTEN</displayName>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ELIE</name>
|
|
<description>End of Line Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSIE</name>
|
|
<description>Vsync Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESEIE</name>
|
|
<description>Embedded Synchronous Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRIE</name>
|
|
<description>FIFO Overrun Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFIE</name>
|
|
<description>End of Frame Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>Interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ELIF</name>
|
|
<description>End of Line Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSIF</name>
|
|
<description>Vsync Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESEIF</name>
|
|
<description>Embedded Synchronous Error Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRIF</name>
|
|
<description>FIFO Overrun Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFIF</name>
|
|
<description>End of Frame Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC</name>
|
|
<displayName>INTC</displayName>
|
|
<description>Interrupt flag clear register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ELFC</name>
|
|
<description>End of Line Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSFC</name>
|
|
<description>Vsync flag clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESEFC</name>
|
|
<description>Clear embedded synchronous Error Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRFC</name>
|
|
<description>Clear FIFO Overrun Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFFC</name>
|
|
<description>Clear End of Frame Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SC</name>
|
|
<displayName>SC</displayName>
|
|
<description>Synchronization codes register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Frame End Code in Embedded Synchronous Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LE</name>
|
|
<description>Line End Code in Embedded Synchronous Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LS</name>
|
|
<description>Line Start Code in Embedded Synchronous Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FS</name>
|
|
<description>Frame Start Code in Embedded Synchronous Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCUMSK</name>
|
|
<displayName>SCUMSK</displayName>
|
|
<description>Synchronization codes unmask register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEM</name>
|
|
<description>Frame End Code unMask Bits in Embedded Synchronous Mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEM</name>
|
|
<description>Line End Code unMask Bits in Embedded Synchronous Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSM</name>
|
|
<description> Line Start Code unMask Bits in Embedded Synchronous Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSM</name>
|
|
<description> Frame Start Code unMask Bits in Embedded Synchronous Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CWSPOS</name>
|
|
<displayName>CWSPOS</displayName>
|
|
<description>Cropping window start position register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WVSP</name>
|
|
<description>Window Vertical Start Position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WHSP</name>
|
|
<description>Window Horizontal Start Position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CWSZ</name>
|
|
<displayName>CWSZ</displayName>
|
|
<description>Cropping window size register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WVSZ</name>
|
|
<description>Window Vertical Size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WHSZ</name>
|
|
<description>Window Horizontal Size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>DATA register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DT3</name>
|
|
<description>Pixel Data 3 </description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT2</name>
|
|
<description>Pixel Data 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT1</name>
|
|
<description>Pixel Data 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT0</name>
|
|
<description>Pixel Data 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA0</name>
|
|
<description>DMA controller</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x40026000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA0_Channel0</name>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel1</name>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel2</name>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel3</name>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel4</name>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel5</name>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel6</name>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA0_Channel7</name>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTF0</name>
|
|
<displayName>INTF0</displayName>
|
|
<description>Interrupt flag register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEEIF0</name>
|
|
<description>FIFO error and exception of channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF0</name>
|
|
<description>Single data mode exception of channel 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF0</name>
|
|
<description>Transfer access error flag of channel 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF0</name>
|
|
<description>Half transfer finish flag of channel 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF0</name>
|
|
<description>Full Transfer finish flag of channel 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF1</name>
|
|
<description>FIFO error and exception of channel 1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF1</name>
|
|
<description>Single data mode exception of channel 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF1</name>
|
|
<description>Transfer access error flag of channel 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF1</name>
|
|
<description>Half transfer finish flag of channel 1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF1</name>
|
|
<description>Full Transfer finish flag of channel 1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF2</name>
|
|
<description>FIFO error and exception of channel 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF2</name>
|
|
<description>Single data mode exception of channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF2</name>
|
|
<description>Transfer access error flag of channel 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF2</name>
|
|
<description>Half transfer finish flag of channel 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF2</name>
|
|
<description>Full Transfer finish flag of channel 2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF3</name>
|
|
<description>FIFO error and exception of channel 3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF3</name>
|
|
<description>Single data mode exception of channel 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF3</name>
|
|
<description>Transfer access error flag of channel 3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF3</name>
|
|
<description>Half transfer finish flag of channel 3</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF3</name>
|
|
<description>Full Transfer finish flag of channel 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF1</name>
|
|
<displayName>INTF1</displayName>
|
|
<description>Interrupt flag register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEEIF4</name>
|
|
<description>FIFO error and exception of channel 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF4</name>
|
|
<description>Single data mode exception of channel 4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF4</name>
|
|
<description>Transfer access error flag of channel 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF4</name>
|
|
<description>Half transfer finish flag of channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF4</name>
|
|
<description>Full Transfer finish flag of channel 4</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF5</name>
|
|
<description>FIFO error and exception of channel 5</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF5</name>
|
|
<description>Single data mode exception of channel 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF5</name>
|
|
<description>Transfer access error flag of channel 5</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF5</name>
|
|
<description>Half transfer finish flag of channel 5</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF5</name>
|
|
<description>Full Transfer finish flag of channel 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF6</name>
|
|
<description>FIFO error and exception of channel 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF6</name>
|
|
<description>Single data mode exception of channel 6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF6</name>
|
|
<description>Transfer access error flag of channel 6</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF6</name>
|
|
<description>Half transfer finish flag of channel 6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF6</name>
|
|
<description>Full Transfer finish flag of channel 6</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIF7</name>
|
|
<description>FIFO error and exception of channel 7</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIF7</name>
|
|
<description>Single data mode exception of channel 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIF7</name>
|
|
<description>Transfer access error flag of channel 7</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIF7</name>
|
|
<description>Half transfer finish flag of channel 7</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF7</name>
|
|
<description>Full Transfer finish flag of channel 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC0</name>
|
|
<displayName>INTC0</displayName>
|
|
<description>Interrupt flag clear register 0</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEEIFC0</name>
|
|
<description>Clear bit for FIFO error and exception of channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC0</name>
|
|
<description>Clear bit for single data mode exception of channel 0</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC0</name>
|
|
<description>Clear bit for transfer access error flag of channel 0</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC0</name>
|
|
<description>Clear bit for half transfer finish flag of channel 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC0</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 0</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC1</name>
|
|
<description>Clear bit for FIFO error and exception of channel 1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC1</name>
|
|
<description>Clear bit for single data mode exception of channel 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC1</name>
|
|
<description>Clear bit for transfer access error flag of channel 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC1</name>
|
|
<description>Clear bit for half transfer finish flag of channel 1</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC1</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC2</name>
|
|
<description>Clear bit for FIFO error and exception of channel 2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC2</name>
|
|
<description>Clear bit for single data mode exception of channel 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC2</name>
|
|
<description>Clear bit for transfer access error flag of channel 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC2</name>
|
|
<description>Clear bit for half transfer finish flag of channel 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC2</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC3</name>
|
|
<description>Clear bit for FIFO error and exception of channel 3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC3</name>
|
|
<description>Clear bit for single data mode exception of channel 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC3</name>
|
|
<description>Clear bit for transfer access error flag of channel 3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC3</name>
|
|
<description>Clear bit for half transfer finish flag of channel 3</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC3</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 3</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC1</name>
|
|
<displayName>INTC1</displayName>
|
|
<description>Interrupt flag clear register 1</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEEIFC4</name>
|
|
<description>Clear bit for FIFO error and exception of channel 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC4</name>
|
|
<description>Clear bit for single data mode exception of channel 4</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC4</name>
|
|
<description>Clear bit for transfer access error flag of channel 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC4</name>
|
|
<description>Clear bit for half transfer finish flag of channel 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC4</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 4</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC5</name>
|
|
<description>Clear bit for FIFO error and exception of channel 5</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC5</name>
|
|
<description>Clear bit for single data mode exception of channel 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC5</name>
|
|
<description>Clear bit for transfer access error flag of channel 5</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC5</name>
|
|
<description>Clear bit for half transfer finish flag of channel 5</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC5</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 5</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC6</name>
|
|
<description>Clear bit for FIFO error and exception of channel 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC6</name>
|
|
<description>Clear bit for single data mode exception of channel 6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC6</name>
|
|
<description>Clear bit for transfer access error flag of channel 6</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC6</name>
|
|
<description>Clear bit for half transfer finish flag of channel 6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC6</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 6</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIFC7</name>
|
|
<description>Clear bit for FIFO error and exception of channel 7</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIFC7</name>
|
|
<description>Clear bit for single data mode exception of channel 7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIFC7</name>
|
|
<description>Clear bit for transfer access error flag of channel 7</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIFC7</name>
|
|
<description>Clear bit for half transfer finish flag of channel 7</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIFC7</name>
|
|
<description>Clear bit for Full transfer finish flag of channel 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CTL</name>
|
|
<displayName>CH0CTL</displayName>
|
|
<description>Channel 0 control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CNT</name>
|
|
<displayName>CH0CNT</displayName>
|
|
<description>Channel 0 counter register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0PADDR</name>
|
|
<displayName>CH0PADDR</displayName>
|
|
<description>Channel 0 peripheral base address register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0M0ADDR</name>
|
|
<displayName>CH0M0ADDR</displayName>
|
|
<description>Channel 0 memory 0 base address register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0M1ADDR</name>
|
|
<displayName>CH0M1ADDR</displayName>
|
|
<description>Channel 0 memory 1 base address register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0FCTL</name>
|
|
<displayName>CH0FCTL</displayName>
|
|
<description>Channel 0 FIFO control register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CTL</name>
|
|
<displayName>CH1CTL</displayName>
|
|
<description>Channel 1 control register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CNT</name>
|
|
<displayName>CH1CNT</displayName>
|
|
<description>Channel 1 counter register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1PADDR</name>
|
|
<displayName>CH1PADDR</displayName>
|
|
<description>Channel 1 peripheral base address register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1M0ADDR</name>
|
|
<displayName>CH1M0ADDR</displayName>
|
|
<description>Channel 1 memory 0 base address register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1M1ADDR</name>
|
|
<displayName>CH1M1ADDR</displayName>
|
|
<description>Channel 1 memory 1 base address register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1FCTL</name>
|
|
<displayName>CH1FCTL</displayName>
|
|
<description>Channel 1 FIFO control register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2CTL</name>
|
|
<displayName>CH2CTL</displayName>
|
|
<description>Channel 2 control register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2CNT</name>
|
|
<displayName>CH2CNT</displayName>
|
|
<description>Channel 2 counter register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2PADDR</name>
|
|
<displayName>CH2PADDR</displayName>
|
|
<description>Channel 2 peripheral base address register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2M0ADDR</name>
|
|
<displayName>CH2M0ADDR</displayName>
|
|
<description>Channel 2 memory 0 base address register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2M1ADDR</name>
|
|
<displayName>CH2M1ADDR</displayName>
|
|
<description>Channel 2 memory 1 base address register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2FCTL</name>
|
|
<displayName>CH2FCTL</displayName>
|
|
<description>Channel 2 FIFO control register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3CTL</name>
|
|
<displayName>CH3CTL</displayName>
|
|
<description>Channel 3 control register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3CNT</name>
|
|
<displayName>CH3CNT</displayName>
|
|
<description>Channel 3 counter register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3PADDR</name>
|
|
<displayName>CH3PADDR</displayName>
|
|
<description>Channel 3 peripheral base address register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3M0ADDR</name>
|
|
<displayName>CH3M0ADDR</displayName>
|
|
<description>Channel 3 memory 0 base address register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3M1ADDR</name>
|
|
<displayName>CH3M1ADDR</displayName>
|
|
<description>Channel 3 memory 1 base address register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3FCTL</name>
|
|
<displayName>CH3FCTL</displayName>
|
|
<description>Channel 3 FIFO control register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4CTL</name>
|
|
<displayName>CH4CTL</displayName>
|
|
<description>Channel 4 control register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4CNT</name>
|
|
<displayName>CH4CNT</displayName>
|
|
<description>Channel 4 counter register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4PADDR</name>
|
|
<displayName>CH4PADDR</displayName>
|
|
<description>Channel 4 peripheral base address register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4M0ADDR</name>
|
|
<displayName>CH4M0ADDR</displayName>
|
|
<description>Channel 4 memory 0 base address register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4M1ADDR</name>
|
|
<displayName>CH4M1ADDR</displayName>
|
|
<description>Channel 4 memory 1 base address register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH4FCTL</name>
|
|
<displayName>CH4FCTL</displayName>
|
|
<description>Channel 4 FIFO control register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5CTL</name>
|
|
<displayName>CH5CTL</displayName>
|
|
<description>Channel 5 control register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5CNT</name>
|
|
<displayName>CH5CNT</displayName>
|
|
<description>Channel 5 counter register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5PADDR</name>
|
|
<displayName>CH5PADDR</displayName>
|
|
<description>Channel 5 peripheral base address register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5M0ADDR</name>
|
|
<displayName>CH5M0ADDR</displayName>
|
|
<description>Channel 5 memory 0 base address register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5M1ADDR</name>
|
|
<displayName>CH5M1ADDR</displayName>
|
|
<description>Channel 5 memory 1 base address register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH5FCTL</name>
|
|
<displayName>CH5FCTL</displayName>
|
|
<description>Channel 5 FIFO control register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6CTL</name>
|
|
<displayName>CH6CTL</displayName>
|
|
<description>Channel 6 control register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6CNT</name>
|
|
<displayName>CH6CNT</displayName>
|
|
<description>Channel 6 counter register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6PADDR</name>
|
|
<displayName>CH6PADDR</displayName>
|
|
<description>Channel 6 peripheral base address register</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6M0ADDR</name>
|
|
<displayName>CH6M0ADDR</displayName>
|
|
<description>Channel 6 memory 0 base address register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6M1ADDR</name>
|
|
<displayName>CH6M1ADDR</displayName>
|
|
<description>Channel 6 memory 1 base address register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH6FCTL</name>
|
|
<displayName>CH6FCTL</displayName>
|
|
<description>Channel 6 FIFO control register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7CTL</name>
|
|
<displayName>CH7CTL</displayName>
|
|
<description>Channel 7 control register</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDEIE</name>
|
|
<description>Enable bit for single data mode exception interrupt</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for tranfer access error interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTFIE</name>
|
|
<description>Enable bit for half transfer finish interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCS</name>
|
|
<description>Transfer flow controller select</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TM</name>
|
|
<description>Transfer mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMEN</name>
|
|
<description>Circulation mode enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNAGA</name>
|
|
<description>Next address generation algorithm of peripheral</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNAGA</name>
|
|
<description>Next address generation algorithm of memory</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWIDTH</name>
|
|
<description>Transfer width of peripheral</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWIDTH</name>
|
|
<description>Transfer width of memory</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PAIF</name>
|
|
<description>Peripheral address increment fixed</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIO</name>
|
|
<description>Priority level</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBMEN</name>
|
|
<description>Switch-buffer mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBS</name>
|
|
<description>Memory buffer select</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBURST</name>
|
|
<description>Transfer burst type of peripheral</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MBURST</name>
|
|
<description>Transfer burst type of memory</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERIEN</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7CNT</name>
|
|
<displayName>CH7CNT</displayName>
|
|
<description>Channel 7 counter register</description>
|
|
<addressOffset>0xBC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Transfer counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7PADDR</name>
|
|
<displayName>CH7PADDR</displayName>
|
|
<description>Channel 7 peripheral base address register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Peripheral base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7M0ADDR</name>
|
|
<displayName>CH7M0ADDR</displayName>
|
|
<description>Channel 7 memory 0 base address register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M0ADDR</name>
|
|
<description>Memory 0 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7M1ADDR</name>
|
|
<displayName>CH7M1ADDR</displayName>
|
|
<description>Channel 7 memory 1 base address register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>M1ADDR</name>
|
|
<description>Memory 1 base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH7FCTL</name>
|
|
<displayName>CH7FCTL</displayName>
|
|
<description>Channel 7 FIFO control register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FCCV</name>
|
|
<description>FIFO counter critical value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMEN</name>
|
|
<description>Multi-data mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEEIE</name>
|
|
<description>Enable bit for FIFO error and exception interrupt</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMA0">
|
|
<name>DMA1</name>
|
|
<baseAddress>0x40026400</baseAddress>
|
|
<interrupt>
|
|
<name>DMA1_Channel0</name>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel1</name>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel2</name>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel3</name>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel4</name>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel5</name>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel6</name>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel7</name>
|
|
<value>70</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET_DMA</name>
|
|
<description>Ethernet: DMA controller operation</description>
|
|
<groupName>ENET</groupName>
|
|
<baseAddress>0x40029000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x60</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DMA_BCTL</name>
|
|
<displayName>DMA_BCTL</displayName>
|
|
<description>Ethernet DMA bus control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00020101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWR</name>
|
|
<description>Software reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAB</name>
|
|
<description>DMA Arbitration</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPSL</name>
|
|
<description>Descriptor skip length</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFM</name>
|
|
<description>Descriptor format mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGBL</name>
|
|
<description>Programmable burst length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTPR</name>
|
|
<description>RxDMA and TxDMA transfer priority ratio</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FB</name>
|
|
<description>Fixed burst</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDP</name>
|
|
<description>Rx DMA PGBL</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIP</name>
|
|
<description>Use independent PGBL</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPBL</name>
|
|
<description>Four times PGBL mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AA</name>
|
|
<description>Address-aligned </description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mixed burst</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TPEN</name>
|
|
<displayName>DMA_TPEN</displayName>
|
|
<description>Ethernet DMA transmit poll enable
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TPE</name>
|
|
<description>Transmit poll enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RPEN</name>
|
|
<displayName>DMA_RPEN</displayName>
|
|
<description>Ethernet DMA receive poll enable
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RPE</name>
|
|
<description>Receive poll enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RDTADDR</name>
|
|
<displayName>DMA_RDTADDR</displayName>
|
|
<description>Ethernet DMA receive descriptor table address
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>Start address of receive table</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_TDTADDR</name>
|
|
<displayName>DMA_TDTADDR</displayName>
|
|
<description>Ethernet DMA transmit descriptor table
|
|
address register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STT</name>
|
|
<description>Start address of transmit table</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_STAT</name>
|
|
<displayName>DMA_STAT</displayName>
|
|
<description>Ethernet DMA status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Transmit status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TPS</name>
|
|
<description>Transmit process stopped
|
|
status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>Transmit buffer unavailable
|
|
status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TJT</name>
|
|
<description>Transmit jabber timeout
|
|
status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RO</name>
|
|
<description>Receive overflow status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TU</name>
|
|
<description>Transmit underflow status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RS</name>
|
|
<description>Receive status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RBU</name>
|
|
<description>Receive buffer unavailable
|
|
status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RPS</name>
|
|
<description>Receive process stopped
|
|
status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RWT</name>
|
|
<description>Receive watchdog timeout
|
|
status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ET</name>
|
|
<description>Early transmit status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FBE</name>
|
|
<description>Fatal bus error status</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ER</name>
|
|
<description>Early receive status</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AI</name>
|
|
<description>Abnormal interrupt summary</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NI</name>
|
|
<description>Normal interrupt summary</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>Receive process state</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TP</name>
|
|
<description>Transmit process state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EB</name>
|
|
<description>Error bits status</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MSC</name>
|
|
<description>MSC status</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WUM</name>
|
|
<description>WUM status</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TST</name>
|
|
<description>Time stamp trigger status</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CTL</name>
|
|
<displayName>DMA_CTL</displayName>
|
|
<description>Ethernet DMA control
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRE</name>
|
|
<description>Start/stop receive enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSF</name>
|
|
<description>Operate on second frame</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTHC</name>
|
|
<description>Receive threshold control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FUF</name>
|
|
<description>Forward undersized good frames</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERF</name>
|
|
<description>Forward error frames</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STE</name>
|
|
<description>Start/stop transmission enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TTHC</name>
|
|
<description>Transmit threshold control</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTF</name>
|
|
<description>Flush transmit FIFO</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSFD</name>
|
|
<description>Transmit Store-and-Forward</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAFRF</name>
|
|
<description>Disable flushing of received frames</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSFD</name>
|
|
<description>Receive Store-and-Forward</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCERFD</name>
|
|
<description>Dropping of TCP/IP checksum error frames disable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_INTEN</name>
|
|
<displayName>DMA_INTEN</displayName>
|
|
<description>Ethernet DMA interrupt enable
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIEN</name>
|
|
<description>Transmit interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TPSIEN</name>
|
|
<description>Transmit process stopped interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBUIEN</name>
|
|
<description>Transmit buffer unavailable interrupt
|
|
enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TJTIEN</name>
|
|
<description>Transmit jabber timeout interrupt
|
|
enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROIEN</name>
|
|
<description>Receive overflow interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TUIEN</name>
|
|
<description>Transmit underflow interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RIEN</name>
|
|
<description>Receive interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBUIEN</name>
|
|
<description>Receive buffer unavailable interrupt
|
|
enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPSIEN</name>
|
|
<description>Receive process stopped interrupt
|
|
enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWTIEN</name>
|
|
<description>receive watchdog timeout interrupt
|
|
enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETIEN</name>
|
|
<description>Early transmit interrupt
|
|
enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FBEIEN</name>
|
|
<description>Fatal bus error interrupt
|
|
enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERIEN</name>
|
|
<description>Early receive interrupt
|
|
enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AIEN</name>
|
|
<description>Abnormal interrupt summary
|
|
enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NIEN</name>
|
|
<description>Normal interrupt summary
|
|
enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_MFBOCNT</name>
|
|
<displayName>DMA_MFBOCNT</displayName>
|
|
<description>Ethernet DMA missed frame and buffer
|
|
overflow counter register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSFC</name>
|
|
<description>Missed frames by the
|
|
controller</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSFA</name>
|
|
<description>Missed frames by the
|
|
application</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_RSWDC</name>
|
|
<displayName>DMA_RSWDC</displayName>
|
|
<description>Ethernet DMA receive state watchdog counter
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDCFRS</name>
|
|
<description> Watchdog counter for receive status (RS)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CTDADDR</name>
|
|
<displayName>DMA_CTDADDR</displayName>
|
|
<description>DMA current transmit descriptor address
|
|
register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDAP</name>
|
|
<description> transmit descriptor address
|
|
pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CRDADDR</name>
|
|
<displayName>DMA_CRDADDR</displayName>
|
|
<description>Ethernet DMA current receive descriptor address
|
|
register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDAP</name>
|
|
<description>Receive descriptor address pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CTBADDR</name>
|
|
<displayName>DMA_CTBADDR</displayName>
|
|
<description>Ethernet DMA current transmit buffer address
|
|
register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBAP</name>
|
|
<description>Transmit buffer address pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMA_CRBADDR</name>
|
|
<displayName>DMA_CRBADDR</displayName>
|
|
<description>Ethernet DMA current receive buffer address
|
|
register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RBAP</name>
|
|
<description> receive buffer address
|
|
pointer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET_MAC_FCTH</name>
|
|
<description>MAC flow control threshold register </description>
|
|
<groupName>ENET</groupName>
|
|
<baseAddress>0x40029080</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x20</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MAC_FCTH</name>
|
|
<displayName>MAC_FCTH</displayName>
|
|
<description>Ethernet MAC flow control threshold
|
|
register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000015</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFA</name>
|
|
<description>Threshold of active flow control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFD</name>
|
|
<description>Threshold of deactive flow control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET_MAC</name>
|
|
<description>Ethernet: media access control</description>
|
|
<groupName>ENET</groupName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ENET</name>
|
|
<value>61</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>ENET_WKUP</name>
|
|
<value>62</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MAC_CFG</name>
|
|
<displayName>MAC_CFG</displayName>
|
|
<description>Ethernet MAC configuration register
|
|
(MAC_CFG)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFC</name>
|
|
<description>Deferral check</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOL</name>
|
|
<description>Back-off limit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>APCD</name>
|
|
<description>Automatic pad/CRC
|
|
drop</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTD</name>
|
|
<description>Retry disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPFCO</name>
|
|
<description>IP frame checksum offload</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPM</name>
|
|
<description>Duplex mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBM</name>
|
|
<description>Loopback mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROD</name>
|
|
<description>Receive own disable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPD</name>
|
|
<description>Fast Ethernet speed</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSD</name>
|
|
<description>Carrier sense disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IGBS</name>
|
|
<description>Inter frame gap bit selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JBD</name>
|
|
<description>Jabber disable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDD</name>
|
|
<description>Watchdog disable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCD</name>
|
|
<description>Type Frame CRC Dropping</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FRMF</name>
|
|
<displayName>MAC_FRMF</displayName>
|
|
<description>Ethernet MAC frame filter register
|
|
(MAC_FRMF)</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Promiscuous mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HUF</name>
|
|
<description>Hash unicast filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HMF</name>
|
|
<description>Hash multicast filter</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAIFLT</name>
|
|
<description>Destination address inverse
|
|
filtering</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MFD</name>
|
|
<description> multicast filter disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFRMD</name>
|
|
<description>Broadcast frames disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCFRM</name>
|
|
<description>Pass control frames</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAIFLT</name>
|
|
<description>Source address inverse
|
|
filtering</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAFLT</name>
|
|
<description>Source address filter</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPFLT</name>
|
|
<description>Hash or perfect filter</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAR</name>
|
|
<description>Frames all receive</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_HLH</name>
|
|
<displayName>MAC_HLH</displayName>
|
|
<description>Ethernet MAC hash list high
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HLH</name>
|
|
<description>Hash list high</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_HLL</name>
|
|
<displayName>MAC_HLL</displayName>
|
|
<description>Ethernet MAC hash list low
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HLL</name>
|
|
<description>Hash list low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_PHY_CTL</name>
|
|
<displayName>MAC_PHY_CTL</displayName>
|
|
<description>Ethernet MAC PHY control register
|
|
(MAC_PHY_CTL)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PB</name>
|
|
<description>PHY busy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PW</name>
|
|
<description>PHY write</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLR</name>
|
|
<description>Clock range</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>PHY register</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>PHY address</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_PHY_DATA</name>
|
|
<displayName>MAC_PHY_DATA</displayName>
|
|
<description>Ethernet MAC MII data register
|
|
(MAC_PHY_DATA)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD</name>
|
|
<description>PHY data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_FCTL</name>
|
|
<displayName>MAC_FCTL</displayName>
|
|
<description>Ethernet MAC flow control register
|
|
(MAC_FCTL)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLCB_BKPA</name>
|
|
<description>Flow control busy/back pressure
|
|
activate</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCEN</name>
|
|
<description>Transmit flow control
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFCEN</name>
|
|
<description>Receive flow control
|
|
enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPFDT</name>
|
|
<description>Unicast pause frame detect</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLTS</name>
|
|
<description>Pause low threshold</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DZQP</name>
|
|
<description>Disable Zero-quanta pause</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTM</name>
|
|
<description>Pause time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_VLT</name>
|
|
<displayName>MAC_VLT</displayName>
|
|
<description>Ethernet MAC VLAN tag register
|
|
(MAC_VLT)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VLTI</name>
|
|
<description>VLAN tag identifier (for receive
|
|
frames)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VLTC</name>
|
|
<description>12-bit VLAN tag comparison</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_RWFF</name>
|
|
<displayName>MAC_RWFF</displayName>
|
|
<description>Ethernet MAC remote wakeup frame filter
|
|
register (MAC_RWFF)</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>MAC_WUM</name>
|
|
<displayName>MAC_WUM</displayName>
|
|
<description>Ethernet MAC wakeup management register
|
|
(MAC_WUM)</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWD</name>
|
|
<description>Power down</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPEN</name>
|
|
<description>Magic Packet enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFEN</name>
|
|
<description>Wakeup frame enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPKR</name>
|
|
<description>Magic packet received</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUFR</name>
|
|
<description>Wakeup frame received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GU</name>
|
|
<description>Global unicast</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUFFRPR</name>
|
|
<description>Wakeup frame filter register pointer
|
|
reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_DBG</name>
|
|
<displayName>MAC_DBG</displayName>
|
|
<description>Ethernet MAC debug register
|
|
(MAC_DBG)</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MRNI</name>
|
|
<description>MAC receive state not idle</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXAFS</name>
|
|
<description>Rx asynchronous FIFO status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFW</name>
|
|
<description>RxFIFO is writing</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFRS</name>
|
|
<description>RxFIFO read operation status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFS</name>
|
|
<description>RxFIFO state</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
|
|
<field>
|
|
<name>MTNI</name>
|
|
<description>MAC transmit state not idle</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOMT</name>
|
|
<description>Status of MAC transmitter</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCS</name>
|
|
<description>Pause condition status</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFRS</name>
|
|
<description>TxFIFO read operation status</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFW</name>
|
|
<description>TxFIFO is writing</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFNE</name>
|
|
<description>TxFIFO not empty flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFF</name>
|
|
<description>TxFIFO Full flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTF</name>
|
|
<displayName>MAC_INTF</displayName>
|
|
<description>Ethernet MAC interrupt flag register
|
|
(MAC_INTF)</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUM</name>
|
|
<description>WUM status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSC</name>
|
|
<description>MSC status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSCR</name>
|
|
<description>MSC receive status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSCT</name>
|
|
<description>MSC transmit status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMST</name>
|
|
<description>Time stamp trigger status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_INTMSK</name>
|
|
<displayName>MAC_INTMSK</displayName>
|
|
<description>Ethernet MAC interrupt mask register
|
|
(MAC_INTMSK)</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUMIM</name>
|
|
<description>WUM interrupt mask</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSTIM</name>
|
|
<description>Time stamp trigger interrupt
|
|
mask</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR0H</name>
|
|
<displayName>MAC_ADDR0H</displayName>
|
|
<description>Ethernet MAC address 0 high register
|
|
(MAC_ADDR0H)</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x8000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR0H</name>
|
|
<description>MAC address0 high</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MO</name>
|
|
<description>Always 1</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR0L</name>
|
|
<displayName>MAC_ADDR0L</displayName>
|
|
<description>Ethernet MAC address 0 low
|
|
register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR0L</name>
|
|
<description>MAC address0 low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR1H</name>
|
|
<displayName>MAC_ADDR1H</displayName>
|
|
<description>Ethernet MAC address 1 high register
|
|
(MAC_ADDR1H)</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR1H</name>
|
|
<description>MAC address1 high</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mask byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAF</name>
|
|
<description>Source address filter</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFE</name>
|
|
<description>Address filter enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR1L</name>
|
|
<displayName>MAC_ADDR1L</displayName>
|
|
<description>Ethernet MAC address1 low
|
|
register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR1L</name>
|
|
<description>MAC address1 low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR2H</name>
|
|
<displayName>MAC_ADDR2H</displayName>
|
|
<description>Ethernet MAC address 2 high register
|
|
(MAC_ADDR2H)</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR2H</name>
|
|
<description>Ethernet MAC address 2 high
|
|
register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mask byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAF</name>
|
|
<description>Source address filter</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFE</name>
|
|
<description>Address filter enable </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR2L</name>
|
|
<displayName>MAC_ADDR2L</displayName>
|
|
<description>Ethernet MAC address 2 low
|
|
register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR2L</name>
|
|
<description>MAC address2 low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR3H</name>
|
|
<displayName>MAC_ADDR3H</displayName>
|
|
<description>Ethernet MAC address 3 high register
|
|
(MAC_ADDR3H)</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR3H</name>
|
|
<description>MAC address3 high</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MB</name>
|
|
<description>Mask byte</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAF</name>
|
|
<description>Source address filter</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFE</name>
|
|
<description>Address filter enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MAC_ADDR3L</name>
|
|
<displayName>MAC_ADDR3L</displayName>
|
|
<description>Ethernet MAC address 3 low
|
|
register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR3L</name>
|
|
<description>MAC address3 low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET_MSC</name>
|
|
<description>Ethernet: MAC statistics counters</description>
|
|
<groupName>ENET</groupName>
|
|
<baseAddress>0x40028100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MSC_CTL</name>
|
|
<displayName>MSC_CTL</displayName>
|
|
<description>Ethernet MSC control register
|
|
(MSC_CTL)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>Counter reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSR</name>
|
|
<description>Counter stop rollover</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOR</name>
|
|
<description>Reset on read</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCFZ</name>
|
|
<description>MSC counter freeze</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMC</name>
|
|
<description>Preset MSC counter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AFHPM</name>
|
|
<description>Almost full or half preset mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_RINTF</name>
|
|
<displayName>MSC_RINTF</displayName>
|
|
<description>Ethernet MSC receive interrupt flag register
|
|
(MSC_RINTF)</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFCE</name>
|
|
<description>Received frames CRC error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFAE</name>
|
|
<description>Received frames alignment error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RGUF</name>
|
|
<description>Received Good Unicast Frames</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_TINTF</name>
|
|
<displayName>MSC_TINTF</displayName>
|
|
<description>Ethernet MSC transmit interrupt flag register
|
|
(MSC_TINTF)</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TGFSC</name>
|
|
<description>Transmitted good frames single collision</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TGFMSC</name>
|
|
<description>Transmitted good frames more single
|
|
collision </description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TGF</name>
|
|
<description>Transmitted good frames</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_RINTMSK</name>
|
|
<displayName>MSC_RINTMSK</displayName>
|
|
<description>Ethernet MSC receive interrupt mask register
|
|
(MSC_RINTMSK)</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFCEIM</name>
|
|
<description>Received frame CRC error interrupt
|
|
mask</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFAEIM</name>
|
|
<description>Received frames alignment error interrupt
|
|
mask</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RGUFIM</name>
|
|
<description>Received good unicast frames interrupt
|
|
mask</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_TINTMSK</name>
|
|
<displayName>MSC_TINTMSK</displayName>
|
|
<description>Ethernet MSC transmit interrupt mask
|
|
register (MSC_TINTMSK)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TGFSCIM</name>
|
|
<description>Transmitted good frames single collision interrupt
|
|
mask</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TGFMSCIM</name>
|
|
<description>Transmitted good frames more single interrupt
|
|
collision mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TGFIM</name>
|
|
<description>Transmitted good frames interrupt
|
|
mask</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_SCCNT</name>
|
|
<displayName>MSC_SCCNT</displayName>
|
|
<description>Ethernet MSC transmitted good frames after a
|
|
single collision counter</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCC</name>
|
|
<description>Transmitted good frames after a single
|
|
collision counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_MSCCNT</name>
|
|
<displayName>MSC_MSCCNT</displayName>
|
|
<description>Ethernet MSC transmitted good frames after
|
|
more than a single collision</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSCC</name>
|
|
<description>Transmitted good frames after more than
|
|
a single collision counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_TGFCNT</name>
|
|
<displayName>MSC_TGFCNT</displayName>
|
|
<description>Ethernet MSC transmitted good frames counter
|
|
register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TGF</name>
|
|
<description>Transmitted good frames
|
|
counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_RFCECNT</name>
|
|
<displayName>MSC_RFCECNT</displayName>
|
|
<description>Ethernet MSC received frames with CRC error
|
|
counter register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFCER</name>
|
|
<description>Received frames with CRC error
|
|
counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_RFAECNT</name>
|
|
<displayName>MSC_RFAECNT</displayName>
|
|
<description>Ethernet MSC received frames with alignment
|
|
error counter register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RFAER</name>
|
|
<description>Received frames with alignment error
|
|
counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MSC_RGUFCNT</name>
|
|
<displayName>MSC_RGUFCNT</displayName>
|
|
<description>MSC received good unicast frames counter
|
|
register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RGUF</name>
|
|
<description>Received good unicast frames
|
|
counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ENET_PTP</name>
|
|
<description>Ethernet: Precision time protocol</description>
|
|
<groupName>ENET</groupName>
|
|
<baseAddress>0x40028700</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PTP_TSCTL</name>
|
|
<displayName>PTP_TSCTL</displayName>
|
|
<description>Ethernet PTP time stamp control register
|
|
(PTP_TSCTL)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMSEN</name>
|
|
<description>Time stamp enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSFCU</name>
|
|
<description>Time stamp fine or coarse
|
|
update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSSTI</name>
|
|
<description>Time stamp system time
|
|
initialize</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSSTU</name>
|
|
<description>Time stamp system time
|
|
update</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSITEN</name>
|
|
<description>Time stamp interrupt trigger
|
|
enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSARU</name>
|
|
<description>Time stamp addend register
|
|
update</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARFSEN</name>
|
|
<description>All received frames snapshot enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCROM</name>
|
|
<description>Subsecond counter rollover mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFSV</name>
|
|
<description>PTP frame snooping version</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESEN</name>
|
|
<description>Received Ethernet snapshot enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IP6SEN</name>
|
|
<description>Received IPv6 snapshot enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IP4SEN</name>
|
|
<description>Received IPv4 snapshot enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETMSEN</name>
|
|
<description>Received event type message snapshot enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNMSEN</name>
|
|
<description>Received master node message snapshot enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKNT</name>
|
|
<description>Clock node type for time stamp</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAFEN</name>
|
|
<description>MAC address filter enable for PTP frame</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_SSINC</name>
|
|
<displayName>PTP_SSINC</displayName>
|
|
<description>Ethernet PTP subsecond increment
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STMSSI</name>
|
|
<description>System time subsecond
|
|
increment</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSH</name>
|
|
<displayName>PTP_TSH</displayName>
|
|
<description>Ethernet PTP time stamp high
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STMS</name>
|
|
<description>System time second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSL</name>
|
|
<displayName>PTP_TSL</displayName>
|
|
<description>Ethernet PTP time stamp low register
|
|
(PTP_TSL)</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STMSS</name>
|
|
<description>System time subseconds</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STS</name>
|
|
<description>System time sign</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSUH</name>
|
|
<displayName>PTP_TSUH</displayName>
|
|
<description>Ethernet PTP time stamp high update
|
|
register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMSUS</name>
|
|
<description>Time stamp update second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSUL</name>
|
|
<displayName>PTP_TSUL</displayName>
|
|
<description>Ethernet PTP time stamp low update register
|
|
(PTP_TSUL)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMSUSS</name>
|
|
<description>Time stamp update
|
|
subseconds</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>31</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMSUPNS</name>
|
|
<description>Time stamp update positive or negative
|
|
sign</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSADDEND</name>
|
|
<displayName>PTP_TSADDEND</displayName>
|
|
<description>Ethernet PTP time stamp addend
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TMSA</name>
|
|
<description>Time stamp addend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_ETH</name>
|
|
<displayName>PTP_ETH</displayName>
|
|
<description>Ethernet PTP expected time high
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETSH</name>
|
|
<description>Expected time stamp high</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_ETL</name>
|
|
<displayName>PTP_ETL</displayName>
|
|
<description>Ethernet PTP expected time low
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETSL</name>
|
|
<description>Expected time stamp low</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_TSF</name>
|
|
<displayName>PTP_TSF</displayName>
|
|
<description>Ethernet PTP time stamp flag
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSSCO</name>
|
|
<description>Timestamp second counter overflow</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TTM</name>
|
|
<description>Target time match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PTP_PPSCTL</name>
|
|
<displayName>PTP_PPSCTL</displayName>
|
|
<description>Ethernet PTP PPS control
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PPSOFC</name>
|
|
<description>PPS output frequency configure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>EXMC</name>
|
|
<description>External memory controller</description>
|
|
<groupName>EXMC</groupName>
|
|
<baseAddress>0xA0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EXMC</name>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SNCTL0</name>
|
|
<displayName>SNCTL0</displayName>
|
|
<description>SRAM/NOR flash control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030DA</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCK</name>
|
|
<description>Consecutive Clock</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWR</name>
|
|
<description>Synchronous write</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPS</name>
|
|
<description>CRAM page size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Asynchronous wait</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXMODEN</name>
|
|
<description>Extended mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTEN</name>
|
|
<description>NWAIT signal enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTCFG</name>
|
|
<description>NWAIT signal configuration, only work in
|
|
synchronous mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrapped burst mode enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTPOL</name>
|
|
<description>NWAIT signal polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBRSTEN</name>
|
|
<description>Synchronous burst enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NREN</name>
|
|
<description>NOR Flash access enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRW</name>
|
|
<description>NOR bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRTP</name>
|
|
<description>NOR bank memory type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRMUX</name>
|
|
<description>NOR bank memory address/data multiplexing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRBKEN</name>
|
|
<description>NOR bank enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNTCFG0</name>
|
|
<displayName>SNTCFG0</displayName>
|
|
<description>SRAM/NOR flash timing configuration register 0</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLAT</name>
|
|
<description>Data latency for NOR Flash</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Synchronous clock divide ratio</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNCTL1</name>
|
|
<displayName>SNCTL1</displayName>
|
|
<description>SRAM/NOR flash control register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCK</name>
|
|
<description>Consecutive Clock</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWR</name>
|
|
<description>Synchronous write</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPS</name>
|
|
<description>CRAM page size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Asynchronous wait</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXMODEN</name>
|
|
<description>Extended mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTEN</name>
|
|
<description>NWAIT signal enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTCFG</name>
|
|
<description>NWAIT signal configuration, only work in
|
|
synchronous mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrapped burst mode enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTPOL</name>
|
|
<description>NWAIT signal polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBRSTEN</name>
|
|
<description>Synchronous burst enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NREN</name>
|
|
<description>NOR Flash access enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRW</name>
|
|
<description>NOR bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRTP</name>
|
|
<description>NOR bank memory type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRMUX</name>
|
|
<description>NOR bank memory address/data multiplexing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRBKEN</name>
|
|
<description>NOR bank enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNTCFG1</name>
|
|
<displayName>SNTCFG1</displayName>
|
|
<description>SRAM/NOR flash timing configuration register 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLAT</name>
|
|
<description>Data latency for NOR Flash</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Synchronous clock divide ratio</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNCTL2</name>
|
|
<displayName>SNCTL2</displayName>
|
|
<description>SRAM/NOR flash control register 2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCK</name>
|
|
<description>Consecutive Clock</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWR</name>
|
|
<description>Synchronous write</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPS</name>
|
|
<description>CRAM page size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Asynchronous wait</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXMODEN</name>
|
|
<description>Extended mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTEN</name>
|
|
<description>NWAIT signal enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTCFG</name>
|
|
<description>NWAIT signal configuration, only work in
|
|
synchronous mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrapped burst mode enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTPOL</name>
|
|
<description>NWAIT signal polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBRSTEN</name>
|
|
<description>Synchronous burst enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NREN</name>
|
|
<description>NOR Flash access enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRW</name>
|
|
<description>NOR bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRTP</name>
|
|
<description>NOR bank memory type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRMUX</name>
|
|
<description>NOR bank memory address/data multiplexing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRBKEN</name>
|
|
<description>NOR bank enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNTCFG2</name>
|
|
<displayName>SNTCFG2</displayName>
|
|
<description>SRAM/NOR flash timing configuration register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLAT</name>
|
|
<description>Data latency for NOR Flash</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Synchronous clock divide ratio</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNCTL3</name>
|
|
<displayName>SNCTL3</displayName>
|
|
<description>SRAM/NOR flash control register 3</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCK</name>
|
|
<description>Consecutive Clock</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWR</name>
|
|
<description>Synchronous write</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPS</name>
|
|
<description>CRAM page size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>Asynchronous wait</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXMODEN</name>
|
|
<description>Extended mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTEN</name>
|
|
<description>NWAIT signal enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>Write enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTCFG</name>
|
|
<description>NWAIT signal configuration, only work in
|
|
synchronous mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRAPEN</name>
|
|
<description>Wrapped burst mode enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRWTPOL</name>
|
|
<description>NWAIT signal polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBRSTEN</name>
|
|
<description>Synchronous burst enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NREN</name>
|
|
<description>NOR Flash access enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRW</name>
|
|
<description>NOR bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRTP</name>
|
|
<description>NOR bank memory type</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRMUX</name>
|
|
<description>NOR bank memory address/data multiplexing</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRBKEN</name>
|
|
<description>NOR bank enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNTCFG3</name>
|
|
<displayName>SNTCFG3</displayName>
|
|
<description>SRAM/NOR flash timing configuration register 3</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLAT</name>
|
|
<description>Data latency for NOR Flash</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Synchronous clock divide ratio</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNWTCFG0</name>
|
|
<displayName>SNWTCFG0</displayName>
|
|
<description>SRAM/NOR flash write timing configuration
|
|
register 0</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNWTCFG1</name>
|
|
<displayName>SNWTCFG1</displayName>
|
|
<description>SRAM/NOR flash write timing configuration
|
|
register 1</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNWTCFG2</name>
|
|
<displayName>SNWTCFG2</displayName>
|
|
<description>SRAM/NOR flash write timing configuration
|
|
register 2</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SNWTCFG3</name>
|
|
<displayName>SNWTCFG3</displayName>
|
|
<description>SRAM/NOR flash write timing configuration
|
|
register 3</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WASYNCMOD</name>
|
|
<description>Asynchronous access mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBUSLAT</name>
|
|
<description>Bus latency</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSET</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAHLD</name>
|
|
<description>Address hold time</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WASET</name>
|
|
<description>Address setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTL1</name>
|
|
<displayName>NPCTL1</displayName>
|
|
<description>NAND flash/PC card control register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000018</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCSZ</name>
|
|
<description>ECC size</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATR</name>
|
|
<description>ALE to RE delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>CLE to RE delay</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCEN</name>
|
|
<description>ECC enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDW</name>
|
|
<description>NAND bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDTP</name>
|
|
<description>NAND bank memory type</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDBKEN</name>
|
|
<description>NAND bank enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDWTEN</name>
|
|
<description>Wait feature enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTL2</name>
|
|
<displayName>NPCTL2</displayName>
|
|
<description>NAND flash/PC card control register 2</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000018</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCSZ</name>
|
|
<description>ECC size</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATR</name>
|
|
<description>ALE to RE delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>CLE to RE delay</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCEN</name>
|
|
<description>ECC enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDW</name>
|
|
<description>NAND bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDTP</name>
|
|
<description>NAND bank memory type</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDBKEN</name>
|
|
<description>NAND bank enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDWTEN</name>
|
|
<description>Wait feature enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTL3</name>
|
|
<displayName>NPCTL3</displayName>
|
|
<description>NAND flash/PC card control register 3</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000018</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCSZ</name>
|
|
<description>ECC size</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATR</name>
|
|
<description>ALE to RE delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>CLE to RE delay</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCEN</name>
|
|
<description>ECC enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDW</name>
|
|
<description>NAND bank memory data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDTP</name>
|
|
<description>NAND bank memory type</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDBKEN</name>
|
|
<description>NAND bank enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NDWTEN</name>
|
|
<description>Wait feature enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPINTEN1</name>
|
|
<displayName>NPINTEN1</displayName>
|
|
<description>NAND flash/PC card interrupt enable register 1</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FFEPT</name>
|
|
<description>FIFO empty flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFEN</name>
|
|
<description>Interrupt falling edge detection enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHEN</name>
|
|
<description>Interrupt high-level detection enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTREN</name>
|
|
<description>Interrupt rising edge detection enable bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFS</name>
|
|
<description>Interrupt falling edge status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHS</name>
|
|
<description>Interrupt high-level status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTRS</name>
|
|
<description>Interrupt rising edge status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPINTEN2</name>
|
|
<displayName>NPINTEN2</displayName>
|
|
<description>NAND flash/PC card interrupt enable register 2</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FFEPT</name>
|
|
<description>FIFO empty flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFEN</name>
|
|
<description>Interrupt falling edge detection enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHEN</name>
|
|
<description>Interrupt high-level detection enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTREN</name>
|
|
<description>Interrupt rising edge detection enable bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFS</name>
|
|
<description>Interrupt falling edge status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHS</name>
|
|
<description>Interrupt high-level status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTRS</name>
|
|
<description>Interrupt rising edge status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPINTEN3</name>
|
|
<displayName>NPINTEN3</displayName>
|
|
<description>NAND flash/PC card interrupt enable register 3</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FFEPT</name>
|
|
<description>FIFO empty flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFEN</name>
|
|
<description>Interrupt falling edge detection enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHEN</name>
|
|
<description>Interrupt high-level detection enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTREN</name>
|
|
<description>Interrupt rising edge detection enable bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTFS</name>
|
|
<description>Interrupt falling edge status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTHS</name>
|
|
<description>Interrupt high-level status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTRS</name>
|
|
<description>Interrupt rising edge status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTCFG1</name>
|
|
<displayName>NPCTCFG1</displayName>
|
|
<description>NAND flash/PC card common space timing
|
|
configuration register 1</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMHIZ</name>
|
|
<description>Common memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMHLD</name>
|
|
<description>Common memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMWAIT</name>
|
|
<description>Common memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMSET</name>
|
|
<description>Common memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTCFG2</name>
|
|
<displayName>NPCTCFG2</displayName>
|
|
<description>NAND flash/PC card common space timing
|
|
configuration register 2</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMHIZ</name>
|
|
<description>Common memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMHLD</name>
|
|
<description>Common memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMWAIT</name>
|
|
<description>Common memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMSET</name>
|
|
<description>Common memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPCTCFG3</name>
|
|
<displayName>NPCTCFG3</displayName>
|
|
<description>NAND flash/PC card common space timing
|
|
configuration register 3</description>
|
|
<addressOffset>0xA8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMHIZ</name>
|
|
<description>Common memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMHLD</name>
|
|
<description>Common memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMWAIT</name>
|
|
<description>Common memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMSET</name>
|
|
<description>Common memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPATCFG1</name>
|
|
<displayName>NPATCFG1</displayName>
|
|
<description>NAND flash/PC card attribute space timing
|
|
configuration register 1</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATTHIZ</name>
|
|
<description>Attribute memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHLD</name>
|
|
<description>Attribute memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTWAIT</name>
|
|
<description>Attribute memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTSET</name>
|
|
<description>Attribute memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPATCFG2</name>
|
|
<displayName>NPATCFG2</displayName>
|
|
<description>NAND flash/PC card attribute space timing
|
|
configuration register 2</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATTHIZ</name>
|
|
<description>Attribute memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHLD</name>
|
|
<description>Attribute memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTWAIT</name>
|
|
<description>Attribute memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTSET</name>
|
|
<description>Attribute memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NPATCFG3</name>
|
|
<displayName>NPATCFG3</displayName>
|
|
<description>NAND flash/PC card attribute space timing
|
|
configuration register 3</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATTHIZ</name>
|
|
<description>Attribute memory data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHLD</name>
|
|
<description>Attribute memory hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTWAIT</name>
|
|
<description>Attribute memory wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTSET</name>
|
|
<description>Attribute memory setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIOTCFG3</name>
|
|
<displayName>PIOTCFG3</displayName>
|
|
<description>PC card I/O space timing configuration
|
|
register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IOHIZ</name>
|
|
<description>IO space data bus HiZ time</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOHLD</name>
|
|
<description>IO space hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOWAIT</name>
|
|
<description>IO space wait time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOSET</name>
|
|
<description>IO space setup time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NECC1</name>
|
|
<displayName>NECC1</displayName>
|
|
<description>NAND flash ECC register 1</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECC</name>
|
|
<description>ECC result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NECC2</name>
|
|
<displayName>NECC2</displayName>
|
|
<description>NAND flash ECC register 2</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECC</name>
|
|
<description>ECC result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCTL0</name>
|
|
<displayName>SDCTL0</displayName>
|
|
<description>SDRAM control register 0</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000002D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PIPED</name>
|
|
<description>Pipeline delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSTRD</name>
|
|
<description>Burst read</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDCLK</name>
|
|
<description>SDRAM clock configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write protection enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CL</name>
|
|
<description>CAS Latency</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBK</name>
|
|
<description>Number of banks</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDW</name>
|
|
<description>SDRAM data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAW</name>
|
|
<description>Row address bit width</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAW</name>
|
|
<description>Column address bit width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCTL1</name>
|
|
<displayName>SDCTL1</displayName>
|
|
<description>SDRAM control register 1</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000002D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PIPED</name>
|
|
<description>Pipeline delay</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRSTRD</name>
|
|
<description>Burst read</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDCLK</name>
|
|
<description>SDRAM clock configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WPEN</name>
|
|
<description>Write protection enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CL</name>
|
|
<description>CAS Latency</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBK</name>
|
|
<description>Number of banks</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDW</name>
|
|
<description>SDRAM data bus width</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RAW</name>
|
|
<description>Row address bit width</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAW</name>
|
|
<description>Column address bit width</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDTCFG0</name>
|
|
<displayName>SDTCFG0</displayName>
|
|
<description>SDRAM timing configuration register 0</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RCD</name>
|
|
<description>Row to column delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPD</name>
|
|
<description>Row precharge delay</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRD</name>
|
|
<description>Write recovery delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARFD</name>
|
|
<description>Auto refresh delay</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RASD</name>
|
|
<description>Row address select delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XSRD</name>
|
|
<description>Exit Self-refresh delay</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LMRD</name>
|
|
<description>Load Mode Register Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDTCFG1</name>
|
|
<displayName>SDTCFG1</displayName>
|
|
<description>SDRAM timing configuration register 1</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RCD</name>
|
|
<description>Row to column delay</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPD</name>
|
|
<description>Row precharge delay</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRD</name>
|
|
<description>Write recovery delay</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARFD</name>
|
|
<description>Auto refresh delay</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RASD</name>
|
|
<description>Row address select delay</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XSRD</name>
|
|
<description>Exit Self-refresh delay</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LMRD</name>
|
|
<description>Load Mode Register Delay</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDCMD</name>
|
|
<displayName>SDCMD</displayName>
|
|
<description>SDRAM command register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MRC</name>
|
|
<description>Mode register content</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NARF</name>
|
|
<description>Number of successive Auto-refresh</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS0</name>
|
|
<description>Device select 0</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS1</name>
|
|
<description>Device select 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDARI</name>
|
|
<displayName>SDARI</displayName>
|
|
<description>SDRAM auto-refresh interval register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REIE</name>
|
|
<description>Refresh error interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARINTV</name>
|
|
<description>Auto-Refresh Interval</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>Refresh error flag clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDSTAT</name>
|
|
<displayName>SDSTAT</displayName>
|
|
<description>SDRAM status register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NRDY</name>
|
|
<description>Not Ready status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STA1</name>
|
|
<description>Device1 status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STA0</name>
|
|
<description>Device 0 status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REIF</name>
|
|
<description>Refresh error interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDRSCTL</name>
|
|
<displayName>SDRSCTL</displayName>
|
|
<description>SDRAM read sample control register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDSC</name>
|
|
<description>Select the delayed sample clock of read data</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSCR</name>
|
|
<description>Select sample cycle of read data</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSEN</name>
|
|
<description>Read sample enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SINIT</name>
|
|
<displayName>SINIT</displayName>
|
|
<description>SPI initialization register</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x18010000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>Read data sample polarity</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDL</name>
|
|
<description>SPI PSRAM ID Length</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRBIT</name>
|
|
<description>Bit number of SPI PSRAM address phase</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDBIT</name>
|
|
<description>Bit number of SPI PSRAM command phase</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCMD</name>
|
|
<displayName>SRCMD</displayName>
|
|
<description>SPI read command register</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDID</name>
|
|
<description>Send SPI Read ID Command</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMODE</name>
|
|
<description>SPI PSRAM Read command mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWAITCYCLE</name>
|
|
<description>SPI Read Wait Cycle number after address phase</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RCMD</name>
|
|
<description>SPI Read Command for AHB read transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWCMD</name>
|
|
<displayName>SWCMD</displayName>
|
|
<description>SPI write command register</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SC</name>
|
|
<description>Send SPI Special Command which does not have address and data
|
|
phase, command code and mode come from WCMD and WMODE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WMODE</name>
|
|
<description>SPI PSRAM Write command mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWAITCYCLE</name>
|
|
<description>SPI Write Wait Cycle number after address phase</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCMD</name>
|
|
<description>SPI Write Command for AHB write transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIDL</name>
|
|
<displayName>SIDL</displayName>
|
|
<description>SPI ID low register</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIDL</name>
|
|
<description>ID Low Data saved for SPI Read ID Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIDH</name>
|
|
<displayName>SIDH</displayName>
|
|
<description>SPI ID high register</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIDH</name>
|
|
<description>ID High Data saved for SPI Read ID Command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTI</name>
|
|
<description>External interrupt/event
|
|
controller</description>
|
|
<groupName>EXTI</groupName>
|
|
<baseAddress>0x40013C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EXTI_Line0</name>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_Line1</name>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_Line2</name>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_Line3</name>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_Line4</name>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_line9_5</name>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI_line15_10</name>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<displayName>INTEN</displayName>
|
|
<description>Interrupt enable register
|
|
(EXTI_INTEN)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTEN0</name>
|
|
<description>Enable Interrupt on line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN1</name>
|
|
<description>Enable Interrupt on line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN2</name>
|
|
<description>Enable Interrupt on line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN3</name>
|
|
<description>Enable Interrupt on line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN4</name>
|
|
<description>Enable Interrupt on line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN5</name>
|
|
<description>Enable Interrupt on line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN6</name>
|
|
<description>Enable Interrupt on line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN7</name>
|
|
<description>Enable Interrupt on line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN8</name>
|
|
<description>Enable Interrupt on line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN9</name>
|
|
<description>Enable Interrupt on line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN10</name>
|
|
<description>Enable Interrupt on line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN11</name>
|
|
<description>Enable Interrupt on line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN12</name>
|
|
<description>Enable Interrupt on line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN13</name>
|
|
<description>Enable Interrupt on line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN14</name>
|
|
<description>Enable Interrupt on line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN15</name>
|
|
<description>Enable Interrupt on line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN16</name>
|
|
<description>Enable Interrupt on line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN17</name>
|
|
<description>Enable Interrupt on line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN18</name>
|
|
<description>Enable Interrupt on line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN19</name>
|
|
<description>Enable Interrupt on line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN20</name>
|
|
<description>Enable Interrupt on line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN21</name>
|
|
<description>Enable Interrupt on line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTEN22</name>
|
|
<description>Enable Interrupt on line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EVEN</name>
|
|
<displayName>EVEN</displayName>
|
|
<description>Event enable register (EXTI_EVEN)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EVEN0</name>
|
|
<description>Enable Event on line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN1</name>
|
|
<description>Enable Event on line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN2</name>
|
|
<description>Enable Event on line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN3</name>
|
|
<description>Enable Event on line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN4</name>
|
|
<description>Enable Event on line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN5</name>
|
|
<description>Enable Event on line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN6</name>
|
|
<description>Enable Event on line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN7</name>
|
|
<description>Enable Event on line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN8</name>
|
|
<description>Enable Event on line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN9</name>
|
|
<description>Enable Event on line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN10</name>
|
|
<description>Enable Event on line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN11</name>
|
|
<description>Enable Event on line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN12</name>
|
|
<description>Enable Event on line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN13</name>
|
|
<description>Enable Event on line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN14</name>
|
|
<description>Enable Event on line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN15</name>
|
|
<description>Enable Event on line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN16</name>
|
|
<description>Enable Event on line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN17</name>
|
|
<description>Enable Event on line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN18</name>
|
|
<description>Enable Event on line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN19</name>
|
|
<description>Enable Event on line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN20</name>
|
|
<description>Enable Event on line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN21</name>
|
|
<description>Enable Event on line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVEN22</name>
|
|
<description>Enable Event on line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTEN</name>
|
|
<displayName>RTEN</displayName>
|
|
<description>Rising Edge Trigger Enable register
|
|
(EXTI_RTEN)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTEN0</name>
|
|
<description>Rising edge trigger enable of
|
|
line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN1</name>
|
|
<description>Rising edge trigger enable of
|
|
line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN2</name>
|
|
<description>Rising edge trigger enable of
|
|
line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN3</name>
|
|
<description>Rising edge trigger enable of
|
|
line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN4</name>
|
|
<description>Rising edge trigger enable of
|
|
line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN5</name>
|
|
<description>Rising edge trigger enable of
|
|
line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN6</name>
|
|
<description>Rising edge trigger enable of
|
|
line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN7</name>
|
|
<description>Rising edge trigger enable of
|
|
line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN8</name>
|
|
<description>Rising edge trigger enable of
|
|
line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN9</name>
|
|
<description>Rising edge trigger enable of
|
|
line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN10</name>
|
|
<description>Rising edge trigger enable of
|
|
line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN11</name>
|
|
<description>Rising edge trigger enable of
|
|
line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN12</name>
|
|
<description>Rising edge trigger enable of
|
|
line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN13</name>
|
|
<description>Rising edge trigger enable of
|
|
line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN14</name>
|
|
<description>Rising edge trigger enable of
|
|
line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN15</name>
|
|
<description>Rising edge trigger enable of
|
|
line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN16</name>
|
|
<description>Rising edge trigger enable of
|
|
line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN17</name>
|
|
<description>Rising edge trigger enable of
|
|
line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN18</name>
|
|
<description>Rising edge trigger enable of
|
|
line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN19</name>
|
|
<description>Rising edge trigger enable of
|
|
line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN20</name>
|
|
<description>Rising edge trigger enable of
|
|
line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN21</name>
|
|
<description>Rising edge trigger enable of
|
|
line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN22</name>
|
|
<description>Rising edge trigger enable of
|
|
line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTEN</name>
|
|
<displayName>FTEN</displayName>
|
|
<description>Falling Egde Trigger Enable register
|
|
(EXTI_FTEN)</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FTEN0</name>
|
|
<description>Falling edge trigger enable of
|
|
line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN1</name>
|
|
<description>Falling edge trigger enable of
|
|
line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN2</name>
|
|
<description>Falling edge trigger enable of
|
|
line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN3</name>
|
|
<description>Falling edge trigger enable of
|
|
line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN4</name>
|
|
<description>Falling edge trigger enable of
|
|
line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN5</name>
|
|
<description>Falling edge trigger enable of
|
|
line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN6</name>
|
|
<description>Falling edge trigger enable of
|
|
line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN7</name>
|
|
<description>Falling edge trigger enable of
|
|
line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN8</name>
|
|
<description>Falling edge trigger enable of
|
|
line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN9</name>
|
|
<description>Falling edge trigger enable of
|
|
line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN10</name>
|
|
<description>Falling edge trigger enable of
|
|
line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN11</name>
|
|
<description>Falling edge trigger enable of
|
|
line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN12</name>
|
|
<description>Falling edge trigger enable of
|
|
line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN13</name>
|
|
<description>Falling edge trigger enable of
|
|
line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN14</name>
|
|
<description>Falling edge trigger enable of
|
|
line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN15</name>
|
|
<description>Falling edge trigger enable of
|
|
line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN16</name>
|
|
<description>Falling edge trigger enable of
|
|
line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN17</name>
|
|
<description>Falling edge trigger enable of
|
|
line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN18</name>
|
|
<description>Falling edge trigger enable of
|
|
line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN19</name>
|
|
<description>Falling edge trigger enable of
|
|
line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN20</name>
|
|
<description>Falling edge trigger enable of
|
|
line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN21</name>
|
|
<description>Falling edge trigger enable of
|
|
line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTEN22</name>
|
|
<description>Falling edge trigger enable of
|
|
line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWIEV</name>
|
|
<displayName>SWIEV</displayName>
|
|
<description>Software interrupt event register
|
|
(EXTI_SWIEV)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWIEV0</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV1</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV2</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV3</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV4</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV5</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV6</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV7</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV8</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV9</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV10</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV11</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV12</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV13</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV14</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV15</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV16</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV17</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV18</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV19</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV20</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV21</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWIEV22</name>
|
|
<description>Interrupt/Event software trigger on line
|
|
22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PD</name>
|
|
<displayName>PD</displayName>
|
|
<description>Pending register (EXTI_PD)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Interrupt pending status of line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Interrupt pending status of line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Interrupt pending status of line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Interrupt pending status of line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Interrupt pending status of line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Interrupt pending status of line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Interrupt pending status of line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Interrupt pending status of line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Interrupt pending status of line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Interrupt pending status of line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Interrupt pending status of line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Interrupt pending status of line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Interrupt pending status of line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Interrupt pending status of line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Interrupt pending status of line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Interrupt pending status of line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD16</name>
|
|
<description>Interrupt pending status of line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD17</name>
|
|
<description>Interrupt pending status of line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD18</name>
|
|
<description>Interrupt pending status of line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD19</name>
|
|
<description>Interrupt pending status of line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD20</name>
|
|
<description>Interrupt pending status of line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD21</name>
|
|
<description>Interrupt pending status of line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD22</name>
|
|
<description>Interrupt pending status of line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FMC</name>
|
|
<description>FMC</description>
|
|
<groupName>FMC</groupName>
|
|
<baseAddress>0x40023C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FMC</name>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>WS</name>
|
|
<displayName>WS</displayName>
|
|
<description>wait state counter register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WSCNT</name>
|
|
<description>wait state counter register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEY</name>
|
|
<displayName>KEY</displayName>
|
|
<description>Unlock key register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>FMC_CTL unlock register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OBKEY</name>
|
|
<displayName>OBKEY</displayName>
|
|
<description>Option byte unlock key register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OBKEY</name>
|
|
<description>FMC_ OBCTL0 option byte operation unlock register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>END</name>
|
|
<description>End of operation flag bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPERR</name>
|
|
<description>Flash operation error flag bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WPERR</name>
|
|
<description>Erase/Program protection error flag bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PGMERR</name>
|
|
<description>Program size not match error flag bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PGSERR</name>
|
|
<description>Program sequence error flag bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDDERR</name>
|
|
<description>Read D-bus protection error flag bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>The flash is busy bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LK</name>
|
|
<description>FMC_CTL lock bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENDIE</name>
|
|
<description>End of operation interrupt enable bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>send erase command to FMC bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MER1</name>
|
|
<description>main flash mass erase for bank1command bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSZ</name>
|
|
<description>Program size bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SN</name>
|
|
<description>Select which sector number to be erased.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MER0</name>
|
|
<description>main flash mass erase for bank0 command bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SER</name>
|
|
<description>main flash sector erase command bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>main flash program command bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OBCTL0</name>
|
|
<displayName>OBCTL0</displayName>
|
|
<description>Option byte control register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2FFFAAED</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OB_LK</name>
|
|
<description>FMC_OBCTL0 lock bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OB_START</name>
|
|
<description>send option byte change command to FMC bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOR_TH</name>
|
|
<description>option byte BOR threshold value</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BB</name>
|
|
<description>option byte boot bank value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nWDG_HW</name>
|
|
<description>option byte watchdog value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nRST_DPSLP</name>
|
|
<description>option byte deepsleep reset value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nRST_STDBY</name>
|
|
<description>option byte standby reset value</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPC</name>
|
|
<description>option byte Security Protection code</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP0</name>
|
|
<description>Erase/program protection of each sector when DRP is 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBS</name>
|
|
<description>Double banks or single bank selection when flash size is 1M</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DRP</name>
|
|
<description>D-bus read protection bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OBCTL1</name>
|
|
<displayName>OBCTL1</displayName>
|
|
<description>Option byte control register 1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Erase/program protection of each sector when DRP is 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WSEN</name>
|
|
<displayName>WSEN</displayName>
|
|
<description>Wait state enable register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WSEN</name>
|
|
<description>FMC wait state enable register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PID</name>
|
|
<displayName>PID</displayName>
|
|
<description>Product ID register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PID</name>
|
|
<description>Product reserved ID code register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FWDGT</name>
|
|
<description>free watchdog timer</description>
|
|
<groupName>FWDGT</groupName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMD</name>
|
|
<description>Key value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RLD</name>
|
|
<displayName>RLD</displayName>
|
|
<description>Reload register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RLD</name>
|
|
<description>Free watchdog timer counter reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUD</name>
|
|
<description>Free watchdog timer prescaler value update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUD</name>
|
|
<description>Free watchdog timer counter reload value update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>GPIO port control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xA8000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTL15</name>
|
|
<description>Port x configuration bits (x =
|
|
15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL14</name>
|
|
<description>Port x configuration bits (x =
|
|
14)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL13</name>
|
|
<description>Port x configuration bits (x =
|
|
13)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL12</name>
|
|
<description>Port x configuration bits (x =
|
|
12)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL11</name>
|
|
<description>Port x configuration bits (x =
|
|
11)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL10</name>
|
|
<description>Port x configuration bits (x =
|
|
10)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL9</name>
|
|
<description>Port x configuration bits (x =
|
|
9)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL8</name>
|
|
<description>Port x configuration bits (x =
|
|
8)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL7</name>
|
|
<description>Port x configuration bits (x =
|
|
7)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL6</name>
|
|
<description>Port x configuration bits (x =
|
|
6 )</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL5</name>
|
|
<description>Port x configuration bits (x =
|
|
5)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL4</name>
|
|
<description>Port x configuration bits (x =
|
|
4 )</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL3</name>
|
|
<description>Port x configuration bits (x =
|
|
3)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL2</name>
|
|
<description>Port x configuration bits (x =
|
|
2)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL1</name>
|
|
<description>Port x configuration bits (x =
|
|
1)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL0</name>
|
|
<description>Port x configuration bits (x =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OMODE</name>
|
|
<displayName>OMODE</displayName>
|
|
<description>GPIO port output mode register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OM15</name>
|
|
<description>Port 15 output mode bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM14</name>
|
|
<description>Port 14 output mode bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM13</name>
|
|
<description>Port 13 output mode bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM12</name>
|
|
<description>Port 12 output mode bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM11</name>
|
|
<description>Port 11 output mode bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM10</name>
|
|
<description>Port 10 output mode bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM9</name>
|
|
<description>Port 9 output mode bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM8</name>
|
|
<description>Port 8 output mode bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM7</name>
|
|
<description>Port 7 output mode bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM6</name>
|
|
<description>Port 6 output mode bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM5</name>
|
|
<description>Port 5 output mode bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM4</name>
|
|
<description>Port 4 output mode bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM3</name>
|
|
<description>Port 3 output mode bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM2</name>
|
|
<description>Port 2 output mode bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM1</name>
|
|
<description>Port 1 output mode bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM0</name>
|
|
<description>Port 0 output mode bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPD</name>
|
|
<displayName>OSPD</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPD15</name>
|
|
<description>Port 15 output max speed bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD14</name>
|
|
<description>Port 14 output max speed bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD13</name>
|
|
<description>Port 13 output max speed bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD12</name>
|
|
<description>Port 12 output max speed bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD11</name>
|
|
<description>Port 11 output max speed bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD10</name>
|
|
<description>Port 10 output max speed bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD9</name>
|
|
<description>Port 9 output max speed bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD8</name>
|
|
<description>Port 8 output max speed bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD7</name>
|
|
<description>Port 7 output max speed bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD6</name>
|
|
<description>Port 6 output max speed bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD5</name>
|
|
<description>Port 5 output max speed bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD4</name>
|
|
<description>Port 4 output max speed bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD3</name>
|
|
<description>Port 3 output max speed bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD2</name>
|
|
<description>Port 2 output max speed bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD1</name>
|
|
<description>Port 1 output max speed bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD0</name>
|
|
<description>Port 0 output max speed bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUD</name>
|
|
<displayName>PUD</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x64000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUD15</name>
|
|
<description>Port 15 pull-up or pull-down bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD14</name>
|
|
<description>Port 14 pull-up or pull-down bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD13</name>
|
|
<description>Port 13 pull-up or pull-down bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD12</name>
|
|
<description>Port 12 pull-up or pull-down bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD11</name>
|
|
<description>Port 11 pull-up or pull-down bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD10</name>
|
|
<description>Port 10 pull-up or pull-down bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD9</name>
|
|
<description>Port 9 pull-up or pull-down bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD8</name>
|
|
<description>Port 8 pull-up or pull-down bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD7</name>
|
|
<description>Port 7 pull-up or pull-down bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD6</name>
|
|
<description>Port 6 pull-up or pull-down bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD5</name>
|
|
<description>Port 5 pull-up or pull-down bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD4</name>
|
|
<description>Port 4 pull-up or pull-down bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD3</name>
|
|
<description>Port 3 pull-up or pull-down bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD2</name>
|
|
<description>Port 2 pull-up or pull-down bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD1</name>
|
|
<description>Port 1 pull-up or pull-down bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD0</name>
|
|
<description>Port 0 pull-up or pull-down bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISTAT</name>
|
|
<displayName>ISTAT</displayName>
|
|
<description>GPIO port input status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISTAT15</name>
|
|
<description>Port input status (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT14</name>
|
|
<description>Port input status (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT13</name>
|
|
<description>Port input status (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT12</name>
|
|
<description>Port input status (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT11</name>
|
|
<description>Port input status (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT10</name>
|
|
<description>Port input status (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT9</name>
|
|
<description>Port input status (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT8</name>
|
|
<description>Port input status (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT7</name>
|
|
<description>Port input status (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT6</name>
|
|
<description>Port input status (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT5</name>
|
|
<description>Port input status (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT4</name>
|
|
<description>Port input status (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT3</name>
|
|
<description>Port input status (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT2</name>
|
|
<description>Port input status (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT1</name>
|
|
<description>Port input status (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT0</name>
|
|
<description>Port input status (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCTL</name>
|
|
<displayName>OCTL</displayName>
|
|
<description>GPIO port output control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCTL15</name>
|
|
<description>Port output control (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL14</name>
|
|
<description>Port output control (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL13</name>
|
|
<description>Port output control (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL12</name>
|
|
<description>Port output control (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL11</name>
|
|
<description>Port output control (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL10</name>
|
|
<description>Port output control (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL9</name>
|
|
<description>Port output control (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL8</name>
|
|
<description>Port output control (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL7</name>
|
|
<description>Port output control (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL6</name>
|
|
<description>Port output control (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL5</name>
|
|
<description>Port output control (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL4</name>
|
|
<description>Port output control (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL3</name>
|
|
<description>Port output control (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL2</name>
|
|
<description>Port output control (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL1</name>
|
|
<description>Port output control (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL0</name>
|
|
<description>Port output control (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOP</name>
|
|
<displayName>BOP</displayName>
|
|
<description>GPIO port bit operate register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port Clear bit 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port Clear bit 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port Clear bit 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port Clear bit 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port Clear bit 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port Clear bit 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port Clear bit 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port Clear bit 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port Clear bit 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port Clear bit 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port Clear bit 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port Clear bit 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port Clear bit 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port Clear bit 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port Clear bit 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port Clear bit 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP15</name>
|
|
<description>Port Set bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP14</name>
|
|
<description>Port Set bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP13</name>
|
|
<description>Port Set bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP12</name>
|
|
<description>Port Set bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP11</name>
|
|
<description>Port Set bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP10</name>
|
|
<description>Port Set bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP9</name>
|
|
<description>Port Set bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP8</name>
|
|
<description>Port Set bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP7</name>
|
|
<description>Port Set bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP6</name>
|
|
<description>Port Set bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP5</name>
|
|
<description>Port Set bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP4</name>
|
|
<description>Port Set bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP3</name>
|
|
<description>Port Set bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP2</name>
|
|
<description>Port Set bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP1</name>
|
|
<description>Port Set bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP0</name>
|
|
<description>Port Set bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<displayName>LOCK</displayName>
|
|
<description>GPIO port configuration lock
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LKK</name>
|
|
<description>Lock sequence key
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK15</name>
|
|
<description>Port Lock bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK14</name>
|
|
<description>Port Lock bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK13</name>
|
|
<description>Port Lock bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK12</name>
|
|
<description>Port Lock bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK11</name>
|
|
<description>Port Lock bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK10</name>
|
|
<description>Port Lock bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK9</name>
|
|
<description>Port Lock bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK8</name>
|
|
<description>Port Lock bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK7</name>
|
|
<description>Port Lock bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK6</name>
|
|
<description>Port Lock bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK5</name>
|
|
<description>Port Lock bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK4</name>
|
|
<description>Port Lock bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK3</name>
|
|
<description>Port Lock bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK2</name>
|
|
<description>Port Lock bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK1</name>
|
|
<description>Port Lock bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK0</name>
|
|
<description>Port Lock bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL0</name>
|
|
<displayName>AFSEL0</displayName>
|
|
<description>GPIO alternate function selected register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL7</name>
|
|
<description>Port 7 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL6</name>
|
|
<description>Port 6 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL5</name>
|
|
<description>Port 5 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL4</name>
|
|
<description>Port 4 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Port 3 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Port 2 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Port 1 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Port 0 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL1</name>
|
|
<displayName>AFSEL1</displayName>
|
|
<description>GPIO alternate function selected register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL15</name>
|
|
<description>Port 15 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL14</name>
|
|
<description>Port 14 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL13</name>
|
|
<description>Port 13 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL12</name>
|
|
<description>Port 12 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL11</name>
|
|
<description>Port 11 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL10</name>
|
|
<description>Port 10 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL9</name>
|
|
<description>Port 9 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL8</name>
|
|
<description>Port 8 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BC</name>
|
|
<displayName>BC</displayName>
|
|
<description>Bit clear register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TG</name>
|
|
<displayName>TG</displayName>
|
|
<description>Port bit toggle register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TG0</name>
|
|
<description>Port toggle bit </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG1</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG2</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG3</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG4</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG5</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG6</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG7</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG8</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG9</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG10</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG11</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG12</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG13</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG14</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG15</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x40020400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>GPIO port control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000280</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTL15</name>
|
|
<description>Port x configuration bits (x =
|
|
15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL14</name>
|
|
<description>Port x configuration bits (x =
|
|
14)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL13</name>
|
|
<description>Port x configuration bits (x =
|
|
13)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL12</name>
|
|
<description>Port x configuration bits (x =
|
|
12)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL11</name>
|
|
<description>Port x configuration bits (x =
|
|
11)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL10</name>
|
|
<description>Port x configuration bits (x =
|
|
10)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL9</name>
|
|
<description>Port x configuration bits (x =
|
|
9)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL8</name>
|
|
<description>Port x configuration bits (x =
|
|
8)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL7</name>
|
|
<description>Port x configuration bits (x =
|
|
7)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL6</name>
|
|
<description>Port x configuration bits (x =
|
|
6 )</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL5</name>
|
|
<description>Port x configuration bits (x =
|
|
5)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL4</name>
|
|
<description>Port x configuration bits (x =
|
|
4 )</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL3</name>
|
|
<description>Port x configuration bits (x =
|
|
3)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL2</name>
|
|
<description>Port x configuration bits (x =
|
|
2)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL1</name>
|
|
<description>Port x configuration bits (x =
|
|
1)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL0</name>
|
|
<description>Port x configuration bits (x =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OMODE</name>
|
|
<displayName>OMODE</displayName>
|
|
<description>GPIO port output mode register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OM15</name>
|
|
<description>Port 15 output mode bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM14</name>
|
|
<description>Port 14 output mode bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM13</name>
|
|
<description>Port 13 output mode bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM12</name>
|
|
<description>Port 12 output mode bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM11</name>
|
|
<description>Port 11 output mode bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM10</name>
|
|
<description>Port 10 output mode bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM9</name>
|
|
<description>Port 9 output mode bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM8</name>
|
|
<description>Port 8 output mode bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM7</name>
|
|
<description>Port 7 output mode bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM6</name>
|
|
<description>Port 6 output mode bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM5</name>
|
|
<description>Port 5 output mode bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM4</name>
|
|
<description>Port 4 output mode bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM3</name>
|
|
<description>Port 3 output mode bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM2</name>
|
|
<description>Port 2 output mode bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM1</name>
|
|
<description>Port 1 output mode bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM0</name>
|
|
<description>Port 0 output mode bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPD</name>
|
|
<displayName>OSPD</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPD15</name>
|
|
<description>Port 15 output max speed bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD14</name>
|
|
<description>Port 14 output max speed bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD13</name>
|
|
<description>Port 13 output max speed bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD12</name>
|
|
<description>Port 12 output max speed bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD11</name>
|
|
<description>Port 11 output max speed bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD10</name>
|
|
<description>Port 10 output max speed bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD9</name>
|
|
<description>Port 9 output max speed bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD8</name>
|
|
<description>Port 8 output max speed bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD7</name>
|
|
<description>Port 7 output max speed bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD6</name>
|
|
<description>Port 6 output max speed bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD5</name>
|
|
<description>Port 5 output max speed bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD4</name>
|
|
<description>Port 4 output max speed bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD3</name>
|
|
<description>Port 3 output max speed bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD2</name>
|
|
<description>Port 2 output max speed bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD1</name>
|
|
<description>Port 1 output max speed bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD0</name>
|
|
<description>Port 0 output max speed bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUD</name>
|
|
<displayName>PUD</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUD15</name>
|
|
<description>Port 15 pull-up or pull-down bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD14</name>
|
|
<description>Port 14 pull-up or pull-down bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD13</name>
|
|
<description>Port 13 pull-up or pull-down bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD12</name>
|
|
<description>Port 12 pull-up or pull-down bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD11</name>
|
|
<description>Port 11 pull-up or pull-down bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD10</name>
|
|
<description>Port 10 pull-up or pull-down bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD9</name>
|
|
<description>Port 9 pull-up or pull-down bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD8</name>
|
|
<description>Port 8 pull-up or pull-down bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD7</name>
|
|
<description>Port 7 pull-up or pull-down bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD6</name>
|
|
<description>Port 6 pull-up or pull-down bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD5</name>
|
|
<description>Port 5 pull-up or pull-down bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD4</name>
|
|
<description>Port 4 pull-up or pull-down bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD3</name>
|
|
<description>Port 3 pull-up or pull-down bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD2</name>
|
|
<description>Port 2 pull-up or pull-down bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD1</name>
|
|
<description>Port 1 pull-up or pull-down bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD0</name>
|
|
<description>Port 0 pull-up or pull-down bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISTAT</name>
|
|
<displayName>ISTAT</displayName>
|
|
<description>GPIO port input status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISTAT15</name>
|
|
<description>Port input status (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT14</name>
|
|
<description>Port input status (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT13</name>
|
|
<description>Port input status (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT12</name>
|
|
<description>Port input status (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT11</name>
|
|
<description>Port input status (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT10</name>
|
|
<description>Port input status (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT9</name>
|
|
<description>Port input status (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT8</name>
|
|
<description>Port input status (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT7</name>
|
|
<description>Port input status (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT6</name>
|
|
<description>Port input status (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT5</name>
|
|
<description>Port input status (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT4</name>
|
|
<description>Port input status (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT3</name>
|
|
<description>Port input status (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT2</name>
|
|
<description>Port input status (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT1</name>
|
|
<description>Port input status (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT0</name>
|
|
<description>Port input status (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCTL</name>
|
|
<displayName>OCTL</displayName>
|
|
<description>GPIO port output control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCTL15</name>
|
|
<description>Port output control (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL14</name>
|
|
<description>Port output control (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL13</name>
|
|
<description>Port output control (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL12</name>
|
|
<description>Port output control (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL11</name>
|
|
<description>Port output control (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL10</name>
|
|
<description>Port output control (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL9</name>
|
|
<description>Port output control (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL8</name>
|
|
<description>Port output control (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL7</name>
|
|
<description>Port output control (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL6</name>
|
|
<description>Port output control (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL5</name>
|
|
<description>Port output control (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL4</name>
|
|
<description>Port output control (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL3</name>
|
|
<description>Port output control (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL2</name>
|
|
<description>Port output control (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL1</name>
|
|
<description>Port output control (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL0</name>
|
|
<description>Port output control (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOP</name>
|
|
<displayName>BOP</displayName>
|
|
<description>GPIO port bit operate register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port Clear bit 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port Clear bit 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port Clear bit 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port Clear bit 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port Clear bit 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port Clear bit 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port Clear bit 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port Clear bit 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port Clear bit 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port Clear bit 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port Clear bit 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port Clear bit 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port Clear bit 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port Clear bit 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port Clear bit 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port Clear bit 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP15</name>
|
|
<description>Port Set bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP14</name>
|
|
<description>Port Set bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP13</name>
|
|
<description>Port Set bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP12</name>
|
|
<description>Port Set bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP11</name>
|
|
<description>Port Set bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP10</name>
|
|
<description>Port Set bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP9</name>
|
|
<description>Port Set bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP8</name>
|
|
<description>Port Set bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP7</name>
|
|
<description>Port Set bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP6</name>
|
|
<description>Port Set bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP5</name>
|
|
<description>Port Set bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP4</name>
|
|
<description>Port Set bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP3</name>
|
|
<description>Port Set bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP2</name>
|
|
<description>Port Set bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP1</name>
|
|
<description>Port Set bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP0</name>
|
|
<description>Port Set bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<displayName>LOCK</displayName>
|
|
<description>GPIO port configuration lock
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LKK</name>
|
|
<description>Lock sequence key
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK15</name>
|
|
<description>Port Lock bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK14</name>
|
|
<description>Port Lock bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK13</name>
|
|
<description>Port Lock bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK12</name>
|
|
<description>Port Lock bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK11</name>
|
|
<description>Port Lock bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK10</name>
|
|
<description>Port Lock bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK9</name>
|
|
<description>Port Lock bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK8</name>
|
|
<description>Port Lock bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK7</name>
|
|
<description>Port Lock bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK6</name>
|
|
<description>Port Lock bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK5</name>
|
|
<description>Port Lock bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK4</name>
|
|
<description>Port Lock bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK3</name>
|
|
<description>Port Lock bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK2</name>
|
|
<description>Port Lock bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK1</name>
|
|
<description>Port Lock bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK0</name>
|
|
<description>Port Lock bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL0</name>
|
|
<displayName>AFSEL0</displayName>
|
|
<description>GPIO alternate function selected register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL7</name>
|
|
<description>Port 7 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL6</name>
|
|
<description>Port 6 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL5</name>
|
|
<description>Port 5 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL4</name>
|
|
<description>Port 4 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Port 3 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Port 2 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Port 1 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Port 0 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL1</name>
|
|
<displayName>AFSEL1</displayName>
|
|
<description>GPIO alternate function selected register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL15</name>
|
|
<description>Port 15 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL14</name>
|
|
<description>Port 14 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL13</name>
|
|
<description>Port 13 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL12</name>
|
|
<description>Port 12 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL11</name>
|
|
<description>Port 11 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL10</name>
|
|
<description>Port 10 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL9</name>
|
|
<description>Port 9 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL8</name>
|
|
<description>Port 8 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BC</name>
|
|
<displayName>BC</displayName>
|
|
<description>Bit clear register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TG</name>
|
|
<displayName>TG</displayName>
|
|
<description>Port bit toggle register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TG0</name>
|
|
<description>Port toggle bit </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG1</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG2</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG3</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG4</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG5</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG6</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG7</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG8</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG9</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG10</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG11</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG12</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG13</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG14</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG15</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOC</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x40020800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>GPIO port control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTL15</name>
|
|
<description>Port x configuration bits (x =
|
|
15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL14</name>
|
|
<description>Port x configuration bits (x =
|
|
14)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL13</name>
|
|
<description>Port x configuration bits (x =
|
|
13)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL12</name>
|
|
<description>Port x configuration bits (x =
|
|
12)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL11</name>
|
|
<description>Port x configuration bits (x =
|
|
11)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL10</name>
|
|
<description>Port x configuration bits (x =
|
|
10)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL9</name>
|
|
<description>Port x configuration bits (x =
|
|
9)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL8</name>
|
|
<description>Port x configuration bits (x =
|
|
8)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL7</name>
|
|
<description>Port x configuration bits (x =
|
|
7)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL6</name>
|
|
<description>Port x configuration bits (x =
|
|
6 )</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL5</name>
|
|
<description>Port x configuration bits (x =
|
|
5)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL4</name>
|
|
<description>Port x configuration bits (x =
|
|
4 )</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL3</name>
|
|
<description>Port x configuration bits (x =
|
|
3)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL2</name>
|
|
<description>Port x configuration bits (x =
|
|
2)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL1</name>
|
|
<description>Port x configuration bits (x =
|
|
1)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTL0</name>
|
|
<description>Port x configuration bits (x =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OMODE</name>
|
|
<displayName>OMODE</displayName>
|
|
<description>GPIO port output mode register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OM15</name>
|
|
<description>Port 15 output mode bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM14</name>
|
|
<description>Port 14 output mode bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM13</name>
|
|
<description>Port 13 output mode bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM12</name>
|
|
<description>Port 12 output mode bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM11</name>
|
|
<description>Port 11 output mode bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM10</name>
|
|
<description>Port 10 output mode bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM9</name>
|
|
<description>Port 9 output mode bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM8</name>
|
|
<description>Port 8 output mode bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM7</name>
|
|
<description>Port 7 output mode bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM6</name>
|
|
<description>Port 6 output mode bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM5</name>
|
|
<description>Port 5 output mode bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM4</name>
|
|
<description>Port 4 output mode bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM3</name>
|
|
<description>Port 3 output mode bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM2</name>
|
|
<description>Port 2 output mode bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM1</name>
|
|
<description>Port 1 output mode bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OM0</name>
|
|
<description>Port 0 output mode bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPD</name>
|
|
<displayName>OSPD</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPD15</name>
|
|
<description>Port 15 output max speed bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD14</name>
|
|
<description>Port 14 output max speed bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD13</name>
|
|
<description>Port 13 output max speed bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD12</name>
|
|
<description>Port 12 output max speed bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD11</name>
|
|
<description>Port 11 output max speed bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD10</name>
|
|
<description>Port 10 output max speed bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD9</name>
|
|
<description>Port 9 output max speed bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD8</name>
|
|
<description>Port 8 output max speed bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD7</name>
|
|
<description>Port 7 output max speed bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD6</name>
|
|
<description>Port 6 output max speed bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD5</name>
|
|
<description>Port 5 output max speed bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD4</name>
|
|
<description>Port 4 output max speed bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD3</name>
|
|
<description>Port 3 output max speed bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD2</name>
|
|
<description>Port 2 output max speed bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD1</name>
|
|
<description>Port 1 output max speed bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPD0</name>
|
|
<description>Port 0 output max speed bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUD</name>
|
|
<displayName>PUD</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUD15</name>
|
|
<description>Port 15 pull-up or pull-down bits</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD14</name>
|
|
<description>Port 14 pull-up or pull-down bits</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD13</name>
|
|
<description>Port 13 pull-up or pull-down bits</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD12</name>
|
|
<description>Port 12 pull-up or pull-down bits</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD11</name>
|
|
<description>Port 11 pull-up or pull-down bits</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD10</name>
|
|
<description>Port 10 pull-up or pull-down bits</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD9</name>
|
|
<description>Port 9 pull-up or pull-down bits</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD8</name>
|
|
<description>Port 8 pull-up or pull-down bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD7</name>
|
|
<description>Port 7 pull-up or pull-down bits</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD6</name>
|
|
<description>Port 6 pull-up or pull-down bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD5</name>
|
|
<description>Port 5 pull-up or pull-down bits</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD4</name>
|
|
<description>Port 4 pull-up or pull-down bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD3</name>
|
|
<description>Port 3 pull-up or pull-down bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD2</name>
|
|
<description>Port 2 pull-up or pull-down bits</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD1</name>
|
|
<description>Port 1 pull-up or pull-down bits</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUD0</name>
|
|
<description>Port 0 pull-up or pull-down bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISTAT</name>
|
|
<displayName>ISTAT</displayName>
|
|
<description>GPIO port input status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISTAT15</name>
|
|
<description>Port input status (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT14</name>
|
|
<description>Port input status (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT13</name>
|
|
<description>Port input status (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT12</name>
|
|
<description>Port input status (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT11</name>
|
|
<description>Port input status (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT10</name>
|
|
<description>Port input status (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT9</name>
|
|
<description>Port input status (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT8</name>
|
|
<description>Port input status (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT7</name>
|
|
<description>Port input status (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT6</name>
|
|
<description>Port input status (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT5</name>
|
|
<description>Port input status (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT4</name>
|
|
<description>Port input status (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT3</name>
|
|
<description>Port input status (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT2</name>
|
|
<description>Port input status (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT1</name>
|
|
<description>Port input status (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISTAT0</name>
|
|
<description>Port input status (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OCTL</name>
|
|
<displayName>OCTL</displayName>
|
|
<description>GPIO port output control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCTL15</name>
|
|
<description>Port output control (y =
|
|
15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL14</name>
|
|
<description>Port output control (y =
|
|
14)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL13</name>
|
|
<description>Port output control (y =
|
|
13)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL12</name>
|
|
<description>Port output control (y =
|
|
12)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL11</name>
|
|
<description>Port output control (y =
|
|
11)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL10</name>
|
|
<description>Port output control (y =
|
|
10)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL9</name>
|
|
<description>Port output control (y =
|
|
9)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL8</name>
|
|
<description>Port output control (y =
|
|
8)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL7</name>
|
|
<description>Port output control (y =
|
|
7)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL6</name>
|
|
<description>Port output control (y =
|
|
6)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL5</name>
|
|
<description>Port output control (y =
|
|
5)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL4</name>
|
|
<description>Port output control (y =
|
|
4)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL3</name>
|
|
<description>Port output control (y =
|
|
3)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL2</name>
|
|
<description>Port output control (y =
|
|
2)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL1</name>
|
|
<description>Port output control (y =
|
|
1)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCTL0</name>
|
|
<description>Port output control (y =
|
|
0)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BOP</name>
|
|
<displayName>BOP</displayName>
|
|
<description>GPIO port bit operate register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port Clear bit 15</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port Clear bit 14</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port Clear bit 13</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port Clear bit 12</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port Clear bit 11</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port Clear bit 10</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port Clear bit 9</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port Clear bit 8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port Clear bit 7</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port Clear bit 6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port Clear bit 5</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port Clear bit 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port Clear bit 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port Clear bit 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port Clear bit 1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port Clear bit 0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP15</name>
|
|
<description>Port Set bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP14</name>
|
|
<description>Port Set bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP13</name>
|
|
<description>Port Set bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP12</name>
|
|
<description>Port Set bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP11</name>
|
|
<description>Port Set bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP10</name>
|
|
<description>Port Set bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP9</name>
|
|
<description>Port Set bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP8</name>
|
|
<description>Port Set bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP7</name>
|
|
<description>Port Set bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP6</name>
|
|
<description>Port Set bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP5</name>
|
|
<description>Port Set bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP4</name>
|
|
<description>Port Set bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP3</name>
|
|
<description>Port Set bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP2</name>
|
|
<description>Port Set bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP1</name>
|
|
<description>Port Set bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOP0</name>
|
|
<description>Port Set bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOCK</name>
|
|
<displayName>LOCK</displayName>
|
|
<description>GPIO port configuration lock
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LKK</name>
|
|
<description>Lock sequence key
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK15</name>
|
|
<description>Port Lock bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK14</name>
|
|
<description>Port Lock bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK13</name>
|
|
<description>Port Lock bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK12</name>
|
|
<description>Port Lock bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK11</name>
|
|
<description>Port Lock bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK10</name>
|
|
<description>Port Lock bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK9</name>
|
|
<description>Port Lock bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK8</name>
|
|
<description>Port Lock bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK7</name>
|
|
<description>Port Lock bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK6</name>
|
|
<description>Port Lock bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK5</name>
|
|
<description>Port Lock bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK4</name>
|
|
<description>Port Lock bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK3</name>
|
|
<description>Port Lock bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK2</name>
|
|
<description>Port Lock bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK1</name>
|
|
<description>Port Lock bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LK0</name>
|
|
<description>Port Lock bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL0</name>
|
|
<displayName>AFSEL0</displayName>
|
|
<description>GPIO alternate function selected register 0</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL7</name>
|
|
<description>Port 7 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL6</name>
|
|
<description>Port 6 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL5</name>
|
|
<description>Port 5 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL4</name>
|
|
<description>Port 4 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL3</name>
|
|
<description>Port 3 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL2</name>
|
|
<description>Port 2 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL1</name>
|
|
<description>Port 1 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL0</name>
|
|
<description>Port 0 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSEL1</name>
|
|
<displayName>AFSEL1</displayName>
|
|
<description>GPIO alternate function selected register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEL15</name>
|
|
<description>Port 15 alternate function selected</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL14</name>
|
|
<description>Port 14 alternate function selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL13</name>
|
|
<description>Port 13 alternate function selected</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL12</name>
|
|
<description>Port 12 alternate function selected</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL11</name>
|
|
<description>Port 11 alternate function selected</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL10</name>
|
|
<description>Port 10 alternate function selected</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL9</name>
|
|
<description>Port 9 alternate function selected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEL8</name>
|
|
<description>Port 8 alternate function selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BC</name>
|
|
<displayName>BC</displayName>
|
|
<description>Bit clear register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR0</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR1</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR2</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR3</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR4</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR5</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR6</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR7</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR8</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR9</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR10</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR11</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR12</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR13</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR14</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CR15</name>
|
|
<description>Port cleat bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TG</name>
|
|
<displayName>TG</displayName>
|
|
<description>Port bit toggle register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TG0</name>
|
|
<description>Port toggle bit </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG1</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG2</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG3</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG4</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG5</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG6</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG7</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG8</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG9</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG10</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG11</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG12</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG13</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG14</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG15</name>
|
|
<description>Port toggle bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOD</name>
|
|
<baseAddress>0x40020C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOE</name>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOF</name>
|
|
<baseAddress>0x40021400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOG</name>
|
|
<baseAddress>0x40021800</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOH</name>
|
|
<baseAddress>0x40021C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOI</name>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Inter integrated circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C0_EV</name>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C0_ER</name>
|
|
<value>32</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRESET</name>
|
|
<description>Software reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SALT</name>
|
|
<description>SMBus alert</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECTRANS</name>
|
|
<description>PEC Transfer</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POAP</name>
|
|
<description>Position of ACK and PEC when receiving</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKEN</name>
|
|
<description>Whether or not to send an ACK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Generate a STOP condition on I2C bus</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Generate a START condition on I2C bus</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISSTRC</name>
|
|
<description>Whether to stretch SCL low when data is not ready in slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCEN</name>
|
|
<description>Whether or not to response to a General Call (0x00)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECEN</name>
|
|
<description>PEC Calculation Switch</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPEN</name>
|
|
<description>ARP protocol in SMBus switch</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMBSEL</name>
|
|
<description>SMBusType Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMBEN</name>
|
|
<description>SMBus/I2C mode switch</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2CEN</name>
|
|
<description>I2C peripheral enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMALST</name>
|
|
<description>Flag indicating DMA last transfer</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAON</name>
|
|
<description>DMA mode switch</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUFIE</name>
|
|
<description>Buffer interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EVIE</name>
|
|
<description>Event interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2CCLK</name>
|
|
<description>I2C Peripheral clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDR0</name>
|
|
<displayName>SADDR0</displayName>
|
|
<description>Slave address register 0</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDFORMAT</name>
|
|
<description>Address mode for the I2C slave</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESS9_8</name>
|
|
<description>Highest two bits of a 10-bit address</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESS7_1</name>
|
|
<description>7-bit address or bits 7:1 of a 10-bit address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRESS0</name>
|
|
<description>Bit 0 of a 10-bit address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SADDR1</name>
|
|
<displayName>SADDR1</displayName>
|
|
<description>Slave address register 1</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS2</name>
|
|
<description>Second I2C address for the slave in Dual-Address mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUADEN</name>
|
|
<description>Dual-Address mode switch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>Transfer buffer register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRB</name>
|
|
<description>Transmission or reception data buffer register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT0</name>
|
|
<displayName>STAT0</displayName>
|
|
<description>Transfer status register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMBALT</name>
|
|
<description>SMBus Alert status</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBTO</name>
|
|
<description>Timeout signal in SMBus mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PECERR</name>
|
|
<description>PEC error when receiving data</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OUERR</name>
|
|
<description>Over-run or under-run situation occurs in slave mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AERR</name>
|
|
<description>Acknowledge error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOSTARB</name>
|
|
<description>Arbitration Lost in master mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>A bus error occurs indication a unexpected START or STOP condition on I2C bus</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>I2C_DATA is Empty during transmitting</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RBNE</name>
|
|
<description>I2C_DATA is not Empty during receiving</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STPDET</name>
|
|
<description>STOP condition detected in slave mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADD10SEND</name>
|
|
<description>Header of 10-bit address is sent in master mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BTC</name>
|
|
<description>Byte transmission completed</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDSEND</name>
|
|
<description>Address is sent in master mode or received and matches in slave mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SBSEND</name>
|
|
<description>START condition sent out in master mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT1</name>
|
|
<displayName>STAT1</displayName>
|
|
<description>Transfer status register 1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECV</name>
|
|
<description>Packet Error Checking Value that calculated by hardware when PEC is enabled</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUMODF</name>
|
|
<description>Dual Flag in slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSTSMB</name>
|
|
<description>SMBus Host Header detected in slave mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEFSMB</name>
|
|
<description>Default address of SMBusDevice</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXGC</name>
|
|
<description>General call address (00h) received</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRS</name>
|
|
<description>Whether the I2C is a transmitter or a receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2CBSY</name>
|
|
<description>Busy flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MASTER</name>
|
|
<description>A flag indicating whether I2C block is in master or slave mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKCFG</name>
|
|
<displayName>CKCFG</displayName>
|
|
<description>Clock configure register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FAST</name>
|
|
<description>I2C speed selection in master mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCY</name>
|
|
<description>Duty cycle in fast mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKC</name>
|
|
<description>I2C Clock control in master mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RT</name>
|
|
<displayName>RT</displayName>
|
|
<description>Rise time register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RISETIME</name>
|
|
<description>Maximum rise time in master mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCTL</name>
|
|
<displayName>FCTL</displayName>
|
|
<description>Filter control register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFD</name>
|
|
<description>Analog noise filter disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DF</name>
|
|
<description>Digital noise filter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAMCS</name>
|
|
<displayName>SAMCS</displayName>
|
|
<description>SAM control and status register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SAMEN</name>
|
|
<description>SAM_V interface enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOEN</name>
|
|
<description>SAM_V interface timeout detect enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFFIE</name>
|
|
<description>Txframe fall interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFRIE</name>
|
|
<description>Txframe rise interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<access>read-write</access>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFFIE</name>
|
|
<description>Rxframe fall interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFRIE</name>
|
|
<description>Rxframe rise interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXF</name>
|
|
<description>Level of Txframe signal</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXF</name>
|
|
<description>Level of Rxframe signal</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TFF</name>
|
|
<description>Txframe fall flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TFR</name>
|
|
<description>Txframe rise flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Rxframe fall flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFR</name>
|
|
<description>Rxframe rise flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C1</name>
|
|
<baseAddress>0x40005800</baseAddress>
|
|
<interrupt>
|
|
<name>I2C1_EV</name>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C1_ER</name>
|
|
<value>34</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C0">
|
|
<name>I2C2</name>
|
|
<baseAddress>0x40005C00</baseAddress>
|
|
<interrupt>
|
|
<name>I2C2_EV</name>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_ER</name>
|
|
<value>73</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IPA</name>
|
|
<description>Image processing accelerator</description>
|
|
<groupName>IPA</groupName>
|
|
<baseAddress>0x4002B000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xC00</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>IPA</name>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IPA_CTL</name>
|
|
<displayName>IPA_CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transfer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>THU</name>
|
|
<description>Transfer hang up</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TST</name>
|
|
<description>Transfer stop</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAEIE</name>
|
|
<description>Enable bit for transfer access error interrupt</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIE</name>
|
|
<description>Enable bit for full transfer finish interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLMIE</name>
|
|
<description>Enable bit for transfer line mark interrupt</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LACIE</name>
|
|
<description>Enable bit for LUT access conflict interrupt</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LLFIE</name>
|
|
<description>Enable bit for LUT loading finish interrupt</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCFIE</name>
|
|
<description>Enable bit for wrong configuration interrupt</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFCM</name>
|
|
<description>Pixel format convert mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_INTF</name>
|
|
<displayName>IPA_INTF</displayName>
|
|
<description>Interrupt flag
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAEIF</name>
|
|
<description>Transfer access error interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTFIF</name>
|
|
<description>Full transfer finish interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLMIF</name>
|
|
<description>Transfer line mark interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LACIF</name>
|
|
<description>LUT access conflict interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LLFIF</name>
|
|
<description>LUT loading finish interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCFIF</name>
|
|
<description>Wrong configuration interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_INTC</name>
|
|
<displayName>IPA_INTC</displayName>
|
|
<description>Interrupt flag clear
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAEIFC</name>
|
|
<description>Clear bit for transfer access error interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFIFC</name>
|
|
<description>Clear bit for full transfer finish interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLMIF</name>
|
|
<description>Clear bit for transfer line mark interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LACIFC</name>
|
|
<description>Clear bit for LUT access conflict interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LLFIFC</name>
|
|
<description>Clear bit for LUT loading finish interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWCFIF</name>
|
|
<description>Clear bit for wrong configuration interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_FMADDR</name>
|
|
<displayName>IPA_FMADDR</displayName>
|
|
<description>Foreground memory base address
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FMADDR</name>
|
|
<description>Foreground memory base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_FLOFF</name>
|
|
<displayName>IPA_FLOFF</displayName>
|
|
<description>Foreground line offset register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLOFF</name>
|
|
<description>Foreground line offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_BMADDR</name>
|
|
<displayName>IPA_BMADDR</displayName>
|
|
<description>Background memory base address register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMADDR</name>
|
|
<description>Background memory base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_BLOFF</name>
|
|
<displayName>IPA_BLOFF</displayName>
|
|
<description>Background line offset
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLOFF</name>
|
|
<description>Background line offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_FPCTL</name>
|
|
<displayName>IPA_FPCTL</displayName>
|
|
<description>Foreground pixel control
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FPF</name>
|
|
<description>Foreground pixel format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLPF</name>
|
|
<description>Foreground LUT pixel format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLLEN</name>
|
|
<description>Foreground LUT loading enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FCNP</name>
|
|
<description>Foreground LUT number of pixel</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAVCA</name>
|
|
<description>Foreground alpha value calculation algorithm</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPDAV</name>
|
|
<description>Foreground pre- defined alpha value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_FPV</name>
|
|
<displayName>IPA_FPV</displayName>
|
|
<description>Foreground pixel value register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FPDBV</name>
|
|
<description>Foreground pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPDGV</name>
|
|
<description>Foreground pre-defined green value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPDRV</name>
|
|
<description>Foreground pre-defined red value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_BPCTL</name>
|
|
<displayName>IPA_BPCTL</displayName>
|
|
<description>Background pixel control
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BPF</name>
|
|
<description> Background pixel format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLPF</name>
|
|
<description> Background LUT pixel format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLLEN</name>
|
|
<description> Background LUT loading enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCNP</name>
|
|
<description> Background LUT number of pixel</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BAVCA</name>
|
|
<description> Background alpha value calculation algorithm</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPDAV</name>
|
|
<description> Background pre- defined alpha value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_BPV</name>
|
|
<displayName>IPA_BPV</displayName>
|
|
<description>Background pixel value
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BPDBV</name>
|
|
<description> Background pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPDGV</name>
|
|
<description> Background pre-defined green value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BPDRV</name>
|
|
<description> Background pre-defined red value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_FLMADDR</name>
|
|
<displayName>IPA_FLMADDR</displayName>
|
|
<description>Foreground LUT memory base address
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLMBADDR</name>
|
|
<description>Foreground LUT memory base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_BLMADDR</name>
|
|
<displayName>IPA_BLMADDR</displayName>
|
|
<description>Background LUT memory base address
|
|
register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLMADDR</name>
|
|
<description>Background LUT memory base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPCTL</name>
|
|
<displayName>IPA_DPCTL</displayName>
|
|
<description>Destination pixel control
|
|
register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPF</name>
|
|
<description> Destination pixel format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPV_ARGB8888</name>
|
|
<displayName>IPA_DPV_ARGB8888</displayName>
|
|
<description>Destination pixel value
|
|
register(When the destination pixel format is ARGB8888)</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPDBV</name>
|
|
<description> Destination pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDGV</name>
|
|
<description> Destination pre-defined green value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDRV</name>
|
|
<description> Destination pre-defined red value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDAV</name>
|
|
<description> Destination pre-defined alpha value</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPV_RGB888</name>
|
|
<displayName>IPA_DPV_RGB888</displayName>
|
|
<description>Destination pixel value
|
|
register(When the destination pixel format is RGB888)</description>
|
|
<alternateRegister>IPA_DPV_ARGB8888</alternateRegister>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPDBV</name>
|
|
<description> Destination pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDGV</name>
|
|
<description> Destination pre-defined green value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDRV</name>
|
|
<description> Destination pre-defined red value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPV_RGB565</name>
|
|
<displayName>IPA_DPV_RGB565</displayName>
|
|
<description>Destination pixel value
|
|
register(When the destination pixel format is RGB565)</description>
|
|
<alternateRegister>IPA_DPV_ARGB8888</alternateRegister>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPDBV</name>
|
|
<description> Destination pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDGV</name>
|
|
<description> Destination pre-defined green value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDRV</name>
|
|
<description> Destination pre-defined red value</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPV_ARGB1555</name>
|
|
<displayName>IPA_DPV_ARGB1555</displayName>
|
|
<description>Destination pixel value
|
|
register(When the destination pixel format is ARGB1555)</description>
|
|
<alternateRegister>IPA_DPV_ARGB8888</alternateRegister>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPDBV</name>
|
|
<description> Destination pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDGV</name>
|
|
<description> Destination pre-defined green value</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDRV</name>
|
|
<description> Destination pre-defined red value</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDAV</name>
|
|
<description> Destination pre-defined alpha value</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DPV_ARGB4444</name>
|
|
<displayName>IPA_DPV_ARGB4444</displayName>
|
|
<description>Destination pixel value
|
|
register(When the destination pixel format is ARGB4444,)</description>
|
|
<alternateRegister>IPA_DPV_ARGB8888</alternateRegister>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DPDBV</name>
|
|
<description> Destination pre-defined blue value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDGV</name>
|
|
<description> Destination pre-defined green value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDRV</name>
|
|
<description> Destination pre-defined red value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPDAV</name>
|
|
<description> Destination pre-defined alpha value</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DMADDR</name>
|
|
<displayName>IPA_DMADDR</displayName>
|
|
<description>Destination memory base address
|
|
register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMADDR</name>
|
|
<description> Destination memory base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_DLOFF</name>
|
|
<displayName>IPA_DLOFF</displayName>
|
|
<description>Destination line offset
|
|
register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLOFF</name>
|
|
<description> Destination line offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_IMS</name>
|
|
<displayName>IPA_IMS</displayName>
|
|
<description>Image size
|
|
register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WIDTH</name>
|
|
<description> Width of the image to be processed</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HEIGHT</name>
|
|
<description> Height of the image to be processed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_LM</name>
|
|
<displayName>IPA_LM</displayName>
|
|
<description>Line mark
|
|
register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LM</name>
|
|
<description> line mark</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPA_ITCTL</name>
|
|
<displayName>IPA_ITCTL</displayName>
|
|
<description>Inter-timer control
|
|
register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ITEN</name>
|
|
<description> Inter-timer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NCCI</name>
|
|
<description>Number of clock cycles interval</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IREF</name>
|
|
<description>Programmable current reference</description>
|
|
<groupName>IREF</groupName>
|
|
<baseAddress>0x4000C400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000F00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSDT</name>
|
|
<description>Current step data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCMOD</name>
|
|
<description>Sink current mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPT</name>
|
|
<description>Current precision trim</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSEL</name>
|
|
<description>Step selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CREN</name>
|
|
<description>Current reference enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt
|
|
Controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xF00</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x33D</offset>
|
|
<size>0xC3</size>
|
|
<usage>reserved</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ISER</name>
|
|
<displayName>ISER</displayName>
|
|
<description>Interrupt Set Enable Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>SETENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER</name>
|
|
<displayName>ICER</displayName>
|
|
<description>Interrupt Clear Enable
|
|
Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>CLRENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR</name>
|
|
<displayName>ISPR</displayName>
|
|
<description>Interrupt Set-Pending Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>SETPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR</name>
|
|
<displayName>ICPR</displayName>
|
|
<description>Interrupt Clear-Pending
|
|
Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>CLRPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR</name>
|
|
<displayName>IABR</displayName>
|
|
<description>Interrupt Active bit
|
|
Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IABR</name>
|
|
<description>IABR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR0</name>
|
|
<displayName>IPR0</displayName>
|
|
<description>Interrupt Priority Register 0</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_00</name>
|
|
<description>PRI_00</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR1</name>
|
|
<displayName>IPR1</displayName>
|
|
<description>Interrupt Priority Register 1</description>
|
|
<addressOffset>0x301</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_01</name>
|
|
<description>PRI_01</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR2</name>
|
|
<displayName>IPR2</displayName>
|
|
<description>Interrupt Priority Register 2</description>
|
|
<addressOffset>0x302</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_02</name>
|
|
<description>PRI_02</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR3</name>
|
|
<displayName>IPR3</displayName>
|
|
<description>Interrupt Priority Register 3</description>
|
|
<addressOffset>0x303</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_03</name>
|
|
<description>PRI_03</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR4</name>
|
|
<displayName>IPR4</displayName>
|
|
<description>Interrupt Priority Register 4</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_04</name>
|
|
<description>PRI_04</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR5</name>
|
|
<displayName>IPR5</displayName>
|
|
<description>Interrupt Priority Register 5</description>
|
|
<addressOffset>0x305</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_05</name>
|
|
<description>PRI_05</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR6</name>
|
|
<displayName>IPR6</displayName>
|
|
<description>Interrupt Priority Register 6</description>
|
|
<addressOffset>0x306</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_06</name>
|
|
<description>PRI_06</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR7</name>
|
|
<displayName>IPR7</displayName>
|
|
<description>Interrupt Priority Register 7</description>
|
|
<addressOffset>0x307</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_07</name>
|
|
<description>PRI_07</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR8</name>
|
|
<displayName>IPR8</displayName>
|
|
<description>Interrupt Priority Register 8</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_08</name>
|
|
<description>PRI_08</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR9</name>
|
|
<displayName>IPR9</displayName>
|
|
<description>Interrupt Priority Register 9</description>
|
|
<addressOffset>0x309</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_09</name>
|
|
<description>PRI_09</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR10</name>
|
|
<displayName>IPR10</displayName>
|
|
<description>Interrupt Priority Register 10</description>
|
|
<addressOffset>0x30A</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_10</name>
|
|
<description>PRI_10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR11</name>
|
|
<displayName>IPR11</displayName>
|
|
<description>Interrupt Priority Register 11</description>
|
|
<addressOffset>0x30B</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>PRI_11</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR12</name>
|
|
<displayName>IPR12</displayName>
|
|
<description>Interrupt Priority Register 12</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_12</name>
|
|
<description>PRI_12</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR13</name>
|
|
<displayName>IPR13</displayName>
|
|
<description>Interrupt Priority Register 13</description>
|
|
<addressOffset>0x30D</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_13</name>
|
|
<description>PRI_13</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR14</name>
|
|
<displayName>IPR14</displayName>
|
|
<description>Interrupt Priority Register 14</description>
|
|
<addressOffset>0x30E</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>PRI_14</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR15</name>
|
|
<displayName>IPR15</displayName>
|
|
<description>Interrupt Priority Register 15</description>
|
|
<addressOffset>0x30F</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>PRI_15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR16</name>
|
|
<displayName>IPR16</displayName>
|
|
<description>Interrupt Priority Register 16</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_16</name>
|
|
<description>PRI_16</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR17</name>
|
|
<displayName>IPR17</displayName>
|
|
<description>Interrupt Priority Register 17</description>
|
|
<addressOffset>0x311</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_17</name>
|
|
<description>PRI_17</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR18</name>
|
|
<displayName>IPR18</displayName>
|
|
<description>Interrupt Priority Register 18</description>
|
|
<addressOffset>0x312</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_18</name>
|
|
<description>PRI_18</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR19</name>
|
|
<displayName>IPR19</displayName>
|
|
<description>Interrupt Priority Register 19</description>
|
|
<addressOffset>0x313</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_19</name>
|
|
<description>PRI_19</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR20</name>
|
|
<displayName>IPR20</displayName>
|
|
<description>Interrupt Priority Register 20</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_20</name>
|
|
<description>PRI_20</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR21</name>
|
|
<displayName>IPR21</displayName>
|
|
<description>Interrupt Priority Register 21</description>
|
|
<addressOffset>0x315</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_21</name>
|
|
<description>PRI_21</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR22</name>
|
|
<displayName>IPR22</displayName>
|
|
<description>Interrupt Priority Register 22</description>
|
|
<addressOffset>0x316</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_22</name>
|
|
<description>PRI_22</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR23</name>
|
|
<displayName>IPR23</displayName>
|
|
<description>Interrupt Priority Register 23</description>
|
|
<addressOffset>0x317</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_23</name>
|
|
<description>PRI_23</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR24</name>
|
|
<displayName>IPR24</displayName>
|
|
<description>Interrupt Priority Register 24</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_24</name>
|
|
<description>PRI_24</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR25</name>
|
|
<displayName>IPR25</displayName>
|
|
<description>Interrupt Priority Register 25</description>
|
|
<addressOffset>0x319</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_25</name>
|
|
<description>PRI_25</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR26</name>
|
|
<displayName>IPR26</displayName>
|
|
<description>Interrupt Priority Register 26</description>
|
|
<addressOffset>0x31A</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_26</name>
|
|
<description>PRI_26</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR27</name>
|
|
<displayName>IPR27</displayName>
|
|
<description>Interrupt Priority Register 27</description>
|
|
<addressOffset>0x31B</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_27</name>
|
|
<description>PRI_27</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR28</name>
|
|
<displayName>IPR28</displayName>
|
|
<description>Interrupt Priority Register 28</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_28</name>
|
|
<description>PRI_28</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR29</name>
|
|
<displayName>IPR29</displayName>
|
|
<description>Interrupt Priority Register 29</description>
|
|
<addressOffset>0x31D</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_29</name>
|
|
<description>PRI_29</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR30</name>
|
|
<displayName>IPR30</displayName>
|
|
<description>Interrupt Priority Register 30</description>
|
|
<addressOffset>0x31E</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_30</name>
|
|
<description>PRI_30</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR31</name>
|
|
<displayName>IPR31</displayName>
|
|
<description>Interrupt Priority Register 31</description>
|
|
<addressOffset>0x31F</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_31</name>
|
|
<description>PRI_31</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR32</name>
|
|
<displayName>IPR32</displayName>
|
|
<description>Interrupt Priority Register 32</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_32</name>
|
|
<description>PRI_32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR33</name>
|
|
<displayName>IPR33</displayName>
|
|
<description>Interrupt Priority Register 33</description>
|
|
<addressOffset>0x321</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_33</name>
|
|
<description>PRI_33</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR34</name>
|
|
<displayName>IPR34</displayName>
|
|
<description>Interrupt Priority Register 34</description>
|
|
<addressOffset>0x322</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_34</name>
|
|
<description>PRI_34</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR35</name>
|
|
<displayName>IPR35</displayName>
|
|
<description>Interrupt Priority Register 35</description>
|
|
<addressOffset>0x323</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_35</name>
|
|
<description>PRI_35</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR36</name>
|
|
<displayName>IPR36</displayName>
|
|
<description>Interrupt Priority Register 36</description>
|
|
<addressOffset>0x324</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_36</name>
|
|
<description>PRI_36</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR37</name>
|
|
<displayName>IPR37</displayName>
|
|
<description>Interrupt Priority Register 37</description>
|
|
<addressOffset>0x325</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_37</name>
|
|
<description>PRI_37</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR38</name>
|
|
<displayName>IPR38</displayName>
|
|
<description>Interrupt Priority Register 38</description>
|
|
<addressOffset>0x326</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_38</name>
|
|
<description>PRI_38</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR39</name>
|
|
<displayName>IPR39</displayName>
|
|
<description>Interrupt Priority Register 39</description>
|
|
<addressOffset>0x327</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_39</name>
|
|
<description>PRI_39</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR40</name>
|
|
<displayName>IPR40</displayName>
|
|
<description>Interrupt Priority Register 40</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_40</name>
|
|
<description>PRI_40</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR41</name>
|
|
<displayName>IPR41</displayName>
|
|
<description>Interrupt Priority Register 41</description>
|
|
<addressOffset>0x329</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_41</name>
|
|
<description>PRI_41</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR42</name>
|
|
<displayName>IPR42</displayName>
|
|
<description>Interrupt Priority Register 42</description>
|
|
<addressOffset>0x32A</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_42</name>
|
|
<description>PRI_42</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR43</name>
|
|
<displayName>IPR43</displayName>
|
|
<description>Interrupt Priority Register 43</description>
|
|
<addressOffset>0x32B</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_43</name>
|
|
<description>PRI_43</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR44</name>
|
|
<displayName>IPR44</displayName>
|
|
<description>Interrupt Priority Register 44</description>
|
|
<addressOffset>0x32C</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_44</name>
|
|
<description>PRI_44</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR45</name>
|
|
<displayName>IPR45</displayName>
|
|
<description>Interrupt Priority Register 45</description>
|
|
<addressOffset>0x32D</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_45</name>
|
|
<description>PRI_45</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR46</name>
|
|
<displayName>IPR46</displayName>
|
|
<description>Interrupt Priority Register 46</description>
|
|
<addressOffset>0x32E</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_46</name>
|
|
<description>PRI_46</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR47</name>
|
|
<displayName>IPR47</displayName>
|
|
<description>Interrupt Priority Register 47</description>
|
|
<addressOffset>0x32F</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_47</name>
|
|
<description>PRI_47</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR48</name>
|
|
<displayName>IPR48</displayName>
|
|
<description>Interrupt Priority Register 48</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_48</name>
|
|
<description>PRI_48</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR49</name>
|
|
<displayName>IPR49</displayName>
|
|
<description>Interrupt Priority Register 49</description>
|
|
<addressOffset>0x331</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_49</name>
|
|
<description>PRI_49</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR50</name>
|
|
<displayName>IPR50</displayName>
|
|
<description>Interrupt Priority Register 50</description>
|
|
<addressOffset>0x332</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_50</name>
|
|
<description>PRI_50</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR51</name>
|
|
<displayName>IPR51</displayName>
|
|
<description>Interrupt Priority Register 51</description>
|
|
<addressOffset>0x333</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_51</name>
|
|
<description>PRI_51</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR52</name>
|
|
<displayName>IPR52</displayName>
|
|
<description>Interrupt Priority Register 52</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_52</name>
|
|
<description>PRI_52</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR53</name>
|
|
<displayName>IPR53</displayName>
|
|
<description>Interrupt Priority Register 53</description>
|
|
<addressOffset>0x335</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_53</name>
|
|
<description>PRI_53</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR54</name>
|
|
<displayName>IPR54</displayName>
|
|
<description>Interrupt Priority Register 54</description>
|
|
<addressOffset>0x336</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_54</name>
|
|
<description>PRI_54</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR55</name>
|
|
<displayName>IPR55</displayName>
|
|
<description>Interrupt Priority Register 55</description>
|
|
<addressOffset>0x337</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_55</name>
|
|
<description>PRI_55</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR56</name>
|
|
<displayName>IPR56</displayName>
|
|
<description>Interrupt Priority Register 56</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_56</name>
|
|
<description>PRI_56</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR57</name>
|
|
<displayName>IPR57</displayName>
|
|
<description>Interrupt Priority Register 57</description>
|
|
<addressOffset>0x339</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_57</name>
|
|
<description>PRI_57</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR58</name>
|
|
<displayName>IPR58</displayName>
|
|
<description>Interrupt Priority Register 58</description>
|
|
<addressOffset>0x33A</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_58</name>
|
|
<description>PRI_58</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR59</name>
|
|
<displayName>IPR59</displayName>
|
|
<description>Interrupt Priority Register 59</description>
|
|
<addressOffset>0x33B</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_59</name>
|
|
<description>PRI_59</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR60</name>
|
|
<displayName>IPR60</displayName>
|
|
<description>Interrupt Priority Register 60</description>
|
|
<addressOffset>0x33C</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_60</name>
|
|
<description>PRI_60</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR61</name>
|
|
<displayName>IPR61</displayName>
|
|
<description>Interrupt Priority Register 61</description>
|
|
<addressOffset>0x33D</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_61</name>
|
|
<description>PRI_61</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR62</name>
|
|
<displayName>IPR62</displayName>
|
|
<description>Interrupt Priority Register 62</description>
|
|
<addressOffset>0x33E</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_62</name>
|
|
<description>PRI_62</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR63</name>
|
|
<displayName>IPR63</displayName>
|
|
<description>Interrupt Priority Register 63</description>
|
|
<addressOffset>0x33F</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_63</name>
|
|
<description>PRI_63</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR64</name>
|
|
<displayName>IPR64</displayName>
|
|
<description>Interrupt Priority Register 64</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_64</name>
|
|
<description>PRI_64</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR65</name>
|
|
<displayName>IPR65</displayName>
|
|
<description>Interrupt Priority Register 65</description>
|
|
<addressOffset>0x341</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_65</name>
|
|
<description>PRI_65</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR66</name>
|
|
<displayName>IPR66</displayName>
|
|
<description>Interrupt Priority Register 66</description>
|
|
<addressOffset>0x342</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_66</name>
|
|
<description>PRI_66</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR67</name>
|
|
<displayName>IPR67</displayName>
|
|
<description>Interrupt Priority Register 67</description>
|
|
<addressOffset>0x343</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_67</name>
|
|
<description>PRI_67</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR68</name>
|
|
<displayName>IPR68</displayName>
|
|
<description>Interrupt Priority Register 68</description>
|
|
<addressOffset>0x344</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_68</name>
|
|
<description>PRI_68</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR69</name>
|
|
<displayName>IPR69</displayName>
|
|
<description>Interrupt Priority Register 69</description>
|
|
<addressOffset>0x345</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_69</name>
|
|
<description>PRI_69</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR70</name>
|
|
<displayName>IPR70</displayName>
|
|
<description>Interrupt Priority Register 70</description>
|
|
<addressOffset>0x346</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_70</name>
|
|
<description>PRI_70</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR71</name>
|
|
<displayName>IPR71</displayName>
|
|
<description>Interrupt Priority Register 71</description>
|
|
<addressOffset>0x347</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_71</name>
|
|
<description>PRI_71</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR72</name>
|
|
<displayName>IPR72</displayName>
|
|
<description>Interrupt Priority Register 72</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_72</name>
|
|
<description>PRI_72</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR73</name>
|
|
<displayName>IPR73</displayName>
|
|
<description>Interrupt Priority Register 73</description>
|
|
<addressOffset>0x349</addressOffset>
|
|
<size>0x08</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_73</name>
|
|
<description>PRI_73</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STIR</name>
|
|
<displayName>STIR</displayName>
|
|
<description>Software Trigger Interrupt Register</description>
|
|
<addressOffset>0xE00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STIR</name>
|
|
<description>STIR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PMU</name>
|
|
<description>Power management unit</description>
|
|
<groupName>PMU</groupName>
|
|
<baseAddress>0x40007000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>power control register</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000C000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LDEN</name>
|
|
<description>Low-driver mode enable in Deep-sleep mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDS</name>
|
|
<description>High-driver mode switch</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDEN</name>
|
|
<description>High-driver mode enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDOVS</name>
|
|
<description>LDO output voltage select</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDNP</name>
|
|
<description>Low-driver mode when use normal power LDO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDLP</name>
|
|
<description>Low-driver mode when use low power LDO.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKPWEN</name>
|
|
<description>Backup Domain Write Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVDT</name>
|
|
<description>Low Voltage Detector Threshold</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LVDEN</name>
|
|
<description>Low Voltage Detector Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STBRST</name>
|
|
<description>Standby Flag Reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WURST</name>
|
|
<description>Wakeup Flag Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STBMOD</name>
|
|
<description>Standby Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDOLP</name>
|
|
<description>LDO Low Power Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CS</name>
|
|
<displayName>CS</displayName>
|
|
<description>power control/status register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LDRF</name>
|
|
<description>Low-driver mode ready flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HDSRF</name>
|
|
<description>High-driver switch ready flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HDRF</name>
|
|
<description>High-driver ready flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LDOVSRF</name>
|
|
<description>LDO voltage select ready flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BLDOON</name>
|
|
<description>Backup SRAM LDO on</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WUPEN</name>
|
|
<description>Enable WKUP pin</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLDORF</name>
|
|
<description>Backup SRAM LDO ready flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LVDF</name>
|
|
<description>Low Voltage Detector Status Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STBF</name>
|
|
<description>Standby flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>Wakeup flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCU</name>
|
|
<description>Reset and clock unit</description>
|
|
<groupName>RCU</groupName>
|
|
<baseAddress>0x40023800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCU_CTC</name>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000083</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRC16MEN</name>
|
|
<description>Internal 16MHz RC oscillator Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MSTB</name>
|
|
<description>IRC16M Internal 16MHz RC Oscillator stabilization Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MADJ</name>
|
|
<description>Internal 16MHz RC Oscillator clock trim adjust value</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MCALIB</name>
|
|
<description>Internal 16MHz RC Oscillator calibration value register</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALEN</name>
|
|
<description>External High Speed oscillator Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALSTB</name>
|
|
<description>External crystal oscillator (HXTAL) clock stabilization flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALBPS</name>
|
|
<description>External crystal oscillator (HXTAL) clock bypass mode enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKMEN</name>
|
|
<description>HXTAL Clock Monitor Enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLEN</name>
|
|
<description>PLL enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSTB</name>
|
|
<description>PLL Clock Stabilization Flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SEN</name>
|
|
<description>PLLI2S enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SSTB</name>
|
|
<description>PLLI2S Clock Stabilization Flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAIEN</name>
|
|
<description>PLLSAI enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAISTB</name>
|
|
<description>PLLSAI Clock Stabilization Flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLL</name>
|
|
<displayName>PLL</displayName>
|
|
<description>PLL register
|
|
(RCU_PLL)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x24003010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLPSC</name>
|
|
<description>The PLL VCO source clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLN</name>
|
|
<description>The PLL VCO clock multi factor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLP</name>
|
|
<description>The PLLP output frequency division factor from PLL VCO clock</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSEL</name>
|
|
<description>PLL Clock Source Selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLQ</name>
|
|
<description>The PLL Q output frequency division factor from PLL VCO clock</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG0</name>
|
|
<displayName>CFG0</displayName>
|
|
<description>Clock configuration register 0
|
|
(RCU_CFG0)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCS</name>
|
|
<description>System clock switch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCSS</name>
|
|
<description>System clock switch status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>AHBPSC</name>
|
|
<description>AHB prescaler selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>APB1PSC</name>
|
|
<description>APB1 prescaler selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>APB2PSC</name>
|
|
<description>APB2 prescaler selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCDIV</name>
|
|
<description>RTC clock divider factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKOUT0SEL</name>
|
|
<description>CKOUT0 Clock Source Selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SSEL</name>
|
|
<description>I2S Clock Source Selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKOUT0DIV</name>
|
|
<description>The CK_OUT0 divider which the CK_OUT0 frequency can be reduced</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKOUT1DIV</name>
|
|
<description>The CK_OUT1 divider which the CK_OUT1 frequency can be reduced</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKOUT1SEL</name>
|
|
<description>CKOUT1 Clock Source Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT</name>
|
|
<displayName>INT</displayName>
|
|
<description>Clock interrupt register
|
|
(RCU_INT)</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRC32KSTBIF</name>
|
|
<description>IRC32K stabilization interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALSTBIF</name>
|
|
<description>LXTAL stabilization interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MSTBIF</name>
|
|
<description>IRC16M stabilization interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALSTBIF</name>
|
|
<description>HXTAL stabilization interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSTBIF</name>
|
|
<description>PLL stabilization interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SSTBIF</name>
|
|
<description>PLLI2S stabilization interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAISTBIF</name>
|
|
<description>PLLSAI stabilization interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CKMIF</name>
|
|
<description>HXTAL Clock Stuck Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC32KSTBIE</name>
|
|
<description>IRC32K Stabilization interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALSTBIE</name>
|
|
<description>LXTAL Stabilization Interrupt Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MSTBIE</name>
|
|
<description>IRC16M Stabilization Interrupt Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALSTBIE</name>
|
|
<description>HXTAL Stabilization Interrupt Enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSTBIE</name>
|
|
<description>PLL Stabilization Interrupt Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SSTBIE</name>
|
|
<description>PLLI2S Stabilization Interrupt Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAISTBIE</name>
|
|
<description>PLLSAI Stabilization Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC32KSTBIC</name>
|
|
<description>IRC32K Stabilization Interrupt Clear</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALSTBIC</name>
|
|
<description>LXTAL Stabilization Interrupt Clear</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC16MSTBIC</name>
|
|
<description>IRC16M Stabilization Interrupt Clear</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HXTALSTBIC</name>
|
|
<description>HXTAL Stabilization Interrupt Clear</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSTBIC</name>
|
|
<description>PLL stabilization Interrupt Clear</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SSTBIC</name>
|
|
<description>PLLI2S stabilization Interrupt Clear</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAISTBIC</name>
|
|
<description>PLLSAI stabilization Interrupt Clear</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CKMIC</name>
|
|
<description>HXTAL Clock Stuck Interrupt Clear</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB1RST</name>
|
|
<displayName>AHB1RST</displayName>
|
|
<description>AHB1 reset register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PARST</name>
|
|
<description>GPIO port A reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBRST</name>
|
|
<description>GPIO port B reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCRST</name>
|
|
<description>GPIO port C reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDRST</name>
|
|
<description>GPIO port D reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERST</name>
|
|
<description>GPIO port E reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFRST</name>
|
|
<description>GPIO port F reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGRST</name>
|
|
<description>GPIO port G reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PHRST</name>
|
|
<description>GPIO port H reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIRST</name>
|
|
<description>GPIO port I reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCRST</name>
|
|
<description>CRC reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA0RST</name>
|
|
<description>DMA0 reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA1RST</name>
|
|
<description>DMA1 reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPARST</name>
|
|
<description>IPA reset</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETRST</name>
|
|
<description>Ethernet reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBHSRST</name>
|
|
<description>USBHS reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB2RST</name>
|
|
<displayName>AHB2RST</displayName>
|
|
<description>AHB2 reset register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCIRST</name>
|
|
<description>DCI reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNGRST</name>
|
|
<description>TRNG reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBFSRST</name>
|
|
<description>USBFS reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB3RST</name>
|
|
<displayName>AHB3RST</displayName>
|
|
<description>AHB3 reset register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXMCRST</name>
|
|
<description>EXMC reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>APB1RST</name>
|
|
<displayName>APB1RST</displayName>
|
|
<description>APB1 reset register
|
|
(RCU_APB1RST)</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER1RST</name>
|
|
<description>TIMER1 timer reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2RST</name>
|
|
<description>TIMER2 timer reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3RST</name>
|
|
<description>TIMER3 timer reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER4RST</name>
|
|
<description>TIMER4 timer reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER5RST</name>
|
|
<description>TIMER5 timer reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER6RST</name>
|
|
<description>TIMER6 timer reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER11RST</name>
|
|
<description>TIMER11 timer reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER12RST</name>
|
|
<description>TIMER12 timer reset</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER13RST</name>
|
|
<description>TIMER13 timer reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGTRST</name>
|
|
<description>Window watchdog timer reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1RST</name>
|
|
<description>SPI1 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2RST</name>
|
|
<description>SPI2 reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1RST</name>
|
|
<description>USART1 reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2RST</name>
|
|
<description>USART2 reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART3RST</name>
|
|
<description>UART3 reset</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4RST</name>
|
|
<description>UART4 reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C0RST</name>
|
|
<description>I2C0 reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1RST</name>
|
|
<description>I2C1 reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2RST</name>
|
|
<description>I2C2 reset</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN0RST</name>
|
|
<description>CAN0 reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN1RST</name>
|
|
<description>CAN1 reset</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMURST</name>
|
|
<description>Power control reset</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACRST</name>
|
|
<description>DAC reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART6RST</name>
|
|
<description>UART6 reset</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART7RST</name>
|
|
<description>UART7 reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2RST</name>
|
|
<displayName>APB2RST</displayName>
|
|
<description>APB2 reset register
|
|
(RCU_APB2RST)</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0RST</name>
|
|
<description>TIMER0 reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER7RST</name>
|
|
<description>TIMER7 reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART0RST</name>
|
|
<description>USART0 reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART5RST</name>
|
|
<description>USART5 reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCRST</name>
|
|
<description>ADC reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIORST</name>
|
|
<description>SDIO reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI0RST</name>
|
|
<description>SPI0 Reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI3RST</name>
|
|
<description>SPI3 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSCFGRST</name>
|
|
<description>SYSCFG Reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER8RST</name>
|
|
<description>TIMER8 reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER9RST</name>
|
|
<description>TIMER9 reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER10RST</name>
|
|
<description>TIMER10 reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4RST</name>
|
|
<description>SPI4 Reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI5RST</name>
|
|
<description>SPI5 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLIRST</name>
|
|
<description>TLI Reset</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB1EN</name>
|
|
<displayName>AHB1EN</displayName>
|
|
<description>AHB1 enable register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00100000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PAEN</name>
|
|
<description>GPIO port A clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBEN</name>
|
|
<description>GPIO port B clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>GPIO port C clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDEN</name>
|
|
<description>GPIO port D clock enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEEN</name>
|
|
<description>GPIO port E clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFEN</name>
|
|
<description>GPIO port F clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGEN</name>
|
|
<description>GPIO port G clock enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PHEN</name>
|
|
<description>GPIO port H clock enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIEN</name>
|
|
<description>GPIO port I clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKPSRAMEN</name>
|
|
<description>BKPSRAM clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCMSRAMEN</name>
|
|
<description>TCMSRAM clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA0EN</name>
|
|
<description>DMA0 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA1EN</name>
|
|
<description>DMA1 clock enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPAEN</name>
|
|
<description>IPA clock enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETEN</name>
|
|
<description>Ethernet clock enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETTXEN</name>
|
|
<description>Ethernet TX clock enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETRXEN</name>
|
|
<description>Ethernet RX clock enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETPTPEN</name>
|
|
<description>Ethernet PTP clock enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBHSEN</name>
|
|
<description>USBHS clock enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBHSULPIEN</name>
|
|
<description>USBHS ULPI clock enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB2EN</name>
|
|
<displayName>AHB2EN</displayName>
|
|
<description>AHB2 enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCIEN</name>
|
|
<description>DCI clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNGEN</name>
|
|
<description>TRNG clock enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBFSEN</name>
|
|
<description>USBFS clock enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB3EN</name>
|
|
<displayName>AHB3EN</displayName>
|
|
<description>AHB3 clock enable register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXMCEN</name>
|
|
<description>EXMC clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>APB1EN</name>
|
|
<displayName>APB1EN</displayName>
|
|
<description>APB1 clock enable register
|
|
(RCU_APB1EN)</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER1EN</name>
|
|
<description>TIMER1 timer clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2EN</name>
|
|
<description>TIMER2 timer clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3EN</name>
|
|
<description>TIMER3 timer clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER4EN</name>
|
|
<description>TIMER4 timer clock enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER5EN</name>
|
|
<description>TIMER5 timer clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER6EN</name>
|
|
<description>TIMER6 timer clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER11EN</name>
|
|
<description>TIMER11 timer clock enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER12EN</name>
|
|
<description>TIMER12 timer clock enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER13EN</name>
|
|
<description>TIMER13 timer clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGTEN</name>
|
|
<description>Window watchdog timer clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2EN</name>
|
|
<description>SPI2 clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1 clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2EN</name>
|
|
<description>USART2 clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART3EN</name>
|
|
<description>UART3 clock enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4EN</name>
|
|
<description>UART4 clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C0EN</name>
|
|
<description>I2C0 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1EN</name>
|
|
<description>I2C1 clock enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2EN</name>
|
|
<description>I2C2 clock enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN0EN</name>
|
|
<description>CAN0 clock enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN1EN</name>
|
|
<description>CAN1 clock enable </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUEN</name>
|
|
<description>Power control clock enable </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC clock enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART6EN</name>
|
|
<description>UART6 clock enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART7EN</name>
|
|
<description>UART7 clock enable </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2EN</name>
|
|
<displayName>APB2EN</displayName>
|
|
<description>APB2 clock enable register
|
|
(RCU_APB2EN)</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0EN</name>
|
|
<description>TIMER0 clock enable </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER7EN</name>
|
|
<description>TIMER7 clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART0EN</name>
|
|
<description>USART0 clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART5EN</name>
|
|
<description>USART5 clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC0EN</name>
|
|
<description>ADC0 clock enable </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1EN</name>
|
|
<description>ADC1 clock enable </description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC2EN</name>
|
|
<description>ADC2 clock enable </description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIOEN</name>
|
|
<description>SDIO clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI0EN</name>
|
|
<description>SPI0 clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI3EN</name>
|
|
<description>SPI3 clock enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSCFGEN</name>
|
|
<description>SYSCFG clock enable </description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER8EN</name>
|
|
<description>TIMER8 clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER9EN</name>
|
|
<description>TIMER9 clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER10EN</name>
|
|
<description>TIMER10 clock enable </description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4EN</name>
|
|
<description>SPI4 clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI5EN</name>
|
|
<description>SPI5 clock enable </description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLIEN</name>
|
|
<description>TLI clock enable </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB1SPEN</name>
|
|
<displayName>AHB1SPEN</displayName>
|
|
<description>AHB1 sleep mode enable register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7EEF97FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PASPEN</name>
|
|
<description>GPIO port A clock enable when sleep mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBSPEN</name>
|
|
<description>GPIO port B clock enable when sleep mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCSPEN</name>
|
|
<description>GPIO port C clock enable when sleep mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDSPEN</name>
|
|
<description>GPIO port D clock enable when sleep mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PESPEN</name>
|
|
<description>GPIO port E clock enable when sleep mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PFSPEN</name>
|
|
<description>GPIO port F clock enable when sleep mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGSPEN</name>
|
|
<description>GPIO port G clock enable when sleep mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PHSPEN</name>
|
|
<description>GPIO port H clock enable when sleep mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PISPEN</name>
|
|
<description>GPIO port I clock enable when sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCSPEN</name>
|
|
<description>CRC clock enable when sleep mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMCSPEN</name>
|
|
<description>FMC clock enable when sleep mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM0SPEN</name>
|
|
<description>SRAM0 clock enable when sleep mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM1SPEN</name>
|
|
<description>SRAM1 clock enable when sleep mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKPSRAMSPEN</name>
|
|
<description>BKPSRAM clock enable when sleep mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM2SPEN</name>
|
|
<description>SRAM2 clock enable when sleep mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA0SPEN</name>
|
|
<description>DMA0 clock enable when sleep mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA1SPEN</name>
|
|
<description>DMA1 clock enable when sleep mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPASPEN</name>
|
|
<description>IPA clock enable when sleep mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETSPEN</name>
|
|
<description>Ethernet clock enable when sleep mode</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETTXSPEN</name>
|
|
<description>Ethernet TX clock enable when sleep mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETRXSPEN</name>
|
|
<description>Ethernet RX clock enable when sleep mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENETPTPSPEN</name>
|
|
<description>Ethernet PTP clock enable when sleep mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBHSSPEN</name>
|
|
<description>USBHS clock enable when sleep mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBHSULPISPEN</name>
|
|
<description>USBHS ULPI clock enable when sleep mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB2SPEN</name>
|
|
<displayName>AHB2SPEN</displayName>
|
|
<description>AHB2 sleep mode enable register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000C1</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCISPEN</name>
|
|
<description>DCI clock enable when sleep mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNGSPEN</name>
|
|
<description>TRNG clock enable when sleep mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBFSSPEN</name>
|
|
<description>USBFS clock enable when sleep mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>AHB3SPEN</name>
|
|
<displayName>AHB3SPEN</displayName>
|
|
<description>AHB3 Sleep mode enable register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXMCSPEN</name>
|
|
<description>EXMC clock enable when sleep mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>APB1SPEN</name>
|
|
<displayName>APB1SPEN</displayName>
|
|
<description>APB1 sleep mode clock enable register
|
|
(RCU_APB1EN)</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF6FEC9FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER1SPEN</name>
|
|
<description>TIMER1 timer clock enable when sleep mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER2SPEN</name>
|
|
<description>TIMER2 timer clock enable when sleep mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER3SPEN</name>
|
|
<description>TIMER3 timer clock enable when sleep mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER4SPEN</name>
|
|
<description>TIMER4 timer clock enable when sleep mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER5SPEN</name>
|
|
<description>TIMER5 timer clock enable when sleep mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER6SPEN</name>
|
|
<description>TIMER6 timer clock enable when sleep mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER11SPEN</name>
|
|
<description>TIMER11 timer clock enable when sleep mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER12SPEN</name>
|
|
<description>TIMER12 timer clock enable when sleep mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER13SPEN</name>
|
|
<description>TIMER13 timer clock enable when sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGTSPEN</name>
|
|
<description>Window watchdog timer clock enable when sleep mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1SPEN</name>
|
|
<description>SPI1 clock enable when sleep mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2SPEN</name>
|
|
<description>SPI2 clock enable when sleep mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1SPEN</name>
|
|
<description>USART1 clock enable when sleep mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2SPEN</name>
|
|
<description>USART2 clock enable when sleep mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART3SPEN</name>
|
|
<description>UART3 clock enable when sleep mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4SPEN</name>
|
|
<description>UART4 clock enable when sleep mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C0SPEN</name>
|
|
<description>I2C0 clock enable when sleep mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1SPEN</name>
|
|
<description>I2C1 clock enable when sleep mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2SPEN</name>
|
|
<description>I2C2 clock enable when sleep mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN0SPEN</name>
|
|
<description>CAN0 clock enable when sleep mode</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAN1SPEN</name>
|
|
<description>CAN1 clock enable when sleep mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMUSPEN</name>
|
|
<description>Power control clock enable when sleep mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSPEN</name>
|
|
<description>DAC clock enable when sleep mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART6SPEN</name>
|
|
<description>UART6 clock enable when sleep mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART7SPEN</name>
|
|
<description>UART7 clock enable when sleep mode</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2SPEN</name>
|
|
<displayName>APB2SPEN</displayName>
|
|
<description>APB2 sleep mode enable register
|
|
(RCU_APB2SPEN)</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x04777F33</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER0SPEN</name>
|
|
<description>TIMER0 clock enable when sleep mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER7SPEN</name>
|
|
<description>TIMER7 clock enable when sleep mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART0SPEN</name>
|
|
<description>USART0 clock enable when sleep mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART5SPEN</name>
|
|
<description>USART5 clock enable when sleep mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC0SPEN</name>
|
|
<description>ADC0 clock enable when sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1SPEN</name>
|
|
<description>ADC1 clock enable when sleep mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC2SPEN</name>
|
|
<description>ADC2 clock enable when sleep mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIOSPEN</name>
|
|
<description>SDIO clock enable when sleep mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI0SPEN</name>
|
|
<description>SPI0 clock enable when sleep mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI3SPEN</name>
|
|
<description>SPI3 clock enable when sleep mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSCFGSPEN</name>
|
|
<description>SYSCFG clock enable when sleep mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER8SPEN</name>
|
|
<description>TIMER8 clock enable when sleep mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER9SPEN</name>
|
|
<description>TIMER9 clock enable when sleep mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMER10SPEN</name>
|
|
<description>TIMER10 clock enable when sleep mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4SPEN</name>
|
|
<description>SPI4 clock enable when sleep mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI5SPEN</name>
|
|
<description>SPI5 clock enable when sleep mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLISPEN</name>
|
|
<description>TLI clock enable when sleep mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDCTL</name>
|
|
<displayName>BDCTL</displayName>
|
|
<description>Backup domain control register
|
|
(RCU_BDCTL)</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LXTALEN</name>
|
|
<description>LXTAL enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALSTB</name>
|
|
<description>External low-speed oscillator stabilization</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALBPS</name>
|
|
<description>LXTAL bypass mode enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LXTALDRI</name>
|
|
<description>LXTAL drive capability</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCSRC</name>
|
|
<description>RTC clock entry selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCEN</name>
|
|
<description>RTC clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKPRST</name>
|
|
<description>Backup domain reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTSCK</name>
|
|
<displayName>RSTSCK</displayName>
|
|
<description>Reset source /clock register
|
|
(RCU_RSTSCK)</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0E000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRC32KEN</name>
|
|
<description>IRC32K enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC32KSTB</name>
|
|
<description>IRC32K stabilization</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTFC</name>
|
|
<description>Reset flag clear</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BORRSTF</name>
|
|
<description>BOR reset flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPRSTF</name>
|
|
<description>External PIN reset flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PORRSTF</name>
|
|
<description>Power reset flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRSTF</name>
|
|
<description>Software reset flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FWDGTRSTF</name>
|
|
<description>Free Watchdog timer reset flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WWDGTRSTF</name>
|
|
<description>Window watchdog timer reset flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LPRSTF</name>
|
|
<description>Low-power reset flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSSCTL</name>
|
|
<displayName>PLLSSCTL</displayName>
|
|
<description>PLL clock spread spectrum control register
|
|
(RCU_PLLSSCTL)</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODCNT</name>
|
|
<description>configure PLL spread spectrum modulation profile amplitude and
|
|
frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODSTEP</name>
|
|
<description>configure PLL spread spectrum modulation profile amplitude and
|
|
frequency</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SS_TYPE</name>
|
|
<description>PLL spread spectrum modulation type select</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSCGON</name>
|
|
<description>PLL spread spectrum modulation enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLI2S</name>
|
|
<displayName>PLLI2S</displayName>
|
|
<description>PLLI2S register
|
|
(RCU_PLLI2S)</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>24003000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLI2SPSC</name>
|
|
<description>The PLLI2S VCO source clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SN</name>
|
|
<description>The PLLI2S VCO clock multi factor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SQ</name>
|
|
<description>The PLLI2S Q output frequency division factor from PLLI2S VCO clock</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLI2SR</name>
|
|
<description>The PLLI2S R output frequency division factor from PLLI2S VCO clock</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSAI</name>
|
|
<displayName>PLLSAI</displayName>
|
|
<description>PLLSAI register
|
|
(RCU_PLLSAI)</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>24003010</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSAIN</name>
|
|
<description>The PLLSAI VCO clock multi factor</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAIP</name>
|
|
<description>The PLLSAI P output frequency division factor from PLLSAI VCO clock</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAIQ</name>
|
|
<description>The PLLI2S Q output frequency division factor from PLLI2S VCO clock</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSAIR</name>
|
|
<description>The PLLSAI R output frequency division factor from PLLSAI VCO clock</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<displayName>CFG1</displayName>
|
|
<description>Clock Configuration register 1</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSAIRDIV</name>
|
|
<description>The divider factor from PLLSAIR clock</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMERSEL</name>
|
|
<description>TIMER clock selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDCTL</name>
|
|
<displayName>ADDCTL</displayName>
|
|
<description>Additional clock control register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CK48MSEL</name>
|
|
<description>48MHz clock selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLL48MSEL</name>
|
|
<description>PLL48M clock selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC48MEN</name>
|
|
<description>Internal 48MHz RC oscillator enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC48MSTB</name>
|
|
<description>Internal 48MHz RC oscillator clock stabilization Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC48MCAL</name>
|
|
<description>Internal 48MHz RC oscillator calibration value register</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>ADDINT</name>
|
|
<displayName>ADDINT</displayName>
|
|
<description>Additional clock interrupt register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IRC48MSTBIF</name>
|
|
<description>IRC48M stabilization interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC48MSTBIE</name>
|
|
<description>Internal 48 MHz RC oscillator Stabilization Interrupt Enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRC48MSTBIC</name>
|
|
<description>Internal 48 MHz RC oscillator Stabilization Interrupt Clear</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>ADDAPB1RST</name>
|
|
<displayName>ADDAPB1RST</displayName>
|
|
<description>APB1 additional reset register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTCRST</name>
|
|
<description>CTC reset</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREFRST</name>
|
|
<description>IREF reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>ADDAPB1EN</name>
|
|
<displayName>ADDAPB1EN</displayName>
|
|
<description>APB1 additional enable register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTCEN</name>
|
|
<description>CTC clock enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREFEN</name>
|
|
<description>IREF interface clock enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADDAPB1SPEN</name>
|
|
<displayName>ADDAPB1SPEN</displayName>
|
|
<description>APB1 additional sleep mode enable register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x88000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTCSPEN</name>
|
|
<description>CTC enable when sleep mode</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREFSPEN</name>
|
|
<description>IREF enable when sleep mode</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VKEY</name>
|
|
<displayName>VKEY</displayName>
|
|
<description>Voltage key register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>The key of RCU_DSV registe</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSV</name>
|
|
<displayName>DSV</displayName>
|
|
<description>Deep sleep mode Voltage register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DSLPVS</name>
|
|
<description>Deep-sleep mode voltage select</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real-time clock</description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC_T amper</name>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTC_WKUP</name>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTC_Alarm</name>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIME</name>
|
|
<displayName>TIME</displayName>
|
|
<description>time register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM notation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRT</name>
|
|
<description>Hour tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRU</name>
|
|
<description>Hour units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCT</name>
|
|
<description>Second tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCU</name>
|
|
<description>Second units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATE</name>
|
|
<displayName>DATE</displayName>
|
|
<description>date register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>YRT</name>
|
|
<description>Year tens in BCD code</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YRU</name>
|
|
<description>Year units in BCD code</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Days of the week</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONT</name>
|
|
<description>Month tens in BCD code</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONU</name>
|
|
<description>Month units in BCD code</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYT</name>
|
|
<description>Date tens in BCD code</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYU</name>
|
|
<description>Date units in BCD code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WTCS</name>
|
|
<description>Auto-wakeup timer clock selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEG</name>
|
|
<description>Valid event edge of time-stamp</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFEN</name>
|
|
<description>Reference clock detection function enable
|
|
enable (50 or 60 Hz)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BPSHAD</name>
|
|
<description>Shadow registers bypass control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CS</name>
|
|
<description>Clock System</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCEN</name>
|
|
<description>Coarse calibration function enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM0EN</name>
|
|
<description>Alarm-0 function enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM1EN</name>
|
|
<description>Alarm-1 function enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WTEN</name>
|
|
<description>Auto-wakeup timer function enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Time-stamp function enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM0IE</name>
|
|
<description>RTC alarm-0 interrupt enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM1IE</name>
|
|
<description>RTC alarm-1 interrupt enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WTIE</name>
|
|
<description>Auto-wakeup timer interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSIE</name>
|
|
<description>Time-stamp interrupt
|
|
enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>A1H</name>
|
|
<description>Add 1 hour (summer time
|
|
change)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>S1H</name>
|
|
<description>Subtract 1 hour (winter time
|
|
change)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DSM</name>
|
|
<description>Daylight saving mark</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COS</name>
|
|
<description>Calibration output
|
|
selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPOL</name>
|
|
<description>Output polarity</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OS</name>
|
|
<description>Output selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COEN</name>
|
|
<description>Calibration output enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description> status
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALRM0WF</name>
|
|
<description>Alarm 0 configuration can be write flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM1WF</name>
|
|
<description>Alarm 1 configuration can be write flag </description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WTWF</name>
|
|
<description>Wakeup timer write enable flag </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOPF</name>
|
|
<description>Shift function operation pending flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>YCM</name>
|
|
<description>Year configuration mark</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSYNF</name>
|
|
<description>Register synchronization flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITF</name>
|
|
<description>Initialization state flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INITM</name>
|
|
<description>Enter initialization mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM0F</name>
|
|
<description>Alarm-0 occurs flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRM1F</name>
|
|
<description>Alarm-1 occurs flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WTF</name>
|
|
<description>Wakeup timer flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSF</name>
|
|
<description>Time-stamp flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSOVRF</name>
|
|
<description>Time-stamp overflow flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TP0F</name>
|
|
<description>RTC_TAMP0 detected flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TP1F</name>
|
|
<description>RTC_TAMP1 detected flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCPF</name>
|
|
<description>Smooth calibration pending flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x007F00FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FACTOR_A</name>
|
|
<description>Asynchronous prescaler
|
|
factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACTOR_S</name>
|
|
<description>Synchronous prescaler
|
|
factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WUT</name>
|
|
<displayName>WUT</displayName>
|
|
<description>Wakeup timer register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WTRV</name>
|
|
<description>Auto-wakeup timer reloads value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COSC</name>
|
|
<displayName>COSC</displayName>
|
|
<description>Coarse calibration register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COSS</name>
|
|
<description>Coarse Calibration step</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COSD</name>
|
|
<description>Coarse Calibration direction</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRM0TD</name>
|
|
<displayName>ALRM0TD</displayName>
|
|
<description>Alarm 0 time and date register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSKD</name>
|
|
<description>Alarm date mask bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOWS</name>
|
|
<description>Day of the week selected</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYT</name>
|
|
<description>Date tens in BCD code.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYU</name>
|
|
<description>Date units or week day in BCD
|
|
code.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKH</name>
|
|
<description>Alarm hours mask bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRT</name>
|
|
<description>Hour tens in BCD code.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRU</name>
|
|
<description>Hour units in BCD code.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKM</name>
|
|
<description>Alarm minutes mask bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD code.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD
|
|
code.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKS</name>
|
|
<description>Alarm seconds mask bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCT</name>
|
|
<description>Second tens in BCD code.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCU</name>
|
|
<description>Second units in BCD
|
|
code.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRM1TD</name>
|
|
<displayName>ALRM1TD</displayName>
|
|
<description>Alarm 1 time and date register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSKD</name>
|
|
<description>Alarm date mask bit</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DOWS</name>
|
|
<description>Day of the week selected</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYT</name>
|
|
<description>Date tens in BCD code.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYU</name>
|
|
<description>Date units or week day in BCD
|
|
code.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKH</name>
|
|
<description>Alarm hours mask bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRT</name>
|
|
<description>Hour tens in BCD code.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRU</name>
|
|
<description>Hour units in BCD code.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKM</name>
|
|
<description>Alarm minutes mask bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD code.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD
|
|
code.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSKS</name>
|
|
<description>Alarm seconds mask bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCT</name>
|
|
<description>Second tens in BCD code.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCU</name>
|
|
<description>Second units in BCD
|
|
code.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPK</name>
|
|
<displayName>WPK</displayName>
|
|
<description>write protection register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WPK</name>
|
|
<description>Write protection key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SS</name>
|
|
<displayName>SS</displayName>
|
|
<description>sub second register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SSC</name>
|
|
<description>Sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTCTL</name>
|
|
<displayName>SHIFTCTL</displayName>
|
|
<description>shift function control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>A1S</name>
|
|
<description>One second add</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFS</name>
|
|
<description>Subtract a fraction of a
|
|
second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTS</name>
|
|
<displayName>TTS</displayName>
|
|
<description>Time of time stamp register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM mark</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRT</name>
|
|
<description>Hour tens in BCD code.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRU</name>
|
|
<description>Hour units in BCD code.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD code.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD
|
|
code.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCT</name>
|
|
<description>Second tens in BCD code.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCU</name>
|
|
<description>Second units in BCD
|
|
code.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTS</name>
|
|
<displayName>DTS</displayName>
|
|
<description>Date of time stamp register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DOW</name>
|
|
<description>Week day units</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONT</name>
|
|
<description>Month tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONU</name>
|
|
<description>Month units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYT</name>
|
|
<description>Date tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAYU</name>
|
|
<description>Date units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSTS</name>
|
|
<displayName>SSTS</displayName>
|
|
<description>Sub second of time stamp register </description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SSC</name>
|
|
<description>Sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HRFC</name>
|
|
<displayName>HRFC</displayName>
|
|
<description>calibration register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FREQI</name>
|
|
<description>Increase RTC frequency by 488.5PPM</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWND8</name>
|
|
<description>Frequency compensation window 8 second selected</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWND16</name>
|
|
<description>Frequency compensation window 16 second selected</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMSK</name>
|
|
<description>Calibration mask number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMP</name>
|
|
<displayName>TAMP</displayName>
|
|
<description>tamper and alternate function configuration
|
|
register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AOT</name>
|
|
<description>RTC_ALARM Output Type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSSEL</name>
|
|
<description>Timestamp input mapping selection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TP0SEL</name>
|
|
<description>Tamper 0 function input mapping selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISPU</name>
|
|
<description>RTC_TAMPx pull-up disable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRCH</name>
|
|
<description>Pre-charge duration time of RTC_TAMPx</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT</name>
|
|
<description>RTC_TAMPx filter count setting</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>Sampling frequency of tamper event detection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TPTS</name>
|
|
<description>Make tamper function used for timestamp function</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TP1EG</name>
|
|
<description>Tamper 1 event trigger edge</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TP1EN</name>
|
|
<description>Tamper 1 detection enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TPIE</name>
|
|
<description>Tamper detection interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TP0EG</name>
|
|
<description>Tamper 0 event trigger edge</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TP0EN</name>
|
|
<description>Tamper 0 detection enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRM0SS</name>
|
|
<displayName>ALRM0SS</displayName>
|
|
<description>alarm A sub second register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSKSSC</name>
|
|
<description>Mask control bit of SSC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSC</name>
|
|
<description>Alarm sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRM1SS</name>
|
|
<displayName>ALRM1SS</displayName>
|
|
<description>Alarm 1 sub second register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSKSSC</name>
|
|
<description>Mask control bit of SSC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSC</name>
|
|
<description>Alarm sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP0</name>
|
|
<displayName>BKP0</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP1</name>
|
|
<displayName>BKP1</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP2</name>
|
|
<displayName>BKP2</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP3</name>
|
|
<displayName>BKP3</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP4</name>
|
|
<displayName>BKP4</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP5</name>
|
|
<displayName>BKP5</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP6</name>
|
|
<displayName>BKP6</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP7</name>
|
|
<displayName>BKP7</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP8</name>
|
|
<displayName>BKP8</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP9</name>
|
|
<displayName>BKP9</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP10</name>
|
|
<displayName>BKP10</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP11</name>
|
|
<displayName>BKP11</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP12</name>
|
|
<displayName>BKP12</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP13</name>
|
|
<displayName>BKP13</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP14</name>
|
|
<displayName>BKP14</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP15</name>
|
|
<displayName>BKP15</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP16</name>
|
|
<displayName>BKP16</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP17</name>
|
|
<displayName>BKP7</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP18</name>
|
|
<displayName>BKP18</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP19</name>
|
|
<displayName>BKP19</displayName>
|
|
<description>backup register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SDIO</name>
|
|
<description>Secure digital input/output
|
|
interface</description>
|
|
<groupName>SDIO</groupName>
|
|
<baseAddress>0x40012C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SDIO</name>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>PWRCTL</name>
|
|
<displayName>PWRCTL</displayName>
|
|
<description>Power control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWRCTL</name>
|
|
<description>SDIO power control bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKCTL</name>
|
|
<displayName>CLKCTL</displayName>
|
|
<description>Clock control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_8</name>
|
|
<description>MSB of Clock division</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HWCLKEN</name>
|
|
<description>Hardware Clock Control enable bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKEDGE</name>
|
|
<description>SDIO_CLK clock edge selection bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSMODE</name>
|
|
<description>SDIO card bus mode control bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKBYP</name>
|
|
<description>Clock bypass enable bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKPWRSAV</name>
|
|
<description>SDIO_CLK clock dynamic switch on/off for
|
|
power saving</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>SDIO_CLK clock output enable bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_7</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDAGMT</name>
|
|
<displayName>CMDAGMT</displayName>
|
|
<description>Command argument register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDAGMT</name>
|
|
<description>SDIO card command argument</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMDCTL</name>
|
|
<displayName>CMDCTL</displayName>
|
|
<description>Command control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMDIDX</name>
|
|
<description>Command index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRESP</name>
|
|
<description>Command response type bits</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTWAIT</name>
|
|
<description>Interrupt wait instead of timeout</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITDEND</name>
|
|
<description>Waits for ends of data transfer</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSMEN</name>
|
|
<description>Command state machine (CSM) enable bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSPEND</name>
|
|
<description>SD I/O suspend command(SD I/O only)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENCMDC</name>
|
|
<description>CMD completion signal enabled (CE-ATA only)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NINTEN</name>
|
|
<description>No CE-ATA Interrupt (CE-ATA only)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATAEN</name>
|
|
<description>CE-ATA command enable(CE-ATA only)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSPCMDIDX</name>
|
|
<displayName>RSPCMDIDX</displayName>
|
|
<description>Command index response register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSPCMDIDX</name>
|
|
<description>Last response command index</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP0</name>
|
|
<displayName>RESP0</displayName>
|
|
<description>Response register 0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESP0</name>
|
|
<description>Card state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP1</name>
|
|
<displayName>RESP1</displayName>
|
|
<description>Response register 1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESP1</name>
|
|
<description>Card state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP2</name>
|
|
<displayName>RESP2</displayName>
|
|
<description>Response register 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESP2</name>
|
|
<description>Card state</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESP3</name>
|
|
<displayName>RESP3</displayName>
|
|
<description>Response register 3</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESP3</name>
|
|
<description>Response register 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATATO</name>
|
|
<displayName>DATATO</displayName>
|
|
<description>Data timeout register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATATO</name>
|
|
<description>Data timeout period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATALEN</name>
|
|
<displayName>DATALEN</displayName>
|
|
<description>Data length register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATALEN</name>
|
|
<description>Data transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATACTL</name>
|
|
<displayName>DATACTL</displayName>
|
|
<description>Data control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAEN</name>
|
|
<description>Data transfer enabled bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATADIR</name>
|
|
<description>Data transfer direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRANSMOD</name>
|
|
<description>Data transfer mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLKSZ</name>
|
|
<description>Data block size</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWEN</name>
|
|
<description>Read wait mode enabled</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWSTOP</name>
|
|
<description>Read wait stop</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWTYPE</name>
|
|
<description>Read wait type</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOEN</name>
|
|
<description>SD I/O specific function enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATACNT</name>
|
|
<displayName>DATACNT</displayName>
|
|
<description>Data counter register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATACNT</name>
|
|
<description>Data count value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>25</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCRCERR</name>
|
|
<description>Command response received</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCRCERR</name>
|
|
<description>Data block sent/received</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDTMOUT</name>
|
|
<description>Command response timeout</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTTMOUT</name>
|
|
<description>Data timeout</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXURE</name>
|
|
<description>Transmit FIFO underrun error occurs</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXORE</name>
|
|
<description>Received FIFO overrun error occurs</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRECV</name>
|
|
<description>Command response received</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDSEND</name>
|
|
<description>Command sent</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEND</name>
|
|
<description>Data end</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STBITE</name>
|
|
<description>Start bit error in the bus</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTBLKEND</name>
|
|
<description>Data block sent/received</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRUN</name>
|
|
<description>Command transmission in progress</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRUN</name>
|
|
<description>Data transmission in progress</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXRUN</name>
|
|
<description>Data reception in progress</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFH</name>
|
|
<description>Transmit FIFO is half empty</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFH</name>
|
|
<description>Receive FIFO is half full</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFF</name>
|
|
<description>Transmit FIFO is full</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFF</name>
|
|
<description>Receive FIFO is full</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>Transmit FIFO is empty</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFE</name>
|
|
<description>Receive FIFO is empty</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDTVAL</name>
|
|
<description>Data is valid in transmit FIFO</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDTVAL</name>
|
|
<description>Data is valid in receive FIFO</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIOINT</name>
|
|
<description>SD I/O interrupt received</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATAEND</name>
|
|
<description>CE-ATA command completion signal received</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC</name>
|
|
<displayName>INTC</displayName>
|
|
<description>Interrupt clear register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCRCERRC</name>
|
|
<description>CCRCERR flag clear bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCRCERRC</name>
|
|
<description>DTCRCERR flag clear bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDTMOUTC</name>
|
|
<description>CMDTMOUT flag clear bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTTMOUTC</name>
|
|
<description>DTTMOUT flag clear bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUREC</name>
|
|
<description>TXURE flag clear bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOREC</name>
|
|
<description>RXORE flag clear bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRECVC</name>
|
|
<description>CMDRECV flag clear bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDSENDC</name>
|
|
<description>CMDSEND flag clear bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTENDC</name>
|
|
<description>DTEND flag clear bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STBITEC</name>
|
|
<description>STBITE flag clear bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTBLKENDC</name>
|
|
<description>DTBLKEND flag clear bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIOINTC</name>
|
|
<description>SDIOINT flag clear bit</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATAENDC</name>
|
|
<description>ATAEND flag clear bit</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<displayName>INTEN</displayName>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCRCERRIE</name>
|
|
<description>Command response CRC fail interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCRCERRIE</name>
|
|
<description>Data CRC fail interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDTMOUTIE</name>
|
|
<description>Command response timeout interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTTMOUTIE</name>
|
|
<description>Data timeout interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUREIE</name>
|
|
<description>Transmit FIFO underrun error interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOREIE</name>
|
|
<description>Received FIFO overrun error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRECVIE</name>
|
|
<description>Command response received interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDSENDIE</name>
|
|
<description>Command sent interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTENDIE</name>
|
|
<description>Data end interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STBITEIE</name>
|
|
<description>Start bit error interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTBLKENDIE</name>
|
|
<description>Data block end interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMDRUNIE</name>
|
|
<description>Command transmission interrupt enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXRUNIE</name>
|
|
<description>Data transmission interrupt enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXRUNIE</name>
|
|
<description>Data reception interrupt enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFHIE</name>
|
|
<description>Transmit FIFO half empty interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFHIE</name>
|
|
<description>Receive FIFO half full interrupt enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFFIE</name>
|
|
<description>Transmit FIFO full interrupt enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFFIE</name>
|
|
<description>Receive FIFO full interrupt enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFEIE</name>
|
|
<description>Transmit FIFO empty interrupt enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RFEIE</name>
|
|
<description>Receive FIFO empty interrupt enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDTVALIE</name>
|
|
<description>Data valid in transmit FIFO interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDTVALIE</name>
|
|
<description>Data valid in receive FIFO interrupt enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDIOINTIE</name>
|
|
<description>SD I/O interrupt received interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATAENDIE</name>
|
|
<description>CE-ATA command completion signal received
|
|
interrupt enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFOCNT</name>
|
|
<displayName>FIFOCNT</displayName>
|
|
<description>FIFO counter register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFOCNT</name>
|
|
<description>FIFO counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FIFO</name>
|
|
<displayName>FIFO</displayName>
|
|
<description>FIFO data register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FIFODT</name>
|
|
<description>Receive FIFO data or transmit FIFO data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI0</name>
|
|
<description>Serial peripheral interface</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI0</name>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BDEN</name>
|
|
<description>Bidirectional
|
|
enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BDOEN</name>
|
|
<description>Bidirectional Transmit output enable
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC Calculation Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCNT</name>
|
|
<description>CRC Next Transfer</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF16</name>
|
|
<description>Data frame format</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RO</name>
|
|
<description>Receive only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWNSSEN</name>
|
|
<description>NSS Software Mode Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWNSS</name>
|
|
<description>NSS Pin Selection In NSS Software Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LF</name>
|
|
<description>LSB First Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Master Clock Prescaler Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTMOD</name>
|
|
<description>Master Mode Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPL</name>
|
|
<description>Clock polarity Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPH</name>
|
|
<description>Clock Phase Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBEIE</name>
|
|
<description>Tx buffer empty interrupt
|
|
enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNEIE</name>
|
|
<description>RX buffer not empty interrupt
|
|
enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMOD</name>
|
|
<description>SPI TI Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSSDRV</name>
|
|
<description>Drive NSS Output</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMATEN</name>
|
|
<description>Transmit Buffer DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAREN</name>
|
|
<description>Rx buffer DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Format Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS</name>
|
|
<description>Transmitting On-going Bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXORERR</name>
|
|
<description>Reception Overrun Error Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONFERR</name>
|
|
<description>SPI Configuration error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>SPI CRC Error Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXURERR</name>
|
|
<description>Transmission underrun error bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SCH</name>
|
|
<description>I2S channel side</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>Transmit Buffer Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RBNE</name>
|
|
<description>Receive Buffer Not Empty</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_DATA</name>
|
|
<description>Data transfer register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPCPOLY</name>
|
|
<displayName>CPCPOLY</displayName>
|
|
<description>CRC polynomial register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>CRC polynomial register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCRC</name>
|
|
<displayName>RCRC</displayName>
|
|
<description>RX CRC register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RCR</name>
|
|
<description>RX CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCRC</name>
|
|
<displayName>TCRC</displayName>
|
|
<description>TX CRC register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Tx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCTL</name>
|
|
<displayName>I2SCTL</displayName>
|
|
<description>I2S control register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SSEL</name>
|
|
<description>I2S mode selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SEN</name>
|
|
<description>I2S Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SOPMOD</name>
|
|
<description>I2S operation mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCMSMOD</name>
|
|
<description>PCM frame synchronization mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>I2S standard selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPL</name>
|
|
<description>Idle state clock polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTLEN</name>
|
|
<description>Data length</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>Channel length (number of bits per audio
|
|
channel)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPSC</name>
|
|
<displayName>I2SPSC</displayName>
|
|
<description>I2S prescaler register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCKOEN</name>
|
|
<description>I2S_MCK output enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Odd factor for the
|
|
prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Dividing factor for the prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI1</name>
|
|
<baseAddress>0x40003800</baseAddress>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<value>36</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI2</name>
|
|
<baseAddress>0x40003C00</baseAddress>
|
|
<interrupt>
|
|
<name>SPI2</name>
|
|
<value>51</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI3</name>
|
|
<baseAddress>0x40013400</baseAddress>
|
|
<interrupt>
|
|
<name>SPI3</name>
|
|
<value>84</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>SPI4</name>
|
|
<baseAddress>0x40015000</baseAddress>
|
|
<interrupt>
|
|
<name>SPI4</name>
|
|
<value>85</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI5</name>
|
|
<description>Serial peripheral interface</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40015400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI5</name>
|
|
<value>86</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BDEN</name>
|
|
<description>Bidirectional
|
|
enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BDOEN</name>
|
|
<description>Bidirectional Transmit output enable
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC Calculation Enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCNT</name>
|
|
<description>CRC Next Transfer</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FF16</name>
|
|
<description>Data frame format</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RO</name>
|
|
<description>Receive only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWNSSEN</name>
|
|
<description>NSS Software Mode Selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWNSS</name>
|
|
<description>NSS Pin Selection In NSS Software Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LF</name>
|
|
<description>LSB First Mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPIEN</name>
|
|
<description>SPI enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Master Clock Prescaler Selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTMOD</name>
|
|
<description>Master Mode Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPL</name>
|
|
<description>Clock polarity Selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPH</name>
|
|
<description>Clock Phase Selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBEIE</name>
|
|
<description>Tx buffer empty interrupt
|
|
enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNEIE</name>
|
|
<description>RX buffer not empty interrupt
|
|
enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TMOD</name>
|
|
<description>SPI TI Mode Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSSDRV</name>
|
|
<description>Drive NSS Output</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMATEN</name>
|
|
<description>Transmit Buffer DMA Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAREN</name>
|
|
<description>Rx buffer DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Format Error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRANS</name>
|
|
<description>Transmitting On-going Bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXORERR</name>
|
|
<description>Reception Overrun Error Bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CONFERR</name>
|
|
<description>SPI Configuration error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>SPI CRC Error Bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXURERR</name>
|
|
<description>Transmission underrun error bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SCH</name>
|
|
<description>I2S channel side</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>Transmit Buffer Empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RBNE</name>
|
|
<description>Receive Buffer Not Empty</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPI_DATA</name>
|
|
<description>Data transfer register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPCPOLY</name>
|
|
<displayName>CPCPOLY</displayName>
|
|
<description>CRC polynomial register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPR</name>
|
|
<description>CRC polynomial register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCRC</name>
|
|
<displayName>RCRC</displayName>
|
|
<description>RX CRC register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RCR</name>
|
|
<description>RX CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TCRC</name>
|
|
<displayName>TCRC</displayName>
|
|
<description>TX CRC register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Tx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCTL</name>
|
|
<displayName>I2SCTL</displayName>
|
|
<description>I2S control register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SSEL</name>
|
|
<description>I2S mode selection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SEN</name>
|
|
<description>I2S Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SOPMOD</name>
|
|
<description>I2S operation mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCMSMOD</name>
|
|
<description>PCM frame synchronization mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>I2S standard selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPL</name>
|
|
<description>Idle state clock polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTLEN</name>
|
|
<description>Data length to be
|
|
transferred</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>Channel length (number of bits per audio
|
|
channel)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPSC</name>
|
|
<displayName>I2SPSC</displayName>
|
|
<description>I2S prescaler register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCKOEN</name>
|
|
<description>I2S_MCK output enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Odd factor for the
|
|
prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>Dividing factor for the prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QCTL</name>
|
|
<displayName>QCTL</displayName>
|
|
<description>Quad-SPI mode control register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IO23_DRV</name>
|
|
<description>Drive IO2 and IO3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QRD</name>
|
|
<description>Quad-SPI mode read select</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QMOD</name>
|
|
<description>Quad-SPI mode enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>I2S1_add</name>
|
|
<baseAddress>0x40003400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI0">
|
|
<name>I2S2_add</name>
|
|
<baseAddress>0x40004000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCFG</name>
|
|
<description>System configuration controller</description>
|
|
<groupName>SYSCFG</groupName>
|
|
<baseAddress>0x40013800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x0400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CFG0</name>
|
|
<displayName>CFG0</displayName>
|
|
<description>Configuration register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXMC_SWP</name>
|
|
<description>EXMC memory mapping swap</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FMC_SWP</name>
|
|
<description>FMC memory mapping swap </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_MODE</name>
|
|
<description>Boot mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<displayName>CFG1</displayName>
|
|
<description>Configuration register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENET_PHY_SEL</name>
|
|
<description>Ethernet PHY selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTISS0</name>
|
|
<displayName>EXTISS0</displayName>
|
|
<description>EXTI sources selection register
|
|
0</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI3_SS</name>
|
|
<description>EXTI 3 sources selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI2_SS</name>
|
|
<description>EXTI 2 sources selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI1_SS</name>
|
|
<description>EXTI 1 sources selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI0_SS</name>
|
|
<description>EXTI 0 sources selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTISS1</name>
|
|
<displayName>EXTISS1</displayName>
|
|
<description>EXTI sources selection register
|
|
1</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI7_SS</name>
|
|
<description>EXTI 7 sources selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI6_SS</name>
|
|
<description>EXTI 6 sources selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI5_SS</name>
|
|
<description>EXTI 5 sources selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI4_SS</name>
|
|
<description>EXTI 4 sources selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTISS2</name>
|
|
<displayName>EXTISS2</displayName>
|
|
<description>EXTI sources selection register
|
|
2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI11_SS</name>
|
|
<description>EXTI 11 sources selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI10_SS</name>
|
|
<description>EXTI 10 sources selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI9_SS</name>
|
|
<description>EXTI 9 sources selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI8_SS</name>
|
|
<description>EXTI 8 sources selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTISS3</name>
|
|
<displayName>EXTISS3</displayName>
|
|
<description>EXTI sources selection register
|
|
3</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI15_SS</name>
|
|
<description>EXTI 15 sources selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI14_SS</name>
|
|
<description>EXTI 14 sources selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI13_SS</name>
|
|
<description>EXTI 13 sources selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI12_SS</name>
|
|
<description>EXTI 12 sources selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPSCTL</name>
|
|
<displayName>CPSCTL</displayName>
|
|
<description>I/O compensation control register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPS_RDY</name>
|
|
<description>I/O compensation cell is ready or not</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPS_EN</name>
|
|
<description>I/O compensation cell enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description>Advanced-timers</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0_BRK_TIMER8</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER0_UP_TIMER9</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER0_TRG_CMT_TIMER10</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER0_CC</name>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARSE</name>
|
|
<description>Auto-reload shadow enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAM</name>
|
|
<description>Counter aligns mode
|
|
selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPM</name>
|
|
<description>Single pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPS</name>
|
|
<description>Update source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ISO3</name>
|
|
<description>Idle state of channel 3 output</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO2N</name>
|
|
<description>Idle state of channel 2 complementary output</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO2</name>
|
|
<description>Idle state of channel 2 output</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO1N</name>
|
|
<description>Idle state of channel 1 complementary output</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO1</name>
|
|
<description>Idle state of channel 1 output</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO0N</name>
|
|
<description>Idle state of channel 0 complementary output</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO0</name>
|
|
<description>Idle state of channel 0 output</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI0S</name>
|
|
<description>Channel 0 trigger input selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMC</name>
|
|
<description>Master mode control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAS</name>
|
|
<description>DMA request source selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCUC</name>
|
|
<description>Commutation control shadow register update control</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCSE</name>
|
|
<description>Commutation control shadow enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCFG</name>
|
|
<displayName>SMCFG</displayName>
|
|
<description>slave mode configuration register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>External trigger polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCM1</name>
|
|
<description>Part of SMC for enable External clock mode1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETPSC</name>
|
|
<description>External trigger prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETFC</name>
|
|
<description>External trigger filter control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master/Slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMC</name>
|
|
<description>Slave mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<displayName>DMAINTEN</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGDEN</name>
|
|
<description>Trigger DMA request enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMTDEN</name>
|
|
<description>Commutation DMA request enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3DEN</name>
|
|
<description>Channel 3 capture/compare DMA request enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2DEN</name>
|
|
<description>Channel 2 capture/compare DMA request enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1DEN</name>
|
|
<description>Channel 1 capture/compare DMA request enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0DEN</name>
|
|
<description>Channel 0 capture/compare DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDEN</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKIE</name>
|
|
<description>Break interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMTIE</name>
|
|
<description>commutation interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3IE</name>
|
|
<description>Channel 3 capture/compare interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2IE</name>
|
|
<description>Channel 2 capture/compare interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IE</name>
|
|
<description>Channel 1 capture/compare interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IE</name>
|
|
<description>Channel 0 capture/compare interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>Interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3OF</name>
|
|
<description>Channel 3 over capture flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2OF</name>
|
|
<description>Channel 2 over capture flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1OF</name>
|
|
<description>Channel 1 over capture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0OF</name>
|
|
<description>Channel 0 over capture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKIF</name>
|
|
<description>Break interrupt flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMTIF</name>
|
|
<description>Channel commutation interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3IF</name>
|
|
<description>Channel 3 capture/compare interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2IF</name>
|
|
<description> Channel 2 capture/compare interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IF</name>
|
|
<description>Channel 1 capture/compare interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IF</name>
|
|
<description>Channel 0 capture/compare interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVG</name>
|
|
<displayName>SWEVG</displayName>
|
|
<description>Software event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BRKG</name>
|
|
<description>Break event generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGG</name>
|
|
<description>Trigger event generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMTG</name>
|
|
<description>Channel commutation event generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3G</name>
|
|
<description>Channel 3 capture or compare event generation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2G</name>
|
|
<description>Channel 2 capture or compare event generation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1G</name>
|
|
<description>Channel 1 capture or compare event generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0G</name>
|
|
<description>Channel 0 capture or compare event generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPG</name>
|
|
<description>Update event generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Output</name>
|
|
<displayName>CHCTL0_Output</displayName>
|
|
<description>Channel control register 0 (output
|
|
mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1COMCEN</name>
|
|
<description>Channel 1 output compare clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMCTL</name>
|
|
<description>Channel 1 compare output control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMSEN</name>
|
|
<description>Channel 1 output compare shadow enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMFEN</name>
|
|
<description>Channel 1 output compare fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCEN</name>
|
|
<description>Channel 0 output compare clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCTL</name>
|
|
<description>Channel 0 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMSEN</name>
|
|
<description>Channel 0 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMFEN</name>
|
|
<description>Channel 0 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Input</name>
|
|
<displayName>CHCTL0_Input</displayName>
|
|
<description>Channel control register 0 (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL0_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1CAPFLT</name>
|
|
<description>Channel 1 input capture filter control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1CAPPSC</name>
|
|
<description>Channel 1 input capture prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPFLT</name>
|
|
<description>Channel 0 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPPSC</name>
|
|
<description>Channel 0 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL1_Output</name>
|
|
<displayName>CHCTL1_Output</displayName>
|
|
<description>Channel control register 1 (output
|
|
mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3COMCEN</name>
|
|
<description>Channel 3 output compare clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMCTL</name>
|
|
<description>Channel 3 compare output control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMSEN</name>
|
|
<description>Channel 3 output compare shadow enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMFEN</name>
|
|
<description>Channel 3 output compare fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3MS</name>
|
|
<description>Channel 3 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMCEN</name>
|
|
<description>Channel 2 output compare clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMCTL</name>
|
|
<description>Channel 2 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMSEN</name>
|
|
<description>Channel 2 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMFEN</name>
|
|
<description>Channel 2 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2MS</name>
|
|
<description>Channel 2 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL1_Input</name>
|
|
<displayName>CHCTL1_Input</displayName>
|
|
<description>Channel control register 1 (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL1_Output</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3CAPFLT</name>
|
|
<description>Channel 3 input capture filter control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3CAPPSC</name>
|
|
<description>Channel 3 input capture prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3MS</name>
|
|
<description>Channel 3 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2CAPFLT</name>
|
|
<description>Channel 2 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2CAPPSC</name>
|
|
<description>Channel 2 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2MS</name>
|
|
<description>Channel 2 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL2</name>
|
|
<displayName>CHCTL2</displayName>
|
|
<description>Channel control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3P</name>
|
|
<description>Channel 3 capture/compare function polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3EN</name>
|
|
<description>Channel 3 capture/compare function enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2NP</name>
|
|
<description>Channel 2 complementary output polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2NEN</name>
|
|
<description>Channel 2 complementary output enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2P</name>
|
|
<description>Channel 2 capture/compare function polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2EN</name>
|
|
<description>Channel 2 capture/compare function enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1NP</name>
|
|
<description>Channel 1 complementary output polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1NEN</name>
|
|
<description>Channel 1 complementary output enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1P</name>
|
|
<description>Channel 1 capture/compare function polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1EN</name>
|
|
<description>Channel 1 capture/compare function enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0NP</name>
|
|
<description>Channel 0 complementary output polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0NEN</name>
|
|
<description>Channel 0 complementary output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0P</name>
|
|
<description>Channel 0 capture/compare function polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0EN</name>
|
|
<description>Channel 0 capture/compare function enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>current counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value of the counter clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAR</name>
|
|
<displayName>CAR</displayName>
|
|
<description>Counter auto reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CAR</name>
|
|
<description>Counter auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CREP</name>
|
|
<displayName>CREP</displayName>
|
|
<description>Counter repetition register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CREP</name>
|
|
<description>Counter repetition value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CV</name>
|
|
<displayName>CH0CV</displayName>
|
|
<description>Channel 0 capture/compare value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0VAL</name>
|
|
<description>Capture or compare value of channel0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CV</name>
|
|
<displayName>CH1CV</displayName>
|
|
<description>Channel 1 capture/compare value register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1VAL</name>
|
|
<description>Capture or compare value of channel1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2CV</name>
|
|
<displayName>CH2CV</displayName>
|
|
<description>Channel 2 capture/compare value register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH2VAL</name>
|
|
<description>Capture or compare value of channel 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3CV</name>
|
|
<displayName>CH3CV</displayName>
|
|
<description>Channel 3 capture/compare value register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3VAL</name>
|
|
<description>Capture or compare value of channel 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCHP</name>
|
|
<displayName>CCHP</displayName>
|
|
<description>channel complementary protection register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>POEN</name>
|
|
<description>Primary output enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OAEN</name>
|
|
<description>Output automatic enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKP</name>
|
|
<description>Break polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BRKEN</name>
|
|
<description>Break enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROS</name>
|
|
<description>Run mode off-state configure</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IOS</name>
|
|
<description>Idle mode off-state configure</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PROT</name>
|
|
<description>Complementary register protect control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTCFG</name>
|
|
<description>Dead time configure</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACFG</name>
|
|
<displayName>DMACFG</displayName>
|
|
<description>DMA configuration register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMATC</name>
|
|
<description>DMA transfer count</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMATA</name>
|
|
<description>DMA transfer access start address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMATB</name>
|
|
<displayName>DMATB</displayName>
|
|
<description>DMA transfer buffer register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMATB</name>
|
|
<description>DMA transfer buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OUTSEL</name>
|
|
<description>The output value selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHVSEL</name>
|
|
<description>Write CHxVAL register selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER1</name>
|
|
<description>General-purpose-timers</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER1</name>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARSE</name>
|
|
<description>Auto-reload shadow enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAM</name>
|
|
<description>Counter aligns mode selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPM</name>
|
|
<description>Single pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPS</name>
|
|
<description>Update source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI0S</name>
|
|
<description>Channel 0 trigger input selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMC</name>
|
|
<description>Master mode control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAS</name>
|
|
<description>DMA request source selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCFG</name>
|
|
<displayName>SMCFG</displayName>
|
|
<description>slave mode control register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>External trigger polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMC1</name>
|
|
<description>Part of SMC for enable External clock mode1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETPSC</name>
|
|
<description>External trigger prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETFC</name>
|
|
<description>External trigger filter control</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master-slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMC</name>
|
|
<description>Slave mode control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<displayName>DMAINTEN</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGDEN</name>
|
|
<description>Trigger DMA request enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3DEN</name>
|
|
<description>Channel 3 capture/compare DMA request enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2DEN</name>
|
|
<description>Channel 2 capture/compare DMA request enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1DEN</name>
|
|
<description>Channel 1 capture/compare DMA request enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0DEN</name>
|
|
<description>Channel 0 capture/compare DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDEN</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3IE</name>
|
|
<description>Channel 3 capture/compare interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2IE</name>
|
|
<description>Channel 2 capture/compare interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IE</name>
|
|
<description>Channel 1 capture/compare interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IE</name>
|
|
<description>Channel 0 capture/compare interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3OF</name>
|
|
<description>Channel 3 over capture flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2OF</name>
|
|
<description>Channel 2 over capture flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1OF</name>
|
|
<description>Channel 1 over capture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0OF</name>
|
|
<description>Channel 0 over capture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3IF</name>
|
|
<description>Channel 3 capture/compare interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2IF</name>
|
|
<description>Channel 2 capture/compare interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IF</name>
|
|
<description>Channel 1 capture/compare interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IF</name>
|
|
<description>Channel 0 capture/compare interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVG</name>
|
|
<displayName>SWEVG</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGG</name>
|
|
<description>Trigger event generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3G</name>
|
|
<description>Channel 3 capture or compare event generation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2G</name>
|
|
<description>Channel 2 capture or compare event generation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1G</name>
|
|
<description>Channel 1 capture or compare event generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0G</name>
|
|
<description>Channel 0 capture or compare event generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Output</name>
|
|
<displayName>CHCTL0_Output</displayName>
|
|
<description>Channel control register 0 (output
|
|
mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1COMCEN</name>
|
|
<description>Channel 1 output compare clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMCTL</name>
|
|
<description>Channel 1 compare output control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMSEN</name>
|
|
<description>Channel 1 output compare shadow enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMFEN</name>
|
|
<description>Channel 1 output compare fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCEN</name>
|
|
<description>Channel 0 output compare clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCTL</name>
|
|
<description> Channel 0 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMSEN</name>
|
|
<description>Channel 0 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMFEN</name>
|
|
<description>Channel 0 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Input</name>
|
|
<displayName>CHCTL0_Input</displayName>
|
|
<description>Channel control register 0 (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL0_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1CAPFLT</name>
|
|
<description>Channel 1 input capture filter control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1CAPPSC</name>
|
|
<description>Channel 1 input capture prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPFLT</name>
|
|
<description>Channel 0 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPPSC</name>
|
|
<description>Channel 0 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL1_Output</name>
|
|
<displayName>CHCTL1_Output</displayName>
|
|
<description>Channel control register 1 (output
|
|
mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3COMCEN</name>
|
|
<description>Channel 3 output compare clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMCTL</name>
|
|
<description>Channel 3 compare output control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMSEN</name>
|
|
<description>Channel 3 output compare shadow enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3COMFEN</name>
|
|
<description>Channel 3 output compare fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3MS</name>
|
|
<description>Channel 3 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMCEN</name>
|
|
<description>Channel 2 output compare clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMCTL</name>
|
|
<description>Channel 2 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMSEN</name>
|
|
<description>Channel 2 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2COMFEN</name>
|
|
<description>Channel 2 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2MS</name>
|
|
<description>Channel 2 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL1_Input</name>
|
|
<displayName>CHCTL1_Input</displayName>
|
|
<description>Channel control register 1 (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL1_Output</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3CAPFLT</name>
|
|
<description>Channel 3 input capture filter control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3CAPPSC</name>
|
|
<description>Channel 3 input capture prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3MS</name>
|
|
<description>Channel 3 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2CAPFLT</name>
|
|
<description>Channel 2 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2CAPPSC</name>
|
|
<description>Channel 2 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2MS</name>
|
|
<description>Channel 2 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL2</name>
|
|
<displayName>CHCTL2</displayName>
|
|
<description>Channel control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3P</name>
|
|
<description>Channel 3 capture/compare function polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH3EN</name>
|
|
<description>Channel 3 capture/compare function enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2NP</name>
|
|
<description>Channel 2 complementary output polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2P</name>
|
|
<description>Channel 2 capture/compare function polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH2EN</name>
|
|
<description>Channel 2 capture/compare function enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1NP</name>
|
|
<description>Channel 1 complementary output polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1P</name>
|
|
<description>Channel 1 capture/compare function polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1EN</name>
|
|
<description>Channel 1 capture/compare function enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0NP</name>
|
|
<description>Channel 0 complementary output polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0P</name>
|
|
<description>Channel 0 capture/compare function polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0EN</name>
|
|
<description>Channel 0 capture/compare function enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value of the counter clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAR</name>
|
|
<displayName>CAR</displayName>
|
|
<description>Counter auto reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CARL</name>
|
|
<description>Counter auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CV</name>
|
|
<displayName>CH0CV</displayName>
|
|
<description>Channel 0 capture/compare value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0VAL</name>
|
|
<description>Capture or compare value of channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CV</name>
|
|
<displayName>CH1CV</displayName>
|
|
<description>Channel 1 capture/compare value register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1VAL</name>
|
|
<description>Capture or compare value of channel1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH2CV</name>
|
|
<displayName>CH2CV</displayName>
|
|
<description>Channel 2 capture/compare value register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH2VAL</name>
|
|
<description>Capture or compare value of channel 2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH3CV</name>
|
|
<displayName>CH3CV</displayName>
|
|
<description>Channel 3 capture/compare value register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH3VAL</name>
|
|
<description>Capture or compare value of channel 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMACFG</name>
|
|
<displayName>DMACFG</displayName>
|
|
<description>DMA configuration register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMATC</name>
|
|
<description>DMA transfer count</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMATA</name>
|
|
<description>DMA transfer access start address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMATB</name>
|
|
<displayName>DMATB</displayName>
|
|
<description>DMA transfer buffer register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMATB</name>
|
|
<description>DMA transfer buffer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRMP</name>
|
|
<displayName>IRMP</displayName>
|
|
<description>Input remap register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CI3_RMP</name>
|
|
<description>Channel 3 input remap</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITI1_RMP</name>
|
|
<description>Internal trigger input1 remap</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>Configuration</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHVSEL</name>
|
|
<description>Write CHxVAL register selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER1">
|
|
<name>TIMER2</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER2</name>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER1">
|
|
<name>TIMER3</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40000800</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER3</name>
|
|
<value>30</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER1">
|
|
<name>TIMER4</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER4</name>
|
|
<value>50</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER5</name>
|
|
<description>Basic-timers</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER5_DAC</name>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARSE</name>
|
|
<description>Auto-reload shadow enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPM</name>
|
|
<description>Single pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPS</name>
|
|
<description>Update source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MMC</name>
|
|
<description>Master mode control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<displayName>DMAINTEN</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDEN</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>Interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVG</name>
|
|
<displayName>SWEVG</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Low counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value of the counter clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAR</name>
|
|
<displayName>CAR</displayName>
|
|
<description>Counter auto reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CAR</name>
|
|
<description>Counter auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER5">
|
|
<name>TIMER6</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER6</name>
|
|
<value>55</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER7</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40010400</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER7_BRK_TIMER11</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER7_UP_TIMER12</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER7_TRG_CMT_TIMER13</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIMER7_CC</name>
|
|
<value>46</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER8</name>
|
|
<description>General-purpose-timers</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0_BRK_TIMER8</name>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARSE</name>
|
|
<description>Auto-reload shadow enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPM</name>
|
|
<description>Single pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPS</name>
|
|
<description>Update source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCFG</name>
|
|
<displayName>SMCFG</displayName>
|
|
<description>slave mode configuration register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master-slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMC</name>
|
|
<description>Slave mode control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<displayName>DMAINTEN</displayName>
|
|
<description>DMA and interrupt enable register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IE</name>
|
|
<description>Channel 1 capture/compare interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IE</name>
|
|
<description>Channel 0 capture/compare interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1OF</name>
|
|
<description>Channel 1 over capture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0OF</name>
|
|
<description>Channel 0 over capture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1IF</name>
|
|
<description>Channel 1 capture/compare interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IF</name>
|
|
<description>Channel 0 capture/compare interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVG</name>
|
|
<displayName>SWEVG</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGG</name>
|
|
<description>Trigger event generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1G</name>
|
|
<description>Channel 1 capture or compare event generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0G</name>
|
|
<description>Channel 0 capture or compare event generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Output</name>
|
|
<displayName>CHCTL0_Output</displayName>
|
|
<description>Channel control register 0 (output
|
|
mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1COMCTL</name>
|
|
<description>Channel 1 compare output control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMSEN</name>
|
|
<description>Channel 1 output compare shadow enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1COMFEN</name>
|
|
<description>Channel 1 output compare fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCTL</name>
|
|
<description>Channel 0 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMSEN</name>
|
|
<description>Channel 0 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMFEN</name>
|
|
<description>Channel 0 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Input</name>
|
|
<displayName>CHCTL0_Input</displayName>
|
|
<description>Channel control register 0 (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL0_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1CAPFLT</name>
|
|
<description>Channel 1 input capture filter control</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1CAPPSC</name>
|
|
<description>Channel 1 input capture prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1MS</name>
|
|
<description>Channel 1 mode selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPFLT</name>
|
|
<description>Channel 0 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPPSC</name>
|
|
<description>Channel 0 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL2</name>
|
|
<displayName>CHCTL2</displayName>
|
|
<description>Channel control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1NP</name>
|
|
<description>Channel 1 complementary output polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1P</name>
|
|
<description>Channel 1 capture/compare function polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH1EN</name>
|
|
<description>Channel 1 capture/compare function enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0NP</name>
|
|
<description>Channel 0 complementary output polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0P</name>
|
|
<description>Channel 0 capture/compare function polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0EN</name>
|
|
<description>Channel 0 capture/compare function enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>current counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value of the counter clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAR</name>
|
|
<displayName>CAR</displayName>
|
|
<description>Counter auto reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CARL</name>
|
|
<description>Counter auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CV</name>
|
|
<displayName>CH0CV</displayName>
|
|
<description>Channel 0 capture/compare value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0VAL</name>
|
|
<description>Capture or compare value of channel0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH1CV</name>
|
|
<displayName>CH1CV</displayName>
|
|
<description>Channel 1 capture/compare value register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH1VAL</name>
|
|
<description>Capture or compare value of channel1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHVSEL</name>
|
|
<description>Write CHxVAL register selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER9</name>
|
|
<description>General-purpose-timers</description>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40014400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIMER0_UP_TIMER9</name>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKDIV</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARSE</name>
|
|
<description>Auto-reload shadow enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPS</name>
|
|
<description>Update source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAINTEN</name>
|
|
<displayName>DMAINTEN</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0IE</name>
|
|
<description>Channel 0 capture/compare interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>interrupt flag register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0OF</name>
|
|
<description>Channel 0 over capture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0IF</name>
|
|
<description>Channel 0 capture/compare interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWEVG</name>
|
|
<displayName>SWEVG</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0G</name>
|
|
<description>Channel 0 capture or compare event generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Output</name>
|
|
<displayName>CHCTL0_Output</displayName>
|
|
<description>Channel control register 0 (output
|
|
mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 I/O mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMFEN</name>
|
|
<description>Channel 0 output compare fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMSEN</name>
|
|
<description>Channel 0 compare output shadow enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0COMCTL</name>
|
|
<description>Channel 0 compare output control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL0_Input</name>
|
|
<displayName>CHCTL0_Input</displayName>
|
|
<description>Channel control register 0 ( (input
|
|
mode)</description>
|
|
<alternateRegister>CHCTL0_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0CAPFLT</name>
|
|
<description>Channel 0 input capture filter control</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0CAPPSC</name>
|
|
<description>Channel 0 input capture prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0MS</name>
|
|
<description>Channel 0 mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHCTL2</name>
|
|
<displayName>CHCTL2</displayName>
|
|
<description>Channel control register 2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0NP</name>
|
|
<description>Channel 0 complementary output polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0P</name>
|
|
<description>Channel 0 capture/compare polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH0EN</name>
|
|
<description>Channel 0 capture/compare function enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>current counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value of the counter clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CAR</name>
|
|
<displayName>CAR</displayName>
|
|
<description>Counter auto reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CARL</name>
|
|
<description>Counter auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CH0CV</name>
|
|
<displayName>CH0CV</displayName>
|
|
<description>Channel 0 capture/compare value register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CH0VAL</name>
|
|
<description>Capture or compare value of channel 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IRMP</name>
|
|
<displayName>IRMP</displayName>
|
|
<description>channel input remap register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ITI1_RMP</name>
|
|
<description>Internal trigger input1 remap</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0xFC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHVSEL</name>
|
|
<description>Write CHxVAL register selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER9">
|
|
<name>TIMER10</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40014800</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER0_TRG_CMT_TIMER10</name>
|
|
<value>26</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER8">
|
|
<name>TIMER11</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40001800</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER7_BRK_TIMER11</name>
|
|
<value>43</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER9">
|
|
<name>TIMER12</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40001C00</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER7_UP_TIMER12</name>
|
|
<value>44</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER9">
|
|
<name>TIMER13</name>
|
|
<groupName>TIMER</groupName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<interrupt>
|
|
<name>TIMER7_TRG_CMT_TIMER13</name>
|
|
<value>45</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TLI</name>
|
|
<description>TFT-LCD interface</description>
|
|
<groupName>TLI</groupName>
|
|
<baseAddress>0x40016800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TLI_ER</name>
|
|
<value>89</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TLI</name>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SPSZ</name>
|
|
<displayName>SPSZ</displayName>
|
|
<description>Synchronous pulse size register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VPSZ</name>
|
|
<description>size of vertical synchronous pluse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPSZ</name>
|
|
<description>size of horizontal synchronous pluse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BPSZ</name>
|
|
<displayName>BPSZ</displayName>
|
|
<description>Back-porch size register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VBPSZ</name>
|
|
<description>Size of the vertical back porch plus synchronous pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HBPSZ</name>
|
|
<description>Size of the horizontal back porch plus synchronous pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASZ</name>
|
|
<displayName>ASZ</displayName>
|
|
<description>Active size register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VASZ</name>
|
|
<description>Size of the vertical active area width plus back porch and synchronous pulse</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HASZ</name>
|
|
<description>Size of the horizontal active area width plus back porch and synchronous pulse</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSZ</name>
|
|
<displayName>TSZ</displayName>
|
|
<description>Total size register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VTSZ</name>
|
|
<description>Vertical total size of the display</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTSZ</name>
|
|
<description>Horizontal total size of the display</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CLT</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002220</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPPS</name>
|
|
<description>Horizontal Pulse Polarity Selection </description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPPS</name>
|
|
<description>Vertical Pulse Polarity Selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEPS</name>
|
|
<description>Data Enable Polarity Selection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKPS</name>
|
|
<description>Pixel Clock Polarity Selection </description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFEN</name>
|
|
<description>Dither Function Enable </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDB</name>
|
|
<description>Red channel Dither Bits Number</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GDB</name>
|
|
<description>Green channel Dither Bits Number</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BDB</name>
|
|
<description>Blue channel Dither Bits Number</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLIEN</name>
|
|
<description>TLI enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RL</name>
|
|
<displayName>RL</displayName>
|
|
<description>Reload layer register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FBR</name>
|
|
<description>Frame Blank Reload</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RQR</name>
|
|
<description>Request Reload</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BGC</name>
|
|
<displayName>BGC</displayName>
|
|
<description>Background color register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BVR</name>
|
|
<description> Background value red </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BVG</name>
|
|
<description> Background value green </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BVB</name>
|
|
<description> Background value blue </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<displayName>INTEN</displayName>
|
|
<description>Interrupt enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCRIE</name>
|
|
<description>Layer Configuration Reloaded Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transaction Error Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEIE</name>
|
|
<description>FIFO Error Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LMIE</name>
|
|
<description>Line Mark Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTF</name>
|
|
<displayName>INTF</displayName>
|
|
<description>Interrupt flag register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCRF</name>
|
|
<description>Layer Configuration Reloaded Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEF</name>
|
|
<description>Transaction Error Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEF</name>
|
|
<description>FIFO Error Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LMF</name>
|
|
<description>Line Mark Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC</name>
|
|
<displayName>INTC</displayName>
|
|
<description>Interrupt flag clear register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCRC</name>
|
|
<description>Layer Configuration Reloaded Flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEC</name>
|
|
<description>Transaction Error Flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEC</name>
|
|
<description>FIFO Error Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LMC</name>
|
|
<description>Line Mark Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LM</name>
|
|
<displayName>LM</displayName>
|
|
<description>Line mark register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LM</name>
|
|
<description>Line Mark value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPPOS</name>
|
|
<displayName>CPPOS</displayName>
|
|
<description>Current pixel position register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPOS</name>
|
|
<description>Horizontal position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPOS</name>
|
|
<description>Vertical position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000000F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HS</name>
|
|
<description>Current HS staus of the TLI </description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VS</name>
|
|
<description>Current VS staus of the TLI </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDE</name>
|
|
<description>Current HDE status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VDE</name>
|
|
<description>Current VDE status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0CTL</name>
|
|
<displayName>L0CTL</displayName>
|
|
<description>Layer 0 control register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LUTEN</name>
|
|
<description> LUT enable </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYEN</name>
|
|
<description>Color keying enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Layer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1CTL</name>
|
|
<displayName>L1CTL</displayName>
|
|
<description>Layer 1 control register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LUTEN</name>
|
|
<description> LUT enable </description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYEN</name>
|
|
<description>Color keying enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LEN</name>
|
|
<description>Layer enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0HPOS</name>
|
|
<displayName>L0HPOS</displayName>
|
|
<description>Layer 0 horizontal position parameters register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WLP</name>
|
|
<description>Window left position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRP</name>
|
|
<description>Window right position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1HPOS</name>
|
|
<displayName>L1HPOS</displayName>
|
|
<description>Layer 1 horizontal position parameters register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WLP</name>
|
|
<description>Window left position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRP</name>
|
|
<description>Window right position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0VPOS</name>
|
|
<displayName>L0VPOS</displayName>
|
|
<description>Layer 0 vertical position parameters register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WTP</name>
|
|
<description>Window top position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBP</name>
|
|
<description>Window bottom position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1VPOS</name>
|
|
<displayName>L1VPOS</displayName>
|
|
<description>Layer 1 vertical position parameters register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WTP</name>
|
|
<description>Window top position</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WBP</name>
|
|
<description>Window bottom position</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0CKEY</name>
|
|
<displayName>L0CKEY</displayName>
|
|
<description>Layer 0 color key register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKEYR</name>
|
|
<description>Color Key Red</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYG</name>
|
|
<description>Color Key Green</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYB</name>
|
|
<description>Color Key Blue</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1CKEY</name>
|
|
<displayName>L1CKEY</displayName>
|
|
<description>Layer 1 color key register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKEYR</name>
|
|
<description>Color Key Red</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYG</name>
|
|
<description>Color Key Green</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEYB</name>
|
|
<description>Color Key Blue</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0PPF</name>
|
|
<displayName>L0PPF</displayName>
|
|
<description>Layer 0 packeted pixel format register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PPF</name>
|
|
<description>Packeted Pixel Format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1PPF</name>
|
|
<displayName>L1PPF</displayName>
|
|
<description>Layer 1 packeted pixel format register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PPF</name>
|
|
<description>Packeted Pixel Format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0SA</name>
|
|
<displayName>L0SA</displayName>
|
|
<description>Layer 0 specified alpha register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Specified alpha</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1SA</name>
|
|
<displayName>L1SA</displayName>
|
|
<description>Layer 1 specified alpha register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SA</name>
|
|
<description>Specified alpha</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0DC</name>
|
|
<displayName>L0DC</displayName>
|
|
<description>Layer 0 default color register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCA</name>
|
|
<description>The default color ALPHA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCR</name>
|
|
<description>The default color red</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCG</name>
|
|
<description>The default color green</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCB</name>
|
|
<description>The default color blue</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1DC</name>
|
|
<displayName>L1DC</displayName>
|
|
<description>Layer 1 default color register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DCA</name>
|
|
<description>The default color ALPHA</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCR</name>
|
|
<description>The default color red</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCG</name>
|
|
<description>The default color green</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCB</name>
|
|
<description>The default color blue</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0BLEND</name>
|
|
<displayName>L0BLEND</displayName>
|
|
<description>Layer 0 blending register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000607</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACF1</name>
|
|
<description>Alpha Calculation Factor 1 of Blending Method</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACF2</name>
|
|
<description>Alpha Calculation Factor 2 of Blending Method</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1BLEND</name>
|
|
<displayName>L1BLEND</displayName>
|
|
<description>Layer 1 blending register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000607</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACF1</name>
|
|
<description>Alpha Calculation Factor 1 of Blending Method</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACF2</name>
|
|
<description>Alpha Calculation Factor 2 of Blending Method</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0FBADDR</name>
|
|
<displayName>L0FBADDR</displayName>
|
|
<description>Layer 0 frame base address register</description>
|
|
<addressOffset>0xAC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FBADD</name>
|
|
<description>Frame Buffer base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1FBADDR</name>
|
|
<displayName>L1FBADDR</displayName>
|
|
<description>Layer 1 frame base address register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FBADD</name>
|
|
<description>Frame Buffer base Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0FLLEN</name>
|
|
<displayName>L0FLLEN</displayName>
|
|
<description>Layer 0 frame line length register</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STDOFF</name>
|
|
<description>Frame Buffer Stride Offset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLL</name>
|
|
<description>Frame Line Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1FLLEN</name>
|
|
<displayName>L1FLLEN</displayName>
|
|
<description>Layer 1 frame line length register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STDOFF</name>
|
|
<description>Frame Buffer Stride Offset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLL</name>
|
|
<description>Frame Line Length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0FTLN</name>
|
|
<displayName>L0FTLN</displayName>
|
|
<description>Layer 0 frame total line number register</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FTLN</name>
|
|
<description>Frame Total Line Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1FTLN</name>
|
|
<displayName>L1FTLN</displayName>
|
|
<description>Layer 1 frame total line number register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FTLN</name>
|
|
<description>Frame Total Line Number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L0LUT</name>
|
|
<displayName>L0LUT</displayName>
|
|
<description>Layer 0 look up table register</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TADD</name>
|
|
<description>Look Up Table Write Address</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Red Channel of a LUT entry</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Green channel of a LUT entry</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB</name>
|
|
<description>Blue channel of a LUT entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>L1LUT</name>
|
|
<displayName>L1LUT</displayName>
|
|
<description>Layer 1 look up table register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TADD</name>
|
|
<description>Look Up Table Write Address</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TR</name>
|
|
<description>Red channel of a LUT entry</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Green channel of a LUT entry</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB</name>
|
|
<description>Blue channel of a LUT entry</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TRNG</name>
|
|
<description>Ture random number generator</description>
|
|
<groupName>TRNG</groupName>
|
|
<baseAddress>0x50060800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TRNG</name>
|
|
<value>80</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRNGEN</name>
|
|
<description>TRNG enable bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEIF</name>
|
|
<description>Seed error interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEIF</name>
|
|
<description>Clock error interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SECS</name>
|
|
<description>Seed error current status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CECS</name>
|
|
<description>Clock error current status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Random data ready status bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRNDATA</name>
|
|
<description>32-bit random data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>USART0</name>
|
|
<description>Universal synchronous asynchronous receiver
|
|
transmitter</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40011000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART0</name>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STAT0</name>
|
|
<displayName>STAT0</displayName>
|
|
<description>Status register 0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTSF</name>
|
|
<description>CTS change flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDF</name>
|
|
<description>LIN break detection flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>Transmit data buffer empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission complete</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNE</name>
|
|
<description>Read data buffer not empty</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEF</name>
|
|
<description>IDLE frame detected flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORERR</name>
|
|
<description>Overrun error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NERR</name>
|
|
<description>Noise error flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Frame error flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity error flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit or read data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<displayName>BAUD</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTDIV</name>
|
|
<description>Integer part of baud-rate divider</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRADIV</name>
|
|
<description>Fraction part of baud-rate divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control register 0</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVSMOD</name>
|
|
<description>Oversampling mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UEN</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WL</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WM</name>
|
|
<description>Wakeup method in mute mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>Parity check function enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Parity mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERRIE</name>
|
|
<description>Parity error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBEIE</name>
|
|
<description>Transmitter buffer empty interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNEIE</name>
|
|
<description>Read data buffer not empty interrupt and overrun error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE line detected interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver wakeup from mute mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKCMD</name>
|
|
<description>Send break command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LMEN</name>
|
|
<description>LIN mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STB</name>
|
|
<description>STOP bits length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN</name>
|
|
<description>CK pin enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPH</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLEN</name>
|
|
<description>CK Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDIE</name>
|
|
<description>LIN break detection interrupt
|
|
enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBLEN</name>
|
|
<description>LIN break frame length</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address of the USART</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSB</name>
|
|
<description>One sample bit method
|
|
enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DENT</name>
|
|
<description>DMA request enable for transmission</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DENR</name>
|
|
<description>DMA request enable for reception</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCEN</name>
|
|
<description>Smartcard mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NKEN</name>
|
|
<description>Smartcard NACK enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDEN</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>IrDA low-power</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>IrDA mode enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GP</name>
|
|
<displayName>GP</displayName>
|
|
<description>Guard time and prescaler
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GUAT</name>
|
|
<description>Guard time value in Smartcard mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL3</name>
|
|
<displayName>CTL3</displayName>
|
|
<description>Control register 3</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSBF</name>
|
|
<description>Most significant bit first</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DINV</name>
|
|
<description>Data bit level inversion</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TINV</name>
|
|
<description>TX pin level inversion</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RINV</name>
|
|
<description>RX pin level inversion</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EBIE</name>
|
|
<description>Interrupt enable bit of end of block event</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTIE</name>
|
|
<description>Interrupt enable bit of receive timeout event</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCRTNUM</name>
|
|
<description>Smartcard auto-retry number</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTEN</name>
|
|
<description>Receiver timeout enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RT</name>
|
|
<displayName>RT</displayName>
|
|
<description>Receiver timeout register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BL</name>
|
|
<description>Block Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>Receiver timeout threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT1</name>
|
|
<displayName>STAT1</displayName>
|
|
<description>Status register 1</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EBF</name>
|
|
<description>End of block flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTF</name>
|
|
<description>Receiver timeout flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHC</name>
|
|
<displayName>CHC</displayName>
|
|
<description>Coherence control register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPERR</name>
|
|
<description>Early parity error flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCM</name>
|
|
<description>Break frame coherence mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCM</name>
|
|
<description>Parity check coherence mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCM</name>
|
|
<description>Hardware flow control coherence mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART1</name>
|
|
<baseAddress>0x40004400</baseAddress>
|
|
<interrupt>
|
|
<name>USART1</name>
|
|
<value>38</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART2</name>
|
|
<baseAddress>0x40004800</baseAddress>
|
|
<interrupt>
|
|
<name>USART2</name>
|
|
<value>39</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART0">
|
|
<name>USART5</name>
|
|
<baseAddress>0x40011400</baseAddress>
|
|
<interrupt>
|
|
<name>USART5</name>
|
|
<value>71</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART3</name>
|
|
<description>Universal asynchronous receiver
|
|
transmitter</description>
|
|
<groupName>UART</groupName>
|
|
<baseAddress>0x40004C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART3</name>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>STAT0</name>
|
|
<displayName>STAT0</displayName>
|
|
<description>Status register 0</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTSF</name>
|
|
<description>CTS change flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDF</name>
|
|
<description>LIN break detection flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>Transmit data buffer empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission complete</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNE</name>
|
|
<description>Read data buffer not empty</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEF</name>
|
|
<description>IDLE frame detected flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORERR</name>
|
|
<description>Overrun error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NERR</name>
|
|
<description>Noise error flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FERR</name>
|
|
<description>Frame error flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>Parity error flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DATA</name>
|
|
<displayName>DATA</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Transmit or read data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BAUD</name>
|
|
<displayName>BAUD</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTDIV</name>
|
|
<description>Integer part of baud-rate divider</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRADIV</name>
|
|
<description>Fraction part of baud-rate divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<displayName>CTL0</displayName>
|
|
<description>Control register 0</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OVSMOD</name>
|
|
<description>Oversampling mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UEN</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WL</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WM</name>
|
|
<description>Wakeup method in mute mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCEN</name>
|
|
<description>Parity check function enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>Parity mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERRIE</name>
|
|
<description>Parity error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBEIE</name>
|
|
<description>Transmitter buffer empty interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RBNEIE</name>
|
|
<description>Read data buffer not empty interrupt and overrun error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE line detected interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REN</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver wakeup from mute mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKCMD</name>
|
|
<description>Send break command</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<displayName>CTL1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LMEN</name>
|
|
<description>LIN mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STB</name>
|
|
<description>STOP bits length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN</name>
|
|
<description>CK pin enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPH</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLEN</name>
|
|
<description>CK Length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDIE</name>
|
|
<description>LIN break detection interrupt
|
|
enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBLEN</name>
|
|
<description>LIN break frame length</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address of the USART</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL2</name>
|
|
<displayName>CTL2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSB</name>
|
|
<description>One sample bit method
|
|
enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSEN</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSEN</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DENT</name>
|
|
<description>DMA request enable for transmission</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DENR</name>
|
|
<description>DMA request enable for reception</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCEN</name>
|
|
<description>Smartcard mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NKEN</name>
|
|
<description>Smartcard NACK enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDEN</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>IrDA low-power</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>IrDA mode enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GP</name>
|
|
<displayName>GP</displayName>
|
|
<description>Guard time and prescaler
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GUAT</name>
|
|
<description>Guard time value in Smartcard mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHC</name>
|
|
<displayName>CHC</displayName>
|
|
<description>Coherence control register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPERR</name>
|
|
<description>Early parity error flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCM</name>
|
|
<description>Break frame coherence mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCM</name>
|
|
<description>Parity check coherence mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HCM</name>
|
|
<description>Hardware flow control coherence mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART3">
|
|
<name>UART4</name>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<interrupt>
|
|
<name>UART4</name>
|
|
<value>53</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART3">
|
|
<name>UART6</name>
|
|
<baseAddress>0x40007800</baseAddress>
|
|
<interrupt>
|
|
<name>UART6</name>
|
|
<value>82</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART3">
|
|
<name>UART7</name>
|
|
<baseAddress>0x40007C00</baseAddress>
|
|
<interrupt>
|
|
<name>UART7</name>
|
|
<value>83</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
|
|
|
|
<peripheral>
|
|
<name>FS_GLOBAL</name>
|
|
<description>USB full speed global registers</description>
|
|
<groupName>USB_FS</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>OTG_FS_WKUP</name>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>OTG_FS</name>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>GOTGCS</name>
|
|
<displayName>GOTGCS</displayName>
|
|
<description>Global OTG control and status register
|
|
(USBFS_GOTGCS)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000800</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRPS</name>
|
|
<description>SRP success</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRPREQ</name>
|
|
<description>SRP request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPS</name>
|
|
<description>Host success</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPREQ</name>
|
|
<description>HNP request</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HHNPEN</name>
|
|
<description>Host HNP enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DHNPEN</name>
|
|
<description>Device HNP enabled</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPS</name>
|
|
<description>ID pin status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DI</name>
|
|
<description>Debounce interval</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASV</name>
|
|
<description>A-session valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSV</name>
|
|
<description>B-session valid</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GOTGINTF</name>
|
|
<displayName>GOTGINTF</displayName>
|
|
<description>Global OTG interrupt flag register
|
|
(OTG_FS_GOTGINTF)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SESEND</name>
|
|
<description>Session end </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRPEND</name>
|
|
<description>Session request success status
|
|
change</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPEND</name>
|
|
<description>HNP end</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPDET</name>
|
|
<description>Host negotiation request detected</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADTO</name>
|
|
<description>A-device timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DF</name>
|
|
<description>Debounce finish</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAHBCS</name>
|
|
<displayName>GAHBCS</displayName>
|
|
<description>Global AHB control and status register
|
|
(USBFS_GAHBCS)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GINTEN</name>
|
|
<description>Global interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFTH</name>
|
|
<description>Tx FIFO threshold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTXFTH</name>
|
|
<description>Periodic Tx FIFO threshold</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GUSBCS</name>
|
|
<displayName>GUSBCS</displayName>
|
|
<description>Global USB control and status register
|
|
(OTG_FS_GUSBCSR)</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000A80</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TOC</name>
|
|
<description>Timeout calibration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRPCEN</name>
|
|
<description>SRP capability enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPCEN</name>
|
|
<description>HNP capability enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTT</name>
|
|
<description>USB turnaround time</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FHM</name>
|
|
<description>Force host mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDM</name>
|
|
<description>Force device mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTCTL</name>
|
|
<displayName>GRSTCTL</displayName>
|
|
<description>Global reset control register (USBFS_GRSTCTL)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSRST</name>
|
|
<description>Core soft reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HCSRST</name>
|
|
<description>HCLK soft reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFCRST</name>
|
|
<description>Host frame counter reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RxFIFO flush</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFF</name>
|
|
<description>TxFIFO flush</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO number</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTF</name>
|
|
<displayName>GINTF</displayName>
|
|
<description>Global interrupt flag register (USBFS_GINTF)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x04000021</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COPM</name>
|
|
<description>Current operation mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MFIF</name>
|
|
<description>Mode fault interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGIF</name>
|
|
<description>OTG interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start of frame</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFNEIF</name>
|
|
<description>RxFIFO non-empty interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEIF</name>
|
|
<description>Non-periodic TxFIFO empty interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GNPINAK</name>
|
|
<description>Global Non-Periodic IN NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GONAK</name>
|
|
<description>Global OUT NAK effective</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ESP</name>
|
|
<description>Early suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>USB suspend</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>USB reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMF</name>
|
|
<description>Enumeration finished</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOPDIF</name>
|
|
<description>Isochronous OUT packet dropped
|
|
interrupt</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPFIF</name>
|
|
<description>End of periodic frame
|
|
interrupt flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPIF</name>
|
|
<description>IN endpoint interrupt flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPIF</name>
|
|
<description>OUT endpoint interrupt flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOINCIF</name>
|
|
<description>Isochronous IN transfer Not Complete Interrupt Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXNCIF_ISOONCIF</name>
|
|
<description>periodic transfer not complete interrupt flag(Host
|
|
mode)/isochronous OUT transfer not complete interrupt flag(Device
|
|
mode)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPIF</name>
|
|
<description>Host port interrupt flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HCIF</name>
|
|
<description>Host channels interrupt flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEIF</name>
|
|
<description>Periodic TxFIFO empty interrupt flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPSC</name>
|
|
<description>ID pin status change</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCIF</name>
|
|
<description>Disconnect interrupt flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESIF</name>
|
|
<description>Session interrupt flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIF</name>
|
|
<description>Wakeup interrupt flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTEN</name>
|
|
<displayName>GINTEN</displayName>
|
|
<description>Global interrupt enable register
|
|
(USBFS_GINTEN)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MFIE</name>
|
|
<description>Mode fault interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGIE</name>
|
|
<description>OTG interrupt enable </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFIE</name>
|
|
<description>Start of frame interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFNEIE</name>
|
|
<description>Receive FIFO non-empty
|
|
interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEIE</name>
|
|
<description>Non-periodic TxFIFO empty
|
|
interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GNPINAKIE</name>
|
|
<description>Global non-periodic IN NAK effective interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GONAKIE</name>
|
|
<description>Global OUT NAK effective
|
|
interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ESPIE</name>
|
|
<description>Early suspend interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>USB suspend interrupt enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>USB reset interrupt enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMFIE</name>
|
|
<description>Enumeration finish interrupt enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOPDIE</name>
|
|
<description>Isochronous OUT packet dropped interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPFIE</name>
|
|
<description>End of periodic frame interrupt enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPIE</name>
|
|
<description>IN endpoints interrupt enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPIE</name>
|
|
<description>OUT endpoints interrupt enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOINCIE</name>
|
|
<description>isochronous IN transfer not complete
|
|
interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXNCIE_ISOONCIE</name>
|
|
<description>periodic transfer not compelete Interrupt enable(Host
|
|
mode)/isochronous OUT transfer not complete interrupt enable(Device
|
|
mode)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPIE</name>
|
|
<description>Host port interrupt enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HCIE</name>
|
|
<description>Host channels interrupt enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEIE</name>
|
|
<description>Periodic TxFIFO empty interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPSCIE</name>
|
|
<description>ID pin status change interrupt enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCIE</name>
|
|
<description>Disconnect interrupt enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESIE</name>
|
|
<description>Session interrupt enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIE</name>
|
|
<description>Wakeup interrupt enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATR_Device</name>
|
|
<displayName>GRSTATR_Device</displayName>
|
|
<description>Global Receive status read(Device
|
|
mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Recieve packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATR_Host</name>
|
|
<displayName>GRSTATR_Host</displayName>
|
|
<description>Global Receive status read(Host
|
|
mode)</description>
|
|
<alternateRegister>GRSTATR_Device</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNUM</name>
|
|
<description>Channel number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Reivece packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>GRSTATP_Device</name>
|
|
<displayName>GRSTATP_Device</displayName>
|
|
<description>Global Receive status pop(Device
|
|
mode)</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Recieve packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATP_Host</name>
|
|
<displayName>GRSTATP_Host</displayName>
|
|
<description>Global Receive status pop(Host
|
|
mode)</description>
|
|
<alternateRegister>GRSTATP_Device</alternateRegister>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNUM</name>
|
|
<description>Channel number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Reivece packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRFLEN</name>
|
|
<displayName>GRFLEN</displayName>
|
|
<description>Global Receive FIFO size register
|
|
(USBFS_GRFLEN)</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFD</name>
|
|
<description>Rx FIFO depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HNPTFLEN</name>
|
|
<displayName>HNPTFLEN</displayName>
|
|
<description>Host non-periodic transmit FIFO length register
|
|
(Host mode)</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HNPTXRSAR</name>
|
|
<description>host non-periodic transmit Tx RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPTXFD</name>
|
|
<description>host non-periodic TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TFLEN</name>
|
|
<displayName>DIEP0TFLEN</displayName>
|
|
<description>Device IN endpoint 0 transmit FIFO length
|
|
(Device mode)</description>
|
|
<alternateRegister>HNPTFLEN</alternateRegister>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEP0TXFD</name>
|
|
<description>in endpoint 0 Tx FIFO depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEP0TXRSAR</name>
|
|
<description>in endpoint 0 Tx RAM start address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HNPTFQSTAT</name>
|
|
<displayName>HNPTFQSTAT</displayName>
|
|
<description>Host non-periodic transmit FIFO/queue
|
|
status register (HNPTFQSTAT)</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00080200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NPTXFS</name>
|
|
<description>Non-periodic TxFIFO space</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NPTXRQS</name>
|
|
<description>Non-periodic transmit request queue
|
|
space </description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NPTXRQTOP</name>
|
|
<description>Top of the non-periodic transmit request
|
|
queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GCCFG</name>
|
|
<displayName>GCCFG</displayName>
|
|
<description>Global core configuration register (USBFS_GCCFG)</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWRON</name>
|
|
<description>Power on</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSACEN</name>
|
|
<description>The VBUS A-device Comparer enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSBCEN</name>
|
|
<description>The VBUS B-device Comparer enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOFOEN</name>
|
|
<description>SOF output enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSIG</name>
|
|
<description>VBUS ignored</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID</name>
|
|
<displayName>CID</displayName>
|
|
<description>core ID register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CID</name>
|
|
<description>Core ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTFLEN</name>
|
|
<displayName>HPTFLEN</displayName>
|
|
<description>Host periodic transmit FIFO length register (HPTFLEN)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000600</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPTXFSAR</name>
|
|
<description>Host periodic TxFIFO start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPTXFD</name>
|
|
<description>Host periodic TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1TFLEN</name>
|
|
<displayName>DIEP1TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP1TFLEN)</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2TFLEN</name>
|
|
<displayName>DIEP2TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP2TFLEN)</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3TFLEN</name>
|
|
<displayName>DIEP3TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (FS_DIEP3TXFLEN)</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO4 transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>FS_HOST</name>
|
|
<description>USB on the go full speed host</description>
|
|
<groupName>USB_FS</groupName>
|
|
<baseAddress>0x50000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>HCTL</name>
|
|
<displayName>HCTL</displayName>
|
|
<description>host configuration register
|
|
(HCTL)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLKSEL</name>
|
|
<description>clock select for USB clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFT</name>
|
|
<displayName>HFT</displayName>
|
|
<description>Host frame interval
|
|
register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000BB80</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRI</name>
|
|
<description>Frame interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFINFR</name>
|
|
<displayName>HFINFR</displayName>
|
|
<description>OTG_FS host frame number/frame time
|
|
remaining register (HFINFR)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xBB800000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRNUM</name>
|
|
<description>Frame number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRT</name>
|
|
<description>Frame remaining time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTFQSTAT</name>
|
|
<displayName>HPTFQSTAT</displayName>
|
|
<description>Host periodic transmit FIFO/queue
|
|
status register (HPTFQSTAT)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00080200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PTXFS</name>
|
|
<description>Periodic transmit data FIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXREQS</name>
|
|
<description>Periodic transmit request queue space
|
|
available</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXREQT</name>
|
|
<description>Top of the periodic transmit request
|
|
queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HACHINT</name>
|
|
<displayName>HACHINT</displayName>
|
|
<description> Host all channels interrupt
|
|
register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HACHINT</name>
|
|
<description>Host all channel interrupts</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HACHINTEN</name>
|
|
<displayName>HACHINTEN</displayName>
|
|
<description>host all channels interrupt mask
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CINTEN</name>
|
|
<description>Channel interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPCS</name>
|
|
<displayName>HPCS</displayName>
|
|
<description>Host port control and status register (USBFS_HPCS)</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCST</name>
|
|
<description>Port connect status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCD</name>
|
|
<description>Port connect detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEDC</name>
|
|
<description>Port enable/disable change</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREM</name>
|
|
<description>Port resume</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSP</name>
|
|
<description>Port suspend</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRST</name>
|
|
<description>Port reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLST</name>
|
|
<description>Port line status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Port power</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Port speed</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0CTL</name>
|
|
<displayName>HCH0CTL</displayName>
|
|
<description>host channel-0 characteristics
|
|
register (HCH0CTL)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1CTL</name>
|
|
<displayName>HCH1CTL</displayName>
|
|
<description> host channel-1 characteristics
|
|
register (HCH1CTL)</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2CTL</name>
|
|
<displayName>HCH2CTL</displayName>
|
|
<description>host channel-2 characteristics
|
|
register (HCH2CTL)</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3CTL</name>
|
|
<displayName>HCH3CTL</displayName>
|
|
<description>host channel-3 characteristics
|
|
register (HCH3CTL)</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4CTL</name>
|
|
<displayName>HCH4CTL</displayName>
|
|
<description> host channel-4 characteristics
|
|
register (HCH4CTL)</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5CTL</name>
|
|
<displayName>HCH5CTL</displayName>
|
|
<description>host channel-5 characteristics
|
|
register (HCH5CTL)</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6CTL</name>
|
|
<displayName>HCH6CTL</displayName>
|
|
<description>host channel-6 characteristics
|
|
register (HCH6CTL)</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7CTL</name>
|
|
<displayName>HCH7CTL</displayName>
|
|
<description>host channel-7 characteristics
|
|
register (HCH7CTL)</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0INTF</name>
|
|
<displayName>HCH0INTF</displayName>
|
|
<description>host channel-0 interrupt register
|
|
(USBFS_HCHxINTF)</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1INTF</name>
|
|
<displayName>HCH1INTF</displayName>
|
|
<description>host channel-1 interrupt register
|
|
(HCH1INTF)</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2INTF</name>
|
|
<displayName>HCH2INTF</displayName>
|
|
<description>host channel-2 interrupt register
|
|
(HCH2INTF)</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3INTF</name>
|
|
<displayName>HCH3INTF</displayName>
|
|
<description>host channel-3 interrupt register
|
|
(HCH3INTF)</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4INTF</name>
|
|
<displayName>HCH4INTF</displayName>
|
|
<description>host channel-4 interrupt register
|
|
(HCH4INTF)</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5INTF</name>
|
|
<displayName>HCH5INTF</displayName>
|
|
<description>host channel-5 interrupt register
|
|
(HCH5INTF)</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6INTF</name>
|
|
<displayName>HCH6INTF</displayName>
|
|
<description>host channel-6 interrupt register
|
|
(HCH6INTF)</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7INTF</name>
|
|
<displayName>HCH7INTF</displayName>
|
|
<description>host channel-7 interrupt register
|
|
(HCH7INTF)</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0INTEN</name>
|
|
<displayName>HCH0INTEN</displayName>
|
|
<description>host channel-0 interrupt enable register
|
|
(HCH0INTEN)</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1INTEN</name>
|
|
<displayName>HCH1INTEN</displayName>
|
|
<description>host channel-1 interrupt enable register
|
|
(HCH1INTEN)</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2INTEN</name>
|
|
<displayName>HCH2INTEN</displayName>
|
|
<description>host channel-2 interrupt enable register
|
|
(HCH2INTEN)</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3INTEN</name>
|
|
<displayName>HCH3INTEN</displayName>
|
|
<description>host channel-3 interrupt enable register
|
|
(HCH3INTEN)</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4INTEN</name>
|
|
<displayName>HCH4INTEN</displayName>
|
|
<description>host channel-4 interrupt enable register
|
|
(HCH4INTEN)</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5INTEN</name>
|
|
<displayName>HCH5INTEN</displayName>
|
|
<description>host channel-5 interrupt enable register
|
|
(HCH5INTEN)</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6INTEN</name>
|
|
<displayName>HCH6INTEN</displayName>
|
|
<description>host channel-6 interrupt enable register
|
|
(HCH6INTEN)</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7INTEN</name>
|
|
<displayName>HCH7INTEN</displayName>
|
|
<description>host channel-7 interrupt enable register
|
|
(HCH7INTEN)</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer completed interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0LEN</name>
|
|
<displayName>HCH0LEN</displayName>
|
|
<description>host channel-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1LEN</name>
|
|
<displayName>HCH1LEN</displayName>
|
|
<description>host channel-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2LEN</name>
|
|
<displayName>HCH2LEN</displayName>
|
|
<description> host channel-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3LEN</name>
|
|
<displayName>HCH3LEN</displayName>
|
|
<description> host channel-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4LEN</name>
|
|
<displayName>HCH4LEN</displayName>
|
|
<description>host channel-4 transfer length
|
|
register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5LEN</name>
|
|
<displayName>HCH5LEN</displayName>
|
|
<description>host channel-5 transfer length
|
|
register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6LEN</name>
|
|
<displayName>HCH6LEN</displayName>
|
|
<description>host channel-6 transfer length
|
|
register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7LEN</name>
|
|
<displayName>HCH7LEN</displayName>
|
|
<description>host channel-7 transfer length
|
|
register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FS_DEVICE</name>
|
|
<description>USB on the go full speed device</description>
|
|
<groupName>USB_FS</groupName>
|
|
<baseAddress>0x50000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DCFG</name>
|
|
<displayName>DCFG</displayName>
|
|
<description>device configuration register
|
|
(DCFG)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Device speed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NZLSOH</name>
|
|
<description>Non-zero-length status OUT
|
|
handshake</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOPFT</name>
|
|
<description>end of periodic frame time</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCTL</name>
|
|
<displayName>DCTL</displayName>
|
|
<description>device control register
|
|
(DCTL)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RWKUP</name>
|
|
<description>Remote wakeup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD</name>
|
|
<description>Soft disconnect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GINS</name>
|
|
<description>Global IN NAK status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GONS</name>
|
|
<description>Global OUT NAK status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SGINAK</name>
|
|
<description>Set global IN NAK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGINAK</name>
|
|
<description>Clear global IN NAK</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SGONAK</name>
|
|
<description>Set global OUT NAK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGONAK</name>
|
|
<description>Clear global OUT NAK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>POIF</name>
|
|
<description>Power-on initialization flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSTAT</name>
|
|
<displayName>DSTAT</displayName>
|
|
<description>device status register
|
|
(DSTAT)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPST</name>
|
|
<description>Suspend status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Enumerated speed</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FNRSOF</name>
|
|
<description>Frame number of the received
|
|
SOF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPINTEN</name>
|
|
<displayName>DIEPINTEN</displayName>
|
|
<description>device IN endpoint common interrupt
|
|
mask register (DIEPINTEN)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer finished interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITOEN</name>
|
|
<description>Control IN timeout condition interrupt enable (Non-isochronous
|
|
endpoints)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUDEN</name>
|
|
<description>Endpoint Tx FIFO underrun interrupt enable bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPNEEN</name>
|
|
<description>IN endpoint NAK effective
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFEEN</name>
|
|
<description>Trabsmit FIFO empty
|
|
interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEPINTEN</name>
|
|
<displayName>DOEPINTEN</displayName>
|
|
<description>device OUT endpoint common interrupt
|
|
enable register (DOEPINTEN)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer finished interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPFEN</name>
|
|
<description>SETUP phase finished interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVREN</name>
|
|
<description> Endpoint Rx FIFO overrun interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTPEN</name>
|
|
<description> Back-to-back SETUP packets
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAEPINT</name>
|
|
<displayName>DAEPINT</displayName>
|
|
<description>device all endpoints interrupt
|
|
register (DAEPINT)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPITB</name>
|
|
<description>Device all IN endpoint interrupt bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEPITB</name>
|
|
<description>Device all OUT endpoint interrupt bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAEPINTEN</name>
|
|
<displayName>DAEPINTEN</displayName>
|
|
<description>Device all endpoints interrupt enable register
|
|
(DAEPINTEN)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPIE</name>
|
|
<description>IN EP interrupt interrupt enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEPIE</name>
|
|
<description>OUT endpoint interrupt enable bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSDT</name>
|
|
<displayName>DVBUSDT</displayName>
|
|
<description>device VBUS discharge time
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000017D7</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSDT</name>
|
|
<description>Device VBUS discharge time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSPT</name>
|
|
<displayName>DVBUSPT</displayName>
|
|
<description>device VBUS pulsing time
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000005B8</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSPT</name>
|
|
<description>Device VBUS pulsing time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPFEINTEN</name>
|
|
<displayName>DIEPFEINTEN</displayName>
|
|
<description>device IN endpoint FIFO empty
|
|
interrupt enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXFEIE</name>
|
|
<description>IN EP Tx FIFO empty interrupt enable
|
|
bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0CTL</name>
|
|
<displayName>DIEP0CTL</displayName>
|
|
<description>device IN endpoint 0 control
|
|
register (DIEP0CTL)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1CTL</name>
|
|
<displayName>DIEP1CTL</displayName>
|
|
<description>device in endpoint-1 control
|
|
register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2CTL</name>
|
|
<displayName>DIEP2CTL</displayName>
|
|
<description>device endpoint-2 control
|
|
register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3CTL</name>
|
|
<displayName>DIEP3CTL</displayName>
|
|
<description>device endpoint-3 control
|
|
register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0CTL</name>
|
|
<displayName>DOEP0CTL</displayName>
|
|
<description>device endpoint-0 control
|
|
register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1CTL</name>
|
|
<displayName>DOEP1CTL</displayName>
|
|
<description>device endpoint-1 control
|
|
register</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2CTL</name>
|
|
<displayName>DOEP2CTL</displayName>
|
|
<description>device endpoint-2 control
|
|
register</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3CTL</name>
|
|
<displayName>DOEP3CTL</displayName>
|
|
<description>device endpoint-3 control
|
|
register</description>
|
|
<addressOffset>0x360</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0INTF</name>
|
|
<displayName>DIEP0INTF</displayName>
|
|
<description>device endpoint-0 interrupt
|
|
register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1INTF</name>
|
|
<displayName>DIEP1INTF</displayName>
|
|
<description>device endpoint-1 interrupt
|
|
register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2INTF</name>
|
|
<displayName>DIEP2INTF</displayName>
|
|
<description>device endpoint-2 interrupt
|
|
register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3INTF</name>
|
|
<displayName>DIEP3INTF</displayName>
|
|
<description>device endpoint-3 interrupt
|
|
register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0INTF</name>
|
|
<displayName>DOEP0INTF</displayName>
|
|
<description>device out endpoint-0 interrupt flag
|
|
register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1INTF</name>
|
|
<displayName>DOEP1INTF</displayName>
|
|
<description>device out endpoint-1 interrupt flag
|
|
register</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2INTF</name>
|
|
<displayName>DOEP2INTF</displayName>
|
|
<description>device out endpoint-2 interrupt flag
|
|
register</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3INTF</name>
|
|
<displayName>DOEP3INTF</displayName>
|
|
<description>device out endpoint-3 interrupt flag
|
|
register</description>
|
|
<addressOffset>0x368</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0LEN</name>
|
|
<displayName>DIEP0LEN</displayName>
|
|
<description>device IN endpoint-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0LEN</name>
|
|
<displayName>DOEP0LEN</displayName>
|
|
<description>device OUT endpoint-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT</name>
|
|
<description>SETUP packet count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1LEN</name>
|
|
<displayName>DIEP1LEN</displayName>
|
|
<description>device IN endpoint-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2LEN</name>
|
|
<displayName>DIEP2LEN</displayName>
|
|
<description>device IN endpoint-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3LEN</name>
|
|
<displayName>DIEP3LEN</displayName>
|
|
<description>device IN endpoint-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1LEN</name>
|
|
<displayName>DOEP1LEN</displayName>
|
|
<description>device OUT endpoint-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2LEN</name>
|
|
<displayName>DOEP2LEN</displayName>
|
|
<description>device OUT endpoint-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3LEN</name>
|
|
<displayName>DOEP3LEN</displayName>
|
|
<description>device OUT endpoint-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x370</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TFSTAT</name>
|
|
<displayName>DIEP0TFSTAT</displayName>
|
|
<description>device IN endpoint 0 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
remaining</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1TFSTAT</name>
|
|
<displayName>DIEP1TFSTAT</displayName>
|
|
<description>device IN endpoint 1 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
remaining</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2TFSTAT</name>
|
|
<displayName>DIEP2TFSTAT</displayName>
|
|
<description>device IN endpoint 2 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
remaining</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3TFSTAT</name>
|
|
<displayName>DIEP3TFSTAT</displayName>
|
|
<description>device IN endpoint 3 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
remaining</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FS_PWRCLK</name>
|
|
<description>USB on the go full speed</description>
|
|
<groupName>USB_FS</groupName>
|
|
<baseAddress>0x50000E00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PWRCLKCTL</name>
|
|
<displayName>PWRCLKCTL</displayName>
|
|
<description>power and clock gating control
|
|
register (PWRCLKCTL)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUCLK</name>
|
|
<description>Stop the USB clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SHCLK</name>
|
|
<description>Stop HCLK</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HS_GLOBAL</name>
|
|
<description>USB high speed global registers</description>
|
|
<groupName>USB_HS</groupName>
|
|
<baseAddress>0x40040000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USBHS_EP1_Out</name>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBHS_EP1_In</name>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBHS_WKUP</name>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBHS</name>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>GOTGCS</name>
|
|
<displayName>GOTGCS</displayName>
|
|
<description> control and status register
|
|
(GOTGCS)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000800</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SRPS</name>
|
|
<description>Session request success</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRPREQ</name>
|
|
<description>SRP request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPS</name>
|
|
<description>Host negotiation success</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPREQ</name>
|
|
<description>HNP request</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HHNPEN</name>
|
|
<description>Host HNP enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DHNPEN</name>
|
|
<description>Device HNP enabled</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIDPS</name>
|
|
<description>ID pin status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DI</name>
|
|
<description>Debounce interval of a detected connection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ASV</name>
|
|
<description>A-session valid</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSV</name>
|
|
<description>B-session valid</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GOTGINTF</name>
|
|
<displayName>GOTGINTF</displayName>
|
|
<description>Global OTG interrupt register
|
|
(GOTGINTF)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SESEND</name>
|
|
<description>Session end </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRPEND</name>
|
|
<description>SRPEND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPEND</name>
|
|
<description>HNP end</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPDET</name>
|
|
<description>Host negotiation detected</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADTO</name>
|
|
<description>A-device timeout</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DF</name>
|
|
<description>Debounce finish</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GAHBCS</name>
|
|
<displayName>GAHBCS</displayName>
|
|
<description>Global AHB configuration register
|
|
(GAHBCS)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GINTEN</name>
|
|
<description>Global interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURST</name>
|
|
<description>AHB burst type used by DMA</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA function enalbed</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFTH</name>
|
|
<description>TxFIFO threshold</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTXFTH</name>
|
|
<description>Periodic TxFIFO empty
|
|
level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GUSBCS</name>
|
|
<displayName>GUSBCS</displayName>
|
|
<description>USB configuration register
|
|
(GUSBCS)</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000A00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TOC</name>
|
|
<description>timeout calibration</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EMBPHY</name>
|
|
<description>Embedded PHY selected</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SRPCEN</name>
|
|
<description>SRP capability enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HNPCEN</name>
|
|
<description>HNP capability enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UTT</name>
|
|
<description>USB turnaround time</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ULPIEVD</name>
|
|
<description>ULPI external VBUS driver</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ULPIEOI</name>
|
|
<description>ULPI external over current indicator</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FHM</name>
|
|
<description>Force host mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDM</name>
|
|
<description>Force device mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTCTL</name>
|
|
<displayName>GRSTCTL</displayName>
|
|
<description> Global reset register
|
|
(GRSTCTL)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSRST</name>
|
|
<description>Core soft reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HCSRST</name>
|
|
<description>HCLK soft reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HFCRST</name>
|
|
<description>Host frame counter reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RxFIFO flush</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFF</name>
|
|
<description>TxFIFO flush</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO number</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMABSY</name>
|
|
<description>DMA Busy</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAIDL</name>
|
|
<description>DMA idle state</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTF</name>
|
|
<displayName>GINTF</displayName>
|
|
<description>Global interrupt flag register
|
|
(GINTF)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x04000021</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COPM</name>
|
|
<description>Current mode of operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MFIF</name>
|
|
<description>Mode fault interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGIF</name>
|
|
<description>OTG interrupt</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Start of frame</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFNEIF</name>
|
|
<description>RxFIFO non-empty</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEIF</name>
|
|
<description>Non-periodic TxFIFO empty interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GNPINAK</name>
|
|
<description>Global IN non-periodic NAK
|
|
effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GONAK</name>
|
|
<description>Global OUT NAK effective</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ESP</name>
|
|
<description>Early suspend</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SP</name>
|
|
<description>USB suspend</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>USB reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMF</name>
|
|
<description>Enumeration finished</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOPDIF</name>
|
|
<description>Isochronous OUT packet dropped
|
|
interrupt flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPFIF</name>
|
|
<description>End of periodic frame
|
|
interrupt flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPIF</name>
|
|
<description>IN endpoint interrupt flag</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPIF</name>
|
|
<description>OUT endpoint interrupt flag</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOINCIF</name>
|
|
<description>Isochronous IN transfer Not Complete Interrupt Flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXNCIF_ISOONCIF</name>
|
|
<description>periodic transfer not complete interrupt flag(Host
|
|
mode)/isochronous OUT transfer not complete interrupt flag(Device
|
|
mode)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPIF</name>
|
|
<description>Host port interrupt flag</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HCIF</name>
|
|
<description>Host channels interrupt flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEIF</name>
|
|
<description>Periodic TxFIFO empty interrupt flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPSC</name>
|
|
<description>ID pin status change</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCIF</name>
|
|
<description>Disconnect interrupt flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESIF</name>
|
|
<description>Session interrupt flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIF</name>
|
|
<description>wakeup interrupt flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GINTEN</name>
|
|
<displayName>GINTEN</displayName>
|
|
<description>Global interrupt enable register
|
|
(GINTEN)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MFIE</name>
|
|
<description>Mode fault interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OTGIE</name>
|
|
<description>OTG interrupt enable </description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SOFIE</name>
|
|
<description>Start of frame interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXFNEIE</name>
|
|
<description>Receive FIFO non-empty
|
|
interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NPTXFEIE</name>
|
|
<description>Non-periodic TxFIFO empty
|
|
interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GNPINAKIE</name>
|
|
<description>Global non-periodic IN NAK interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GONAKIE</name>
|
|
<description>Global OUT NAK effective interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ESPIE</name>
|
|
<description>Early suspend interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPIE</name>
|
|
<description>USB suspend interrupt enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>USB reset interrupt enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENUMFIE</name>
|
|
<description>Enumeration finish enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOOPDIE</name>
|
|
<description>Isochronous OUT packet dropped interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPFIE</name>
|
|
<description>End of periodic frame interrupt enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPIE</name>
|
|
<description>IN endpoints interrupt enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OEPIE</name>
|
|
<description>OUT endpoints interrupt enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ISOINCIE</name>
|
|
<description>isochronous IN transfer not complete
|
|
interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXNCIE_ISOONCIE</name>
|
|
<description>periodic transfer not compelete Interrupt enable(Host
|
|
mode)/isochronous OUT transfer not complete interrupt enable(Device
|
|
mode)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPIE</name>
|
|
<description>Host port interrupt enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HCIE</name>
|
|
<description>Host channels interrupt enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXFEIE</name>
|
|
<description>Periodic TxFIFO empty interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDPSCIE</name>
|
|
<description>ID pin status change interrupt enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DISCIE</name>
|
|
<description>Disconnect interrupt enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SESIE</name>
|
|
<description>Session interrupt enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WKUPIE</name>
|
|
<description>Wakeup interrupt enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATR_Device</name>
|
|
<displayName>GRSTATR_Device</displayName>
|
|
<description>Global Receive status read(Device
|
|
mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Recieve packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATR_Host</name>
|
|
<displayName>GRSTATR_Host</displayName>
|
|
<description>Global Receive status debug read(Host
|
|
mode)</description>
|
|
<alternateRegister>GRSTATR_Device</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNUM</name>
|
|
<description>Channel number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Reivece packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATP_Device</name>
|
|
<displayName>GRSTATP_Device</displayName>
|
|
<description>Global Receive status pop(Device
|
|
mode)</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Recieve packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRSTATP_Host</name>
|
|
<displayName>GRSTATP_Host</displayName>
|
|
<description>Global Receive status debug pop(Host
|
|
mode)</description>
|
|
<alternateRegister>GRSTATP_Device</alternateRegister>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNUM</name>
|
|
<description>Channel number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BCOUNT</name>
|
|
<description>Byte count</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RPCKST</name>
|
|
<description>Reivece packet status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GRFLEN</name>
|
|
<displayName>GRFLEN</displayName>
|
|
<description>Global Receive FIFO size register
|
|
(OTG_FS_GRFLEN)</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFD</name>
|
|
<description>Rx FIFO depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HNPTFLEN</name>
|
|
<displayName>HNPTFLEN</displayName>
|
|
<description> Host non-periodic transmit FIFO size
|
|
register (Host mode)</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HNPTXRSAR</name>
|
|
<description>host non-periodic transmit Tx RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HNPTXFD</name>
|
|
<description>host non-periodic TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TFLEN</name>
|
|
<displayName>DIEP0TFLEN</displayName>
|
|
<description>Device IN endpoint 0 transmit FIFO length
|
|
(Device mode)</description>
|
|
<alternateRegister>HNPTFLEN</alternateRegister>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEP0TXFD</name>
|
|
<description>in endpoint 0 Tx FIFO depth</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEP0TXRSAR</name>
|
|
<description>in endpoint 0 Tx RAM start address</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HNPTFQSTAT</name>
|
|
<displayName>HNPTFQSTAT</displayName>
|
|
<description>Host non-periodic transmit FIFO/queue
|
|
status register (HNPTFQSTAT)</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00080200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NPTXFS</name>
|
|
<description>Non-periodic TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NPTXRQS</name>
|
|
<description>Non-periodic transmit request queue
|
|
space</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NPTXRQTOP</name>
|
|
<description>Top entry of the non-periodic Tx request queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GCCFG</name>
|
|
<displayName>GCCFG</displayName>
|
|
<description>Global core configuration register
|
|
(GCCFG)</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWRON</name>
|
|
<description>Power on</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSACEN</name>
|
|
<description>The VBUS A-device Comparer enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSBCEN</name>
|
|
<description>The VBUS B-device Comparer enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOFOEN</name>
|
|
<description>SOF output enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBUSIG</name>
|
|
<description>VBUS ignored</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CID</name>
|
|
<displayName>CID</displayName>
|
|
<description>core ID register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CID</name>
|
|
<description>Core ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTFLEN</name>
|
|
<displayName>HPTFLEN</displayName>
|
|
<description> Host periodic transmit FIFO size
|
|
register (HPTFLEN)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000600</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HPTXFSAR</name>
|
|
<description>Host periodic TxFIFO start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPTXFD</name>
|
|
<description>Host periodic TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1TFLEN</name>
|
|
<displayName>DIEP1TFLEN</displayName>
|
|
<description> device IN endpoint transmit FIFO size
|
|
register (DIEP1TFLEN)</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2TFLEN</name>
|
|
<displayName>DIEP2TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP2TFLEN)</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3TFLEN</name>
|
|
<displayName>DIEP3TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP3TXFLEN)</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4TFLEN</name>
|
|
<displayName>DIEP4TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP4TXFLEN)</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5TFLEN</name>
|
|
<displayName>DIEP5TFLEN</displayName>
|
|
<description>device IN endpoint transmit FIFO size
|
|
register (DIEP5TXFLEN)</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x02000400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXRSAR</name>
|
|
<description>IN endpoint FIFO4 transmit RAM start
|
|
address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPTXFD</name>
|
|
<description>IN endpoint TxFIFO depth</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HS_HOST</name>
|
|
<description>USB on the go full speed host</description>
|
|
<groupName>USB_HS</groupName>
|
|
<baseAddress>0x40040400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>HCTL</name>
|
|
<displayName>HCTL</displayName>
|
|
<description>host control register
|
|
(HCTL)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPDFSLS</name>
|
|
<description>Speed limited to FS and LS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFT</name>
|
|
<displayName>HFT</displayName>
|
|
<description>Host frame interval
|
|
register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000BB80</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRI</name>
|
|
<description>Frame interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFINFR</name>
|
|
<displayName>HFINFR</displayName>
|
|
<description>host frame number/frame time
|
|
remaining register (HFINFR)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0xBB800000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRNUM</name>
|
|
<description>Frame number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRT</name>
|
|
<description>Frame remaining time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPTFQSTAT</name>
|
|
<displayName>HPTFQSTAT</displayName>
|
|
<description>Host periodic transmit FIFO/queue
|
|
status register (HPTFQSTAT)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00080200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PTXFS</name>
|
|
<description>Periodic transmit data FIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXREQS</name>
|
|
<description>Periodic Tx request queue space</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PTXREQT</name>
|
|
<description>Top of the periodic transmit request
|
|
queue</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HACHINT</name>
|
|
<displayName>HACHINT</displayName>
|
|
<description> Host all channels interrupt
|
|
register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HACHINT</name>
|
|
<description>Host all channel interrupts</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HACHINTEN</name>
|
|
<displayName>HACHINTEN</displayName>
|
|
<description>host all channels interrupt mask
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CINTEN</name>
|
|
<description>Channel interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPCS</name>
|
|
<displayName>HPCS</displayName>
|
|
<description>host port control and status register
|
|
(HPCS)</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCST</name>
|
|
<description>Port connect status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PCD</name>
|
|
<description>Port connect detected</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Port enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEDC</name>
|
|
<description>Port enable/disable change</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PREM</name>
|
|
<description>Port resume</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSP</name>
|
|
<description>Port suspend</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRST</name>
|
|
<description>Port reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLST</name>
|
|
<description>Port line status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PP</name>
|
|
<description>Port power</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Port speed</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0CTL</name>
|
|
<displayName>HCH0CTL</displayName>
|
|
<description>host channel-0 control
|
|
register (HCH0CTL)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1CTL</name>
|
|
<displayName>HCH1CTL</displayName>
|
|
<description> host channel-1 control
|
|
register (HCH1CTL)</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2CTL</name>
|
|
<displayName>HCH2CTL</displayName>
|
|
<description>host channel-2 control
|
|
register (HCH2CTL)</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3CTL</name>
|
|
<displayName>HCH3CTL</displayName>
|
|
<description>host channel-3 control
|
|
register (HCH3CTL)</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4CTL</name>
|
|
<displayName>HCH4CTL</displayName>
|
|
<description> host channel-4 control
|
|
register (HCH4CTL)</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5CTL</name>
|
|
<displayName>HCH5CTL</displayName>
|
|
<description>host channel-5 control
|
|
register (HCH5CTL)</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6CTL</name>
|
|
<displayName>HCH6CTL</displayName>
|
|
<description>host channel-6 control
|
|
register (HCH6CTL)</description>
|
|
<addressOffset>0x1C0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7CTL</name>
|
|
<displayName>HCH7CTL</displayName>
|
|
<description>host channel-7 control
|
|
register (HCH7CTL)</description>
|
|
<addressOffset>0x1E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH8CTL</name>
|
|
<displayName>HCH8CTL</displayName>
|
|
<description>host channel-8 control
|
|
register (HCH8CTL)</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH9CTL</name>
|
|
<displayName>HCH9CTL</displayName>
|
|
<description>host channel-9 control
|
|
register (HCH9CTL)</description>
|
|
<addressOffset>0x220</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH10CTL</name>
|
|
<displayName>HCH10CTL</displayName>
|
|
<description>host channel-10 control
|
|
register (HCH10CTL)</description>
|
|
<addressOffset>0x240</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH11CTL</name>
|
|
<displayName>HCH11CTL</displayName>
|
|
<description>host channel-11 control
|
|
register (HCH11CTL)</description>
|
|
<addressOffset>0x260</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet size</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPNUM</name>
|
|
<description>Endpoint number</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIR</name>
|
|
<description>Endpoint direction</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSD</name>
|
|
<description>Low-speed device</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPC</name>
|
|
<description>Multiple packet count</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODDFRM</name>
|
|
<description>Odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CDIS</name>
|
|
<description>Channel disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Channel enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0STCTL</name>
|
|
<displayName>HCH0STCTL</displayName>
|
|
<description>host channel-0 split transaction control register
|
|
(HCH0STCTL)</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1STCTL</name>
|
|
<displayName>HCH1STCTL</displayName>
|
|
<description>host channel-1 split transaction control register
|
|
(HCH1STCTL)</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2STCTL</name>
|
|
<displayName>HCH2STCTL</displayName>
|
|
<description>host channel-2 split transaction control register
|
|
(HCH2STCTL)</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3STCTL</name>
|
|
<displayName>HCH3STCTL</displayName>
|
|
<description>host channel-3 split transaction control register
|
|
(HCH3STCTL)</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4STCTL</name>
|
|
<displayName>HCH4STCTL</displayName>
|
|
<description>host channel-4 split transaction control register
|
|
(HCH4STCTL)</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5STCTL</name>
|
|
<displayName>HCH5STCTL</displayName>
|
|
<description>host channel-5 split transaction control register
|
|
(HCH5STCTL)</description>
|
|
<addressOffset>0x1A4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6STCTL</name>
|
|
<displayName>HCH6STCTL</displayName>
|
|
<description>host channel-6 split transaction control register
|
|
(HCH6STCTL)</description>
|
|
<addressOffset>0x1C4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7STCTL</name>
|
|
<displayName>HCH7STCTL</displayName>
|
|
<description>host channel-7 split transaction control register
|
|
(HCH7STCTL)</description>
|
|
<addressOffset>0x1E4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH8STCTL</name>
|
|
<displayName>HCH8STCTL</displayName>
|
|
<description>host channel-8 split transaction control register
|
|
(HCH8STCTL)</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH9STCTL</name>
|
|
<displayName>HCH9STCTL</displayName>
|
|
<description>host channel-9 split transaction control register
|
|
(HCH9STCTL)</description>
|
|
<addressOffset>0x224</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH10STCTL</name>
|
|
<displayName>HCH10STCTL</displayName>
|
|
<description>host channel-10 split transaction control register
|
|
(HCH10STCTL)</description>
|
|
<addressOffset>0x244</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH11STCTL</name>
|
|
<displayName>HCH11STCTL</displayName>
|
|
<description>host channel-11 split transaction control register
|
|
(HCH11STCTL)</description>
|
|
<addressOffset>0x264</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PADDR</name>
|
|
<description>Port address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HADDR</name>
|
|
<description>HUB address</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISOPCE</name>
|
|
<description>Isochronous OUT payload continuation encoding</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSPLT</name>
|
|
<description>Complete split enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPLEN</name>
|
|
<description> Enable high speed split transaction</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0INTF</name>
|
|
<displayName>HCH0INTF</displayName>
|
|
<description>host channel-0 interrupt flag register
|
|
(HCH0INTF)</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1INTF</name>
|
|
<displayName>HCH1INTF</displayName>
|
|
<description>host channel-1 interrupt flag register
|
|
(HCH1INTF)</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH2INTF</name>
|
|
<displayName>HCH2INTF</displayName>
|
|
<description>host channel-2 interrupt flag register
|
|
(HCH2INTF)</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH3INTF</name>
|
|
<displayName>HCH3INTF</displayName>
|
|
<description>host channel-3 interrupt flag register
|
|
(HCH3INTF)</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH4INTF</name>
|
|
<displayName>HCH4INTF</displayName>
|
|
<description>host channel-4 interrupt flag register
|
|
(HCH4INTF)</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH5INTF</name>
|
|
<displayName>HCH5INTF</displayName>
|
|
<description>host channel-5 interrupt flag register
|
|
(HCH5INTF)</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6INTF</name>
|
|
<displayName>HCH6INTF</displayName>
|
|
<description>host channel-6 interrupt flag register
|
|
(HCH6INTF)</description>
|
|
<addressOffset>0x1C8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH7INTF</name>
|
|
<displayName>HCH7INTF</displayName>
|
|
<description>host channel-7 interrupt flag register
|
|
(HCH7INTF)</description>
|
|
<addressOffset>0x1E8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH8INTF</name>
|
|
<displayName>HCH8INTF</displayName>
|
|
<description>host channel-8 interrupt flag register
|
|
(HCH8INTF)</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH9INTF</name>
|
|
<displayName>HCH9INTF</displayName>
|
|
<description>host channel-9 interrupt flag register
|
|
(HCH9INTF)</description>
|
|
<addressOffset>0x228</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH10INTF</name>
|
|
<displayName>HCH10INTF</displayName>
|
|
<description>host channel-10 interrupt flag register
|
|
(HCH10INTF)</description>
|
|
<addressOffset>0x248</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH11INTF</name>
|
|
<displayName>HCH11INTF</displayName>
|
|
<description>host channel-11 interrupt flag register
|
|
(HCH11INTF)</description>
|
|
<addressOffset>0x268</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer completed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CH</name>
|
|
<description>Channel halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAER</name>
|
|
<description>DMA Error</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL response received
|
|
interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK response received
|
|
interrupt</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>ACK response received/transmitted
|
|
interrupt</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBER</name>
|
|
<description>USB bus error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBER</name>
|
|
<description>Babble error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVR</name>
|
|
<description>Request queue overrun</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTER</name>
|
|
<description>Data toggle error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0INTEN</name>
|
|
<displayName>HCH0INTEN</displayName>
|
|
<description>host channel-0 interrupt enable register
|
|
(HCH0INTEN)</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH1INTEN</name>
|
|
<displayName>HCH1INTEN</displayName>
|
|
<description>host channel-1 interrupt enable register
|
|
(HCH1INTEN)</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH2INTEN</name>
|
|
<displayName>HCH2INTEN</displayName>
|
|
<description>host channel-2 interrupt enable register
|
|
(HCH2INTEN)</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH3INTEN</name>
|
|
<displayName>HCH3INTEN</displayName>
|
|
<description>host channel-3 interrupt enable register
|
|
(HCH3INTEN)</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH4INTEN</name>
|
|
<displayName>HCH4INTEN</displayName>
|
|
<description>host channel-4 interrupt enable register
|
|
(HCH4INTEN)</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH5INTEN</name>
|
|
<displayName>HCH5INTEN</displayName>
|
|
<description>host channel-5 interrupt enable register
|
|
(HCH5INTEN)</description>
|
|
<addressOffset>0x1AC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH6INTEN</name>
|
|
<displayName>HCH6INTEN</displayName>
|
|
<description>host channel-6 interrupt enable register
|
|
(HCH6INTEN)</description>
|
|
<addressOffset>0x1CC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH7INTEN</name>
|
|
<displayName>HCH7INTEN</displayName>
|
|
<description>host channel-7 interrupt enable register
|
|
(HCH7INTEN)</description>
|
|
<addressOffset>0x1EC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH8INTEN</name>
|
|
<displayName>HCH8INTEN</displayName>
|
|
<description>host channel-8 interrupt enable register
|
|
(HCH8INTEN)</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH9INTEN</name>
|
|
<displayName>HCH9INTEN</displayName>
|
|
<description>host channel-9 interrupt enable register
|
|
(HCH9INTEN)</description>
|
|
<addressOffset>0x22C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH10INTEN</name>
|
|
<displayName>HCH10INTEN</displayName>
|
|
<description>host channel-10 interrupt enable register
|
|
(HCH10INTEN)</description>
|
|
<addressOffset>0x24C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH11INTEN</name>
|
|
<displayName>HCH11INTEN</displayName>
|
|
<description>host channel-11 interrupt enable register
|
|
(HCH11INTEN)</description>
|
|
<addressOffset>0x26C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFIE</name>
|
|
<description>Transfer finished interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHIE</name>
|
|
<description>Channel halted interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAERIE</name>
|
|
<description>DMA error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STALLIE</name>
|
|
<description>STALL interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKIE</name>
|
|
<description>NAK interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACKIE</name>
|
|
<description>ACK interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETIE</name>
|
|
<description>NYET
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBERIE</name>
|
|
<description>USB bus error interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BBERIE</name>
|
|
<description>Babble error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REQOVRIE</name>
|
|
<description>request queue overrun interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTERIE</name>
|
|
<description>Data toggle error interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>HCH0LEN</name>
|
|
<displayName>HCH0LEN</displayName>
|
|
<description>host channel-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1LEN</name>
|
|
<displayName>HCH1LEN</displayName>
|
|
<description>host channel-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2LEN</name>
|
|
<displayName>HCH2LEN</displayName>
|
|
<description> host channel-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3LEN</name>
|
|
<displayName>HCH3LEN</displayName>
|
|
<description> host channel-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4LEN</name>
|
|
<displayName>HCH4LEN</displayName>
|
|
<description>host channel-4 transfer length
|
|
register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5LEN</name>
|
|
<displayName>HCH5LEN</displayName>
|
|
<description>host channel-5 transfer length
|
|
register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6LEN</name>
|
|
<displayName>HCH6LEN</displayName>
|
|
<description>host channel-6 transfer length
|
|
register</description>
|
|
<addressOffset>0x1D0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7LEN</name>
|
|
<displayName>HCH7LEN</displayName>
|
|
<description>host channel-7 transfer length
|
|
register</description>
|
|
<addressOffset>0x1F0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH8LEN</name>
|
|
<displayName>HCH8LEN</displayName>
|
|
<description>host channel-8 transfer length
|
|
register</description>
|
|
<addressOffset>0x210</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH9LEN</name>
|
|
<displayName>HCH9LEN</displayName>
|
|
<description>host channel-9 transfer length
|
|
register</description>
|
|
<addressOffset>0x230</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH10LEN</name>
|
|
<displayName>HCH10LEN</displayName>
|
|
<description>host channel-10 transfer length
|
|
register</description>
|
|
<addressOffset>0x250</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH11LEN</name>
|
|
<displayName>HCH11LEN</displayName>
|
|
<description>host channel-11 transfer length
|
|
register</description>
|
|
<addressOffset>0x270</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DPID</name>
|
|
<description>Data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PING</name>
|
|
<description>Ping token request</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH0DMAADDR</name>
|
|
<displayName>HCH0DMAADDR</displayName>
|
|
<description>host channel-0 DMA address
|
|
register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH1DMAADDR</name>
|
|
<displayName>HCH1DMAADDR</displayName>
|
|
<description>host channel-1 DMA address
|
|
register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH2DMAADDR</name>
|
|
<displayName>HCH2DMAADDR</displayName>
|
|
<description>host channel-2 DMA address
|
|
register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH3DMAADDR</name>
|
|
<displayName>HCH3DMAADDR</displayName>
|
|
<description>host channel-3 DMA address
|
|
register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH4DMAADDR</name>
|
|
<displayName>HCH4DMAADDR</displayName>
|
|
<description>host channel-4 DMA address
|
|
register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH5DMAADDR</name>
|
|
<displayName>HCH5DMAADDR</displayName>
|
|
<description>host channel-5 DMA address
|
|
register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH6DMAADDR</name>
|
|
<displayName>HCH6DMAADDR</displayName>
|
|
<description>host channel-6 DMA address
|
|
register</description>
|
|
<addressOffset>0x1D4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH7DMAADDR</name>
|
|
<displayName>HCH7DMAADDR</displayName>
|
|
<description>host channel-7 DMA address
|
|
register</description>
|
|
<addressOffset>0x1F4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH8DMAADDR</name>
|
|
<displayName>HCH8DMAADDR</displayName>
|
|
<description>host channel-8 DMA address
|
|
register</description>
|
|
<addressOffset>0x214</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH9DMAADDR</name>
|
|
<displayName>HCH9DMAADDR</displayName>
|
|
<description>host channel-9 DMA address
|
|
register</description>
|
|
<addressOffset>0x234</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH10DMAADDR</name>
|
|
<displayName>HCH10DMAADDR</displayName>
|
|
<description>host channel-10 DMA address
|
|
register</description>
|
|
<addressOffset>0x254</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HCH11DMAADDR</name>
|
|
<displayName>HCH11DMAADDR</displayName>
|
|
<description>host channel-11 DMA address
|
|
register</description>
|
|
<addressOffset>0x274</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HS_DEVICE</name>
|
|
<description>USB on the go high speed device</description>
|
|
<groupName>USB_HS</groupName>
|
|
<baseAddress>0x40040800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DCFG</name>
|
|
<displayName>DCFG</displayName>
|
|
<description>device configuration register
|
|
(DCFG)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Device speed</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NZLSOH</name>
|
|
<description>Non-zero-length status OUT
|
|
handshake</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>Device address</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOPFT</name>
|
|
<description>end of periodic frame time</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCTL</name>
|
|
<displayName>DCTL</displayName>
|
|
<description>device control register
|
|
(DCTL)</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RWKUP</name>
|
|
<description>Remote wakeup signaling</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD</name>
|
|
<description>Soft disconnect</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GINS</name>
|
|
<description>Global IN NAK status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GONS</name>
|
|
<description>Global OUT NAK status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SGINAK</name>
|
|
<description>Set global IN NAK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CGINAK</name>
|
|
<description>Clear global IN NAK</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SGONAK</name>
|
|
<description>Set global OUT NAK</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CGONAK</name>
|
|
<description>Clear global OUT NAK</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POIF</name>
|
|
<description>Power-on initialization finished</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSTAT</name>
|
|
<displayName>DSTAT</displayName>
|
|
<description>device status register
|
|
(DSTAT)</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SPST</name>
|
|
<description>Suspend status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ES</name>
|
|
<description>Enumerated speed</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FNRSOF</name>
|
|
<description>Frame number of the received
|
|
SOF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPINTEN</name>
|
|
<displayName>DIEPINTEN</displayName>
|
|
<description>device IN endpoint common interrupt
|
|
mask register (DIEPINTEN)</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer completed interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITOEN</name>
|
|
<description>Control IN timeout condition interrupt enable (Non-isochronous
|
|
endpoints)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUDEN</name>
|
|
<description>Endpoint Tx FIFO underrun interrupt enable bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPNEEN</name>
|
|
<description>IN endpoint NAK effective
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFEEN</name>
|
|
<description>Trabsmit FIFO empty
|
|
interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKEN</name>
|
|
<description>NAK handshake sent by USBHS interrupt enable bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEPINTEN</name>
|
|
<displayName>DOEPINTEN</displayName>
|
|
<description>device OUT endpoint common interrupt
|
|
enable register (DOEPINTEN)</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer completed interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPFEN</name>
|
|
<description>SETUP phase done interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVREN</name>
|
|
<description> Endpoint Rx FIFO overrun interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTPEN</name>
|
|
<description> Back-to-back SETUP packets
|
|
( Only for control OUT endpoint) interrupt enable bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETEN</name>
|
|
<description> NYET handshake is sent
|
|
interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAEPINT</name>
|
|
<displayName>DAEPINT</displayName>
|
|
<description>device all endpoints interrupt
|
|
register (DAEPINT)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPITB</name>
|
|
<description>Device all IN endpoint interrupt bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEPITB</name>
|
|
<description>Device all OUT endpoint interrupt
|
|
bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAEPINTEN</name>
|
|
<displayName>DAEPINTEN</displayName>
|
|
<description>Device all endpoints interrupt enable register
|
|
(DAEPINTEN)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPIE</name>
|
|
<description>IN endpoint interrupt enable bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEPIE</name>
|
|
<description>OUT endpoint interrupt enable bits</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSDT</name>
|
|
<displayName>DVBUSDT</displayName>
|
|
<description>device VBUS discharge time
|
|
register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000017D7</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSDT</name>
|
|
<description>Device VBUS discharge time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DVBUSPT</name>
|
|
<displayName>DVBUSPT</displayName>
|
|
<description>device VBUS pulsing time
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000005B8</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DVBUSPT</name>
|
|
<description>Device VBUS pulsing time</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEPFEINTEN</name>
|
|
<displayName>DIEPFEINTEN</displayName>
|
|
<description>device IN endpoint FIFO empty
|
|
interrupt enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTXFEIE</name>
|
|
<description>IN EP Tx FIFO empty interrupt enable
|
|
bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEP1INT</name>
|
|
<displayName>DEP1INT</displayName>
|
|
<description>device endpoint 1
|
|
interrupt register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEP1INT</name>
|
|
<description>IN endpoint 1 interrupt
|
|
bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEP1INT</name>
|
|
<description>OUT endpoint 1 interrupt
|
|
bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEP1INTEN</name>
|
|
<displayName>DEP1INTEN</displayName>
|
|
<description>device endpoint 1
|
|
interrupt enable register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEP1INTEN</name>
|
|
<description>IN endpoint 1 interrupt enable
|
|
bits</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OEP1INTEN</name>
|
|
<description>OUT endpoint 1 interrupt enable
|
|
bits</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1INTEN</name>
|
|
<displayName>DIEP1INTEN</displayName>
|
|
<description>device IN endpoint 1 interrupt
|
|
mask register (DIEP1INTEN)</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer finished interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITOEN</name>
|
|
<description>Control IN timeout condition interrupt enable (Non-isochronous
|
|
endpoints)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUDEN</name>
|
|
<description>Endpoint Tx FIFO underrun interrupt enable bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEPNEEN</name>
|
|
<description>IN endpoint NAK effective
|
|
interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NAKEN</name>
|
|
<description>NAK handshake sent by USBHS
|
|
interrupt enable bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1INTEN</name>
|
|
<displayName>DOEP1INTEN</displayName>
|
|
<description>device OUT endpoint common interrupt
|
|
enable register (DOEP1INTEN)</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFEN</name>
|
|
<description>Transfer completed interrupt
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDISEN</name>
|
|
<description>Endpoint disabled interrupt
|
|
enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPFEN</name>
|
|
<description>SETUP phase done interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVREN</name>
|
|
<description> Endpoint Rx FIFO overrun interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTPEN</name>
|
|
<description> Back-to-back SETUP packets ( Only for control OUT endpoint)
|
|
interrupt enable bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NYETEN</name>
|
|
<description>NYET handshake is sent interrupt enable bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0CTL</name>
|
|
<displayName>DIEP0CTL</displayName>
|
|
<description>Device IN endpoint 0 control register
|
|
(USBHS_DIEP0CTL)</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>TxFIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1CTL</name>
|
|
<displayName>DIEP1CTL</displayName>
|
|
<description>Device IN endpoint-x control register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2CTL</name>
|
|
<displayName>DIEP2CTL</displayName>
|
|
<description>device endpoint-2 control
|
|
register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3CTL</name>
|
|
<displayName>DIEP3CTL</displayName>
|
|
<description>device endpoint-3 control
|
|
register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4CTL</name>
|
|
<displayName>DIEP4CTL</displayName>
|
|
<description>device endpoint-4 control
|
|
register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5CTL</name>
|
|
<displayName>DIEP5CTL</displayName>
|
|
<description>device endpoint-5 control
|
|
register</description>
|
|
<addressOffset>0x1A0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>Set DATA1 PID/Set odd frame</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVNFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFNUM</name>
|
|
<description>Tx FIFO number</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0CTL</name>
|
|
<displayName>DOEP0CTL</displayName>
|
|
<description>Device OUT endpoint-0 control
|
|
register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>Maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1CTL</name>
|
|
<displayName>DOEP1CTL</displayName>
|
|
<description>Device OUT endpoint-1 control
|
|
register</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2CTL</name>
|
|
<displayName>DOEP2CTL</displayName>
|
|
<description>Device OUT endpoint-2 control
|
|
register</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3CTL</name>
|
|
<displayName>DOEP3CTL</displayName>
|
|
<description>Device OUT endpoint-3 control
|
|
register</description>
|
|
<addressOffset>0x360</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4CTL</name>
|
|
<displayName>DOEP4CTL</displayName>
|
|
<description>Device OUT endpoint-4 control
|
|
register</description>
|
|
<addressOffset>0x380</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5CTL</name>
|
|
<displayName>DOEP5CTL</displayName>
|
|
<description>Device OUT endpoint-5 control
|
|
register</description>
|
|
<addressOffset>0x3A0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EPEN</name>
|
|
<description>Endpoint enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPD</name>
|
|
<description>Endpoint disable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SD1PID_SODDFRM</name>
|
|
<description>SD1PID/SODDFRM</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SD0PID_SEVENFRM</name>
|
|
<description>SD0PID/SEVENFRM</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SNAK</name>
|
|
<description>Set NAK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNAK</name>
|
|
<description>Clear NAK</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STALL</name>
|
|
<description>STALL handshake</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SNOOP</name>
|
|
<description>Snoop mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTYPE</name>
|
|
<description>Endpoint type</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NAKS</name>
|
|
<description>NAK status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EOFRM_DPID</name>
|
|
<description>EOFRM/DPID</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EPACT</name>
|
|
<description>Endpoint active</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MPL</name>
|
|
<description>maximum packet length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0INTF</name>
|
|
<displayName>DIEP0INTF</displayName>
|
|
<description>Device IN endpoint-0 interrupt
|
|
register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1INTF</name>
|
|
<displayName>DIEP1INTF</displayName>
|
|
<description>Device IN endpoint-1 interrupt
|
|
register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2INTF</name>
|
|
<displayName>DIEP2INTF</displayName>
|
|
<description>Device IN endpoint-2 interrupt
|
|
register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3INTF</name>
|
|
<displayName>DIEP3INTF</displayName>
|
|
<description>Device IN endpoint-3 interrupt
|
|
register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4INTF</name>
|
|
<displayName>DIEP4INTF</displayName>
|
|
<description>Device IN endpoint-4 interrupt
|
|
register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5INTF</name>
|
|
<displayName>DIEP5INTF</displayName>
|
|
<description>Device IN endpoint-5 interrupt
|
|
register</description>
|
|
<addressOffset>0x1A8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NAK</name>
|
|
<description>NAK handshake sent by USBHS</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>Transmit FIFO empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IEPNE</name>
|
|
<description>IN endpoint NAK effective</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPTXFUD</name>
|
|
<description>Endpoint Tx FIFO underrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CITO</name>
|
|
<description>Control in timeout interrupt</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint finished</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0INTF</name>
|
|
<displayName>DOEP0INTF</displayName>
|
|
<description>device out endpoint-0 interrupt
|
|
register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1INTF</name>
|
|
<displayName>DOEP1INTF</displayName>
|
|
<description>device out endpoint-1 interrupt
|
|
register</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2INTF</name>
|
|
<displayName>DOEP2INTF</displayName>
|
|
<description>device out endpoint-2 interrupt
|
|
register</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3INTF</name>
|
|
<displayName>DOEP3INTF</displayName>
|
|
<description>device out endpoint-3 interrupt
|
|
register</description>
|
|
<addressOffset>0x368</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4INTF</name>
|
|
<displayName>DOEP4INTF</displayName>
|
|
<description>device out endpoint-4 interrupt
|
|
register</description>
|
|
<addressOffset>0x388</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5INTF</name>
|
|
<displayName>DOEP5INTF</displayName>
|
|
<description>device out endpoint-5 interrupt
|
|
register</description>
|
|
<addressOffset>0x3A8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NYET</name>
|
|
<description>NYET handshake is sent</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BTBSTP</name>
|
|
<description>Back-to-back SETUP packets</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPRXFOVR</name>
|
|
<description>Endpoint Rx FIFO overrun</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STPF</name>
|
|
<description>Setup phase finished</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPDIS</name>
|
|
<description>Endpoint disabled</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF</name>
|
|
<description>Transfer finished</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0LEN</name>
|
|
<displayName>DIEP0LEN</displayName>
|
|
<description>device IN endpoint-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0LEN</name>
|
|
<displayName>DOEP0LEN</displayName>
|
|
<description>device OUT endpoint-0 transfer length
|
|
register</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT</name>
|
|
<description>SETUP packet count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1LEN</name>
|
|
<displayName>DIEP1LEN</displayName>
|
|
<description>device IN endpoint-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Multi count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2LEN</name>
|
|
<displayName>DIEP2LEN</displayName>
|
|
<description>device IN endpoint-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Multi count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3LEN</name>
|
|
<displayName>DIEP3LEN</displayName>
|
|
<description>device IN endpoint-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Multi count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4LEN</name>
|
|
<displayName>DIEP4LEN</displayName>
|
|
<description>device IN endpoint-4 transfer length
|
|
register</description>
|
|
<addressOffset>0x190</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Multi count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5LEN</name>
|
|
<displayName>DIEP5LEN</displayName>
|
|
<description>device IN endpoint-5 transfer length
|
|
register</description>
|
|
<addressOffset>0x1B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Multi count</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1LEN</name>
|
|
<displayName>DOEP1LEN</displayName>
|
|
<description>device OUT endpoint-1 transfer length
|
|
register</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2LEN</name>
|
|
<displayName>DOEP2LEN</displayName>
|
|
<description>device OUT endpoint-2 transfer length
|
|
register</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3LEN</name>
|
|
<displayName>DOEP3LEN</displayName>
|
|
<description>device OUT endpoint-3 transfer length
|
|
register</description>
|
|
<addressOffset>0x370</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4LEN</name>
|
|
<displayName>DOEP4LEN</displayName>
|
|
<description>device OUT endpoint-4 transfer length
|
|
register</description>
|
|
<addressOffset>0x390</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5LEN</name>
|
|
<displayName>DOEP5LEN</displayName>
|
|
<description>device OUT endpoint-5 transfer length
|
|
register</description>
|
|
<addressOffset>0x3B0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STPCNT_RXDPID</name>
|
|
<description>SETUP packet count/Received data PID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCNT</name>
|
|
<description>Packet count</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TLEN</name>
|
|
<description>Transfer length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0DMAADDR</name>
|
|
<displayName>DIEP0DMAADDR</displayName>
|
|
<description>device IN endpoint 0 DMA address register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1DMAADDR</name>
|
|
<displayName>DIEP1DMAADDR</displayName>
|
|
<description>device IN endpoint 1 DMA address register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2DMAADDR</name>
|
|
<displayName>DIEP2DMAADDR</displayName>
|
|
<description>device IN endpoint 2 DMA address register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3DMAADDR</name>
|
|
<displayName>DIEP3DMAADDR</displayName>
|
|
<description>device IN endpoint 3 DMA address register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4DMAADDR</name>
|
|
<displayName>DIEP4DMAADDR</displayName>
|
|
<description>device IN endpoint 4 DMA address register</description>
|
|
<addressOffset>0x194</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5DMAADDR</name>
|
|
<displayName>DIEP5DMAADDR</displayName>
|
|
<description>device IN endpoint 5 DMA address register</description>
|
|
<addressOffset>0x1B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP0DMAADDR</name>
|
|
<displayName>DOEP0DMAADDR</displayName>
|
|
<description>device OUT endpoint 0 DMA address register</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP1DMAADDR</name>
|
|
<displayName>DOEP1DMAADDR</displayName>
|
|
<description>device OUT endpoint 1 DMA address register</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP2DMAADDR</name>
|
|
<displayName>DOEP2DMAADDR</displayName>
|
|
<description>device OUT endpoint 2 DMA address register</description>
|
|
<addressOffset>0x354</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP3DMAADDR</name>
|
|
<displayName>DOEP3DMAADDR</displayName>
|
|
<description>device OUT endpoint 3 DMA address register</description>
|
|
<addressOffset>0x374</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP4DMAADDR</name>
|
|
<displayName>DOEP4DMAADDR</displayName>
|
|
<description>device OUT endpoint 4 DMA address register</description>
|
|
<addressOffset>0x394</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOEP5DMAADDR</name>
|
|
<displayName>DOEP5DMAADDR</displayName>
|
|
<description>device OUT endpoint 5 DMA address register</description>
|
|
<addressOffset>0x3B4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAADDR</name>
|
|
<description>DMA address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP0TFSTAT</name>
|
|
<displayName>DIEP0TFSTAT</displayName>
|
|
<description>device IN endpoint 0 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP1TFSTAT</name>
|
|
<displayName>DIEP1TFSTAT</displayName>
|
|
<description>device IN endpoint 1 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP2TFSTAT</name>
|
|
<displayName>DIEP2TFSTAT</displayName>
|
|
<description>device IN endpoint 2 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP3TFSTAT</name>
|
|
<displayName>DIEP3TFSTAT</displayName>
|
|
<description>device IN endpoint 3 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP4TFSTAT</name>
|
|
<displayName>DIEP4TFSTAT</displayName>
|
|
<description>device IN endpoint 4 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x198</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIEP5TFSTAT</name>
|
|
<displayName>DIEP5TFSTAT</displayName>
|
|
<description>device IN endpoint 5 transmit FIFO
|
|
status register</description>
|
|
<addressOffset>0x1B8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IEPTFS</name>
|
|
<description>IN endpoint TxFIFO space
|
|
available</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HS_PWRCLK</name>
|
|
<description>USB on the go high speed power and clock</description>
|
|
<groupName>USB_HS</groupName>
|
|
<baseAddress>0x40040E00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>PWRCLKCTL</name>
|
|
<displayName>PWRCLKCTL</displayName>
|
|
<description>power and clock gating control
|
|
register (PWRCLKCTL)</description>
|
|
<addressOffset>0x00</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SUCLK</name>
|
|
<description>Stop the USB clock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SHCLK</name>
|
|
<description>Stop HCLK</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>WWDGT</name>
|
|
<description>Window watchdog timer</description>
|
|
<groupName>WWDGT</groupName>
|
|
<baseAddress>0x40002C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>WWDGT</name>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<displayName>CTL</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDGTEN</name>
|
|
<description>Activation bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>7-bit counter</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG</name>
|
|
<displayName>CFG</displayName>
|
|
<description>Configuration register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000007F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWIE</name>
|
|
<description>Early wakeup interrupt</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIN</name>
|
|
<description>7-bit window value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x08</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWIF</name>
|
|
<description>Early wakeup interrupt
|
|
flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
</peripherals>
|
|
</device>
|