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compare: hulk:b24c0853c94416d320a081f847b92cba8edbb620
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3 Commits
8adabcd08d ... b24c0853c9

Author SHA1 Message Date
yelvlab
b24c0853c9 rewrite write 16bits 2025-08-16 15:53:47 +08:00
yelvlab
77a6525168 rewrite read 16bits 2025-08-16 04:06:46 +08:00
yelvlab
6cc7b2dae2 add task button 2025-08-16 04:05:22 +08:00
2 changed files with 285 additions and 255 deletions
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6
.vscode/tasks.json vendored
View File

@@ -11,7 +11,11 @@
"Build", "Build",
"Flash MCU" "Flash MCU"
], ],
"dependsOrder": "sequence" "dependsOrder": "sequence",
"icon": {
"id": "play",
"tooltip": "Build and Flash"
}
}, },
{ {
"label": "Flash MCU", "label": "Flash MCU",

532
Src/i2c.c
View File

@@ -156,7 +156,6 @@ i2c_result_t i2c_bus_reset(void) {
return I2C_RECOVERY_OK; return I2C_RECOVERY_OK;
} }
#ifdef DEBUG_VERBOSE
/** /**
* @brief 扫描I2C总线，查找连接的设备 * @brief 扫描I2C总线，查找连接的设备
* *
@@ -263,364 +262,391 @@ void i2c_scan(void) {
while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {} while (usart_flag_get(I2C_DEBUG_UART, USART_FLAG_TC) == RESET) {}
} }
} }
#endif
i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) { i2c_result_t i2c_write_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t data[2]) {
uint8_t state = I2C_STATE_START; i2c_state_t state = I2C_STATE_START;
uint16_t timeout = 0; uint16_t timeout = 0;
uint8_t i2c_timeout_flag = 0; uint8_t retry_count = 0;
/* parameter validation */ /* parameter validation */
if (data == NULL || slave_addr > 0x7F) { if (data == NULL || slave_addr > 0x7F) {
return I2C_RESULT_INVALID_PARAM; return I2C_RESULT_INVALID_PARAM;
} }
/* enable acknowledge */ while (retry_count < I2C_MAX_RETRY) {
i2c_ack_config(I2C0, I2C_ACK_ENABLE);
while (!(i2c_timeout_flag)) {
switch (state) { switch (state) {
case I2C_STATE_START: case I2C_STATE_START:
/* i2c master sends start signal only when the bus is idle */ timeout = 0;
/* wait for bus to be idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) { while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
i2c_start_on_bus(I2C0); state = I2C_STATE_ERROR;
timeout = 0; break;
state = I2C_STATE_SEND_ADDRESS;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c bus is busy in WRITE BYTE!\n");
#endif
} }
i2c_start_on_bus(I2C0);
timeout = 0;
state = I2C_STATE_SEND_ADDRESS;
break; break;
case I2C_STATE_SEND_ADDRESS: case I2C_STATE_SEND_ADDRESS:
/* i2c master sends START signal successfully */ /* wait for start condition to be sent. SBSEND flag */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { while((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER); state = I2C_STATE_ERROR;
timeout = 0; break;
state = I2C_STATE_CLEAR_ADDRESS;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends start signal timeout in WRITE BYTE!\n");
#endif
} }
/* send slave address */
i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER);
timeout = 0;
state = I2C_STATE_CLEAR_ADDRESS;
break; break;
case I2C_STATE_CLEAR_ADDRESS: case I2C_STATE_CLEAR_ADDRESS:
/* address flag set means i2c slave sends ACK */ /* wait for address to be acknowledged.ADDSEND set means i2c slave sends ACK */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) { while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (!i2c_flag_get(I2C0, I2C_FLAG_AERR)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
} else if (i2c_flag_get(I2C0, I2C_FLAG_ADDSEND))
{
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
timeout = 0; timeout =0;
state = I2C_STATE_TRANSMIT_DATA; state = I2C_STATE_TRANSMIT_REG;
break;
} else { } else {
timeout = 0; i2c_flag_clear(I2C0, I2C_FLAG_AERR);
state = I2C_STATE_START; timeout =0;
#ifdef DEBUG_VERBOES #ifdef DEBUG_VERBOES
printf("i2c master clears address flag timeout in WRITE BYTE!\n"); printf("IIC write failed for Error Slave Address. \n");
#endif #endif
return I2C_RESULT_NACK;
} }
case I2C_STATE_TRANSMIT_REG:
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
/* send register address */
i2c_data_transmit(I2C0, reg_addr);
timeout = 0;
state = I2C_STATE_TRANSMIT_DATA;
break; break;
case I2C_STATE_TRANSMIT_DATA: case I2C_STATE_TRANSMIT_DATA:
/* wait until the transmit data buffer is empty */ /* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
/* send IIC register address */ state = I2C_STATE_ERROR;
i2c_data_transmit(I2C0, reg_addr); break;
timeout = 0;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends data timeout in WRITE BYTE!\n");
#endif
} }
/* wait until BTC bit is set */ /* send register MSB value */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { i2c_data_transmit(I2C0, data[0]);
timeout = 0;
/* wait until the transmit data buffer is empty */
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
/* send register MSB value */ state = I2C_STATE_ERROR;
i2c_data_transmit(I2C0, data[0]); break;
timeout = 0;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends MSB data timeout in WRITE BYTE!\n");
#endif
} }
/* wait until BTC bit is set */ if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { i2c_stop_on_bus(I2C0);
timeout++; return I2C_RESULT_NACK;
} } else if (i2c_flag_get(I2C0, I2C_FLAG_BERR) || i2c_flag_get(I2C0, I2C_FLAG_LOSTARB)) {
if (timeout < I2C_TIME_OUT) { // 可按需清标志
/* send register LSB value */ i2c_stop_on_bus(I2C0);
i2c_data_transmit(I2C0, data[1]); return I2C_RESULT_ERROR;
timeout = 0;
state = I2C_STATE_STOP;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends LSB data timeout in WRITE BYTE!\n");
#endif
} }
/* wait until BTC bit is set */ /* send register LSB value */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) { i2c_data_transmit(I2C0, data[1]);
timeout = 0;
/* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_STOP; state = I2C_STATE_ERROR;
timeout = 0; break;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends data timeout in WRITE BYTE!\n");
#endif
} }
state = I2C_STATE_STOP;
break; break;
case I2C_STATE_STOP: case I2C_STATE_STOP:
/* send a stop condition to I2C bus */ /* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0); i2c_stop_on_bus(I2C0);
/* i2c master sends STOP signal successfully */
timeout = 0;
while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
timeout = 0; state = I2C_STATE_ERROR;
state = I2C_STATE_END; break;
i2c_timeout_flag = I2C_OK;
} else {
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c master sends stop signal timeout in WRITE BYTE!\n");
#endif
} }
/* i2c master sends STOP signal successfully */
/* success */
return I2C_RESULT_SUCCESS;
case I2C_STATE_ERROR:
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
timeout = 0;
while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
return I2C_RESULT_ERROR;
}
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_flag_clear(I2C0, I2C_FLAG_BERR);
i2c_flag_clear(I2C0, I2C_FLAG_LOSTARB);
retry_count ++;
if (retry_count >= I2C_MAX_RETRY)
{
#ifdef DEBUG_VERBOES
printf("IIC write failed after %d retries\n", I2C_MAX_RETRY);
#endif
return I2C_RESULT_ERROR;
}
/* reset state machine for retry */
state = I2C_STATE_START;
timeout = 0;
/* small delay before retry */
delay_10us(10);
break; break;
default: default:
state = I2C_STATE_START; state = I2C_STATE_START;
i2c_timeout_flag = I2C_OK;
timeout = 0;
#ifdef DEBUG_VERBOES
printf("i2c master sends start signal in WRITE BYTE.\n");
#endif
break; break;
} }
} }
return I2C_RESULT_SUCCESS; return I2C_RESULT_TIMEOUT;
} }
i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) { i2c_result_t i2c_read_16bits(uint8_t slave_addr, uint8_t reg_addr, uint8_t *data) {
i2c_state_t state = I2C_STATE_START;
uint16_t timeout = 0;
uint8_t retry_count = 0;
bool write_phase = true;
// 参数检查：防止空指针和非法地址 // 参数检查：防止空指针和非法地址
if (data == NULL || slave_addr > 0x7F) { if (data == NULL || slave_addr > 0x7F) {
return I2C_RESULT_INVALID_PARAM; return I2C_RESULT_INVALID_PARAM;
} }
i2c_state_t state = I2C_STATE_START;
bool read_cycle = false;
bool i2c_timeout_flag = false;
uint16_t timeout = 0;
uint8_t number_of_byte = 2;
/* enable acknowledge */ /* enable acknowledge */
i2c_ack_config(I2C0, I2C_ACK_ENABLE); i2c_ack_config(I2C0, I2C_ACK_ENABLE);
while (!(i2c_timeout_flag)) { while (retry_count < (uint8_t)I2C_MAX_RETRY) {
switch (state) { switch (state) {
case I2C_STATE_START: case I2C_STATE_START:
if (RESET == read_cycle) {
/* i2c master sends start signal only when the bus is idle */
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
/* whether to send ACK or not for the next byte */
i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT);
} else {
// i2c_bus_reset();
timeout = 0;
state = I2C_STATE_START;
#ifdef DEBUG_VERBOES
printf("i2c bus is busy in READ!\n");
#endif
}
}
/* send the start signal */
i2c_start_on_bus(I2C0);
timeout = 0; timeout = 0;
// wait for bus to be idle
while (i2c_flag_get(I2C0, I2C_FLAG_I2CBSY) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
// send start condition
i2c_start_on_bus(I2C0);
state = I2C_STATE_SEND_ADDRESS; state = I2C_STATE_SEND_ADDRESS;
timeout = 0;
break; break;
case I2C_STATE_SEND_ADDRESS: case I2C_STATE_SEND_ADDRESS:
/* i2c master sends START signal successfully */ /* wait for start condition to be sent */
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) { while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
if (RESET == read_cycle) { state = I2C_STATE_ERROR;
i2c_master_addressing(I2C0, slave_addr << 1, I2C_TRANSMITTER); break;
state = I2C_STATE_CLEAR_ADDRESS;
} else {
i2c_master_addressing(I2C0, slave_addr << 1, I2C_RECEIVER);
i2c_ack_config(I2C0, I2C_ACK_DISABLE);
state = I2C_STATE_CLEAR_ADDRESS;
}
timeout = 0;
} else {
timeout = 0;
state = I2C_STATE_START;
read_cycle = RESET;
#ifdef DEBUG_VERBOES
printf("i2c master sends start signal timeout in READ!\n");
#endif
} }
// send slave address
if (write_phase) {
/* write phase: send address with write bit */
i2c_master_addressing(I2C0, (slave_addr << 1), I2C_TRANSMITTER);
} else {
/* read phase: send address with read bit */
i2c_master_addressing(I2C0, (slave_addr << 1) | 0x01, I2C_RECEIVER);
}
state = I2C_STATE_CLEAR_ADDRESS;
timeout = 0;
break; break;
case I2C_STATE_CLEAR_ADDRESS: case I2C_STATE_CLEAR_ADDRESS:
/* address flag set means i2c slave sends ACK */ /* wait for address to be acknowledged */
while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) { while ((!i2c_flag_get(I2C0, I2C_FLAG_ADDSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
/* Check for NACK before clearing address flag */ state = I2C_STATE_ERROR;
if (i2c_flag_get(I2C0, I2C_FLAG_AERR)) { break;
/* NACK received - slave did not acknowledge address */ }
i2c_flag_clear(I2C0, I2C_FLAG_AERR);
i2c_stop_on_bus(I2C0);
#ifdef DEBUG_VERBOES
printf("i2c NACK received for address 0x%02X in read!\n", slave_addr);
#endif
return I2C_RESULT_NACK;
}
if (write_phase) {
/* clear address flag (write phase) */
i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND); i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
if ((SET == read_cycle) && (1 == number_of_byte)) {
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
}
timeout = 0;
state = I2C_STATE_TRANSMIT_DATA; state = I2C_STATE_TRANSMIT_DATA;
} else { } else {
timeout = 0; /* READ phase for 2 bytes: set POS=NEXT and disable ACK BEFORE clearing ADDR */
state = I2C_STATE_START; i2c_ackpos_config(I2C0, I2C_ACKPOS_NEXT);
read_cycle = RESET; i2c_ack_config(I2C0, I2C_ACK_DISABLE);
#ifdef DEBUG_VERBOES
printf("i2c master clears address flag timeout in READ!\n"); /* now clear address flag to release SCL and enter data phase */
#endif i2c_flag_clear(I2C0, I2C_FLAG_ADDSEND);
state = I2C_STATE_RECEIVE_DATA;
} }
timeout = 0;
break; break;
case I2C_STATE_TRANSMIT_DATA: case I2C_STATE_TRANSMIT_DATA:
if (RESET == read_cycle) { /* wait for transmit buffer to be empty */
/* wait until the transmit data buffer is empty */ while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) {
while ((!i2c_flag_get(I2C0, I2C_FLAG_TBE)) && (timeout < I2C_TIME_OUT)) { timeout++;
timeout++;
}
if (timeout < I2C_TIME_OUT) {
/* send the EEPROM's internal address to write to : only one byte address */
i2c_data_transmit(I2C0, reg_addr);
timeout = 0;
} else {
timeout = 0;
state = I2C_STATE_START;
read_cycle = RESET;
#ifdef DEBUG_VERBOES
printf("i2c master wait data buffer is empty timeout in READ!\n");
#endif
}
/* wait until BTC bit is set */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout < I2C_TIME_OUT) {
timeout = 0;
state = I2C_STATE_START;
read_cycle = SET;
} else {
timeout = 0;
state = I2C_STATE_START;
read_cycle = RESET;
#ifdef DEBUG_VERBOES
printf("i2c master sends register address timeout in READ!\n");
#endif
}
} else {
while (number_of_byte) {
timeout++;
if (2 == number_of_byte) {
/* wait until BTC bit is set */
while (!i2c_flag_get(I2C0, I2C_FLAG_BTC));
/* send a stop condition to I2C bus */
i2c_stop_on_bus(I2C0);
}
/* wait until RBNE bit is set */
if (i2c_flag_get(I2C0, I2C_FLAG_RBNE)) {
/* read a byte from the EEPROM */
*data = i2c_data_receive(I2C0);
/* point to the next location where the byte read will be saved */
data++;
/* decrement the read bytes counter */
number_of_byte--;
timeout = 0;
}
if (timeout > I2C_TIME_OUT) {
timeout = 0;
state = I2C_STATE_START;
read_cycle = 0;
#ifdef DEBUG_VERBOES
printf("i2c master sends data timeout in READ!\n");
#endif
}
}
timeout = 0;
state = I2C_STATE_STOP;
} }
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
/* send register address */
i2c_data_transmit(I2C0, reg_addr);
state = I2C_STATE_RESTART;
timeout = 0;
break; break;
case I2C_STATE_RESTART:
/* wait for byte transfer complete BTC: Bit Transfer Complete */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
/* generate repeated start condition */
i2c_start_on_bus(I2C0);
/* wait for repeated start condition to be sent */
timeout = 0;
while ((!i2c_flag_get(I2C0, I2C_FLAG_SBSEND)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
/* send slave address with read bit (R/W bit is set by library) */
i2c_master_addressing(I2C0, (slave_addr << 1), I2C_RECEIVER);
/* switch to read phase */
write_phase = false;
state = I2C_STATE_CLEAR_ADDRESS;
timeout = 0;
break;
case I2C_STATE_RECEIVE_DATA:
/* Wait for BTC (both bytes received) */
while ((!i2c_flag_get(I2C0, I2C_FLAG_BTC)) && (timeout < I2C_TIME_OUT)) {
timeout++;
}
if (timeout >= I2C_TIME_OUT) {
state = I2C_STATE_ERROR;
break;
}
/* Send STOP before reading the last two bytes */
i2c_stop_on_bus(I2C0);
/* Read the two bytes back-to-back */
data[0] = i2c_data_receive(I2C0);
data[1] = i2c_data_receive(I2C0);
state = I2C_STATE_STOP;
break;
case I2C_STATE_STOP: case I2C_STATE_STOP:
/* i2c master sends STOP signal successfully */ /* wait for stop condition to complete */
while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) { while ((I2C_CTL0(I2C0) & I2C_CTL0_STOP) && (timeout < I2C_TIME_OUT)) {
timeout++; timeout++;
} }
if (timeout < I2C_TIME_OUT) { if (timeout >= I2C_TIME_OUT) {
timeout = 0; state = I2C_STATE_ERROR;
state = I2C_STATE_END; break;
i2c_timeout_flag = I2C_OK;
} else {
timeout = 0;
state = I2C_STATE_START;
read_cycle = 0;
#ifdef DEBUG_VERBOES
printf("i2c master sends stop signal timeout in READ!\n");
#endif
} }
/* i2c master sends STOP signal successfully */
/* success */
return I2C_RESULT_SUCCESS;
case I2C_STATE_ERROR:
/* send stop condition to release bus */
i2c_stop_on_bus(I2C0);
retry_count++;
if (retry_count >= I2C_MAX_RETRY) {
#ifdef DEBUG_VERBOES
printf("IIC read failed after %d retries\n", I2C_RETRY_MAX);
#endif
return I2C_RESULT_ERROR;
}
/* reset state machine for retry */
state = I2C_STATE_START;
write_phase = true;
timeout = 0;
/* small delay before retry */
delay_10us(10);
break; break;
default: default:
state = I2C_STATE_START; state = I2C_STATE_START;
read_cycle = 0;
i2c_timeout_flag = I2C_OK;
timeout = 0;
#ifdef DEBUG_VERBOES
printf("i2c master sends start signal in READ.\n");
#endif
break; break;
} }
} }
return I2C_RESULT_SUCCESS; return I2C_RESULT_TIMEOUT;
} }
#ifdef DEBUG_VERBOSE #ifdef DEBUG_VERBOSE