generated from hulk/gd32e23x_template
132 lines
7.3 KiB
C
132 lines
7.3 KiB
C
/*!
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\file gd32e23x_cmp.h
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\brief definitions for the CMP
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\version 2024-02-22, V2.1.0, firmware for GD32E23x
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*/
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/*
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Copyright (c) 2024, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32E23X_CMP_H
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#define GD32E23X_CMP_H
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#include "gd32e23x.h"
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/* CMP definitions */
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#define CMP CMP_BASE /*!< CMP base address */
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/* registers definitions */
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#define CMP_CS REG32((CMP) + 0x00000000U) /*!< CMP control and status register */
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/* bits definitions */
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/* CMP_CS */
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#define CMP_CS_CMP0EN BIT(0) /*!< CMP0 enable */
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#define CMP_CS_CMP0SW BIT(1) /*!< CMP switch mode enable */
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#define CMP_CS_CMP0M BITS(2,3) /*!< CMP0 mode */
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#define CMP_CS_CMP0MSEL BITS(4,6) /*!< CMP_IM input selection */
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#define CMP_CS_CMP0OSEL BITS(8,10) /*!< CMP0 output selection */
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#define CMP_CS_CMP0PL BIT(11) /*!< CMP0 output polarity */
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#define CMP_CS_CMP0HST BITS(12,13) /*!< CMP0 hysteresis */
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#define CMP_CS_CMP0O BIT(14) /*!< CMP0 output state bit */
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#define CMP_CS_CMP0LK BIT(15) /*!< CMP0 lock */
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/* constants definitions */
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/* CMP units */
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typedef enum{
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CMP0, /*!< comparator 0 */
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}cmp_enum;
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/* CMP operating mode */
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#define CS_CMPXM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2U))
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#define CMP_MODE_HIGHSPEED CS_CMPXM(0) /*!< CMP mode high speed */
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#define CMP_MODE_MIDDLESPEED CS_CMPXM(1) /*!< CMP mode middle speed */
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#define CMP_MODE_LOWSPEED CS_CMPXM(2) /*!< CMP mode low speed */
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#define CMP_MODE_VERYLOWSPEED CS_CMPXM(3) /*!< CMP mode very low speed */
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/* CMP hysteresis */
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#define CS_CMPXHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12U))
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#define CMP_HYSTERESIS_NO CS_CMPXHST(0) /*!< CMP output no hysteresis */
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#define CMP_HYSTERESIS_LOW CS_CMPXHST(1) /*!< CMP output low hysteresis */
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#define CMP_HYSTERESIS_MIDDLE CS_CMPXHST(2) /*!< CMP output middle hysteresis */
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#define CMP_HYSTERESIS_HIGH CS_CMPXHST(3) /*!< CMP output high hysteresis */
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/* CMP inverting input */
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#define CS_CMPXMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4U))
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#define CMP_INVERTING_INPUT_1_4VREFINT CS_CMPXMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
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#define CMP_INVERTING_INPUT_1_2VREFINT CS_CMPXMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
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#define CMP_INVERTING_INPUT_3_4VREFINT CS_CMPXMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
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#define CMP_INVERTING_INPUT_VREFINT CS_CMPXMSEL(3) /*!< CMP inverting input Vrefint */
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#define CMP_INVERTING_INPUT_PA4 CS_CMPXMSEL(4) /*!< CMP inverting input PA4 */
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#define CMP_INVERTING_INPUT_PA5 CS_CMPXMSEL(5) /*!< CMP inverting input PA5 */
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#define CMP_INVERTING_INPUT_PA0_PA2 CS_CMPXMSEL(6) /*!< CMP inverting input PA0 for CMP0 or PA2 for CMP1 */
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/* CMP output */
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#define CS_CMPXOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U))
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#define CMP_OUTPUT_NONE CS_CMPXOSEL(0) /*!< CMP output none */
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#define CMP_OUTPUT_TIMER0_BKIN CS_CMPXOSEL(1) /*!< CMP output TIMER0 break input */
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#define CMP_OUTPUT_TIMER0_IC0 CS_CMPXOSEL(2) /*!< CMP output TIMER0_CH0 input capture */
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#define CMP_OUTPUT_TIMER0_OCPRECLR CS_CMPXOSEL(3) /*!< CMP output TIMER0 OCPRE_CLR input */
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#define CMP_OUTPUT_TIMER2_IC0 CS_CMPXOSEL(6) /*!< CMP output TIMER2_CH0 input capture */
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#define CMP_OUTPUT_TIMER2_OCPRECLR CS_CMPXOSEL(7) /*!< CMP output TIMER2 OCPRE_CLR input */
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/* CMP output polarity*/
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#define CS_CMPXPL(regval) (BIT(11) & ((uint32_t)(regval) << 11U))
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#define CMP_OUTPUT_POLARITY_NONINVERTED CS_CMPXPL(0) /*!< CMP output not inverted */
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#define CMP_OUTPUT_POLARITY_INVERTED CS_CMPXPL(1) /*!< CMP output inverted */
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/* CMP output level */
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#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001U) /*!< CMP output high */
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#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000U) /*!< CMP output low */
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/* function declarations */
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/* initialization functions */
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/* CMP deinit */
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void cmp_deinit(cmp_enum cmp_periph);
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/* CMP mode init */
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void cmp_mode_init(cmp_enum cmp_periph, uint32_t operating_mode, uint32_t inverting_input, uint32_t output_hysteresis);
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/* CMP output init */
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void cmp_output_init(cmp_enum cmp_periph, uint32_t output_selection, uint32_t output_polarity);
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/* enable functions */
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/* enable CMP */
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void cmp_enable(cmp_enum cmp_periph);
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/* disable CMP */
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void cmp_disable(cmp_enum cmp_periph);
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/* enable CMP switch */
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void cmp_switch_enable(void);
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/* disable CMP switch */
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void cmp_switch_disable(void);
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/* lock the CMP */
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void cmp_lock_enable(cmp_enum cmp_periph);
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/* get state related functions */
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/* get output level */
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uint32_t cmp_output_level_get(cmp_enum cmp_periph);
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#endif /* GD32E23X_CMP_H */
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