79 lines
3.4 KiB
C
79 lines
3.4 KiB
C
/*! \file ch101_sonicsync.h
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*
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* \brief Internal definitions for the Chirp CH101 SonicSync sensor firmware.
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*
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* This file contains register offsets and other values for use with the CH101 SonicSync
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* sensor firmware. These values are subject to change without notice.
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*
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* You should not need to edit this file or call the driver functions directly. Doing so
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* will reduce your ability to benefit from future enhancements and releases from Chirp.
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*
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*/
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/*
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* Copyright © 2016-2019, Chirp Microsystems. All rights reserved.
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*
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* Chirp Microsystems CONFIDENTIAL
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CHIRP MICROSYSTEMS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You can contact the authors of this program by email at support@chirpmicro.com
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* or by mail at 2560 Ninth Street, Suite 220, Berkeley, CA 94710.
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*/
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#ifndef CH101_SONICSYNC_H_
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#define CH101_SONICSYNC_H_
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#include "ch101.h"
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#include "soniclib.h"
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#include <stdint.h>
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/* SmartSonic SonicSync firmware registers */
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#define CH101_SONICSYNC_REG_OPMODE 0x01
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#define CH101_SONICSYNC_REG_TICK_INTERVAL 0x02
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#define CH101_SONICSYNC_REG_PERIOD 0x05
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#define CH101_SONICSYNC_REG_MAX_RANGE 0x07
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#define CH101_SONICSYNC_REG_TIME_PLAN 0x09
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#define CH101_SONICSYNC_REG_STAT_RANGE 0x12
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#define CH101_SONICSYNC_REG_STAT_COEFF 0x13
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#define CH101_SONICSYNC_REG_READY 0x14
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#define CH101_SONICSYNC_REG_TOF_SF 0x16
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#define CH101_SONICSYNC_REG_TOF 0x18
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#define CH101_SONICSYNC_REG_AMPLITUDE 0x1A
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#define CH101_SONICSYNC_REG_CAL_TRIG 0x06
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#define CH101_SONICSYNC_REG_CAL_RESULT 0x0A
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#define CH101_SONICSYNC_REG_DATA 0x1C
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#define CH101_SONICSYNC_MAX_SAMPLES (150)
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#define CH101_SONICSYNC_READY_FREQ_LOCKED (0x02 | 0x04)
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extern const char * ch101_sonicsync_master_version; // version string in fw .c file
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extern const char * ch101_sonicsync_slave_version; // version string in fw .c file
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extern const uint8_t ch101_sonicsync_master_fw[CH101_FW_SIZE];
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extern const uint8_t ch101_sonicsync_slave_fw[CH101_FW_SIZE];
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uint16_t get_ch101_sonicsync_master_fw_ram_init_addr(void);
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uint16_t get_ch101_sonicsync_master_fw_ram_init_size(void);
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uint16_t get_ch101_sonicsync_slave_fw_ram_init_addr(void);
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uint16_t get_ch101_sonicsync_slave_fw_ram_init_size(void);
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const unsigned char * get_ram_ch101_sonicsync_master_init_ptr(void);
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const unsigned char * get_ram_ch101_sonicsync_slave_init_ptr(void);
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uint8_t ch101_sonicsync_master_init(ch_dev_t *dev_ptr, ch_group_t *grp_ptr, uint8_t i2c_addr, uint8_t dev_num, uint8_t i2c_bus_index);
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uint8_t ch101_sonicsync_slave_init(ch_dev_t *dev_ptr, ch_group_t *grp_ptr, uint8_t i2c_addr, uint8_t dev_num, uint8_t i2c_bus_index);
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uint8_t ch_sonicsync_get_locked_state(ch_dev_t *dev_ptr);
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#endif
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