From 7a7ed3e36956e76fa6a561009513abbff74abbb8 Mon Sep 17 00:00:00 2001 From: yelvlab Date: Thu, 26 Dec 2024 01:01:26 +0800 Subject: [PATCH] =?UTF-8?q?=E6=B5=8B=E8=AF=95=E6=8F=90=E4=BA=A4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/main.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/src/main.c b/src/main.c index 814f3b7..6a6294b 100644 --- a/src/main.c +++ b/src/main.c @@ -20,17 +20,24 @@ uint32_t g_eddy_current_value_uint32; void watchdog_init(void) { /* Enable the LSI clock */ - rcu_osci_on(RCU_IRC8M); - rcu_osci_stab_wait(RCU_IRC8M); + rcu_osci_on(RCU_IRC40K); + rcu_osci_stab_wait(RCU_IRC40K); /* Enable the FWDGT clock */ - rcu_periph_clock_enable(RCU_WWDGT); + // rcu_periph_clock_enable(RCU_FWDGT); - /* Configure FWDGT counter clock: 40KHz(IRC40K) / 256 = 0.15625 KHz */ - fwdgt_config(156, FWDGT_PSC_DIV256); // Set timeout to 4 seconds (625 / 0.15625 KHz) + /* Configure FWDGT counter clock: 40KHz(IRC40K) / 64 = 0.625 KHz */ + fwdgt_config(625, FWDGT_PSC_DIV64); // Set timeout to 1 seconds (625 / 0.625 KHz) /* Enable FWDGT */ fwdgt_enable(); + + if(RESET != rcu_flag_get(RCU_FLAG_FWDGTRST)){ + // gd_eval_led_on(LED2); + rcu_all_reset_flag_clear(); + + // while(1); + } } /*!