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296
SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s
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296
SDK/CMSIS/GD/GD32E23x/Source/IAR/startup_gd32e23x.s
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;/*!
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; \file startup_gd32e23x.s
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; \brief start up file
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;
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; \version 2025-02-10, V2.3.0, firmware for GD32E23x
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;*/
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;/* Copyright (c) 2012 ARM LIMITED
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; Copyright (c) 2025, GigaDevice Semiconductor Inc.
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; - Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; - Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; - Neither the name of ARM nor the names of its contributors may be used
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; to endorse or promote products derived from this software without
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; specific prior written permission.
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; *
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;*/
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;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK) ; top of stack
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DCD Reset_Handler ; Vector Number 1,Reset Handler
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DCD NMI_Handler ; Vector Number 2,NMI Handler
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DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; Vector Number 11,SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; Vector Number 14,PendSV Handler
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DCD SysTick_Handler ; Vector Number 15,SysTick Handler
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; External Interrupts
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DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
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DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
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DCD RTC_IRQHandler ; 18:RTC through EXTI Line
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DCD FMC_IRQHandler ; 19:FMC
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DCD RCU_IRQHandler ; 20:RCU
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DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
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DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
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DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
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DCD 0 ; Reserved
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DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
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DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
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DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
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DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
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DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
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DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
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DCD 0 ; Reserved
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DCD TIMER2_IRQHandler ; 32:TIMER2
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DCD TIMER5_IRQHandler ; 33:TIMER5
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DCD 0 ; Reserved
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DCD TIMER13_IRQHandler ; 35:TIMER13
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DCD TIMER14_IRQHandler ; 36:TIMER14
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DCD TIMER15_IRQHandler ; 37:TIMER15
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DCD TIMER16_IRQHandler ; 38:TIMER16
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DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
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DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
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DCD SPI0_IRQHandler ; 41:SPI0
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DCD SPI1_IRQHandler ; 42:SPI1
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DCD USART0_IRQHandler ; 43:USART0
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DCD USART1_IRQHandler ; 44:USART1
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
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DCD 0 ; Reserved
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DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:NOROOT:REORDER(2)
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Reset_Handler
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LDR R0, =0x1FFFF7E0
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LDR R2, [R0]
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LDR R0, = 0xFFFF0000
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ANDS R2, R2, R0
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LSRS R2, R2, #16
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LSLS R2, R2, #10
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LDR R1, =0x20000000
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MOV R0, #0x00
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SRAM_INIT STM R1!, {R0}
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SUBS R2, R2, #4
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CMP R2, #0x00
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BNE SRAM_INIT
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDGT_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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WWDGT_IRQHandler
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B WWDGT_IRQHandler
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PUBWEAK LVD_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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LVD_IRQHandler
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B LVD_IRQHandler
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PUBWEAK RTC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RTC_IRQHandler
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B RTC_IRQHandler
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PUBWEAK FMC_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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FMC_IRQHandler
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B FMC_IRQHandler
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PUBWEAK RCU_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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RCU_IRQHandler
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B RCU_IRQHandler
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PUBWEAK EXTI0_1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI0_1_IRQHandler
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B EXTI0_1_IRQHandler
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PUBWEAK EXTI2_3_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI2_3_IRQHandler
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B EXTI2_3_IRQHandler
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PUBWEAK EXTI4_15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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EXTI4_15_IRQHandler
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B EXTI4_15_IRQHandler
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PUBWEAK DMA_Channel0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA_Channel0_IRQHandler
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B DMA_Channel0_IRQHandler
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PUBWEAK DMA_Channel1_2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA_Channel1_2_IRQHandler
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B DMA_Channel1_2_IRQHandler
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PUBWEAK DMA_Channel3_4_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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DMA_Channel3_4_IRQHandler
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B DMA_Channel3_4_IRQHandler
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PUBWEAK ADC_CMP_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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ADC_CMP_IRQHandler
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B ADC_CMP_IRQHandler
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PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER0_BRK_UP_TRG_COM_IRQHandler
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B TIMER0_BRK_UP_TRG_COM_IRQHandler
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PUBWEAK TIMER0_Channel_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER0_Channel_IRQHandler
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B TIMER0_Channel_IRQHandler
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PUBWEAK TIMER2_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER2_IRQHandler
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B TIMER2_IRQHandler
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PUBWEAK TIMER5_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER5_IRQHandler
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B TIMER5_IRQHandler
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PUBWEAK TIMER13_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER13_IRQHandler
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B TIMER13_IRQHandler
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PUBWEAK TIMER14_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER14_IRQHandler
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B TIMER14_IRQHandler
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PUBWEAK TIMER15_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER15_IRQHandler
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B TIMER15_IRQHandler
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PUBWEAK TIMER16_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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TIMER16_IRQHandler
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B TIMER16_IRQHandler
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PUBWEAK I2C0_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C0_EV_IRQHandler
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B I2C0_EV_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK SPI0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI0_IRQHandler
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B SPI0_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK USART0_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART0_IRQHandler
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B USART0_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK I2C0_ER_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C0_ER_IRQHandler
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B I2C0_ER_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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SECTION .text:CODE:NOROOT:REORDER(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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END
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