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b822b9360a
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189f69a7d4
| Author | SHA1 | Date | |
|---|---|---|---|
 hulk
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189f69a7d4 | ||
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hulk
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96986b4444 |
@@ -0,0 +1,2 @@
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# 忽略构建输出目录
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Build/
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Vendored
+2
@@ -0,0 +1,2 @@
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erase
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exit
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Vendored
+8
@@ -0,0 +1,8 @@
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{
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"recommendations": [
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"marus25.cortex-debug",
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"ms-vscode.cmake-tools",
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"twxs.cmake",
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"ms-vscode.cpptools"
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]
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}
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Vendored
+4
@@ -0,0 +1,4 @@
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loadfile Application.hex
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r
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go
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exit
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Vendored
+58
@@ -0,0 +1,58 @@
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{
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"version": "0.2.0",
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"configurations": [
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{
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"cwd": "${workspaceFolder}",
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"executable": "${workspaceFolder}/Build/Debug/Application/Application.elf",
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"name": "Debug with OpenOCD",
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"request": "launch",
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"type": "cortex-debug",
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"runToEntryPoint": "main",
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"showDevDebugOutput": "none",
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"gdbPath": "${env:GD32_GCC_BIN}/arm-none-eabi-gdb.exe",
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"servertype": "openocd",
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"serverpath": "${env:GD32_OPENOCD_BIN}/openocd.exe",
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"svdFile": "${workspaceFolder}/GD32F4xx.svd",
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"configFiles": [
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"${config:gd32.openocd.targetConfig}"
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],
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"serverArgs": [
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"-s", "${env:GD32_OPENOCD_SCRIPTS}"
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],
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"env": {
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"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
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},
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"searchDir": [
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"${workspaceFolder}"
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],
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"preLaunchTask": "Build",
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"preRestartCommands": [
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"load",
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"continue"
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]
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},
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{
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"cwd": "${workspaceFolder}",
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"executable": "${workspaceFolder}/Build/Debug/Application/Application.elf",
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"name": "Debug with J-Link",
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"request": "launch",
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"type": "cortex-debug",
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"runToEntryPoint": "main",
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"showDevDebugOutput": "none",
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"gdbPath": "${env:GD32_GCC_BIN}/arm-none-eabi-gdb.exe",
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"servertype": "jlink",
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"device": "${config:gd32.jlink.device}",
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"interface": "${config:gd32.jlink.interface}",
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"svdFile": "${workspaceFolder}/GD32F4xx.svd",
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"liveWatch": {
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"enabled": true,
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"samplesPerSecond": 1
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},
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"preLaunchTask": "Build",
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"preRestartCommands": [
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"load",
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"continue"
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]
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}
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]
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}
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Vendored
+2
@@ -0,0 +1,2 @@
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r
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exit
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Vendored
+22
@@ -0,0 +1,22 @@
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{
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"cmake.configureOnOpen": true,
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"cmake.useCMakePresets": "always",
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"C_Cpp.default.configurationProvider": "ms-vscode.cmake-tools",
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"cortex-debug.variableUseNaturalFormat": true,
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"gd32.openocd.targetConfig": "${workspaceFolder}/OpenOCD/gd32f405_gdlink_cmsis_dap.cfg",
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"gd32.openocd.massEraseCommand": "stm32f4x mass_erase 0",
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"gd32.jlink.device": "GD32F405RE",
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"gd32.jlink.interface": "SWD",
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"gd32.jlink.speed": "4000",
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"files.associations": {
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"*.h": "c",
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"*.c": "c"
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},
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|
"files.exclude": {
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"GD32F4xx_Demo_Suites_V3.3.3": true
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},
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"search.exclude": {
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"GD32F4xx_Demo_Suites_V3.3.3": true,
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"Build": true
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}
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}
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Vendored
+229
@@ -0,0 +1,229 @@
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{
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"version": "2.0.0",
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"tasks": [
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{
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"label": "Build",
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"type": "cmake",
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"command": "build",
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"group": {
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"kind": "build",
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|
"isDefault": true
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|
},
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|
"problemMatcher": [
|
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|
{
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|
"base": "$gcc",
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|
"fileLocation": [
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|
"relative",
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|
"${command:cmake.buildDirectory}"
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|
]
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|
}
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],
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"options": {
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"environment": {
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"CLICOLOR_FORCE": "1",
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"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
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}
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|
},
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|
"presentation": {
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|
"clear": true
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|
},
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|
"icon": {
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||||||
|
"id": "code",
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|
"tooltip": "Build"
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||||||
|
}
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|
},
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|
{
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|
"label": "Build and Flash",
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|
"dependsOn": [
|
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"Build",
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|
"Flash MCU"
|
||||||
|
],
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|
"dependsOrder": "sequence",
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|
"group": "build",
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|
"icon": {
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|
"id": "insert",
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|
"tooltip": "Build and Flash"
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|
}
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|
},
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{
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"label": "Flash MCU",
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"type": "process",
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"command": "${env:GD32_OPENOCD_BIN}/openocd.exe",
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"args": [
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"-s", "${env:GD32_OPENOCD_SCRIPTS}",
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"-f", "${config:gd32.openocd.targetConfig}",
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"-c", "init; reset halt; flash write_image erase ${command:cmake.launchTargetFilename}; reset; exit"
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|
],
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"group": "build",
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|
"problemMatcher": [],
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|
"options": {
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"cwd": "${command:cmake.buildDirectory}/Application",
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"environment": {
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"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
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}
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},
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"presentation": {
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"clear": true
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},
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"icon": {
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"id": "gather",
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"tooltip": "Flash MCU"
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}
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},
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{
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"label": "Reset MCU",
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"type": "process",
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"command": "${env:GD32_OPENOCD_BIN}/openocd.exe",
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"args": [
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"-s", "${env:GD32_OPENOCD_SCRIPTS}",
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"-f", "${config:gd32.openocd.targetConfig}",
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"-c", "init; reset; exit"
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],
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"group": "build",
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"problemMatcher": [],
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"options": {
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"cwd": "${command:cmake.buildDirectory}/Application",
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"environment": {
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"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
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}
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},
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"presentation": {
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"clear": true
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},
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"icon": {
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"id": "discard",
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"tooltip": "Reset MCU"
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}
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},
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{
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"label": "Mass Erase MCU",
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"type": "process",
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"command": "${env:GD32_OPENOCD_BIN}/openocd.exe",
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"args": [
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"-s", "${env:GD32_OPENOCD_SCRIPTS}",
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"-f", "${config:gd32.openocd.targetConfig}",
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"-c", "init; reset halt; ${config:gd32.openocd.massEraseCommand}; exit"
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],
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"group": "build",
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"problemMatcher": [],
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"options": {
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|
"cwd": "${command:cmake.buildDirectory}/Application",
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"environment": {
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"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
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||||||
|
}
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},
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"presentation": {
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||||||
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"clear": true
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},
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"icon": {
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"id": "clear-all",
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|
"tooltip": "Erase MCU"
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||||||
|
}
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||||||
|
},
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{
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"label": "OpenOCD Server",
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||||||
|
"type": "process",
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||||||
|
"command": "${env:GD32_OPENOCD_BIN}/openocd.exe",
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||||||
|
"args": [
|
||||||
|
"-s", "${env:GD32_OPENOCD_SCRIPTS}",
|
||||||
|
"-f", "${config:gd32.openocd.targetConfig}"
|
||||||
|
],
|
||||||
|
"group": "build",
|
||||||
|
"problemMatcher": [],
|
||||||
|
"options": {
|
||||||
|
"cwd": "${command:cmake.buildDirectory}/Application",
|
||||||
|
"environment": {
|
||||||
|
"OPENOCD_SCRIPTS": "${env:GD32_OPENOCD_SCRIPTS}"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"presentation": {
|
||||||
|
"clear": true
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"label": "Build and Flash (Jlink)",
|
||||||
|
"dependsOn": [
|
||||||
|
"Build",
|
||||||
|
"Flash MCU (Jlink)"
|
||||||
|
],
|
||||||
|
"dependsOrder": "sequence",
|
||||||
|
"group": "build",
|
||||||
|
"icon": {
|
||||||
|
"id": "insert",
|
||||||
|
"tooltip": "Build and Flash (Jlink)"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"label": "Flash MCU (Jlink)",
|
||||||
|
"type": "process",
|
||||||
|
"command": "JLink.exe",
|
||||||
|
"args": [
|
||||||
|
"-device", "${config:gd32.jlink.device}",
|
||||||
|
"-if", "${config:gd32.jlink.interface}",
|
||||||
|
"-speed", "${config:gd32.jlink.speed}",
|
||||||
|
"-autoconnect", "1",
|
||||||
|
"-CommanderScript", "${workspaceFolder}/.vscode/flash.jlink"
|
||||||
|
],
|
||||||
|
"group": "build",
|
||||||
|
"problemMatcher": [],
|
||||||
|
"options": {
|
||||||
|
"cwd": "${command:cmake.buildDirectory}/Application"
|
||||||
|
},
|
||||||
|
"presentation": {
|
||||||
|
"clear": true
|
||||||
|
},
|
||||||
|
"icon": {
|
||||||
|
"id": "gather",
|
||||||
|
"tooltip": "Flash MCU (Jlink)"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"label": "Reset MCU (Jlink)",
|
||||||
|
"type": "process",
|
||||||
|
"command": "JLink.exe",
|
||||||
|
"args": [
|
||||||
|
"-device", "${config:gd32.jlink.device}",
|
||||||
|
"-if", "${config:gd32.jlink.interface}",
|
||||||
|
"-speed", "${config:gd32.jlink.speed}",
|
||||||
|
"-autoconnect", "1",
|
||||||
|
"-CommanderScript", "${workspaceFolder}/.vscode/reset.jlink"
|
||||||
|
],
|
||||||
|
"group": "build",
|
||||||
|
"problemMatcher": [],
|
||||||
|
"options": {
|
||||||
|
"cwd": "${workspaceFolder}"
|
||||||
|
},
|
||||||
|
"presentation": {
|
||||||
|
"clear": true
|
||||||
|
},
|
||||||
|
"icon": {
|
||||||
|
"id": "discard",
|
||||||
|
"tooltip": "Reset MCU (Jlink)"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"label": "Mass Erase MCU (Jlink)",
|
||||||
|
"type": "process",
|
||||||
|
"command": "JLink.exe",
|
||||||
|
"args": [
|
||||||
|
"-device", "${config:gd32.jlink.device}",
|
||||||
|
"-if", "${config:gd32.jlink.interface}",
|
||||||
|
"-speed", "${config:gd32.jlink.speed}",
|
||||||
|
"-autoconnect", "1",
|
||||||
|
"-CommanderScript", "${workspaceFolder}/.vscode/erase.jlink"
|
||||||
|
],
|
||||||
|
"group": "build",
|
||||||
|
"problemMatcher": [],
|
||||||
|
"options": {
|
||||||
|
"cwd": "${workspaceFolder}"
|
||||||
|
},
|
||||||
|
"presentation": {
|
||||||
|
"clear": true
|
||||||
|
},
|
||||||
|
"icon": {
|
||||||
|
"id": "clear-all",
|
||||||
|
"tooltip": "Erase MCU (Jlink)"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
]
|
||||||
|
}
|
||||||
@@ -0,0 +1,105 @@
|
|||||||
|
# GD32F4xx 工程模板 — AGENTS.md
|
||||||
|
|
||||||
|
## 项目约定
|
||||||
|
|
||||||
|
- **用途**：兆易创新 GD32F4xx 系列 MCU（Cortex-M4）的 CMake + VSCode 工程模板，
|
||||||
|
组织方式与编译方法沿用 `E:\Hulk-Coding\gd32e23x_template_cmake_vscode`（其源头为
|
||||||
|
celalkismiroglu/gd32e23x-demo-suites-cmake）。
|
||||||
|
- **默认目标**：GD32F405RET6（设备宏 `GD32F405`，硬件 FPU fpv4-sp-d16 / hard ABI；
|
||||||
|
512K Flash / 128K RAM + 64K TCMRAM，链接脚本 xE）。
|
||||||
|
- **板级实际配置（demo 板实测）**：无外部晶振 → 时钟源 **IRC16M PLL 168MHz**
|
||||||
|
（`system_gd32f4xx.c` 启用 `__SYSTEM_CLOCK_168M_PLL_IRC16M`；HXTAL 方案在无晶振
|
||||||
|
时会死循环等待）；LED = **PA15**；调试串口 = **USART1（PA2 TX / PA3 RX，AF7，
|
||||||
|
纯串口非 RS485；GD 外设编号比 STM32 小 1，PA2/PA3=USART1@0x40004400）**，
|
||||||
|
printf 经 `syscalls.c` 的 `_write`→`__io_putchar` 重定向到
|
||||||
|
USART1（`DEBUG_UART` 宏），`DEBUG_MODE` 打开后输出（模板现阶段默认开启，
|
||||||
|
发布前改回 `CFG_DISABLE`）。
|
||||||
|
- **语言/工具链**：C（gnu11）+ ARM GCC 交叉工具链（本机已验证 xpack 15.2.1；
|
||||||
|
E23x 侧曾验证 11.3.1 / 12.3.1）、CMake ≥ 3.20 + Ninja、VSCode + CMake Tools +
|
||||||
|
cortex-debug。工具链路径经环境变量 `GD32_GCC_BIN` 提供，不入仓库。
|
||||||
|
- **目录约定**：
|
||||||
|
- `Build/` —— CMake 构建树与产物（`Build/<Debug|Release>`），gitignore，
|
||||||
|
可随时整目录删除。
|
||||||
|
- `SDK/` —— CMSIS（core_cm4 + GD32F4xx 设备头 + GCC 启动文件）、标准外设库
|
||||||
|
V3.3.3（取自 GD32F4xx_Demo_Suites_V3.3.3）、SEGGER_RTT。SDK 代码不做业务修改。
|
||||||
|
- `LD/` —— 链接脚本（xE 512K / xG 1024K / xK 2048K 三种容量，默认 xE）。
|
||||||
|
- `Inc/`+`Src/` —— 应用层；板级引脚与功能开关集中在 `Inc/board_config.h`。
|
||||||
|
- `OpenOCD/` —— 工程内 OpenOCD 会话配置（CMSIS-DAP + stm32f4x target 驱动 GD32F4）。
|
||||||
|
- `doc/` —— 芯片文档（数据手册/用户手册/固件库指南/AN，已齐备）。
|
||||||
|
- `GD32F4xx_Demo_Suites_V3.3.3/` —— 官方原始素材包，仅本地参考，已 gitignore。
|
||||||
|
- **编译方法**（与 E23x 一致）：
|
||||||
|
```bash
|
||||||
|
cmake --preset Debug && cmake --build Build/Debug
|
||||||
|
cmake --preset Release && cmake --build Build/Release
|
||||||
|
```
|
||||||
|
产物（elf/hex/bin/map/list 及版本化命名文件）全部生成在 `Build/<配置>/` 下。
|
||||||
|
- **构建特性**：`project_config.cmake` 管版本号/变体；`version.h` 自动生成；
|
||||||
|
POST_BUILD 产出 `[工程名_版本_变体_日期]` 系列文件；外设库为 OBJECT 库 +
|
||||||
|
`--gc-sections` 裁剪，未引用模块不进最终镜像。
|
||||||
|
- **换型号**：改 `GD32F405` 宏（project.cmake 与外设库 CMakeLists）、启动文件
|
||||||
|
（407_427 / 405_425 / 450_470）、链接脚本（xE/xG/xK），详见 README“更换目标型号”。
|
||||||
|
|
||||||
|
## 开发进度
|
||||||
|
|
||||||
|
### 已完成
|
||||||
|
|
||||||
|
- 模板骨架：目录结构、CMakeLists、CMakePresets（构建树位于工程根 `Build/`）、
|
||||||
|
工具链文件（cortex-m4 + 硬件 FPU + GCC15 兼容 `--no-warn-rwx-segments`）。
|
||||||
|
- **目标型号切换为 GD32F405RET6**：设备宏 `GD32F405`、启动文件 `startup_gd32f405_425.S`、
|
||||||
|
链接脚本 `gd32f405_407_xE_flash.ld`（512K）、J-Link device `GD32F405RE`、
|
||||||
|
OpenOCD cfg 更名 `gd32f405_gdlink_cmsis_dap.cfg`；切换后全新编译 Debug/Release 通过。
|
||||||
|
- **Flash 容量改为 CMake 编译期切换**：`GD32_FLASH_CAPACITY`（cache 变量，默认 xE）
|
||||||
|
决定链接脚本（xE/xG/xK）并注入 `GD32_FLASH_SIZE_KB` 宏；已验证 xG 切换生效。
|
||||||
|
- **删除 E230 式运行时串口分发结构**：去掉 `usart_config_t`/`g_usart_config`/
|
||||||
|
`mcu_detect_and_config()`/`Src/board_config.c`，串口静态绑定 USART0（宏直连），
|
||||||
|
中断直接调用处理函数；LED 改 demo 板实测引脚 **PA15**（复位默认 JTDI，
|
||||||
|
配 GPIO 输出即接管，不影响 SWD）。
|
||||||
|
- SDK 就位：CMSIS（core_cm4.h 系）、GD32F4xx 标准外设库 29 模块、SEGGER_RTT、
|
||||||
|
GCC 启动文件（F405/425）、三种容量链接脚本。
|
||||||
|
- 应用层移植（自 E23x 模板）：main / systick（M4 延时校准系数）/ led（心跳，
|
||||||
|
demo 板 PA15）/ uart（USART0 PA9/PA10 AF7、RS485 改 GPIO 控 DE）/
|
||||||
|
uart_ring_buffer / gd32f4xx_it（含 M4 特有 fault）/ syscalls（printf 重定向
|
||||||
|
USART0）/ system_gd32f4xx（168MHz_HXTAL，SystemInit 含 FPU 使能）。
|
||||||
|
- `GD32F4xx.svd` 已下载就位（社区镜像，与官方同源，覆盖全 F4 家族）。
|
||||||
|
- OpenOCD 工程内会话配置（借鉴 metax-sensors/gd32-cmake-example：CMSIS-DAP +
|
||||||
|
stm32f4x.cfg 驱动 GD32F4 flash）+ .vscode 全套（tasks/launch/settings/jlink 脚本）。
|
||||||
|
- 编译验证：Debug 与 Release 均通过（GCC 15.2.1），ELF 检查正确（vectors @
|
||||||
|
0x08000000、hard-float、.data 加载地址正确）。Release text≈7.6KB。
|
||||||
|
- **上板验证通过（GD-LINK/CMSIS-DAP + OpenOCD stm32f4x）**：芯片识别
|
||||||
|
`device id 0x16080413`（F405xE/512K）；固件烧录+verify OK；LED 心跳周期 2 秒整
|
||||||
|
（SysTick 1ms 精确，168MHz PLL 生效，SCSS=PLLP 硬件确认）；USART1 寄存器实测
|
||||||
|
CTL0=0x202C（使能+收发+RBNE 中断）、BAUD=365（42MHz APB1/115200 精确）、
|
||||||
|
TC=1（printf 数据完整发出）。
|
||||||
|
调试经验：GD32F4xx RCU 寄存器偏移为 CTL0=0x00、**PLL=0x04、CFG0=0x08**；
|
||||||
|
外设编号比 STM32 小 1（GD USART0=STM32 USART1@0x40011000、GD USART1=STM32
|
||||||
|
USART2@0x40004400、GD USART2=STM32 USART3@0x40004800），在线排查时勿混淆——
|
||||||
|
曾因按 STM32 习惯把 PA2/PA3 当 USART2 配置导致串口无输出，后更正为 USART1。
|
||||||
|
|
||||||
|
### 计划 / TODO（已提出尚未实现）
|
||||||
|
|
||||||
|
- [ ] **i2c 驱动移植**：从 E23x 工程 `Src/i2c.c`(50KB)/`Inc/i2c.h` 移植到 F4
|
||||||
|
（API 同名：i2c_clock_config/i2c_mode_addr_config 等已确认存在；引脚已定义
|
||||||
|
PB6/PB7 AF4；需将 include 的 gd32e23x* 改为 gd32f4xx*，并按 F4 时序实测
|
||||||
|
20kHz 总线速度与超时参数）。完成后在 CMakeLists 的 TARGET_SRC 启用 `Src/i2c.c`。
|
||||||
|
- [ ] **串口命令协议移植**：从 E23x 工程 `Src/command.c`/`Inc/command.h` 移植
|
||||||
|
（include 改 gd32f4xx_usart.h、core_cm23.h→core_cm4.h），启用后 main.c 中
|
||||||
|
打开 `command_process()` 调用。
|
||||||
|
- [ ] **上板验证（剩余项）**：串口助手（PA2/PA3，115200-8-N-1）实测 printf 输出与
|
||||||
|
收发；`stm32f4x mass_erase 0` 整片擦除命令实测；RTT 通道实测。
|
||||||
|
（已通过：烧录/verify、LED 心跳 2s、168MHz PLL、USART2 初始化与 printf 发送。）
|
||||||
|
- [ ] **delay_10us 校准**：M4@168MHz 系数为估算值（/300000），需逻辑分析仪实测修正。
|
||||||
|
- [x] **doc/ 已齐备**：GD32F405 数据手册 Rev2.8、GD32F4xx 用户手册 Rev3.3、
|
||||||
|
固件库使用指南 Rev1.2（中英）、AN059/AN200（用户补充+官方库包 Docs 拷贝）。
|
||||||
|
|
||||||
|
- **SDK 版本核对（2026-10）**：官网最新 GD32F4xx_Firmware_Library_V3.3.3（2026-02-05）
|
||||||
|
与工程 SDK（取自 Demo_Suites_V3.3.3）经逐文件 SHA1 对比**完全一致**，无需更新。
|
||||||
|
- **GD32F4xx_usb_library 已搬入 SDK**（源自官方包，temp 删除后不依赖）：含
|
||||||
|
driver/device/host/ustd 全量源码 + conf/ 模板配置（cdc_acm 例程基准）。
|
||||||
|
默认 `GD32_ENABLE_USB=OFF` 不参与构建；开启方式与限制见 SDK/GD32F4xx_usb_library/
|
||||||
|
CMakeLists.txt 头部注释（默认编译范围 = driver + device core + CDC 虚拟串口，
|
||||||
|
GCC 15 已验证；其余 class/host 依赖例程级 conf 宏，按注释从 Examples 取）。
|
||||||
|
|
||||||
|
## 备注
|
||||||
|
|
||||||
|
- 本机凭据/发布约定见用户级 `C:\Users\Lenovo\.zcode\AGENTS.md`。
|
||||||
|
- E23x 工程位置：`E:\Hulk-Coding\gd32e23x_template_cmake_vscode`（模板对标工程）。
|
||||||
+121
@@ -0,0 +1,121 @@
|
|||||||
|
cmake_minimum_required(VERSION 3.20)
|
||||||
|
|
||||||
|
# 包含项目配置
|
||||||
|
include(${CMAKE_SOURCE_DIR}/cmake/project_config.cmake)
|
||||||
|
include(${CMAKE_SOURCE_DIR}/cmake/project.cmake)
|
||||||
|
|
||||||
|
project(${PROJECT_NAME} LANGUAGES C CXX ASM)
|
||||||
|
|
||||||
|
# Generate version header from CMake version variables
|
||||||
|
file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/generated)
|
||||||
|
configure_file(${CMAKE_SOURCE_DIR}/cmake/version.h.in ${CMAKE_BINARY_DIR}/generated/version.h @ONLY)
|
||||||
|
|
||||||
|
# 添加SDK库
|
||||||
|
add_subdirectory(SDK/CMSIS)
|
||||||
|
add_subdirectory(SDK/GD32F4xx_standard_peripheral)
|
||||||
|
add_subdirectory(SDK/SEGGER_RTT)
|
||||||
|
# USB 库默认不编译，需要时：cmake --preset Debug -DGD32_ENABLE_USB=ON，
|
||||||
|
# 并在下方链接区追加 target_link_libraries(${PROJECT_NAME} PRIVATE GD32F4xx_usb_library)
|
||||||
|
add_subdirectory(SDK/GD32F4xx_usb_library)
|
||||||
|
|
||||||
|
# 业务代码源文件
|
||||||
|
set(TARGET_SRC
|
||||||
|
# Core
|
||||||
|
Src/gd32f4xx_it.c
|
||||||
|
Src/main.c
|
||||||
|
Src/systick.c
|
||||||
|
Src/system_gd32f4xx.c
|
||||||
|
|
||||||
|
# Startup
|
||||||
|
SDK/CMSIS/startup/startup_gd32f405_425.S
|
||||||
|
|
||||||
|
# User
|
||||||
|
Src/syscalls.c
|
||||||
|
|
||||||
|
# Add new source files here
|
||||||
|
Src/uart.c
|
||||||
|
Src/led.c
|
||||||
|
Src/uart_ring_buffer.c
|
||||||
|
|
||||||
|
# TODO: 待从 GD32E23x 工程移植后启用
|
||||||
|
# Src/command.c
|
||||||
|
# Src/i2c.c
|
||||||
|
)
|
||||||
|
|
||||||
|
# 设置输出目录
|
||||||
|
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Application)
|
||||||
|
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Application)
|
||||||
|
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/Application)
|
||||||
|
|
||||||
|
add_executable(${PROJECT_NAME} ${TARGET_SRC})
|
||||||
|
set_target_properties(${PROJECT_NAME} PROPERTIES OUTPUT_NAME Application)
|
||||||
|
project_add_target_properties(${PROJECT_NAME})
|
||||||
|
|
||||||
|
# 头文件路径
|
||||||
|
target_include_directories(${PROJECT_NAME} PRIVATE
|
||||||
|
${CMAKE_SOURCE_DIR}/Inc
|
||||||
|
${CMAKE_BINARY_DIR}/generated
|
||||||
|
|
||||||
|
# Add new include directories here, e.g. ${CMAKE_SOURCE_DIR}/Application/User/Inc
|
||||||
|
|
||||||
|
)
|
||||||
|
|
||||||
|
# 按 GD32_FLASH_CAPACITY 选择链接脚本与容量宏（cmake/project_config.cmake 中定义）
|
||||||
|
if(GD32_FLASH_CAPACITY STREQUAL "xE")
|
||||||
|
set(GD32_FLASH_LD "gd32f405_407_xE_flash.ld")
|
||||||
|
set(GD32_FLASH_SIZE_KB 512)
|
||||||
|
elseif(GD32_FLASH_CAPACITY STREQUAL "xG")
|
||||||
|
set(GD32_FLASH_LD "gd32f405_407_xG_flash.ld")
|
||||||
|
set(GD32_FLASH_SIZE_KB 1024)
|
||||||
|
elseif(GD32_FLASH_CAPACITY STREQUAL "xK")
|
||||||
|
set(GD32_FLASH_LD "gd32f405_407_xK_flash.ld")
|
||||||
|
set(GD32_FLASH_SIZE_KB 2048)
|
||||||
|
else()
|
||||||
|
message(FATAL_ERROR "Invalid GD32_FLASH_CAPACITY='${GD32_FLASH_CAPACITY}', expected xE/xG/xK")
|
||||||
|
endif()
|
||||||
|
message(STATUS "Target flash capacity: ${GD32_FLASH_CAPACITY} (${GD32_FLASH_SIZE_KB} KB), LD: ${GD32_FLASH_LD}")
|
||||||
|
|
||||||
|
# 链接脚本
|
||||||
|
target_link_options(${PROJECT_NAME} PRIVATE
|
||||||
|
-T${CMAKE_SOURCE_DIR}/LD/${GD32_FLASH_LD} -Xlinker
|
||||||
|
-L${CMAKE_SOURCE_DIR}/LD
|
||||||
|
)
|
||||||
|
|
||||||
|
# 容量宏（代码中如需按容量分支使用 GD32_FLASH_SIZE_KB）
|
||||||
|
target_compile_definitions(${PROJECT_NAME} PRIVATE GD32_FLASH_SIZE_KB=${GD32_FLASH_SIZE_KB})
|
||||||
|
|
||||||
|
# 生成 map 文件等
|
||||||
|
target_link_options(${PROJECT_NAME} PRIVATE
|
||||||
|
-Wl,-Map=${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/Application.map
|
||||||
|
-Wl,--no-warn-rwx-segments
|
||||||
|
)
|
||||||
|
|
||||||
|
# 链接SDK库
|
||||||
|
target_link_libraries(${PROJECT_NAME} PRIVATE CMSIS)
|
||||||
|
target_link_libraries(${PROJECT_NAME} PRIVATE GD32F4xx_standard_peripheral)
|
||||||
|
target_link_libraries(${PROJECT_NAME} PRIVATE SEGGER_RTT)
|
||||||
|
|
||||||
|
# 生成 bin/hex/list 文件名格式：[工程名_版本号_编译条件_编译日期]
|
||||||
|
set(OUTPUT_PREFIX "${PROJECT_NAME}_${VERSION}_${BUILD_VARIANT}_${BUILD_DATE}")
|
||||||
|
|
||||||
|
add_custom_command(TARGET ${PROJECT_NAME}
|
||||||
|
POST_BUILD
|
||||||
|
COMMAND echo -- Running Post Build Commands
|
||||||
|
COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${PROJECT_NAME}> ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_PREFIX}.hex
|
||||||
|
COMMAND ${CMAKE_OBJCOPY} -O ihex $<TARGET_FILE:${PROJECT_NAME}> $<TARGET_FILE_DIR:${PROJECT_NAME}>/Application.hex
|
||||||
|
COMMAND ${CMAKE_OBJCOPY} -O binary $<TARGET_FILE:${PROJECT_NAME}> ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_PREFIX}.bin
|
||||||
|
COMMAND ${CMAKE_SIZE} $<TARGET_FILE:${PROJECT_NAME}>
|
||||||
|
COMMAND ${CMAKE_OBJDUMP} -h -S $<TARGET_FILE:${PROJECT_NAME}> > ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_PREFIX}.list
|
||||||
|
COMMAND ${CMAKE_SIZE} --format=berkeley $<TARGET_FILE:${PROJECT_NAME}> > ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_PREFIX}.bsz
|
||||||
|
COMMAND ${CMAKE_SIZE} --format=sysv -x $<TARGET_FILE:${PROJECT_NAME}> > ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_PREFIX}.ssz
|
||||||
|
)
|
||||||
|
|
||||||
|
# =========================
|
||||||
|
# Tips for project maintainers:
|
||||||
|
# 1. If you add new source files (e.g. Src/my_module.c), add them to TARGET_SRC above.
|
||||||
|
# 2. If you add new header files or directories, add them to target_include_directories above.
|
||||||
|
# 3. If you add new SDK modules, use add_subdirectory(SDK/YourModule) and link with target_link_libraries.
|
||||||
|
# 4. 换用其它型号时：修改 cmake/project.cmake 与 SDK/GD32F4xx_standard_peripheral/CMakeLists.txt 中的
|
||||||
|
# GD32F405 宏、TARGET_SRC 中的启动文件（startup_gd32f405_425.S / startup_gd32f407_427.S /
|
||||||
|
# startup_gd32f450_470.S）以及上面的链接脚本（LD/gd32f405_407_xE_flash.ld 等）。
|
||||||
|
# =========================
|
||||||
@@ -0,0 +1,54 @@
|
|||||||
|
{
|
||||||
|
"version": 2,
|
||||||
|
"configurePresets": [
|
||||||
|
{
|
||||||
|
"name": "default",
|
||||||
|
"hidden": true,
|
||||||
|
"generator": "Ninja",
|
||||||
|
"binaryDir": "${sourceDir}/Build/${presetName}",
|
||||||
|
"cacheVariables": {
|
||||||
|
"CMAKE_INSTALL_PREFIX": "${sourceDir}/Build/${presetName}/Install",
|
||||||
|
"CMAKE_TOOLCHAIN_FILE": {
|
||||||
|
"type": "FILEPATH",
|
||||||
|
"value": "${sourceDir}/cmake/arm-none-eabi-gcc.cmake"
|
||||||
|
}
|
||||||
|
,"CMAKE_EXPORT_COMPILE_COMMANDS": "ON"
|
||||||
|
},
|
||||||
|
"architecture": {
|
||||||
|
"value": "unspecified",
|
||||||
|
"strategy": "external"
|
||||||
|
},
|
||||||
|
"vendor": {
|
||||||
|
"microsoft.com/VisualStudioSettings/CMake/1.0": {
|
||||||
|
"intelliSenseMode": "linux-gcc-arm"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name": "Debug",
|
||||||
|
"inherits": "default",
|
||||||
|
"cacheVariables": {
|
||||||
|
"CMAKE_BUILD_TYPE": "Debug",
|
||||||
|
"PRESET_NAME": "Debug"
|
||||||
|
}
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name": "Release",
|
||||||
|
"inherits": "default",
|
||||||
|
"cacheVariables": {
|
||||||
|
"CMAKE_BUILD_TYPE": "Release",
|
||||||
|
"PRESET_NAME": "Release"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"buildPresets": [
|
||||||
|
{
|
||||||
|
"name": "Debug",
|
||||||
|
"configurePreset": "Debug"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name": "Release",
|
||||||
|
"configurePreset": "Release"
|
||||||
|
}
|
||||||
|
]
|
||||||
|
}
|
||||||
+55016
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,104 @@
|
|||||||
|
#ifndef BOARD_CONFIG_H
|
||||||
|
#define BOARD_CONFIG_H
|
||||||
|
|
||||||
|
#ifndef CFG_DISABLE
|
||||||
|
#define CFG_DISABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef CFG_ENABLE
|
||||||
|
#define CFG_ENABLE 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define PROTOCOL_BOARD_TYPE 0x01 /**< 板卡类型标识 */
|
||||||
|
|
||||||
|
#include "version.h"
|
||||||
|
|
||||||
|
/* GD32_FLASH_SIZE_KB（512/1024/2048）由 CMake 按 GD32_FLASH_CAPACITY 注入，
|
||||||
|
切换容量：cmake --preset Debug -DGD32_FLASH_CAPACITY=xG */
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[IIC TYPE DEFINE]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define SOFTWARE_IIC CFG_DISABLE // CFG_DISABLE: Hardware IIC; CFG_ENABLE: Software IIC
|
||||||
|
/* TODO: I2C 驱动尚未从 GD32E23x 工程移植，先保证工程可编译（见 AGENTS.md 进度清单） */
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[DEBUG MODE]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define DEBUG_MODE CFG_ENABLE // CFG_DISABLE: Release Mode; CFG_ENABLE: Debug Mode（发布/量产前改回 CFG_DISABLE）
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[COMMAND DEBUG]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define COM_DEBUG CFG_DISABLE // CFG_DISABLE: Command debug off; CFG_ENABLE: Command debug on
|
||||||
|
/* TODO: 串口命令协议模块（command.c）尚未移植（见 AGENTS.md 进度清单） */
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[DEBUG ASSERTIONS DEFINE]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define DEBUG_VERBOSE CFG_DISABLE // CFG_DISABLE: Verbose debug off; CFG_ENABLE: Verbose debug on
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[SEGGER RTT DETECTION]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define SEGGER_RTT_DETECTION CFG_ENABLE // CFG_DISABLE: SEGGER RTT off; CFG_ENABLE: SEGGER RTT on
|
||||||
|
|
||||||
|
#if SEGGER_RTT_DETECTION == CFG_ENABLE
|
||||||
|
#include "SEGGER_RTT.h"
|
||||||
|
#define RTT_printf(ch, ...) SEGGER_RTT_printf(ch, __VA_ARGS__)
|
||||||
|
#define RTT_WriteString(ch, s) SEGGER_RTT_WriteString(ch, s)
|
||||||
|
#define RTT_PutChar(ch, c) SEGGER_RTT_PutChar(ch, c)
|
||||||
|
#else
|
||||||
|
#define RTT_printf(ch, ...)
|
||||||
|
#define RTT_WriteString(ch, s)
|
||||||
|
#define RTT_PutChar(ch, c)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* >>>>>>>>>>>>>>>>>>>>[RS485 MODE]<<<<<<<<<<<<<<<<<<<< */
|
||||||
|
|
||||||
|
#define RS485_MODE CFG_DISABLE // CFG_DISABLE: RS485 off; CFG_ENABLE: RS485 on
|
||||||
|
/* GD32F4xx USART 无硬件 RS485 DE 驱动（E23x 特有），DE 引脚由 GPIO 手动控制 */
|
||||||
|
|
||||||
|
#if RS485_MODE == CFG_ENABLE
|
||||||
|
#define RS485_DE_RCU RCU_GPIOA
|
||||||
|
#define RS485_DE_PORT GPIOA
|
||||||
|
#define RS485_DE_PIN GPIO_PIN_1 // 根据实际硬件修改 DE 引脚
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/* 调试串口：USART1（PA2 TX / PA3 RX，AF7），纯串口，非 RS485。
|
||||||
|
注意 GD32F4xx 外设编号比 STM32 整体小 1：PA2/PA3 是 USART1（=STM32 的 USART2），
|
||||||
|
PA9/PA10 才是 USART0（=STM32 的 USART1） */
|
||||||
|
#define UART_RCU RCU_USART1
|
||||||
|
#define UART_PHY USART1
|
||||||
|
#define UART_IRQ USART1_IRQn
|
||||||
|
#define UART_GPIO_RCU RCU_GPIOA
|
||||||
|
#define UART_GPIO_PORT GPIOA
|
||||||
|
#define UART_TX_PIN GPIO_PIN_2
|
||||||
|
#define UART_RX_PIN GPIO_PIN_3
|
||||||
|
#define UART_BAUDRATE 115200U
|
||||||
|
|
||||||
|
/* USART中断处理函数声明 */
|
||||||
|
void usart0_irq_handler(void);
|
||||||
|
void usart1_irq_handler(void);
|
||||||
|
void usart2_irq_handler(void);
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/* I2C0: PB6 SCL / PB7 SDA, AF4 */
|
||||||
|
#define RCU_GPIO_I2C RCU_GPIOB
|
||||||
|
#define RCU_I2C RCU_I2C0
|
||||||
|
#define I2C_SCL_PORT GPIOB
|
||||||
|
#define I2C_SCL_PIN GPIO_PIN_6
|
||||||
|
#define I2C_SDA_PORT GPIOB
|
||||||
|
#define I2C_SDA_PIN GPIO_PIN_7
|
||||||
|
#define I2C_GPIO_AF GPIO_AF_4
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
/* LED: PA15（demo 板实测引脚，低电平点亮按原理图确认） */
|
||||||
|
#define LED_RCU RCU_GPIOA
|
||||||
|
#define LED_PORT GPIOA
|
||||||
|
#define LED_PIN GPIO_PIN_15
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
#define DEBUG_UART USART1
|
||||||
|
|
||||||
|
#endif //BOARD_CONFIG_H
|
||||||
@@ -0,0 +1,58 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_it.h
|
||||||
|
\brief the header file of the ISR
|
||||||
|
|
||||||
|
\version 2025-02-10, V2.4.0, demo for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2025, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_IT_H
|
||||||
|
#define GD32F4XX_IT_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* this function handles NMI exception */
|
||||||
|
void NMI_Handler(void);
|
||||||
|
/* this function handles HardFault exception */
|
||||||
|
void HardFault_Handler(void);
|
||||||
|
/* this function handles MemManage exception */
|
||||||
|
void MemManage_Handler(void);
|
||||||
|
/* this function handles BusFault exception */
|
||||||
|
void BusFault_Handler(void);
|
||||||
|
/* this function handles UsageFault exception */
|
||||||
|
void UsageFault_Handler(void);
|
||||||
|
/* this function handles SVC exception */
|
||||||
|
void SVC_Handler(void);
|
||||||
|
/* this function handles PendSV exception */
|
||||||
|
void PendSV_Handler(void);
|
||||||
|
/* this function handles SysTick exception */
|
||||||
|
void SysTick_Handler(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_IT_H */
|
||||||
@@ -0,0 +1,78 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_libopt.h
|
||||||
|
\brief library optional for gd32f4xx
|
||||||
|
|
||||||
|
\version 2026-02-12, V3.3.3, demo for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_LIBOPT_H
|
||||||
|
#define GD32F4XX_LIBOPT_H
|
||||||
|
|
||||||
|
#if defined (GD32F450) || defined (GD32F405) || defined (GD32F407) || defined (GD32F470) || defined (GD32F425) || defined (GD32F427)
|
||||||
|
#include "gd32f4xx_rcu.h"
|
||||||
|
#include "gd32f4xx_adc.h"
|
||||||
|
#include "gd32f4xx_can.h"
|
||||||
|
#include "gd32f4xx_crc.h"
|
||||||
|
#include "gd32f4xx_ctc.h"
|
||||||
|
#include "gd32f4xx_dac.h"
|
||||||
|
#include "gd32f4xx_dbg.h"
|
||||||
|
#include "gd32f4xx_dci.h"
|
||||||
|
#include "gd32f4xx_dma.h"
|
||||||
|
#include "gd32f4xx_exti.h"
|
||||||
|
#include "gd32f4xx_fmc.h"
|
||||||
|
#include "gd32f4xx_fwdgt.h"
|
||||||
|
#include "gd32f4xx_gpio.h"
|
||||||
|
#include "gd32f4xx_syscfg.h"
|
||||||
|
#include "gd32f4xx_i2c.h"
|
||||||
|
#include "gd32f4xx_iref.h"
|
||||||
|
#include "gd32f4xx_pmu.h"
|
||||||
|
#include "gd32f4xx_rtc.h"
|
||||||
|
#include "gd32f4xx_sdio.h"
|
||||||
|
#include "gd32f4xx_spi.h"
|
||||||
|
#include "gd32f4xx_timer.h"
|
||||||
|
#include "gd32f4xx_trng.h"
|
||||||
|
#include "gd32f4xx_usart.h"
|
||||||
|
#include "gd32f4xx_wwdgt.h"
|
||||||
|
#include "gd32f4xx_misc.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (GD32F450) || defined (GD32F470)
|
||||||
|
#include "gd32f4xx_enet.h"
|
||||||
|
#include "gd32f4xx_exmc.h"
|
||||||
|
#include "gd32f4xx_ipa.h"
|
||||||
|
#include "gd32f4xx_tli.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (GD32F407) || defined (GD32F427)
|
||||||
|
#include "gd32f4xx_enet.h"
|
||||||
|
#include "gd32f4xx_exmc.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_LIBOPT_H */
|
||||||
@@ -0,0 +1,13 @@
|
|||||||
|
#ifndef LED_H
|
||||||
|
#define LED_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
#include "board_config.h"
|
||||||
|
|
||||||
|
void led_init(void);
|
||||||
|
void led_on(void);
|
||||||
|
void led_off(void);
|
||||||
|
void led_toggle(void);
|
||||||
|
void led_heart_beat(void);
|
||||||
|
|
||||||
|
#endif // LED_H
|
||||||
@@ -0,0 +1,30 @@
|
|||||||
|
/**
|
||||||
|
* ************************************************************************
|
||||||
|
*
|
||||||
|
* @file systick.h
|
||||||
|
* @author GD32
|
||||||
|
* @brief
|
||||||
|
*
|
||||||
|
* ************************************************************************
|
||||||
|
* @copyright Copyright (c) 2024 GD32
|
||||||
|
* ************************************************************************
|
||||||
|
*/
|
||||||
|
#ifndef SYS_TICK_H
|
||||||
|
#define SYS_TICK_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* configure systick */
|
||||||
|
void systick_config(void);
|
||||||
|
|
||||||
|
/* delay a time in 10 microseconds */
|
||||||
|
void delay_10us(uint32_t count);
|
||||||
|
|
||||||
|
/* delay a time in milliseconds */
|
||||||
|
void delay_ms(uint32_t count);
|
||||||
|
|
||||||
|
/* decrement delay counters */
|
||||||
|
void delay_decrement(void);
|
||||||
|
|
||||||
|
#endif /* SYS_TICK_H */
|
||||||
+38
@@ -0,0 +1,38 @@
|
|||||||
|
#ifndef UART_H
|
||||||
|
#define UART_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
#include "board_config.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize UART interface
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void uart_init(void);
|
||||||
|
void debug_usart_init(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief pause UART RX interrupt (RBNE)
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void uart_rx_irq_pause(void);
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief resume UART RX interrupt (RBNE)
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void uart_rx_irq_resume(void);
|
||||||
|
|
||||||
|
#if RS485_MODE == CFG_ENABLE
|
||||||
|
/* RS485 DE 引脚手动控制（GD32F4xx USART 无硬件 DE 驱动） */
|
||||||
|
void rs485_de_set(void);
|
||||||
|
void rs485_de_clear(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // UART_H
|
||||||
@@ -0,0 +1,125 @@
|
|||||||
|
/**
|
||||||
|
* @file uart_ring_buffer.h
|
||||||
|
* @brief 简单高效的环形接收缓冲区（字节队列）接口声明。
|
||||||
|
* @details 提供字节写入/读取、可读长度查询、清空与丢弃统计等 API，
|
||||||
|
* 适用于中断接收（写）与主循环解析（读）的典型嵌入式串口场景。
|
||||||
|
*/
|
||||||
|
#ifndef UART_RING_BUFFER_H
|
||||||
|
#define UART_RING_BUFFER_H
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <stdbool.h>
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @def UART_RX_BUFFER_SIZE
|
||||||
|
* @brief 接收环形缓冲区容量（单位：字节）。
|
||||||
|
* @note 采用“预留一格”区分空/满策略，最大可用容量为 UART_RX_BUFFER_SIZE-1。
|
||||||
|
*/
|
||||||
|
#define UART_RX_BUFFER_SIZE 64
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @defgroup RingBuffer 环形缓冲区
|
||||||
|
* @brief 字节环形缓冲区（接收端）
|
||||||
|
* @{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @section RingBuffer_Usage 使用说明
|
||||||
|
* 典型用法：中断接收（写入环形缓冲）、主循环解析（读取环形缓冲）。
|
||||||
|
*
|
||||||
|
* 并发访问约束（SPSC，无锁单写单读）：
|
||||||
|
* - ISR 生产者：仅调用 uart_ring_buffer_put() 写入数据。
|
||||||
|
* - 主循环消费者：仅调用 uart_ring_buffer_get()/uart_ring_buffer_available() 读取数据。
|
||||||
|
* - uart_ring_buffer_init()/uart_ring_buffer_clear() 会同时修改读写索引，内部使用最小临界区保护。
|
||||||
|
* - 建议在主循环调用 clear/init 前先暂停 UART RX 中断，完成后再恢复，避免与 ISR 竞争。
|
||||||
|
*
|
||||||
|
* 1) 初始化
|
||||||
|
* @code{.c}
|
||||||
|
* uart_ring_buffer_init();
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* 2) 使能串口接收非空中断（RBNE）并开启中断（以 USART0 为例）
|
||||||
|
* @code{.c}
|
||||||
|
* usart_interrupt_enable(USART0, USART_INT_RBNE);
|
||||||
|
* nvic_irq_enable(USART0_IRQn, 2, 0); // 根据工程需要设置优先级
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* 3) 在中断服务函数中写入环形缓冲（参考你当前工程的写法）
|
||||||
|
* @code{.c}
|
||||||
|
* void USART0_IRQHandler(void) {
|
||||||
|
* if (RESET != usart_interrupt_flag_get(USART0, USART_INT_FLAG_RBNE)) {
|
||||||
|
* uint8_t data = usart_data_receive(USART0);
|
||||||
|
* (void)uart_ring_buffer_put(data); // 缓冲满时丢弃并计数
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* 4) 在主循环中读取处理
|
||||||
|
* @code{.c}
|
||||||
|
* while (uart_ring_buffer_available() > 0) {
|
||||||
|
* int b = uart_ring_buffer_get();
|
||||||
|
* if (b >= 0) {
|
||||||
|
* // 处理字节 b
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* @note 缓冲区满时新字节会被丢弃，可用 uart_ring_buffer_drop_count() 查看累计丢弃数。
|
||||||
|
* @note 采用“预留一格”区分空/满，最大可用容量为 UART_RX_BUFFER_SIZE-1。
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 初始化环形缓冲区。
|
||||||
|
* @details 复位读/写索引与丢弃计数，准备接收数据。
|
||||||
|
* @note 若在中断环境使用，初始化前建议关闭相关接收中断以避免并发竞争。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
void uart_ring_buffer_init(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 获取当前可读的字节数。
|
||||||
|
* @details 返回范围为 [0, UART_RX_BUFFER_SIZE-1]。
|
||||||
|
* @return 可读字节数（uint8_t）。
|
||||||
|
* @note 预留一个空槽区分“空/满”，因此满时返回 UART_RX_BUFFER_SIZE-1。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
uint8_t uart_ring_buffer_available(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 从环形缓冲区读取一个字节。
|
||||||
|
* @details 若缓冲区非空，返回队头字节并推进读指针；若为空，返回 -1。
|
||||||
|
* @return 读取到的字节（0..255），或 -1 表示缓冲区为空。
|
||||||
|
* @retval -1 缓冲区为空，无数据可读。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
int uart_ring_buffer_get(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 向环形缓冲区写入一个字节。
|
||||||
|
* @param data 待写入的字节。
|
||||||
|
* @return 是否写入成功。
|
||||||
|
* @retval true 写入成功。
|
||||||
|
* @retval false 写入失败（缓冲区已满，数据被丢弃并计数）。
|
||||||
|
* @note 如需改为“覆盖写入”策略，可在满时先推进读指针再写入。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
bool uart_ring_buffer_put(uint8_t data);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 清空环形缓冲区。
|
||||||
|
* @details 复位读/写索引与丢弃计数，相当于逻辑上丢弃所有已接收数据，不擦除数据区内容。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
void uart_ring_buffer_clear(void);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief 获取因缓冲区满而被丢弃的字节累计数量。
|
||||||
|
* @details 该计数在 init/clear 时清零。
|
||||||
|
* @return 丢弃的累计字节数。
|
||||||
|
* @ingroup RingBuffer
|
||||||
|
*/
|
||||||
|
uint32_t uart_ring_buffer_drop_count(void);
|
||||||
|
|
||||||
|
/** @} */
|
||||||
|
|
||||||
|
#endif // UART_RING_BUFFER_H
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xE_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xG_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xK_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,15 @@
|
|||||||
|
# GD32F405RET6 OpenOCD 会话配置（GD-LINK / CMSIS-DAP 调试器）
|
||||||
|
#
|
||||||
|
# 说明：
|
||||||
|
# - GD32F4xx 的 SWD ID 与 flash 扇区布局与 STM32F4 兼容，OpenOCD 使用 stm32f4x target 驱动
|
||||||
|
# （参考 metax-sensors/gd32-cmake-example 的做法，已在其 GD32F450 板上验证）。
|
||||||
|
# - interface/cmsis-dap.cfg 与 target/stm32f4x.cfg 通过 [find] 从 GD32_OPENOCD_SCRIPTS
|
||||||
|
# 根目录解析，因此任务/调试命令需附带 `-s %GD32_OPENOCD_SCRIPTS%`。
|
||||||
|
# - 如使用其它调试器，把第一行换成对应的 interface cfg，例如：
|
||||||
|
# source [find interface/jlink.cfg]
|
||||||
|
|
||||||
|
source [find interface/cmsis-dap.cfg]
|
||||||
|
source [find target/stm32f4x.cfg]
|
||||||
|
|
||||||
|
# 显式声明 512KB flash bank（GD32F405xE），避免自动探测偏差；1024K(xG) 时改为 0x100000
|
||||||
|
# flash bank stm32f2x.flash 0x08000000 0x80000 0 0 0
|
||||||
@@ -1,3 +1,355 @@
|
|||||||
# gd32f4xx_template_cmake_vscode
|
# GD32F4xx 工程模板
|
||||||
|
|
||||||
GD32F4xx系列芯片工程模板
|
本仓库为兆易创新 GD32F4xx 系列 MCU（Cortex-M4）的 CMake + VSCode 工程模板，
|
||||||
|
组织方式与编译方法沿用 [gd32e23x_template_cmake_vscode](../gd32e23x_template_cmake_vscode)，
|
||||||
|
在其基础上适配 **GD32F405RET6**（默认型号，64 脚 LQFP，512KB Flash / 192KB SRAM）。
|
||||||
|
构建输出位于工程根 `Build/`。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 目录
|
||||||
|
|
||||||
|
- [适用范围](#适用范围)
|
||||||
|
- [默认配置](#默认配置)
|
||||||
|
- [快速开始](#快速开始)
|
||||||
|
- [工程结构](#工程结构)
|
||||||
|
- [板级配置](#板级配置)
|
||||||
|
- [更换目标型号](#更换目标型号)
|
||||||
|
- [Flash 偏移配置（配合 Bootloader）](#flash-偏移配置配合-bootloader)
|
||||||
|
- [工具链准备](#工具链准备)
|
||||||
|
- [使用说明](#使用说明)
|
||||||
|
- [时钟配置说明](#时钟配置说明)
|
||||||
|
- [芯片文档清单](#芯片文档清单)
|
||||||
|
- [致谢](#致谢)
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 适用范围
|
||||||
|
|
||||||
|
- 适用于兆易创新 GD32F4xx 系列 Cortex-M4 内核单片机（默认按 GD32F405RET6 配置）
|
||||||
|
- 支持标准外设库开发（GD32F4xx_Firmware_Library V3.3.x，取自 GD32F4xx_Demo_Suites_V3.3.3）
|
||||||
|
- 推荐开发环境：VSCode + CMake + ARM GCC 工具链
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 默认配置
|
||||||
|
|
||||||
|
- 目标型号：**GD32F405RET6**（64 脚 LQFP；设备宏 `GD32F405`，启动文件 `startup_gd32f405_425.S`，链接脚本 `gd32f405_407_xE_flash.ld`，512K Flash / 128K RAM + 64K TCMRAM）
|
||||||
|
- MCU 主频：**内部 IRC16M 经 PLL 倍频至 168MHz**（板子无外部晶振；时钟源切换方法见[时钟配置说明](#时钟配置说明)）
|
||||||
|
- 调试串口：USART1（PA2 TX / PA3 RX，AF7，纯串口非 RS485），115200 波特率，printf 已重定向到该串口。注意 GD32F4xx 外设编号比 STM32 整体小 1：PA2/PA3 是 USART1，PA9/PA10 才是 USART0
|
||||||
|
- LED：PA15（demo 板实测引脚；复位后默认 JTDI 功能，配置为 GPIO 输出即接管，SWD 调试不受影响）
|
||||||
|
- I2C0：PB6 SCL / PB7 SDA（AF4）——驱动尚未移植，见 [AGENTS.md](AGENTS.md) 进度清单
|
||||||
|
- 浮点：硬件 FPU（`-mfpu=fpv4-sp-d16 -mfloat-abi=hard`），SystemInit 中自动使能
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 快速开始
|
||||||
|
|
||||||
|
### 基于模板创建新项目
|
||||||
|
|
||||||
|
1. **克隆或复制本仓库**
|
||||||
|
|
||||||
|
2. **修改项目配置** — 编辑 `cmake/project_config.cmake`：
|
||||||
|
```cmake
|
||||||
|
set(PROJECT_NAME "MyProject") # 项目名称
|
||||||
|
set(BOARD_TYPE_CODE 40) # 板卡类型码（协议帧中的标识）
|
||||||
|
set(VERSION_MAJOR 1) # 主版本号
|
||||||
|
set(VERSION_MINOR 0) # 次版本号
|
||||||
|
set(VERSION_PATCH 0) # 修订号
|
||||||
|
set(BUILD_VARIANT "APP") # 编译变体
|
||||||
|
```
|
||||||
|
|
||||||
|
3. **添加业务源文件** — 编辑 `CMakeLists.txt`，在 `TARGET_SRC` 中添加你的 `.c` 文件。
|
||||||
|
|
||||||
|
4. **配置板级引脚** — 编辑 `Inc/board_config.h`，修改 LED、UART、I2C 等引脚定义。
|
||||||
|
|
||||||
|
5. **编译**
|
||||||
|
```bash
|
||||||
|
cmake --preset Debug
|
||||||
|
cmake --build Build/Debug
|
||||||
|
```
|
||||||
|
产物在 `Build/Debug/` 下，包含 `.elf`、`.hex`、`.bin`、`.map`、`.list`。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 工程结构
|
||||||
|
|
||||||
|
```
|
||||||
|
.
|
||||||
|
├── CMakeLists.txt # 主构建文件
|
||||||
|
├── CMakePresets.json # CMake 预设（Debug/Release，构建树位于 Build/）
|
||||||
|
├── cmake/
|
||||||
|
│ ├── arm-none-eabi-gcc.cmake # ARM GCC 工具链配置（cortex-m4 + 硬件 FPU）
|
||||||
|
│ ├── project.cmake # 编译选项（-Os/-O0, -mcpu=cortex-m4）
|
||||||
|
│ ├── project_config.cmake # 项目名/版本号/编译变体
|
||||||
|
│ └── version.h.in # 自动生成固件版本头
|
||||||
|
├── Inc/ # 头文件
|
||||||
|
│ ├── board_config.h # 板级引脚定义 + 功能开关
|
||||||
|
│ ├── gd32f4xx_libopt.h # 标准外设库统一包含
|
||||||
|
│ ├── gd32f4xx_it.h / led.h / systick.h / uart.h
|
||||||
|
│ └── uart_ring_buffer.h
|
||||||
|
├── Src/ # 源码
|
||||||
|
│ ├── main.c # 入口函数
|
||||||
|
│ ├── board_config.c # Flash 容量检测 + 串口资源配置
|
||||||
|
│ ├── uart.c / led.c / systick.c / uart_ring_buffer.c
|
||||||
|
│ └── gd32f4xx_it.c / system_gd32f4xx.c / syscalls.c
|
||||||
|
├── SDK/
|
||||||
|
│ ├── CMSIS/ # CMSIS core_cm4 + GD32F4xx 设备头 + 启动文件
|
||||||
|
│ │ └── startup/startup_gd32f405_425.S # GCC 版启动文件
|
||||||
|
│ ├── GD32F4xx_standard_peripheral/ # GD32 标准外设库（29 个模块）
|
||||||
|
│ ├── GD32F4xx_usb_library/ # USB 库（默认不编译，-DGD32_ENABLE_USB=ON 启用，
|
||||||
|
│ │ └── ... # 默认含 driver+device core+CDC 虚拟串口，详见其 CMakeLists）
|
||||||
|
│ └── SEGGER_RTT/ # SEGGER RTT 调试输出
|
||||||
|
├── LD/ # 链接脚本（gd32f405_407_xE/xG/xK 三种容量）
|
||||||
|
├── OpenOCD/ # 工程内 OpenOCD 会话配置（GD-LINK/CMSIS-DAP）
|
||||||
|
├── GD32F4xx.svd # CMSIS-SVD 外设寄存器描述（调试视图用）
|
||||||
|
├── doc/ # 芯片数据手册/用户手册/固件库指南/AN（已齐备）
|
||||||
|
├── Build/ # 构建输出目录（temp 之外，gitignore）
|
||||||
|
├── GD32F4xx_Demo_Suites_V3.3.3/# 官方原始素材包（本地参考，不入库）
|
||||||
|
└── .vscode/ # VSCode 调试/烧录配置
|
||||||
|
```
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 板级配置（`Inc/board_config.h`）
|
||||||
|
|
||||||
|
所有功能开关和引脚定义集中在 `Inc/board_config.h`。功能开关均为单行数值宏：将右侧的
|
||||||
|
`ENABLE` 或 `DISABLE` 改为另一值即可；其中 `ENABLE` 为 `1`，`DISABLE` 为 `0`。
|
||||||
|
|
||||||
|
### 功能开关速查表
|
||||||
|
|
||||||
|
| 宏 | 作用 | 默认值 | Release 建议 |
|
||||||
|
|---|------|:---:|:---:|
|
||||||
|
| `SOFTWARE_IIC` | I2C 实现方式 | `DISABLE`（硬件） | `DISABLE` |
|
||||||
|
| `DEBUG_MODE` | printf 串口输出 | `DISABLE` | `DISABLE` |
|
||||||
|
| `COM_DEBUG` | 命令帧调试打印 | `DISABLE` | `DISABLE` |
|
||||||
|
| `DEBUG_VERBOSE` | 详细调试信息 | `DISABLE` | `DISABLE` |
|
||||||
|
| `SEGGER_RTT_DETECTION` | SEGGER RTT 支持 | `ENABLE` | `DISABLE` |
|
||||||
|
| `RS485_MODE` | RS485 DE 引脚控制 | `DISABLE` | 按需 |
|
||||||
|
|
||||||
|
> `RS485_MODE`：GD32F4xx 的 USART 没有 E23x 那样的硬件 RS485 DE 驱动，本模板用
|
||||||
|
> GPIO 手动控制 DE 引脚（`rs485_de_set()/rs485_de_clear()`），收发切换逻辑需在
|
||||||
|
> 业务层调用。
|
||||||
|
|
||||||
|
### 引脚定义
|
||||||
|
|
||||||
|
```c
|
||||||
|
/* I2C0（驱动待移植） */
|
||||||
|
#define RCU_GPIO_I2C RCU_GPIOB
|
||||||
|
#define I2C_SCL_PORT GPIOB
|
||||||
|
#define I2C_SCL_PIN GPIO_PIN_6
|
||||||
|
#define I2C_SDA_PORT GPIOB
|
||||||
|
#define I2C_SDA_PIN GPIO_PIN_7
|
||||||
|
#define I2C_GPIO_AF GPIO_AF_4
|
||||||
|
|
||||||
|
/* LED（demo 板: PA15） */
|
||||||
|
#define LED_RCU RCU_GPIOA
|
||||||
|
#define LED_PORT GPIOA
|
||||||
|
#define LED_PIN GPIO_PIN_15
|
||||||
|
|
||||||
|
/* 调试串口 USART1（PA2/PA3，纯串口；GD 编号比 STM32 小 1） */
|
||||||
|
#define UART_GPIO_PORT GPIOA
|
||||||
|
#define UART_TX_PIN GPIO_PIN_2
|
||||||
|
#define UART_RX_PIN GPIO_PIN_3
|
||||||
|
#define UART_BAUDRATE 115200U
|
||||||
|
```
|
||||||
|
|
||||||
|
### Flash 容量切换（xE / xG / xK）
|
||||||
|
|
||||||
|
同系列不同容量的芯片（如 GD32F405RE 512K → GD32F405RG 1024K）在**编译期**切换，
|
||||||
|
无需改代码：CMake 变量 `GD32_FLASH_CAPACITY`（定义在 `cmake/project_config.cmake`，
|
||||||
|
默认 `xE`）决定链接脚本（`LD/gd32f405_407_xE|xG|xK_flash.ld`）并向代码注入
|
||||||
|
`GD32_FLASH_SIZE_KB` 宏（512/1024/2048）。
|
||||||
|
|
||||||
|
```bash
|
||||||
|
# 切换到 1024K 容量（对当前 preset 的构建目录生效）
|
||||||
|
cmake --preset Debug -DGD32_FLASH_CAPACITY=xG
|
||||||
|
cmake --build Build/Debug
|
||||||
|
```
|
||||||
|
|
||||||
|
> 注意：该变量写入 CMake cache，切换后会保持——恢复默认需显式
|
||||||
|
> `-DGD32_FLASH_CAPACITY=xE` 或删除 `Build/<Config>` 目录重新配置。
|
||||||
|
> 也可在 VSCode CMake Tools 的缓存编辑界面直接修改。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 更换目标型号
|
||||||
|
|
||||||
|
换用 GD32F405/425、GD32F450/470 等 F4 家族其它型号时，修改 4 处：
|
||||||
|
|
||||||
|
1. **设备宏** — `cmake/project.cmake` 与 `SDK/GD32F4xx_standard_peripheral/CMakeLists.txt`
|
||||||
|
中的 `GD32F405` 改为 `GD32F407` / `GD32F425` / `GD32F450` / `GD32F470`。
|
||||||
|
2. **启动文件** — `CMakeLists.txt` 的 `TARGET_SRC`：
|
||||||
|
- F405/F425：`startup_gd32f405_425.S`（默认）
|
||||||
|
- F407/F427：`startup_gd32f407_427.S`
|
||||||
|
- F450/F470：`startup_gd32f450_470.S`
|
||||||
|
|
||||||
|
备份均在 `SDK/CMSIS/GD/GD32F4xx/Source/GCC/` 下，复制到 `SDK/CMSIS/startup/` 使用。
|
||||||
|
3. **链接脚本** — `CMakeLists.txt` 中 `-T` 参数按容量选择
|
||||||
|
`LD/gd32f405_407_xE_flash.ld`（512K，默认）/ `xG`（1024K）/ `xK`（2048K）。
|
||||||
|
4. **时钟上限** — `Src/system_gd32f4xx.c`：F405/407 最高 168MHz、F450/425/427 最高
|
||||||
|
200MHz、F470 最高 240MHz（该文件已按型号条件编译，换宏后默认值自动跟随）。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## Flash 偏移配置（配合 Bootloader）
|
||||||
|
|
||||||
|
如果固件需要通过 Bootloader 启动（Bootloader 占用 Flash 前部区域），需修改两处：
|
||||||
|
|
||||||
|
**1. 链接脚本** — `LD/gd32f405_407_xE_flash.ld` 开头的 MEMORY：
|
||||||
|
```c
|
||||||
|
// 默认：从 Flash 起始运行
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
|
||||||
|
// 配合 Bootloader：前 64KB 留给 Bootloader，App 从 0x08010000 开始
|
||||||
|
FLASH (rx): ORIGIN = 0x08010000, LENGTH = 960K
|
||||||
|
```
|
||||||
|
|
||||||
|
**2. 向量表偏移** — `Src/system_gd32f4xx.c` 第 44 行：
|
||||||
|
```c
|
||||||
|
// 默认
|
||||||
|
#define VECT_TAB_OFFSET (uint32_t)0x00
|
||||||
|
|
||||||
|
// 配合 Bootloader（值 = Flash 偏移量，不含 0x0800 前缀）
|
||||||
|
#define VECT_TAB_OFFSET (uint32_t)0x10000
|
||||||
|
```
|
||||||
|
|
||||||
|
> ⚠️ 两个偏移值必须对应修改：`LD` 中的 `ORIGIN` 减去 `0x08000000` 应等于 `VECT_TAB_OFFSET`。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 工具链准备
|
||||||
|
|
||||||
|
### 1. ARM GCC 工具链
|
||||||
|
|
||||||
|
- **验证版本**：xpack-arm-none-eabi-gcc-15.2.1-1.1（本机当前使用，已验证编译链接通过）
|
||||||
|
- **安装位置**：每台电脑本机任意目录，工具包不放入工程仓库
|
||||||
|
- **官方下载地址**：https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases
|
||||||
|
- **活动变量**：`GD32_GCC_BIN`，值为工具链的 `bin` 目录（也接受工具链根目录）
|
||||||
|
|
||||||
|
### 2. OpenOCD（调试/烧录）
|
||||||
|
|
||||||
|
- **版本**：xpack-openocd-0.11.0-3（与 E23x 工程一致）
|
||||||
|
- **获取地址**：https://github.com/burakenez/gd32-tools-xpack-openocd/tree/v0.11.0-3
|
||||||
|
- **活动变量**：`GD32_OPENOCD_BIN`、`GD32_OPENOCD_SCRIPTS`
|
||||||
|
|
||||||
|
与 E23x 工程不同，本模板的 OpenOCD 目标配置**放在工程内**（借鉴
|
||||||
|
[metax-sensors/gd32-cmake-example](https://github.com/metax-sensors/gd32-cmake-example)）：
|
||||||
|
`OpenOCD/gd32f405_gdlink_cmsis_dap.cfg`，内容为 CMSIS-DAP 接口 + `target/stm32f4x.cfg`
|
||||||
|
（GD32F4xx 的 SWD ID 与 flash 扇区布局与 STM32F4 兼容）。标准脚本仍通过
|
||||||
|
`GD32_OPENOCD_SCRIPTS` 解析。换 J-Link/OpenOCD 时只需改这一份文件。
|
||||||
|
|
||||||
|
每台开发电脑配置一次用户环境变量（路径按本机实际位置填写）：
|
||||||
|
|
||||||
|
```powershell
|
||||||
|
[Environment]::SetEnvironmentVariable("GD32_GCC_BIN", "D:\toolchain\xpack-arm-none-eabi-gcc-15.2.1-1.1\bin", "User")
|
||||||
|
[Environment]::SetEnvironmentVariable("GD32_OPENOCD_BIN", "D:\Tools\xpack-openocd-0.11.0-3\bin", "User")
|
||||||
|
[Environment]::SetEnvironmentVariable("GD32_OPENOCD_SCRIPTS", "D:\Tools\xpack-openocd-0.11.0-3\scripts", "User")
|
||||||
|
```
|
||||||
|
|
||||||
|
环境变量命名、工具链切换方法（多套 GCC 变量 + `GD32_GCC_ENV_VAR`）与 E23x 模板完全一致，
|
||||||
|
详见 E23x 工程 README 的"工具链切换"章节。
|
||||||
|
|
||||||
|
### 环境要求清单
|
||||||
|
|
||||||
|
| 变量名 | 值 | 用途 |
|
||||||
|
|---|---|---|
|
||||||
|
| `GD32_GCC_BIN` | 活动 ARM GCC 的 `bin` 目录 | CMake 编译、GDB 调试、binutils |
|
||||||
|
| `GD32_OPENOCD_BIN` | 包含 `openocd.exe` 的 `bin` 目录 | OpenOCD 任务/调试 |
|
||||||
|
| `GD32_OPENOCD_SCRIPTS` | OpenOCD `scripts` 根目录 | `-s` 脚本搜索路径 |
|
||||||
|
|
||||||
|
另需：CMake ≥ 3.20、Ninja、VSCode CMake Tools、cortex-debug；J-Link 任务另需
|
||||||
|
`JLink.exe` 在 PATH 中（device 为 `GD32F405RE`，见 `.vscode/settings.json`）。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 使用说明
|
||||||
|
|
||||||
|
### 编译
|
||||||
|
|
||||||
|
```bash
|
||||||
|
# Debug 构建（-O0, -g3）
|
||||||
|
cmake --preset Debug
|
||||||
|
cmake --build Build/Debug
|
||||||
|
|
||||||
|
# Release 构建（-Os, -g0）
|
||||||
|
cmake --preset Release
|
||||||
|
cmake --build Build/Release
|
||||||
|
```
|
||||||
|
|
||||||
|
构建树与产物位于工程根的 `Build/<配置名>/`（与 E23x 模板一致），可随时整目录删除重新配置。
|
||||||
|
|
||||||
|
### 烧录
|
||||||
|
|
||||||
|
通过 VSCode 任务栏运行 `Flash MCU`（OpenOCD/GD-LINK）或 `Flash MCU (Jlink)` 任务。
|
||||||
|
|
||||||
|
### 产物
|
||||||
|
|
||||||
|
编译输出位于 `Build/<Config>/`：
|
||||||
|
|
||||||
|
| 文件 | 说明 |
|
||||||
|
|------|------|
|
||||||
|
| `Application/Application.elf` | ELF 固件（调试用） |
|
||||||
|
| `Application/Application.hex/.map` | 烧录用 hex、内存映射 |
|
||||||
|
| `{项目名}_{版本}_{编译条件}_{日期}.hex/.bin` | 版本化发布产物 |
|
||||||
|
| `{项目名}_{版本}_{编译条件}_{日期}.list/.bsz/.ssz` | 反汇编清单、尺寸记录 |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 时钟配置说明
|
||||||
|
|
||||||
|
本工程默认系统时钟为**内部 16MHz IRC 振荡器（IRC16M）经 PLL 倍频后的 168MHz**——
|
||||||
|
因为当前 demo 板**没有外部晶振**。注意：HXTAL 方案在晶振不起振时会**死循环等待**
|
||||||
|
（`system_gd32f4xx.c` 各 HXTAL 分支的 `while` 等待），表现为程序完全不动，因此
|
||||||
|
无晶振的板子必须使用 IRC16M 方案。
|
||||||
|
|
||||||
|
### 时钟源切换方法
|
||||||
|
|
||||||
|
修改 `Src/system_gd32f4xx.c` 的宏定义区（约第 46~69 行），**同一型号组内只保留
|
||||||
|
一行未注释**：
|
||||||
|
|
||||||
|
```c
|
||||||
|
#if defined (GD32F405) || defined (GD32F407)
|
||||||
|
#define __SYSTEM_CLOCK_168M_PLL_IRC16M (uint32_t)(168000000) // 无外部晶振（默认）
|
||||||
|
//#define __SYSTEM_CLOCK_168M_PLL_8M_HXTAL (uint32_t)(168000000) // 板载 8MHz 晶振
|
||||||
|
//#define __SYSTEM_CLOCK_168M_PLL_25M_HXTAL (uint32_t)(168000000) // 板载 25MHz 晶振
|
||||||
|
#endif
|
||||||
|
```
|
||||||
|
|
||||||
|
- **切换到外部晶振（8M/25M HXTAL）**：改用对应宏之外，还需同步修改
|
||||||
|
`SDK/CMSIS/GD/GD32F4xx/Include/gd32f4xx.h` 中的 `HXTAL_VALUE`
|
||||||
|
（默认 25000000，8M 晶振改为 8000000），两处必须一致。
|
||||||
|
- **切换回内部时钟（IRC16M）**：注释 HXTAL 行、放开 IRC16M 行即可，无需其它修改。
|
||||||
|
- 主频也可在宏区选择 120MHz 档（详见文件内注释），F405/407 最高 168MHz。
|
||||||
|
|
||||||
|
改完保存，重新编译烧录即生效。
|
||||||
|
|
||||||
|
> 实测参考：IRC16M 方案下 SCSS=PLLP（系统时钟已锁定 PLL）、SysTick 1ms 精确、
|
||||||
|
> LED 心跳周期 2 秒整、USART1@APB1(42MHz) 波特率寄存器 365 对应 115200 精确。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 芯片文档清单
|
||||||
|
|
||||||
|
`doc/` 目录已齐备：
|
||||||
|
|
||||||
|
| 文件 | 说明 |
|
||||||
|
|------|------|
|
||||||
|
| GD32F405xx_Datasheet_Rev2.8.pdf | 芯片数据手册（RET6 属 xE 容量档） |
|
||||||
|
| GD32F4xx_User_Manual_Rev3.3.pdf | 用户手册（寄存器/外设描述） |
|
||||||
|
| GD32F4xx_Firmware_Library_User_Guide_Rev1.2.pdf | 固件库使用指南（英文） |
|
||||||
|
| GD32F4xx_固件库使用指南_Rev1.2.pdf | 固件库使用指南（中文） |
|
||||||
|
| AN059 提高ADC采样精度的方法.pdf | 应用笔记 |
|
||||||
|
| AN200 GD32 Embedded Builder 链接脚本说明_Rev1.0.pdf | 应用笔记 |
|
||||||
|
|
||||||
|
另：`GD32F4xx.svd`（调试寄存器视图）在工程根目录。
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 致谢
|
||||||
|
|
||||||
|
- [celalkismiroglu/gd32e23x-demo-suites-cmake](https://github.com/celalkismiroglu/gd32e23x-demo-suites-cmake)
|
||||||
|
—— E23x 模板的起点，本工程的模板体系由其迭代而来。
|
||||||
|
- [metax-sensors/gd32-cmake-example](https://github.com/metax-sensors/gd32-cmake-example)
|
||||||
|
—— GD32F4xx + CMake 的开源参考（OpenOCD stm32f4x 驱动方案、工程内 cfg 组织）。
|
||||||
|
- 兆易创新 GD32F4xx_Demo_Suites_V3.3.3 / GD32F4xx_Firmware_Library —— SDK 来源。
|
||||||
|
|||||||
@@ -0,0 +1,13 @@
|
|||||||
|
project(CMSIS LANGUAGES C CXX ASM)
|
||||||
|
|
||||||
|
add_library(CMSIS INTERFACE)
|
||||||
|
|
||||||
|
target_include_directories(CMSIS INTERFACE
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/CMSIS
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/CMSIS/GD/GD32F4xx/Include
|
||||||
|
|
||||||
|
# Added directory of "gd32f4xx_libopt.h".
|
||||||
|
${CMAKE_SOURCE_DIR}/Inc
|
||||||
|
|
||||||
|
# 如有其它需要的头文件目录，可继续添加
|
||||||
|
)
|
||||||
@@ -0,0 +1,370 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx.h
|
||||||
|
\brief general definitions for GD32F4xx
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_H
|
||||||
|
#define GD32F4XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* define GD32F4xx */
|
||||||
|
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||||
|
/* #define GD32F450 */
|
||||||
|
/* #define GD32F405 */
|
||||||
|
/* #define GD32F407 */
|
||||||
|
/* #define GD32F470 */
|
||||||
|
/* #define GD32F425 */
|
||||||
|
/* #define GD32F427 */
|
||||||
|
#endif /* define GD32F4xx */
|
||||||
|
|
||||||
|
#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
|
||||||
|
#error "Please select the target GD32F4xx device in gd32f4xx.h file"
|
||||||
|
#endif /* undefine GD32F4xx tip */
|
||||||
|
|
||||||
|
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||||
|
#if !defined (HXTAL_VALUE)
|
||||||
|
#define HXTAL_VALUE ((uint32_t)25000000)
|
||||||
|
#endif /* high speed crystal oscillator value */
|
||||||
|
|
||||||
|
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||||
|
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||||
|
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
|
||||||
|
#endif /* high speed crystal oscillator startup timeout */
|
||||||
|
|
||||||
|
/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
|
||||||
|
#if !defined (IRC16M_VALUE)
|
||||||
|
#define IRC16M_VALUE ((uint32_t)16000000)
|
||||||
|
#endif /* internal 16MHz RC oscillator value */
|
||||||
|
|
||||||
|
/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
|
||||||
|
#if !defined (IRC16M_STARTUP_TIMEOUT)
|
||||||
|
#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||||
|
#endif /* internal 16MHz RC oscillator startup timeout */
|
||||||
|
|
||||||
|
/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
|
||||||
|
#if !defined (IRC32K_VALUE)
|
||||||
|
#define IRC32K_VALUE ((uint32_t)32000)
|
||||||
|
#endif /* internal 32KHz RC oscillator value */
|
||||||
|
|
||||||
|
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||||
|
#if !defined (LXTAL_VALUE)
|
||||||
|
#define LXTAL_VALUE ((uint32_t)32768)
|
||||||
|
#endif /* low speed crystal oscillator value */
|
||||||
|
|
||||||
|
/* I2S external clock in selection */
|
||||||
|
//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
|
||||||
|
|
||||||
|
/* GD32F4xx firmware library version number V1.0 */
|
||||||
|
#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
|
||||||
|
#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
|
||||||
|
#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||||
|
#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||||
|
#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
|
||||||
|
|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
|
||||||
|
|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
|
||||||
|
|(__GD32F4xx_STDPERIPH_VERSION_RC))
|
||||||
|
|
||||||
|
/* configuration of the cortex-M4 processor and core peripherals */
|
||||||
|
#define __CM4_REV 0x0001 /*!< core revision r0p1 */
|
||||||
|
#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
|
||||||
|
#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
|
||||||
|
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||||
|
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||||
|
/* define interrupt number */
|
||||||
|
typedef enum IRQn
|
||||||
|
{
|
||||||
|
/* cortex-M4 processor exceptions numbers */
|
||||||
|
NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
|
||||||
|
HardFault_IRQn = -13, /*!< hard-fault interrupt */
|
||||||
|
MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
|
||||||
|
BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
|
||||||
|
UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
|
||||||
|
SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
|
||||||
|
DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
|
||||||
|
PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
|
||||||
|
SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
|
||||||
|
/* interruput numbers */
|
||||||
|
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||||
|
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||||
|
TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
|
||||||
|
RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
|
||||||
|
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||||
|
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||||
|
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
|
||||||
|
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
|
||||||
|
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
|
||||||
|
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
|
||||||
|
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
|
||||||
|
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
|
||||||
|
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
|
||||||
|
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||||
|
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||||
|
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||||
|
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||||
|
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||||
|
ADC_IRQn = 18, /*!< ADC interrupt */
|
||||||
|
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||||
|
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||||
|
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||||
|
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||||
|
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||||
|
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
|
||||||
|
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
|
||||||
|
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||||
|
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||||
|
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||||
|
TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
|
||||||
|
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||||
|
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||||
|
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||||
|
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||||
|
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||||
|
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||||
|
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||||
|
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||||
|
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||||
|
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||||
|
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||||
|
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||||
|
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
|
||||||
|
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
|
||||||
|
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||||
|
DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
|
||||||
|
|
||||||
|
#if defined (GD32F450) || defined (GD32F470)
|
||||||
|
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||||
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
|
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||||
|
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||||
|
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||||
|
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||||
|
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||||
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||||
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||||
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||||
|
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||||
|
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||||
|
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||||
|
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||||
|
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||||
|
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||||
|
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||||
|
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||||
|
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||||
|
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||||
|
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||||
|
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||||
|
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||||
|
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||||
|
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||||
|
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||||
|
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||||
|
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||||
|
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||||
|
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||||
|
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||||
|
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||||
|
UART6_IRQn = 82, /*!< UART6 interrupt */
|
||||||
|
UART7_IRQn = 83, /*!< UART7 interrupt */
|
||||||
|
SPI3_IRQn = 84, /*!< SPI3 interrupt */
|
||||||
|
SPI4_IRQn = 85, /*!< SPI4 interrupt */
|
||||||
|
SPI5_IRQn = 86, /*!< SPI5 interrupt */
|
||||||
|
TLI_IRQn = 88, /*!< TLI interrupt */
|
||||||
|
TLI_ER_IRQn = 89, /*!< TLI error interrupt */
|
||||||
|
IPA_IRQn = 90, /*!< IPA interrupt */
|
||||||
|
#endif /* GD32F450 and GD32F470 */
|
||||||
|
|
||||||
|
#if defined (GD32F405) || defined (GD32F425)
|
||||||
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
|
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||||
|
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||||
|
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||||
|
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||||
|
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||||
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||||
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||||
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||||
|
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||||
|
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||||
|
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||||
|
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||||
|
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||||
|
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||||
|
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||||
|
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||||
|
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||||
|
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||||
|
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||||
|
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||||
|
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||||
|
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
|
||||||
|
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||||
|
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||||
|
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||||
|
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||||
|
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||||
|
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||||
|
#endif /* GD32F405 and GD32F425 */
|
||||||
|
|
||||||
|
#if defined (GD32F407) || defined (GD32F427)
|
||||||
|
EXMC_IRQn = 48, /*!< EXMC interrupt */
|
||||||
|
SDIO_IRQn = 49, /*!< SDIO interrupt */
|
||||||
|
TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
|
||||||
|
SPI2_IRQn = 51, /*!< SPI2 interrupt */
|
||||||
|
UART3_IRQn = 52, /*!< UART3 interrupt */
|
||||||
|
UART4_IRQn = 53, /*!< UART4 interrupt */
|
||||||
|
TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
|
||||||
|
TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
|
||||||
|
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
|
||||||
|
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
|
||||||
|
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
|
||||||
|
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
|
||||||
|
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
|
||||||
|
ENET_IRQn = 61, /*!< ENET interrupt */
|
||||||
|
ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
|
||||||
|
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||||
|
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||||
|
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||||
|
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||||
|
USBFS_IRQn = 67, /*!< USBFS interrupt */
|
||||||
|
DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
|
||||||
|
DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
|
||||||
|
DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
|
||||||
|
USART5_IRQn = 71, /*!< USART5 interrupt */
|
||||||
|
I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
|
||||||
|
I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
|
||||||
|
USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
|
||||||
|
USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
|
||||||
|
USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
|
||||||
|
USBHS_IRQn = 77, /*!< USBHS interrupt */
|
||||||
|
DCI_IRQn = 78, /*!< DCI interrupt */
|
||||||
|
TRNG_IRQn = 80, /*!< TRNG interrupt */
|
||||||
|
FPU_IRQn = 81, /*!< FPU interrupt */
|
||||||
|
#endif /* GD32F407 and GD32F427 */
|
||||||
|
|
||||||
|
} IRQn_Type;
|
||||||
|
|
||||||
|
/* includes */
|
||||||
|
#include "core_cm4.h"
|
||||||
|
#include "system_gd32f4xx.h"
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* enum definitions */
|
||||||
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||||
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||||
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||||
|
|
||||||
|
/* bit operations */
|
||||||
|
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||||
|
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||||
|
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||||
|
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||||
|
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||||
|
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||||
|
|
||||||
|
/* main flash and SRAM memory map */
|
||||||
|
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||||
|
#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
|
||||||
|
#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
|
||||||
|
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||||
|
|
||||||
|
/* peripheral memory map */
|
||||||
|
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||||
|
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||||
|
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||||
|
#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
|
||||||
|
|
||||||
|
/* EXMC memory map */
|
||||||
|
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||||
|
|
||||||
|
/* advanced peripheral bus 1 memory map */
|
||||||
|
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||||
|
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||||
|
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||||
|
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||||
|
#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
|
||||||
|
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||||
|
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||||
|
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||||
|
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||||
|
#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
|
||||||
|
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||||
|
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||||
|
#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
|
||||||
|
|
||||||
|
/* advanced peripheral bus 2 memory map */
|
||||||
|
#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
|
||||||
|
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
|
||||||
|
#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
|
||||||
|
#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
|
||||||
|
#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
|
||||||
|
/* advanced high performance bus 1 memory map */
|
||||||
|
#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||||
|
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||||
|
#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
|
||||||
|
#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
|
||||||
|
#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
|
||||||
|
#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
|
||||||
|
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||||||
|
#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
|
||||||
|
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||||||
|
|
||||||
|
/* advanced high performance bus 2 memory map */
|
||||||
|
#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
|
||||||
|
#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
|
||||||
|
#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
|
||||||
|
/* option byte and debug memory map */
|
||||||
|
#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
|
||||||
|
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||||
|
|
||||||
|
/* define marco USE_STDPERIPH_DRIVER */
|
||||||
|
#if !defined USE_STDPERIPH_DRIVER
|
||||||
|
#define USE_STDPERIPH_DRIVER
|
||||||
|
#endif
|
||||||
|
#ifdef USE_STDPERIPH_DRIVER
|
||||||
|
#include "gd32f4xx_libopt.h"
|
||||||
|
#endif /* USE_STDPERIPH_DRIVER */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
@@ -0,0 +1,65 @@
|
|||||||
|
/*!
|
||||||
|
\file system_gd32f4xx.h
|
||||||
|
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||||
|
GD32F4xx Device Series
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
#ifndef SYSTEM_GD32F4XX_H
|
||||||
|
#define SYSTEM_GD32F4XX_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
/* firmware version can be aquired by uncommenting the macro */
|
||||||
|
#define __FIRMWARE_VERSION_DEFINE
|
||||||
|
|
||||||
|
/* system clock frequency (core clock) */
|
||||||
|
extern uint32_t SystemCoreClock;
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialize the system and update the SystemCoreClock variable */
|
||||||
|
extern void SystemInit (void);
|
||||||
|
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||||
|
extern void SystemCoreClockUpdate (void);
|
||||||
|
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||||
|
/* get firmware version */
|
||||||
|
extern uint32_t gd32f4xx_firmware_version_get(void);
|
||||||
|
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* SYSTEM_GD32F4XX_H */
|
||||||
@@ -0,0 +1,423 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD 0 ; 64:Reserved
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD 0 ; 77:Reserved
|
||||||
|
DCD 0 ; 78:Reserved
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
@@ -0,0 +1,429 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f407_427.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT EXMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
EXMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
ENET_IRQHandler
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
@@ -0,0 +1,454 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
; <h> Stack Configuration
|
||||||
|
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Stack_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||||
|
Stack_Mem SPACE Stack_Size
|
||||||
|
__initial_sp
|
||||||
|
|
||||||
|
|
||||||
|
; <h> Heap Configuration
|
||||||
|
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||||
|
; </h>
|
||||||
|
|
||||||
|
Heap_Size EQU 0x00000400
|
||||||
|
|
||||||
|
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||||
|
__heap_base
|
||||||
|
Heap_Mem SPACE Heap_Size
|
||||||
|
__heap_limit
|
||||||
|
|
||||||
|
PRESERVE8
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
; /* reset Vector Mapped to at Address 0 */
|
||||||
|
AREA RESET, DATA, READONLY
|
||||||
|
EXPORT __Vectors
|
||||||
|
EXPORT __Vectors_End
|
||||||
|
EXPORT __Vectors_Size
|
||||||
|
|
||||||
|
__Vectors DCD __initial_sp ; Top of Stack
|
||||||
|
DCD Reset_Handler ; Reset Handler
|
||||||
|
DCD NMI_Handler ; NMI Handler
|
||||||
|
DCD HardFault_Handler ; Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; PendSV Handler
|
||||||
|
DCD SysTick_Handler ; SysTick Handler
|
||||||
|
|
||||||
|
; /* external interrupts handler */
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
DCD UART6_IRQHandler ; 98:UART6
|
||||||
|
DCD UART7_IRQHandler ; 99:UART7
|
||||||
|
DCD SPI3_IRQHandler ; 100:SPI3
|
||||||
|
DCD SPI4_IRQHandler ; 101:SPI4
|
||||||
|
DCD SPI5_IRQHandler ; 102:SPI5
|
||||||
|
DCD 0 ; 103:Reserved
|
||||||
|
DCD TLI_IRQHandler ; 104:TLI
|
||||||
|
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||||
|
DCD IPA_IRQHandler ; 106:IPA
|
||||||
|
|
||||||
|
__Vectors_End
|
||||||
|
|
||||||
|
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||||
|
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
|
||||||
|
;/* reset Handler */
|
||||||
|
Reset_Handler PROC
|
||||||
|
EXPORT Reset_Handler [WEAK]
|
||||||
|
IMPORT SystemInit
|
||||||
|
IMPORT __main
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__main
|
||||||
|
BX R0
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
;/* dummy Exception Handlers */
|
||||||
|
NMI_Handler PROC
|
||||||
|
EXPORT NMI_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
HardFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT HardFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
MemManage_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT MemManage_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
BusFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT BusFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
UsageFault_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT UsageFault_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SVC_Handler PROC
|
||||||
|
EXPORT SVC_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
DebugMon_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT DebugMon_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
PendSV_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT PendSV_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
SysTick_Handler\
|
||||||
|
PROC
|
||||||
|
EXPORT SysTick_Handler [WEAK]
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
Default_Handler PROC
|
||||||
|
; /* external interrupts handler */
|
||||||
|
EXPORT WWDGT_IRQHandler [WEAK]
|
||||||
|
EXPORT LVD_IRQHandler [WEAK]
|
||||||
|
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT FMC_IRQHandler [WEAK]
|
||||||
|
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI0_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI1_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI3_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT ADC_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER1_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER2_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER3_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI0_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART0_IRQHandler [WEAK]
|
||||||
|
EXPORT USART1_IRQHandler [WEAK]
|
||||||
|
EXPORT USART2_IRQHandler [WEAK]
|
||||||
|
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||||
|
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT EXMC_IRQHandler [WEAK]
|
||||||
|
EXPORT SDIO_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI2_IRQHandler [WEAK]
|
||||||
|
EXPORT UART3_IRQHandler [WEAK]
|
||||||
|
EXPORT UART4_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||||
|
EXPORT TIMER6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_IRQHandler [WEAK]
|
||||||
|
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||||
|
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||||
|
EXPORT USBFS_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||||
|
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||||
|
EXPORT USART5_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||||
|
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||||
|
EXPORT USBHS_IRQHandler [WEAK]
|
||||||
|
EXPORT DCI_IRQHandler [WEAK]
|
||||||
|
EXPORT TRNG_IRQHandler [WEAK]
|
||||||
|
EXPORT FPU_IRQHandler [WEAK]
|
||||||
|
EXPORT UART6_IRQHandler [WEAK]
|
||||||
|
EXPORT UART7_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI3_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI4_IRQHandler [WEAK]
|
||||||
|
EXPORT SPI5_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_IRQHandler [WEAK]
|
||||||
|
EXPORT TLI_ER_IRQHandler [WEAK]
|
||||||
|
EXPORT IPA_IRQHandler [WEAK]
|
||||||
|
|
||||||
|
;/* external interrupts handler */
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
LVD_IRQHandler
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
FMC_IRQHandler
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
ADC_IRQHandler
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
SPI0_IRQHandler
|
||||||
|
SPI1_IRQHandler
|
||||||
|
USART0_IRQHandler
|
||||||
|
USART1_IRQHandler
|
||||||
|
USART2_IRQHandler
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
EXMC_IRQHandler
|
||||||
|
SDIO_IRQHandler
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
SPI2_IRQHandler
|
||||||
|
UART3_IRQHandler
|
||||||
|
UART4_IRQHandler
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
ENET_IRQHandler
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
USBFS_IRQHandler
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
USART5_IRQHandler
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
USBHS_IRQHandler
|
||||||
|
DCI_IRQHandler
|
||||||
|
TRNG_IRQHandler
|
||||||
|
FPU_IRQHandler
|
||||||
|
UART6_IRQHandler
|
||||||
|
UART7_IRQHandler
|
||||||
|
SPI3_IRQHandler
|
||||||
|
SPI4_IRQHandler
|
||||||
|
SPI5_IRQHandler
|
||||||
|
TLI_IRQHandler
|
||||||
|
TLI_ER_IRQHandler
|
||||||
|
IPA_IRQHandler
|
||||||
|
|
||||||
|
B .
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
; user Initial Stack & Heap
|
||||||
|
|
||||||
|
IF :DEF:__MICROLIB
|
||||||
|
|
||||||
|
EXPORT __initial_sp
|
||||||
|
EXPORT __heap_base
|
||||||
|
EXPORT __heap_limit
|
||||||
|
|
||||||
|
ELSE
|
||||||
|
|
||||||
|
IMPORT __use_two_region_memory
|
||||||
|
EXPORT __user_initial_stackheap
|
||||||
|
|
||||||
|
__user_initial_stackheap PROC
|
||||||
|
LDR R0, = Heap_Mem
|
||||||
|
LDR R1, =(Stack_Mem + Stack_Size)
|
||||||
|
LDR R2, = (Heap_Mem + Heap_Size)
|
||||||
|
LDR R3, = Stack_Mem
|
||||||
|
BX LR
|
||||||
|
ENDP
|
||||||
|
|
||||||
|
ALIGN
|
||||||
|
|
||||||
|
ENDIF
|
||||||
|
|
||||||
|
END
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xE_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xG_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f405_407_xK_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f425_427_xE_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f425_427_xG_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f425_427_xK_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f450xE_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f450xG_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,179 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f450xI_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 2048K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 448K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f450xK_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f470xE_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f470xG_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f470xI_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 2048K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 704K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f470xK_flash.ld
|
||||||
|
\brief linker script file
|
||||||
|
|
||||||
|
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||||
|
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
* not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
/* memory map */
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||||
|
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||||
|
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||||
|
}
|
||||||
|
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||||
|
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||||
|
|
||||||
|
/* ISR vectors */
|
||||||
|
.vectors :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(.vectors))
|
||||||
|
. = ALIGN(4);
|
||||||
|
__Vectors_End = .;
|
||||||
|
__Vectors_Size = __Vectors_End - __gVectors;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* text section, such as program code */
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text*)
|
||||||
|
*(.glue_7)
|
||||||
|
*(.glue_7t)
|
||||||
|
*(.eh_frame)
|
||||||
|
KEEP (*(.init))
|
||||||
|
KEEP (*(.fini))
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_etext' will be defined at the end of code section */
|
||||||
|
_etext = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ro-data section, such as constant data */
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table */
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* exception process table index */
|
||||||
|
.ARM :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* ARM attributes */
|
||||||
|
.ARM.attributes :
|
||||||
|
{
|
||||||
|
*(.ARM.attributes)
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array*))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT(.init_array.*)))
|
||||||
|
KEEP (*(.init_array*))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(.fini_array*))
|
||||||
|
KEEP (*(SORT(.fini_array.*)))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for initialized data */
|
||||||
|
_sidata = LOADADDR(.data);
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sdata' will be defined at the data section end start */
|
||||||
|
_sdata = .;
|
||||||
|
*(.data)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_edata' will be defined at the data section end */
|
||||||
|
_edata = .;
|
||||||
|
} > RAM AT> FLASH
|
||||||
|
|
||||||
|
/* provide some necessary symbols for uninitialized data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_sbss' will be defined at the bss section start */
|
||||||
|
_sbss = .;
|
||||||
|
__bss_start__ = _sbss;
|
||||||
|
*(.bss)
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* the symbol '_ebss' will be defined at the bss section end */
|
||||||
|
_ebss = .;
|
||||||
|
__bss_end__ = _ebss;
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* heap and stack space */
|
||||||
|
.heap_stack :
|
||||||
|
{
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE ( end = _ebss );
|
||||||
|
PROVIDE ( _end = _ebss );
|
||||||
|
. = . + __heap_size;
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _sp = . );
|
||||||
|
. = ALIGN(8);
|
||||||
|
} > RAM
|
||||||
|
|
||||||
|
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||||
|
_sitcmram = LOADADDR(.tcmram);
|
||||||
|
.tcmram :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
.stcmram = .;
|
||||||
|
*(.tcmram)
|
||||||
|
*(.tcmram*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
_etcmram = .;
|
||||||
|
} > TCMRAM AT> FLASH
|
||||||
|
}
|
||||||
|
|
||||||
|
/* input sections */
|
||||||
|
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||||
|
|
||||||
@@ -0,0 +1,191 @@
|
|||||||
|
/*!
|
||||||
|
\file syscall.c
|
||||||
|
\brief system calls file
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <_ansi.h>
|
||||||
|
#include <sys/types.h>
|
||||||
|
#include <sys/stat.h>
|
||||||
|
#include <sys/fcntl.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <time.h>
|
||||||
|
#include <sys/time.h>
|
||||||
|
#include <sys/times.h>
|
||||||
|
#include <errno.h>
|
||||||
|
#include <reent.h>
|
||||||
|
#include <unistd.h>
|
||||||
|
#include <sys/wait.h>
|
||||||
|
|
||||||
|
#undef errno
|
||||||
|
extern int errno;
|
||||||
|
|
||||||
|
extern int __io_putchar(int ch) __attribute__((weak));
|
||||||
|
extern int __io_getchar(void) __attribute__((weak));
|
||||||
|
|
||||||
|
caddr_t _sbrk(int incr)
|
||||||
|
{
|
||||||
|
extern char _end[];
|
||||||
|
extern char _heap_end[];
|
||||||
|
static char *curbrk = _end;
|
||||||
|
|
||||||
|
if((curbrk + incr < _end) || (curbrk + incr > _heap_end)) {
|
||||||
|
return NULL - 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
curbrk += incr;
|
||||||
|
return curbrk - incr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _gettimeofday primitive (Stub function)
|
||||||
|
* */
|
||||||
|
int _gettimeofday (struct timeval * tp, struct timezone * tzp)
|
||||||
|
{
|
||||||
|
/* Return fixed data for the timezone. */
|
||||||
|
if(tzp) {
|
||||||
|
tzp->tz_minuteswest = 0;
|
||||||
|
tzp->tz_dsttime = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
void initialise_monitor_handles()
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
int _getpid(void)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _kill(int pid, int sig)
|
||||||
|
{
|
||||||
|
errno = EINVAL;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void _exit (int status)
|
||||||
|
{
|
||||||
|
_kill(status, -1);
|
||||||
|
while(1) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int _write(int file, char *ptr, int len)
|
||||||
|
{
|
||||||
|
int DataIdx;
|
||||||
|
|
||||||
|
for(DataIdx = 0; DataIdx < len; DataIdx++) {
|
||||||
|
__io_putchar(*ptr++);
|
||||||
|
}
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _close(int file)
|
||||||
|
{
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _fstat(int file, struct stat *st)
|
||||||
|
{
|
||||||
|
st->st_mode = S_IFCHR;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _isatty(int file)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _lseek(int file, int ptr, int dir)
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _read(int file, char *ptr, int len)
|
||||||
|
{
|
||||||
|
int DataIdx;
|
||||||
|
|
||||||
|
for(DataIdx = 0; DataIdx < len; DataIdx++) {
|
||||||
|
*ptr++ = __io_getchar();
|
||||||
|
}
|
||||||
|
|
||||||
|
return len;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _open(char *path, int flags, ...)
|
||||||
|
{
|
||||||
|
/* Pretend like we always fail */
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _wait(int *status)
|
||||||
|
{
|
||||||
|
errno = ECHILD;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _unlink(char *name)
|
||||||
|
{
|
||||||
|
errno = ENOENT;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _times(struct tms *buf)
|
||||||
|
{
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _stat(char *file, struct stat *st)
|
||||||
|
{
|
||||||
|
st->st_mode = S_IFCHR;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _link(char *old, char *new)
|
||||||
|
{
|
||||||
|
errno = EMLINK;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _fork(void)
|
||||||
|
{
|
||||||
|
errno = EAGAIN;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
int _execve(char *name, char **argv, char **env)
|
||||||
|
{
|
||||||
|
errno = ENOMEM;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
@@ -0,0 +1,454 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.S
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||||
|
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
; * SPDX-License-Identifier: Apache-2.0
|
||||||
|
; *
|
||||||
|
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
; * not use this file except in compliance with the License.
|
||||||
|
; * You may obtain a copy of the License at
|
||||||
|
; *
|
||||||
|
; * www.apache.org/licenses/LICENSE-2.0
|
||||||
|
; *
|
||||||
|
; * Unless required by applicable law or agreed to in writing, software
|
||||||
|
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
; * See the License for the specific language governing permissions and
|
||||||
|
; * limitations under the License.
|
||||||
|
; */
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* necessary symbols defined in linker script to initialize data */
|
||||||
|
.word _sidata
|
||||||
|
.word _sdata
|
||||||
|
.word _edata
|
||||||
|
.word _sbss
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
|
||||||
|
/* reset Handler */
|
||||||
|
Reset_Handler:
|
||||||
|
movs r1, #0
|
||||||
|
b DataInit
|
||||||
|
|
||||||
|
CopyData:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
DataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyData
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b Zerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
Zerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call SystemInit function */
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/*Call the main function */
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
.section .vectors,"a",%progbits
|
||||||
|
.global __gVectors
|
||||||
|
|
||||||
|
__gVectors:
|
||||||
|
.word _sp /* Top of Stack */
|
||||||
|
.word Reset_Handler /* Reset Handler */
|
||||||
|
.word NMI_Handler /* NMI Handler */
|
||||||
|
.word HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.word MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.word BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.word UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SVC_Handler /* SVCall Handler */
|
||||||
|
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word PendSV_Handler /* PendSV Handler */
|
||||||
|
.word SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts handler */
|
||||||
|
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||||
|
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||||
|
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||||
|
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||||
|
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||||
|
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||||
|
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||||
|
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||||
|
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||||
|
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||||
|
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||||
|
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||||
|
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||||
|
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||||
|
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||||
|
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||||
|
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||||
|
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||||
|
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||||
|
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||||
|
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||||
|
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||||
|
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||||
|
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */
|
||||||
|
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||||
|
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||||
|
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||||
|
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||||
|
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||||
|
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||||
|
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||||
|
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||||
|
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||||
|
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||||
|
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||||
|
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||||
|
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||||
|
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||||
|
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||||
|
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||||
|
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||||
|
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
|
||||||
|
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||||
|
.word 0 /* Vector Number 64,Reserved */
|
||||||
|
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||||
|
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||||
|
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||||
|
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||||
|
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||||
|
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||||
|
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||||
|
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||||
|
.word 0 /* Vector Number 77,Reserved */
|
||||||
|
.word 0 /* Vector Number 78,Reserved */
|
||||||
|
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||||
|
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||||
|
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||||
|
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||||
|
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||||
|
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||||
|
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||||
|
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||||
|
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||||
|
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||||
|
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||||
|
.word 0 /* Vector Number 95,Reserved */
|
||||||
|
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||||
|
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||||
|
|
||||||
|
.size __gVectors, . - __gVectors
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDGT_IRQHandler
|
||||||
|
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LVD_IRQHandler
|
||||||
|
.thumb_set LVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCU_CTC_IRQHandler
|
||||||
|
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_TX_IRQHandler
|
||||||
|
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX0_IRQHandler
|
||||||
|
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX1_IRQHandler
|
||||||
|
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI5_9_IRQHandler
|
||||||
|
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER1_IRQHandler
|
||||||
|
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER2_IRQHandler
|
||||||
|
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER3_IRQHandler
|
||||||
|
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_EV_IRQHandler
|
||||||
|
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_ER_IRQHandler
|
||||||
|
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI0_IRQHandler
|
||||||
|
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART0_IRQHandler
|
||||||
|
.thumb_set USART0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI10_15_IRQHandler
|
||||||
|
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER4_IRQHandler
|
||||||
|
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART3_IRQHandler
|
||||||
|
.thumb_set UART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER5_DAC_IRQHandler
|
||||||
|
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER6_IRQHandler
|
||||||
|
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_IRQHandler
|
||||||
|
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART5_IRQHandler
|
||||||
|
.thumb_set USART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_Out_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_In_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_IRQHandler
|
||||||
|
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCI_IRQHandler
|
||||||
|
.thumb_set DCI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TRNG_IRQHandler
|
||||||
|
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
@@ -0,0 +1,463 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f407_427.S
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||||
|
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
; * SPDX-License-Identifier: Apache-2.0
|
||||||
|
; *
|
||||||
|
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
; * not use this file except in compliance with the License.
|
||||||
|
; * You may obtain a copy of the License at
|
||||||
|
; *
|
||||||
|
; * www.apache.org/licenses/LICENSE-2.0
|
||||||
|
; *
|
||||||
|
; * Unless required by applicable law or agreed to in writing, software
|
||||||
|
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
; * See the License for the specific language governing permissions and
|
||||||
|
; * limitations under the License.
|
||||||
|
; */
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* necessary symbols defined in linker script to initialize data */
|
||||||
|
.word _sidata
|
||||||
|
.word _sdata
|
||||||
|
.word _edata
|
||||||
|
.word _sbss
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
|
||||||
|
/* reset Handler */
|
||||||
|
Reset_Handler:
|
||||||
|
movs r1, #0
|
||||||
|
b DataInit
|
||||||
|
|
||||||
|
CopyData:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
DataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyData
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b Zerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
Zerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call SystemInit function */
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/*Call the main function */
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
.section .vectors,"a",%progbits
|
||||||
|
.global __gVectors
|
||||||
|
|
||||||
|
__gVectors:
|
||||||
|
.word _sp /* Top of Stack */
|
||||||
|
.word Reset_Handler /* Reset Handler */
|
||||||
|
.word NMI_Handler /* NMI Handler */
|
||||||
|
.word HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.word MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.word BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.word UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SVC_Handler /* SVCall Handler */
|
||||||
|
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word PendSV_Handler /* PendSV Handler */
|
||||||
|
.word SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts handler */
|
||||||
|
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||||
|
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||||
|
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||||
|
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||||
|
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||||
|
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||||
|
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||||
|
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||||
|
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||||
|
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||||
|
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||||
|
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||||
|
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||||
|
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||||
|
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||||
|
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||||
|
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||||
|
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||||
|
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||||
|
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||||
|
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||||
|
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||||
|
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||||
|
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */
|
||||||
|
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||||
|
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||||
|
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||||
|
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||||
|
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||||
|
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||||
|
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||||
|
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||||
|
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||||
|
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||||
|
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||||
|
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||||
|
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||||
|
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||||
|
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||||
|
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||||
|
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||||
|
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Capture Compare */
|
||||||
|
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||||
|
.word EXMC_IRQHandler /* Vector Number 64,EXMC */
|
||||||
|
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||||
|
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||||
|
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||||
|
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||||
|
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||||
|
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||||
|
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||||
|
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||||
|
.word ENET_IRQHandler /* Vector Number 77,Ethernet */
|
||||||
|
.word ENET_WKUP_IRQHandler /* Vector Number 78,Ethernet Wakeup through EXTI Line */
|
||||||
|
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||||
|
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||||
|
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||||
|
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||||
|
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||||
|
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||||
|
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||||
|
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||||
|
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||||
|
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||||
|
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||||
|
.word 0 /* Vector Number 95,Reserved */
|
||||||
|
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||||
|
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||||
|
|
||||||
|
.size __gVectors, . - __gVectors
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDGT_IRQHandler
|
||||||
|
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LVD_IRQHandler
|
||||||
|
.thumb_set LVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCU_CTC_IRQHandler
|
||||||
|
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_TX_IRQHandler
|
||||||
|
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX0_IRQHandler
|
||||||
|
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX1_IRQHandler
|
||||||
|
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI5_9_IRQHandler
|
||||||
|
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER1_IRQHandler
|
||||||
|
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER2_IRQHandler
|
||||||
|
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER3_IRQHandler
|
||||||
|
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_EV_IRQHandler
|
||||||
|
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_ER_IRQHandler
|
||||||
|
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI0_IRQHandler
|
||||||
|
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART0_IRQHandler
|
||||||
|
.thumb_set USART0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI10_15_IRQHandler
|
||||||
|
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXMC_IRQHandler
|
||||||
|
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER4_IRQHandler
|
||||||
|
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART3_IRQHandler
|
||||||
|
.thumb_set UART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER5_DAC_IRQHandler
|
||||||
|
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER6_IRQHandler
|
||||||
|
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ENET_IRQHandler
|
||||||
|
.thumb_set ENET_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ENET_WKUP_IRQHandler
|
||||||
|
.thumb_set ENET_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_IRQHandler
|
||||||
|
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART5_IRQHandler
|
||||||
|
.thumb_set USART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_Out_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_In_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_IRQHandler
|
||||||
|
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCI_IRQHandler
|
||||||
|
.thumb_set DCI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TRNG_IRQHandler
|
||||||
|
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
@@ -0,0 +1,496 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.S
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||||
|
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
; * SPDX-License-Identifier: Apache-2.0
|
||||||
|
; *
|
||||||
|
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
; * not use this file except in compliance with the License.
|
||||||
|
; * You may obtain a copy of the License at
|
||||||
|
; *
|
||||||
|
; * www.apache.org/licenses/LICENSE-2.0
|
||||||
|
; *
|
||||||
|
; * Unless required by applicable law or agreed to in writing, software
|
||||||
|
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
; * See the License for the specific language governing permissions and
|
||||||
|
; * limitations under the License.
|
||||||
|
; */
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* necessary symbols defined in linker script to initialize data */
|
||||||
|
.word _sidata
|
||||||
|
.word _sdata
|
||||||
|
.word _edata
|
||||||
|
.word _sbss
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
|
||||||
|
/* reset Handler */
|
||||||
|
Reset_Handler:
|
||||||
|
movs r1, #0
|
||||||
|
b DataInit
|
||||||
|
|
||||||
|
CopyData:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
DataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyData
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b Zerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
Zerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call SystemInit function */
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/*Call the main function */
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
.section .vectors,"a",%progbits
|
||||||
|
.global __gVectors
|
||||||
|
|
||||||
|
__gVectors:
|
||||||
|
.word _sp /* Top of Stack */
|
||||||
|
.word Reset_Handler /* Reset Handler */
|
||||||
|
.word NMI_Handler /* NMI Handler */
|
||||||
|
.word HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.word MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.word BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.word UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SVC_Handler /* SVCall Handler */
|
||||||
|
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word PendSV_Handler /* PendSV Handler */
|
||||||
|
.word SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts handler */
|
||||||
|
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||||
|
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||||
|
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||||
|
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||||
|
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||||
|
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||||
|
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||||
|
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||||
|
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||||
|
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||||
|
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||||
|
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||||
|
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||||
|
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||||
|
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||||
|
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||||
|
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||||
|
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||||
|
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||||
|
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||||
|
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||||
|
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||||
|
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||||
|
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Capture Compare */
|
||||||
|
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||||
|
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||||
|
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||||
|
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||||
|
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||||
|
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||||
|
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||||
|
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||||
|
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||||
|
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||||
|
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||||
|
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||||
|
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||||
|
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||||
|
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||||
|
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||||
|
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||||
|
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
|
||||||
|
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||||
|
.word EXMC_IRQHandler /* Vector Number 64,EXMC */
|
||||||
|
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||||
|
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||||
|
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||||
|
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||||
|
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||||
|
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||||
|
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||||
|
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||||
|
.word ENET_IRQHandler /* Vector Number 77,Ethernet */
|
||||||
|
.word ENET_WKUP_IRQHandler /* Vector Number 78,Ethernet Wakeup through EXTI Line */
|
||||||
|
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||||
|
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||||
|
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||||
|
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||||
|
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||||
|
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||||
|
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||||
|
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||||
|
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||||
|
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||||
|
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||||
|
.word 0 /* Vector Number 95,Reserved */
|
||||||
|
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||||
|
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||||
|
.word UART6_IRQHandler /* Vector Number 98,UART6 */
|
||||||
|
.word UART7_IRQHandler /* Vector Number 99,UART7 */
|
||||||
|
.word SPI3_IRQHandler /* Vector Number 100,SPI3 */
|
||||||
|
.word SPI4_IRQHandler /* Vector Number 101,SPI4 */
|
||||||
|
.word SPI5_IRQHandler /* Vector Number 102,SPI5 */
|
||||||
|
.word 0 /* Vector Number 103,Reserved */
|
||||||
|
.word TLI_IRQHandler /* Vector Number 104,TLI */
|
||||||
|
.word TLI_ER_IRQHandler /* Vector Number 105,TLI Error */
|
||||||
|
.word IPA_IRQHandler /* Vector Number 106,IPA */
|
||||||
|
|
||||||
|
.size __gVectors, . - __gVectors
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDGT_IRQHandler
|
||||||
|
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LVD_IRQHandler
|
||||||
|
.thumb_set LVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCU_CTC_IRQHandler
|
||||||
|
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_TX_IRQHandler
|
||||||
|
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX0_IRQHandler
|
||||||
|
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX1_IRQHandler
|
||||||
|
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI5_9_IRQHandler
|
||||||
|
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER1_IRQHandler
|
||||||
|
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER2_IRQHandler
|
||||||
|
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER3_IRQHandler
|
||||||
|
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_EV_IRQHandler
|
||||||
|
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_ER_IRQHandler
|
||||||
|
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI0_IRQHandler
|
||||||
|
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART0_IRQHandler
|
||||||
|
.thumb_set USART0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI10_15_IRQHandler
|
||||||
|
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXMC_IRQHandler
|
||||||
|
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER4_IRQHandler
|
||||||
|
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART3_IRQHandler
|
||||||
|
.thumb_set UART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER5_DAC_IRQHandler
|
||||||
|
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER6_IRQHandler
|
||||||
|
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ENET_IRQHandler
|
||||||
|
.thumb_set ENET_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ENET_WKUP_IRQHandler
|
||||||
|
.thumb_set ENET_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_IRQHandler
|
||||||
|
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART5_IRQHandler
|
||||||
|
.thumb_set USART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_Out_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_In_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_IRQHandler
|
||||||
|
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCI_IRQHandler
|
||||||
|
.thumb_set DCI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TRNG_IRQHandler
|
||||||
|
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART6_IRQHandler
|
||||||
|
.thumb_set UART6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART7_IRQHandler
|
||||||
|
.thumb_set UART7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI3_IRQHandler
|
||||||
|
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI4_IRQHandler
|
||||||
|
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI5_IRQHandler
|
||||||
|
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TLI_IRQHandler
|
||||||
|
.thumb_set TLI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TLI_ER_IRQHandler
|
||||||
|
.thumb_set TLI_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak IPA_IRQHandler
|
||||||
|
.thumb_set IPA_IRQHandler,Default_Handler
|
||||||
@@ -0,0 +1,602 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD 0 ; 64:Reserved
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD 0 ; 77:Reserved
|
||||||
|
DCD 0 ; 78:Reserved
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
@@ -0,0 +1,617 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f407_427.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXMC_IRQHandler
|
||||||
|
B EXMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_IRQHandler
|
||||||
|
B ENET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
B ENET_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
END
|
||||||
@@ -0,0 +1,666 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f450_470.s
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/* Copyright (c) 2012 ARM LIMITED
|
||||||
|
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
;
|
||||||
|
; All rights reserved.
|
||||||
|
; Redistribution and use in source and binary forms, with or without
|
||||||
|
; modification, are permitted provided that the following conditions are met:
|
||||||
|
; - Redistributions of source code must retain the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer.
|
||||||
|
; - Redistributions in binary form must reproduce the above copyright
|
||||||
|
; notice, this list of conditions and the following disclaimer in the
|
||||||
|
; documentation and/or other materials provided with the distribution.
|
||||||
|
; - Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
; to endorse or promote products derived from this software without
|
||||||
|
; specific prior written permission.
|
||||||
|
; *
|
||||||
|
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
; POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
; ---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
MODULE ?cstartup
|
||||||
|
|
||||||
|
;; Forward declaration of sections.
|
||||||
|
SECTION CSTACK:DATA:NOROOT(3)
|
||||||
|
|
||||||
|
SECTION .intvec:CODE:NOROOT(2)
|
||||||
|
|
||||||
|
EXTERN __iar_program_start
|
||||||
|
EXTERN SystemInit
|
||||||
|
PUBLIC __vector_table
|
||||||
|
|
||||||
|
DATA
|
||||||
|
__vector_table
|
||||||
|
DCD sfe(CSTACK) ; top of stack
|
||||||
|
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||||
|
|
||||||
|
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||||
|
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||||
|
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||||
|
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||||
|
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||||
|
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||||
|
DCD 0 ; Reserved
|
||||||
|
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||||
|
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||||
|
|
||||||
|
; External Interrupts
|
||||||
|
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||||
|
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||||
|
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||||
|
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||||
|
DCD FMC_IRQHandler ; 20:FMC
|
||||||
|
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||||
|
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||||
|
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||||
|
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||||
|
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||||
|
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||||
|
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||||
|
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||||
|
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||||
|
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||||
|
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||||
|
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||||
|
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||||
|
DCD ADC_IRQHandler ; 34:ADC
|
||||||
|
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||||
|
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||||
|
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||||
|
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||||
|
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||||
|
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||||
|
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||||
|
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||||
|
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||||
|
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||||
|
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||||
|
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||||
|
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||||
|
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||||
|
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||||
|
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||||
|
DCD SPI0_IRQHandler ; 51:SPI0
|
||||||
|
DCD SPI1_IRQHandler ; 52:SPI1
|
||||||
|
DCD USART0_IRQHandler ; 53:USART0
|
||||||
|
DCD USART1_IRQHandler ; 54:USART1
|
||||||
|
DCD USART2_IRQHandler ; 55:USART2
|
||||||
|
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||||
|
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||||
|
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||||
|
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||||
|
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||||
|
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||||
|
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||||
|
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||||
|
DCD EXMC_IRQHandler ; 64:EXMC
|
||||||
|
DCD SDIO_IRQHandler ; 65:SDIO
|
||||||
|
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||||
|
DCD SPI2_IRQHandler ; 67:SPI2
|
||||||
|
DCD UART3_IRQHandler ; 68:UART3
|
||||||
|
DCD UART4_IRQHandler ; 69:UART4
|
||||||
|
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||||
|
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||||
|
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||||
|
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||||
|
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||||
|
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||||
|
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||||
|
DCD ENET_IRQHandler ; 77:Ethernet
|
||||||
|
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||||
|
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||||
|
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||||
|
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||||
|
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||||
|
DCD USBFS_IRQHandler ; 83:USBFS
|
||||||
|
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||||
|
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||||
|
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||||
|
DCD USART5_IRQHandler ; 87:USART5
|
||||||
|
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||||
|
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||||
|
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||||
|
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||||
|
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||||
|
DCD USBHS_IRQHandler ; 93:USBHS
|
||||||
|
DCD DCI_IRQHandler ; 94:DCI
|
||||||
|
DCD 0 ; 95:Reserved
|
||||||
|
DCD TRNG_IRQHandler ; 96:TRNG
|
||||||
|
DCD FPU_IRQHandler ; 97:FPU
|
||||||
|
DCD UART6_IRQHandler ; 98:UART6
|
||||||
|
DCD UART7_IRQHandler ; 99:UART7
|
||||||
|
DCD SPI3_IRQHandler ; 100:SPI3
|
||||||
|
DCD SPI4_IRQHandler ; 101:SPI4
|
||||||
|
DCD SPI5_IRQHandler ; 102:SPI5
|
||||||
|
DCD 0 ; 103:Reserved
|
||||||
|
DCD TLI_IRQHandler ; 104:TLI
|
||||||
|
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||||
|
DCD IPA_IRQHandler ; 106:IPA
|
||||||
|
|
||||||
|
|
||||||
|
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||||
|
;;
|
||||||
|
;; Default interrupt handlers.
|
||||||
|
;;
|
||||||
|
THUMB
|
||||||
|
|
||||||
|
PUBWEAK Reset_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||||
|
Reset_Handler
|
||||||
|
LDR R0, =SystemInit
|
||||||
|
BLX R0
|
||||||
|
LDR R0, =__iar_program_start
|
||||||
|
BX R0
|
||||||
|
|
||||||
|
PUBWEAK NMI_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
NMI_Handler
|
||||||
|
B NMI_Handler
|
||||||
|
|
||||||
|
PUBWEAK HardFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
HardFault_Handler
|
||||||
|
B HardFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK MemManage_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
MemManage_Handler
|
||||||
|
B MemManage_Handler
|
||||||
|
|
||||||
|
PUBWEAK BusFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
BusFault_Handler
|
||||||
|
B BusFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK UsageFault_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UsageFault_Handler
|
||||||
|
B UsageFault_Handler
|
||||||
|
|
||||||
|
PUBWEAK SVC_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SVC_Handler
|
||||||
|
B SVC_Handler
|
||||||
|
|
||||||
|
PUBWEAK DebugMon_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DebugMon_Handler
|
||||||
|
B DebugMon_Handler
|
||||||
|
|
||||||
|
PUBWEAK PendSV_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
PendSV_Handler
|
||||||
|
B PendSV_Handler
|
||||||
|
|
||||||
|
PUBWEAK SysTick_Handler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SysTick_Handler
|
||||||
|
B SysTick_Handler
|
||||||
|
|
||||||
|
PUBWEAK WWDGT_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
WWDGT_IRQHandler
|
||||||
|
B WWDGT_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK LVD_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
LVD_IRQHandler
|
||||||
|
B LVD_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TAMPER_STAMP_IRQHandler
|
||||||
|
B TAMPER_STAMP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_WKUP_IRQHandler
|
||||||
|
B RTC_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FMC_IRQHandler
|
||||||
|
B FMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RCU_CTC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RCU_CTC_IRQHandler
|
||||||
|
B RCU_CTC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI0_IRQHandler
|
||||||
|
B EXTI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI1_IRQHandler
|
||||||
|
B EXTI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI2_IRQHandler
|
||||||
|
B EXTI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI3_IRQHandler
|
||||||
|
B EXTI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI4_IRQHandler
|
||||||
|
B EXTI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel0_IRQHandler
|
||||||
|
B DMA0_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel1_IRQHandler
|
||||||
|
B DMA0_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel2_IRQHandler
|
||||||
|
B DMA0_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel3_IRQHandler
|
||||||
|
B DMA0_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel4_IRQHandler
|
||||||
|
B DMA0_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel5_IRQHandler
|
||||||
|
B DMA0_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel6_IRQHandler
|
||||||
|
B DMA0_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ADC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ADC_IRQHandler
|
||||||
|
B ADC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_TX_IRQHandler
|
||||||
|
B CAN0_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX0_IRQHandler
|
||||||
|
B CAN0_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_RX1_IRQHandler
|
||||||
|
B CAN0_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN0_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN0_EWMC_IRQHandler
|
||||||
|
B CAN0_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI5_9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI5_9_IRQHandler
|
||||||
|
B EXTI5_9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
B TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
B TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER0_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER0_Channel_IRQHandler
|
||||||
|
B TIMER0_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER1_IRQHandler
|
||||||
|
B TIMER1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER2_IRQHandler
|
||||||
|
B TIMER2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER3_IRQHandler
|
||||||
|
B TIMER3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_EV_IRQHandler
|
||||||
|
B I2C0_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C0_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C0_ER_IRQHandler
|
||||||
|
B I2C0_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_EV_IRQHandler
|
||||||
|
B I2C1_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C1_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C1_ER_IRQHandler
|
||||||
|
B I2C1_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI0_IRQHandler
|
||||||
|
B SPI0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI1_IRQHandler
|
||||||
|
B SPI1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART0_IRQHandler
|
||||||
|
B USART0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART1_IRQHandler
|
||||||
|
B USART1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART2_IRQHandler
|
||||||
|
B USART2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXTI10_15_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXTI10_15_IRQHandler
|
||||||
|
B EXTI10_15_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK RTC_Alarm_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
RTC_Alarm_IRQHandler
|
||||||
|
B RTC_Alarm_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_WKUP_IRQHandler
|
||||||
|
B USBFS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
B TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
B TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER7_Channel_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER7_Channel_IRQHandler
|
||||||
|
B TIMER7_Channel_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA0_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA0_Channel7_IRQHandler
|
||||||
|
B DMA0_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK EXMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
EXMC_IRQHandler
|
||||||
|
B EXMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SDIO_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SDIO_IRQHandler
|
||||||
|
B SDIO_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER4_IRQHandler
|
||||||
|
B TIMER4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI2_IRQHandler
|
||||||
|
B SPI2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART3_IRQHandler
|
||||||
|
B UART3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART4_IRQHandler
|
||||||
|
B UART4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER5_DAC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER5_DAC_IRQHandler
|
||||||
|
B TIMER5_DAC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TIMER6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TIMER6_IRQHandler
|
||||||
|
B TIMER6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel0_IRQHandler
|
||||||
|
B DMA1_Channel0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel1_IRQHandler
|
||||||
|
B DMA1_Channel1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel2_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel2_IRQHandler
|
||||||
|
B DMA1_Channel2_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel3_IRQHandler
|
||||||
|
B DMA1_Channel3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel4_IRQHandler
|
||||||
|
B DMA1_Channel4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_IRQHandler
|
||||||
|
B ENET_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK ENET_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
ENET_WKUP_IRQHandler
|
||||||
|
B ENET_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_TX_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_TX_IRQHandler
|
||||||
|
B CAN1_TX_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX0_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX0_IRQHandler
|
||||||
|
B CAN1_RX0_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_RX1_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_RX1_IRQHandler
|
||||||
|
B CAN1_RX1_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK CAN1_EWMC_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
CAN1_EWMC_IRQHandler
|
||||||
|
B CAN1_EWMC_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBFS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBFS_IRQHandler
|
||||||
|
B USBFS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel5_IRQHandler
|
||||||
|
B DMA1_Channel5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel6_IRQHandler
|
||||||
|
B DMA1_Channel6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DMA1_Channel7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DMA1_Channel7_IRQHandler
|
||||||
|
B DMA1_Channel7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USART5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USART5_IRQHandler
|
||||||
|
B USART5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_EV_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_EV_IRQHandler
|
||||||
|
B I2C2_EV_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK I2C2_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
I2C2_ER_IRQHandler
|
||||||
|
B I2C2_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_Out_IRQHandler
|
||||||
|
B USBHS_EP1_Out_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_EP1_In_IRQHandler
|
||||||
|
B USBHS_EP1_In_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_WKUP_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_WKUP_IRQHandler
|
||||||
|
B USBHS_WKUP_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK USBHS_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
USBHS_IRQHandler
|
||||||
|
B USBHS_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK DCI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
DCI_IRQHandler
|
||||||
|
B DCI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TRNG_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TRNG_IRQHandler
|
||||||
|
B TRNG_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK FPU_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
FPU_IRQHandler
|
||||||
|
B FPU_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART6_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART6_IRQHandler
|
||||||
|
B UART6_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK UART7_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
UART7_IRQHandler
|
||||||
|
B UART7_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI3_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI3_IRQHandler
|
||||||
|
B SPI3_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI4_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI4_IRQHandler
|
||||||
|
B SPI4_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK SPI5_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
SPI5_IRQHandler
|
||||||
|
B SPI5_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TLI_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TLI_IRQHandler
|
||||||
|
B TLI_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK TLI_ER_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
TLI_ER_IRQHandler
|
||||||
|
B TLI_ER_IRQHandler
|
||||||
|
|
||||||
|
PUBWEAK IPA_IRQHandler
|
||||||
|
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||||
|
IPA_IRQHandler
|
||||||
|
B IPA_IRQHandler
|
||||||
|
END
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,697 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cm4_simd.h
|
||||||
|
* @brief CMSIS Cortex-M4 SIMD Header File
|
||||||
|
* @version V3.30
|
||||||
|
* @date 17. February 2014
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
/* Copyright (c) 2009 - 2014 ARM LIMITED
|
||||||
|
|
||||||
|
All rights reserved.
|
||||||
|
Redistribution and use in source and binary forms, with or without
|
||||||
|
modification, are permitted provided that the following conditions are met:
|
||||||
|
- Redistributions of source code must retain the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer.
|
||||||
|
- Redistributions in binary form must reproduce the above copyright
|
||||||
|
notice, this list of conditions and the following disclaimer in the
|
||||||
|
documentation and/or other materials provided with the distribution.
|
||||||
|
- Neither the name of ARM nor the names of its contributors may be used
|
||||||
|
to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
*
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||||
|
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||||
|
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||||
|
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
---------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
#if defined ( __ICCARM__ )
|
||||||
|
#pragma system_include /* treat file as system include file for MISRA check */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef __CORE_CM4_SIMD_H
|
||||||
|
#define __CORE_CM4_SIMD_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* Hardware Abstraction Layer
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
|
||||||
|
/* ################### Compiler specific Intrinsics ########################### */
|
||||||
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||||
|
Access to dedicated SIMD instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
#define __SADD8 __sadd8
|
||||||
|
#define __QADD8 __qadd8
|
||||||
|
#define __SHADD8 __shadd8
|
||||||
|
#define __UADD8 __uadd8
|
||||||
|
#define __UQADD8 __uqadd8
|
||||||
|
#define __UHADD8 __uhadd8
|
||||||
|
#define __SSUB8 __ssub8
|
||||||
|
#define __QSUB8 __qsub8
|
||||||
|
#define __SHSUB8 __shsub8
|
||||||
|
#define __USUB8 __usub8
|
||||||
|
#define __UQSUB8 __uqsub8
|
||||||
|
#define __UHSUB8 __uhsub8
|
||||||
|
#define __SADD16 __sadd16
|
||||||
|
#define __QADD16 __qadd16
|
||||||
|
#define __SHADD16 __shadd16
|
||||||
|
#define __UADD16 __uadd16
|
||||||
|
#define __UQADD16 __uqadd16
|
||||||
|
#define __UHADD16 __uhadd16
|
||||||
|
#define __SSUB16 __ssub16
|
||||||
|
#define __QSUB16 __qsub16
|
||||||
|
#define __SHSUB16 __shsub16
|
||||||
|
#define __USUB16 __usub16
|
||||||
|
#define __UQSUB16 __uqsub16
|
||||||
|
#define __UHSUB16 __uhsub16
|
||||||
|
#define __SASX __sasx
|
||||||
|
#define __QASX __qasx
|
||||||
|
#define __SHASX __shasx
|
||||||
|
#define __UASX __uasx
|
||||||
|
#define __UQASX __uqasx
|
||||||
|
#define __UHASX __uhasx
|
||||||
|
#define __SSAX __ssax
|
||||||
|
#define __QSAX __qsax
|
||||||
|
#define __SHSAX __shsax
|
||||||
|
#define __USAX __usax
|
||||||
|
#define __UQSAX __uqsax
|
||||||
|
#define __UHSAX __uhsax
|
||||||
|
#define __USAD8 __usad8
|
||||||
|
#define __USADA8 __usada8
|
||||||
|
#define __SSAT16 __ssat16
|
||||||
|
#define __USAT16 __usat16
|
||||||
|
#define __UXTB16 __uxtb16
|
||||||
|
#define __UXTAB16 __uxtab16
|
||||||
|
#define __SXTB16 __sxtb16
|
||||||
|
#define __SXTAB16 __sxtab16
|
||||||
|
#define __SMUAD __smuad
|
||||||
|
#define __SMUADX __smuadx
|
||||||
|
#define __SMLAD __smlad
|
||||||
|
#define __SMLADX __smladx
|
||||||
|
#define __SMLALD __smlald
|
||||||
|
#define __SMLALDX __smlaldx
|
||||||
|
#define __SMUSD __smusd
|
||||||
|
#define __SMUSDX __smusdx
|
||||||
|
#define __SMLSD __smlsd
|
||||||
|
#define __SMLSDX __smlsdx
|
||||||
|
#define __SMLSLD __smlsld
|
||||||
|
#define __SMLSLDX __smlsldx
|
||||||
|
#define __SEL __sel
|
||||||
|
#define __QADD __qadd
|
||||||
|
#define __QSUB __qsub
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||||
|
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||||
|
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||||
|
|
||||||
|
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||||
|
((int64_t)(ARG3) << 32) ) >> 32))
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __SSAT16(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __USAT16(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||||
|
{
|
||||||
|
union llreg_u{
|
||||||
|
uint32_t w32[2];
|
||||||
|
uint64_t w64;
|
||||||
|
} llr;
|
||||||
|
llr.w64 = acc;
|
||||||
|
|
||||||
|
#ifndef __ARMEB__ // Little endian
|
||||||
|
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||||
|
#else // Big endian
|
||||||
|
__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return(llr.w64);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||||
|
{
|
||||||
|
union llreg_u{
|
||||||
|
uint32_t w32[2];
|
||||||
|
uint64_t w64;
|
||||||
|
} llr;
|
||||||
|
llr.w64 = acc;
|
||||||
|
|
||||||
|
#ifndef __ARMEB__ // Little endian
|
||||||
|
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||||
|
#else // Big endian
|
||||||
|
__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return(llr.w64);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||||
|
{
|
||||||
|
union llreg_u{
|
||||||
|
uint32_t w32[2];
|
||||||
|
uint64_t w64;
|
||||||
|
} llr;
|
||||||
|
llr.w64 = acc;
|
||||||
|
|
||||||
|
#ifndef __ARMEB__ // Little endian
|
||||||
|
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||||
|
#else // Big endian
|
||||||
|
__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return(llr.w64);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
|
||||||
|
{
|
||||||
|
union llreg_u{
|
||||||
|
uint32_t w32[2];
|
||||||
|
uint64_t w64;
|
||||||
|
} llr;
|
||||||
|
llr.w64 = acc;
|
||||||
|
|
||||||
|
#ifndef __ARMEB__ // Little endian
|
||||||
|
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
|
||||||
|
#else // Big endian
|
||||||
|
__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return(llr.w64);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||||
|
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||||
|
if (ARG3 == 0) \
|
||||||
|
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||||
|
else \
|
||||||
|
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
/* not yet supported */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
|
||||||
|
/* Cosmic specific functions */
|
||||||
|
#include <cmsis_csm.h>
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CORE_CM4_SIMD_H */
|
||||||
@@ -0,0 +1,616 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cmFunc.h
|
||||||
|
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||||
|
* @version V3.01
|
||||||
|
* @date 06. March 2012
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __CORE_CMFUNC_H
|
||||||
|
#define __CORE_CMFUNC_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################### Core Function Access ########################### */
|
||||||
|
/** \ingroup CMSIS_Core_FunctionInterface
|
||||||
|
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* intrinsic void __enable_irq(); */
|
||||||
|
/* intrinsic void __disable_irq(); */
|
||||||
|
|
||||||
|
/** \brief Get Control Register
|
||||||
|
|
||||||
|
This function returns the content of the Control Register.
|
||||||
|
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
return(__regControl);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Control Register
|
||||||
|
|
||||||
|
This function writes the given value to the Control Register.
|
||||||
|
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
register uint32_t __regControl __ASM("control");
|
||||||
|
__regControl = control;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get IPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the IPSR Register.
|
||||||
|
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regIPSR __ASM("ipsr");
|
||||||
|
return(__regIPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get APSR Register
|
||||||
|
|
||||||
|
This function returns the content of the APSR Register.
|
||||||
|
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regAPSR __ASM("apsr");
|
||||||
|
return(__regAPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get xPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the xPSR Register.
|
||||||
|
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regXPSR __ASM("xpsr");
|
||||||
|
return(__regXPSR);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Process Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
return(__regProcessStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Process Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||||
|
__regProcessStackPointer = topOfProcStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Main Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
return(__regMainStackPointer);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Main Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
register uint32_t __regMainStackPointer __ASM("msp");
|
||||||
|
__regMainStackPointer = topOfMainStack;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Priority Mask
|
||||||
|
|
||||||
|
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
return(__regPriMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Priority Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Priority Mask Register.
|
||||||
|
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regPriMask __ASM("primask");
|
||||||
|
__regPriMask = (priMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Enable FIQ
|
||||||
|
|
||||||
|
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __enable_fault_irq __enable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable FIQ
|
||||||
|
|
||||||
|
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
#define __disable_fault_irq __disable_fiq
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Base Priority
|
||||||
|
|
||||||
|
This function returns the current value of the Base Priority register.
|
||||||
|
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
return(__regBasePri);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Base Priority
|
||||||
|
|
||||||
|
This function assigns the given value to the Base Priority register.
|
||||||
|
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||||
|
{
|
||||||
|
register uint32_t __regBasePri __ASM("basepri");
|
||||||
|
__regBasePri = (basePri & 0xff);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Fault Mask
|
||||||
|
|
||||||
|
This function returns the current value of the Fault Mask register.
|
||||||
|
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
return(__regFaultMask);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Fault Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Fault Mask register.
|
||||||
|
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
register uint32_t __regFaultMask __ASM("faultmask");
|
||||||
|
__regFaultMask = (faultMask & (uint32_t)1);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
This function returns the current value of the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
return(__regfpscr);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set FPSCR
|
||||||
|
|
||||||
|
This function assigns the given value to the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
register uint32_t __regfpscr __ASM("fpscr");
|
||||||
|
__regfpscr = (fpscr);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/** \brief Enable IRQ Interrupts
|
||||||
|
|
||||||
|
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsie i");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable IRQ Interrupts
|
||||||
|
|
||||||
|
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsid i");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Control Register
|
||||||
|
|
||||||
|
This function returns the content of the Control Register.
|
||||||
|
|
||||||
|
\return Control Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Control Register
|
||||||
|
|
||||||
|
This function writes the given value to the Control Register.
|
||||||
|
|
||||||
|
\param [in] control Control Register value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get IPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the IPSR Register.
|
||||||
|
|
||||||
|
\return IPSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get APSR Register
|
||||||
|
|
||||||
|
This function returns the content of the APSR Register.
|
||||||
|
|
||||||
|
\return APSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get xPSR Register
|
||||||
|
|
||||||
|
This function returns the content of the xPSR Register.
|
||||||
|
|
||||||
|
\return xPSR Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Process Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\return PSP Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Process Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||||
|
|
||||||
|
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Main Stack Pointer
|
||||||
|
|
||||||
|
This function returns the current value of the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\return MSP Register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||||
|
{
|
||||||
|
register uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Main Stack Pointer
|
||||||
|
|
||||||
|
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||||
|
|
||||||
|
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Priority Mask
|
||||||
|
|
||||||
|
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||||
|
|
||||||
|
\return Priority Mask value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Priority Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Priority Mask Register.
|
||||||
|
|
||||||
|
\param [in] priMask Priority Mask
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Enable FIQ
|
||||||
|
|
||||||
|
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsie f");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Disable FIQ
|
||||||
|
|
||||||
|
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||||
|
Can only be executed in Privileged modes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("cpsid f");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Base Priority
|
||||||
|
|
||||||
|
This function returns the current value of the Base Priority register.
|
||||||
|
|
||||||
|
\return Base Priority register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Base Priority
|
||||||
|
|
||||||
|
This function assigns the given value to the Base Priority register.
|
||||||
|
|
||||||
|
\param [in] basePri Base Priority value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Get Fault Mask
|
||||||
|
|
||||||
|
This function returns the current value of the Fault Mask register.
|
||||||
|
|
||||||
|
\return Fault Mask register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set Fault Mask
|
||||||
|
|
||||||
|
This function assigns the given value to the Fault Mask register.
|
||||||
|
|
||||||
|
\param [in] faultMask Fault Mask value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||||
|
{
|
||||||
|
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M == 0x04)
|
||||||
|
|
||||||
|
/** \brief Get FPSCR
|
||||||
|
|
||||||
|
This function returns the current value of the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\return Floating Point Status/Control register value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||||
|
return(result);
|
||||||
|
#else
|
||||||
|
return(0);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Set FPSCR
|
||||||
|
|
||||||
|
This function assigns the given value to the Floating Point Status/Control register.
|
||||||
|
|
||||||
|
\param [in] fpscr Floating Point Status/Control value to set
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||||
|
{
|
||||||
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||||
|
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M == 0x04) */
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* __CORE_CMFUNC_H */
|
||||||
@@ -0,0 +1,618 @@
|
|||||||
|
/**************************************************************************//**
|
||||||
|
* @file core_cmInstr.h
|
||||||
|
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||||
|
* @version V3.01
|
||||||
|
* @date 06. March 2012
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||||
|
* processor based microcontrollers. This file can be freely distributed
|
||||||
|
* within development tools that are supporting such ARM based processors.
|
||||||
|
*
|
||||||
|
* @par
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||||
|
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||||
|
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __CORE_CMINSTR_H
|
||||||
|
#define __CORE_CMINSTR_H
|
||||||
|
|
||||||
|
|
||||||
|
/* ########################## Core Instruction Access ######################### */
|
||||||
|
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||||
|
Access to dedicated instructions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||||
|
/* ARM armcc specific functions */
|
||||||
|
|
||||||
|
#if (__ARMCC_VERSION < 400677)
|
||||||
|
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief No Operation
|
||||||
|
|
||||||
|
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
#define __NOP __nop
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Interrupt
|
||||||
|
|
||||||
|
Wait For Interrupt is a hint instruction that suspends execution
|
||||||
|
until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFI __wfi
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Event
|
||||||
|
|
||||||
|
Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
#define __WFE __wfe
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Send Event
|
||||||
|
|
||||||
|
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
#define __SEV __sev
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Instruction Synchronization Barrier
|
||||||
|
|
||||||
|
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or
|
||||||
|
memory, after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
#define __ISB() __isb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Synchronization Barrier
|
||||||
|
|
||||||
|
This function acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
#define __DSB() __dsb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Memory Barrier
|
||||||
|
|
||||||
|
This function ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
#define __DMB() __dmb(0xF)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (32 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in integer value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __REV __rev
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (16 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in two unsigned short values.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
rev16 r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order in signed short value
|
||||||
|
|
||||||
|
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||||
|
{
|
||||||
|
revsh r0, r0
|
||||||
|
bx lr
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||||||
|
|
||||||
|
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\param [in] value Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
#define __ROR __ror
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
This function reverses the bit order of the given value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
#define __RBIT __rbit
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Remove the exclusive lock
|
||||||
|
|
||||||
|
This function removes the exclusive lock which is created by LDREX.
|
||||||
|
|
||||||
|
*/
|
||||||
|
#define __CLREX __clrex
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Signed Saturate
|
||||||
|
|
||||||
|
This function saturates a signed value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT __ssat
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Unsigned Saturate
|
||||||
|
|
||||||
|
This function saturates an unsigned value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT __usat
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
|
This function counts the number of leading zeros of a data value.
|
||||||
|
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
#define __CLZ __clz
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||||
|
/* IAR iccarm specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_iar.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||||
|
/* TI CCS specific functions */
|
||||||
|
|
||||||
|
#include <cmsis_ccs.h>
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||||
|
/* GNU gcc specific functions */
|
||||||
|
|
||||||
|
/** \brief No Operation
|
||||||
|
|
||||||
|
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("nop");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Interrupt
|
||||||
|
|
||||||
|
Wait For Interrupt is a hint instruction that suspends execution
|
||||||
|
until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Wait For Event
|
||||||
|
|
||||||
|
Wait For Event is a hint instruction that permits the processor to enter
|
||||||
|
a low-power state until one of a number of events occurs.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("wfe");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Send Event
|
||||||
|
|
||||||
|
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("sev");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Instruction Synchronization Barrier
|
||||||
|
|
||||||
|
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||||
|
so that all instructions following the ISB are fetched from cache or
|
||||||
|
memory, after the instruction has been completed.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("isb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Synchronization Barrier
|
||||||
|
|
||||||
|
This function acts as a special kind of Data Memory Barrier.
|
||||||
|
It completes when all explicit memory accesses before this instruction complete.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("dsb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Data Memory Barrier
|
||||||
|
|
||||||
|
This function ensures the apparent order of the explicit memory operations before
|
||||||
|
and after the instruction, without ensuring their completion.
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("dmb");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (32 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in integer value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order (16 bit)
|
||||||
|
|
||||||
|
This function reverses the byte order in two unsigned short values.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Reverse byte order in signed short value
|
||||||
|
|
||||||
|
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Rotate Right in unsigned value (32 bit)
|
||||||
|
|
||||||
|
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||||
|
|
||||||
|
\param [in] value Value to rotate
|
||||||
|
\param [in] value Number of Bits to rotate
|
||||||
|
\return Rotated value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||||
|
{
|
||||||
|
|
||||||
|
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||||
|
return(op1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if (__CORTEX_M >= 0x03)
|
||||||
|
|
||||||
|
/** \brief Reverse bit order of value
|
||||||
|
|
||||||
|
This function reverses the bit order of the given value.
|
||||||
|
|
||||||
|
\param [in] value Value to reverse
|
||||||
|
\return Reversed value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 8 bit value.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint8_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint8_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint16_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint16_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief LDR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive LDR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] ptr Pointer to data
|
||||||
|
\return value of type uint32_t at (*ptr)
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (8 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 8 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (16 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 16 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief STR Exclusive (32 bit)
|
||||||
|
|
||||||
|
This function performs a exclusive STR command for 32 bit values.
|
||||||
|
|
||||||
|
\param [in] value Value to store
|
||||||
|
\param [in] ptr Pointer to location
|
||||||
|
\return 0 Function succeeded
|
||||||
|
\return 1 Function failed
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Remove the exclusive lock
|
||||||
|
|
||||||
|
This function removes the exclusive lock which is created by LDREX.
|
||||||
|
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||||
|
{
|
||||||
|
__ASM volatile ("clrex");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Signed Saturate
|
||||||
|
|
||||||
|
This function saturates a signed value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (1..32)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __SSAT(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Unsigned Saturate
|
||||||
|
|
||||||
|
This function saturates an unsigned value.
|
||||||
|
|
||||||
|
\param [in] value Value to be saturated
|
||||||
|
\param [in] sat Bit position to saturate to (0..31)
|
||||||
|
\return Saturated value
|
||||||
|
*/
|
||||||
|
#define __USAT(ARG1,ARG2) \
|
||||||
|
({ \
|
||||||
|
uint32_t __RES, __ARG1 = (ARG1); \
|
||||||
|
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||||
|
__RES; \
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
/** \brief Count leading zeros
|
||||||
|
|
||||||
|
This function counts the number of leading zeros of a data value.
|
||||||
|
|
||||||
|
\param [in] value Value to count the leading zeros
|
||||||
|
\return number of leading zeros in value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||||
|
{
|
||||||
|
uint8_t result;
|
||||||
|
|
||||||
|
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||||
|
return(result);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* (__CORTEX_M >= 0x03) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||||
|
/* TASKING carm specific functions */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||||
|
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||||
|
* Including the CMSIS ones.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||||
|
|
||||||
|
#endif /* __CORE_CMINSTR_H */
|
||||||
@@ -0,0 +1,454 @@
|
|||||||
|
;/*!
|
||||||
|
; \file startup_gd32f405_425.S
|
||||||
|
; \brief start up file
|
||||||
|
;
|
||||||
|
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||||
|
;*/
|
||||||
|
;
|
||||||
|
;/*
|
||||||
|
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||||
|
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
; * SPDX-License-Identifier: Apache-2.0
|
||||||
|
; *
|
||||||
|
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||||
|
; * not use this file except in compliance with the License.
|
||||||
|
; * You may obtain a copy of the License at
|
||||||
|
; *
|
||||||
|
; * www.apache.org/licenses/LICENSE-2.0
|
||||||
|
; *
|
||||||
|
; * Unless required by applicable law or agreed to in writing, software
|
||||||
|
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||||
|
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
; * See the License for the specific language governing permissions and
|
||||||
|
; * limitations under the License.
|
||||||
|
; */
|
||||||
|
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||||
|
|
||||||
|
.syntax unified
|
||||||
|
.cpu cortex-m4
|
||||||
|
.fpu softvfp
|
||||||
|
.thumb
|
||||||
|
|
||||||
|
.global Default_Handler
|
||||||
|
|
||||||
|
/* necessary symbols defined in linker script to initialize data */
|
||||||
|
.word _sidata
|
||||||
|
.word _sdata
|
||||||
|
.word _edata
|
||||||
|
.word _sbss
|
||||||
|
.word _ebss
|
||||||
|
|
||||||
|
.section .text.Reset_Handler
|
||||||
|
.weak Reset_Handler
|
||||||
|
.type Reset_Handler, %function
|
||||||
|
|
||||||
|
/* reset Handler */
|
||||||
|
Reset_Handler:
|
||||||
|
movs r1, #0
|
||||||
|
b DataInit
|
||||||
|
|
||||||
|
CopyData:
|
||||||
|
ldr r3, =_sidata
|
||||||
|
ldr r3, [r3, r1]
|
||||||
|
str r3, [r0, r1]
|
||||||
|
adds r1, r1, #4
|
||||||
|
|
||||||
|
DataInit:
|
||||||
|
ldr r0, =_sdata
|
||||||
|
ldr r3, =_edata
|
||||||
|
adds r2, r0, r1
|
||||||
|
cmp r2, r3
|
||||||
|
bcc CopyData
|
||||||
|
ldr r2, =_sbss
|
||||||
|
b Zerobss
|
||||||
|
|
||||||
|
FillZerobss:
|
||||||
|
movs r3, #0
|
||||||
|
str r3, [r2], #4
|
||||||
|
|
||||||
|
Zerobss:
|
||||||
|
ldr r3, = _ebss
|
||||||
|
cmp r2, r3
|
||||||
|
bcc FillZerobss
|
||||||
|
/* Call SystemInit function */
|
||||||
|
bl SystemInit
|
||||||
|
/* Call static constructors */
|
||||||
|
bl __libc_init_array
|
||||||
|
/*Call the main function */
|
||||||
|
bl main
|
||||||
|
bx lr
|
||||||
|
.size Reset_Handler, .-Reset_Handler
|
||||||
|
|
||||||
|
.section .text.Default_Handler,"ax",%progbits
|
||||||
|
Default_Handler:
|
||||||
|
Infinite_Loop:
|
||||||
|
b Infinite_Loop
|
||||||
|
.size Default_Handler, .-Default_Handler
|
||||||
|
|
||||||
|
.section .vectors,"a",%progbits
|
||||||
|
.global __gVectors
|
||||||
|
|
||||||
|
__gVectors:
|
||||||
|
.word _sp /* Top of Stack */
|
||||||
|
.word Reset_Handler /* Reset Handler */
|
||||||
|
.word NMI_Handler /* NMI Handler */
|
||||||
|
.word HardFault_Handler /* Hard Fault Handler */
|
||||||
|
.word MemManage_Handler /* MPU Fault Handler */
|
||||||
|
.word BusFault_Handler /* Bus Fault Handler */
|
||||||
|
.word UsageFault_Handler /* Usage Fault Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word SVC_Handler /* SVCall Handler */
|
||||||
|
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||||
|
.word 0 /* Reserved */
|
||||||
|
.word PendSV_Handler /* PendSV Handler */
|
||||||
|
.word SysTick_Handler /* SysTick Handler */
|
||||||
|
|
||||||
|
/* External interrupts handler */
|
||||||
|
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||||
|
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||||
|
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||||
|
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||||
|
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||||
|
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||||
|
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||||
|
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||||
|
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||||
|
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||||
|
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||||
|
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||||
|
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||||
|
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||||
|
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||||
|
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||||
|
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||||
|
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||||
|
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||||
|
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||||
|
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||||
|
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||||
|
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||||
|
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||||
|
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||||
|
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||||
|
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||||
|
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */
|
||||||
|
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||||
|
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||||
|
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||||
|
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||||
|
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||||
|
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||||
|
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||||
|
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||||
|
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||||
|
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||||
|
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||||
|
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||||
|
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||||
|
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||||
|
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||||
|
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||||
|
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||||
|
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||||
|
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
|
||||||
|
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||||
|
.word 0 /* Vector Number 64,Reserved */
|
||||||
|
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||||
|
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||||
|
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||||
|
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||||
|
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||||
|
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||||
|
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||||
|
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||||
|
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||||
|
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||||
|
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||||
|
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||||
|
.word 0 /* Vector Number 77,Reserved */
|
||||||
|
.word 0 /* Vector Number 78,Reserved */
|
||||||
|
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||||
|
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||||
|
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||||
|
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||||
|
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||||
|
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||||
|
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||||
|
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||||
|
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||||
|
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||||
|
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||||
|
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||||
|
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||||
|
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||||
|
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||||
|
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||||
|
.word 0 /* Vector Number 95,Reserved */
|
||||||
|
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||||
|
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||||
|
|
||||||
|
.size __gVectors, . - __gVectors
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak MemManage_Handler
|
||||||
|
.thumb_set MemManage_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak BusFault_Handler
|
||||||
|
.thumb_set BusFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak UsageFault_Handler
|
||||||
|
.thumb_set UsageFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak DebugMon_Handler
|
||||||
|
.thumb_set DebugMon_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDGT_IRQHandler
|
||||||
|
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LVD_IRQHandler
|
||||||
|
.thumb_set LVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TAMPER_STAMP_IRQHandler
|
||||||
|
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_WKUP_IRQHandler
|
||||||
|
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FMC_IRQHandler
|
||||||
|
.thumb_set FMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCU_CTC_IRQHandler
|
||||||
|
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_IRQHandler
|
||||||
|
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI1_IRQHandler
|
||||||
|
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_IRQHandler
|
||||||
|
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI3_IRQHandler
|
||||||
|
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_IRQHandler
|
||||||
|
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_IRQHandler
|
||||||
|
.thumb_set ADC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_TX_IRQHandler
|
||||||
|
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX0_IRQHandler
|
||||||
|
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_RX1_IRQHandler
|
||||||
|
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN0_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI5_9_IRQHandler
|
||||||
|
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||||
|
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||||
|
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||||
|
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER0_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER1_IRQHandler
|
||||||
|
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER2_IRQHandler
|
||||||
|
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER3_IRQHandler
|
||||||
|
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_EV_IRQHandler
|
||||||
|
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C0_ER_IRQHandler
|
||||||
|
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_EV_IRQHandler
|
||||||
|
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_ER_IRQHandler
|
||||||
|
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI0_IRQHandler
|
||||||
|
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART0_IRQHandler
|
||||||
|
.thumb_set USART0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI10_15_IRQHandler
|
||||||
|
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_Alarm_IRQHandler
|
||||||
|
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||||
|
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||||
|
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||||
|
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER7_Channel_IRQHandler
|
||||||
|
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA0_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SDIO_IRQHandler
|
||||||
|
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER4_IRQHandler
|
||||||
|
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART3_IRQHandler
|
||||||
|
.thumb_set UART3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak UART4_IRQHandler
|
||||||
|
.thumb_set UART4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER5_DAC_IRQHandler
|
||||||
|
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIMER6_IRQHandler
|
||||||
|
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel0_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel4_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_TX_IRQHandler
|
||||||
|
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX0_IRQHandler
|
||||||
|
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_RX1_IRQHandler
|
||||||
|
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak CAN1_EWMC_IRQHandler
|
||||||
|
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBFS_IRQHandler
|
||||||
|
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel5_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel6_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel7_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART5_IRQHandler
|
||||||
|
.thumb_set USART5_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_EV_IRQHandler
|
||||||
|
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_ER_IRQHandler
|
||||||
|
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_Out_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_EP1_In_IRQHandler
|
||||||
|
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_WKUP_IRQHandler
|
||||||
|
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USBHS_IRQHandler
|
||||||
|
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DCI_IRQHandler
|
||||||
|
.thumb_set DCI_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TRNG_IRQHandler
|
||||||
|
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FPU_IRQHandler
|
||||||
|
.thumb_set FPU_IRQHandler,Default_Handler
|
||||||
@@ -0,0 +1,42 @@
|
|||||||
|
project(GD32F4xx_standard_peripheral LANGUAGES C CXX ASM)
|
||||||
|
|
||||||
|
add_library(GD32F4xx_standard_peripheral OBJECT
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_adc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_can.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_crc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_ctc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_dac.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_dbg.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_dci.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_dma.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_enet.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_exmc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_exti.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_fmc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_fwdgt.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_gpio.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_i2c.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_iref.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_misc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_pmu.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_rcu.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_rtc.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_sdio.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_spi.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_syscfg.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_timer.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_tli.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_trng.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_usart.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_wwdgt.c
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Source/gd32f4xx_ipa.c
|
||||||
|
)
|
||||||
|
|
||||||
|
target_include_directories(GD32F4xx_standard_peripheral PUBLIC
|
||||||
|
${CMAKE_SOURCE_DIR}/SDK/GD32F4xx_standard_peripheral/Include
|
||||||
|
)
|
||||||
|
|
||||||
|
target_compile_definitions(GD32F4xx_standard_peripheral PUBLIC GD32F405)
|
||||||
|
|
||||||
|
# CMSIS header only library is linked.
|
||||||
|
target_link_libraries(GD32F4xx_standard_peripheral PUBLIC CMSIS)
|
||||||
@@ -0,0 +1,513 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_adc.h
|
||||||
|
\brief definitions for the ADC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_ADC_H
|
||||||
|
#define GD32F4XX_ADC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* ADC definitions */
|
||||||
|
#define ADC0 ADC_BASE
|
||||||
|
#define ADC1 (ADC_BASE + 0x100U)
|
||||||
|
#define ADC2 (ADC_BASE + 0x200U)
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||||
|
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||||
|
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||||
|
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||||
|
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||||
|
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||||
|
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||||
|
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||||
|
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||||
|
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||||
|
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||||
|
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC routine sequence register 0 */
|
||||||
|
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC routine sequence register 1 */
|
||||||
|
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC routine sequence register 2 */
|
||||||
|
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||||
|
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||||
|
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||||
|
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||||
|
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||||
|
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC routine data register */
|
||||||
|
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
||||||
|
#define ADC_SSTAT REG32((ADC_BASE) + 0x300U) /*!< ADC summary status register */
|
||||||
|
#define ADC_SYNCCTL REG32((ADC_BASE) + 0x304U) /*!< ADC synchronization control register */
|
||||||
|
#define ADC_SYNCDATA REG32((ADC_BASE) + 0x308U) /*!< ADC synchronization routine data register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* ADC_STAT */
|
||||||
|
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||||
|
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||||
|
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||||
|
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||||
|
#define ADC_STAT_STRC BIT(4) /*!< routine channel start flag */
|
||||||
|
#define ADC_STAT_ROVF BIT(5) /*!< routine data register overflow */
|
||||||
|
|
||||||
|
/* ADC_CTL0 */
|
||||||
|
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||||
|
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||||
|
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||||
|
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||||
|
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||||
|
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||||
|
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted sequence conversion */
|
||||||
|
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on routine channels */
|
||||||
|
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||||
|
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||||
|
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||||
|
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on routine channels */
|
||||||
|
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||||
|
#define ADC_CTL0_ROVFIE BIT(26) /*!< interrupt enable for ROVF */
|
||||||
|
|
||||||
|
/* ADC_CTL1 */
|
||||||
|
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||||
|
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||||
|
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||||
|
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||||
|
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||||
|
#define ADC_CTL1_DDM BIT(9) /*!< DMA disable mode */
|
||||||
|
#define ADC_CTL1_EOCM BIT(10) /*!< end of conversion mode */
|
||||||
|
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||||
|
#define ADC_CTL1_ETSIC BITS(16,19) /*!< external event select for inserted sequence */
|
||||||
|
#define ADC_CTL1_ETMIC BITS(20,21) /*!< external trigger conversion mode for inserted channels */
|
||||||
|
#define ADC_CTL1_SWICST BIT(22) /*!< start conversion of inserted channels */
|
||||||
|
#define ADC_CTL1_ETSRC BITS(24,27) /*!< external event select for routine sequence */
|
||||||
|
#define ADC_CTL1_ETMRC BITS(28,29) /*!< external trigger conversion mode for routine channels */
|
||||||
|
#define ADC_CTL1_SWRCST BIT(30) /*!< start conversion of routine channels */
|
||||||
|
|
||||||
|
/* ADC_SAMPTx x=0..1 */
|
||||||
|
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
||||||
|
|
||||||
|
/* ADC_IOFFx x=0..3 */
|
||||||
|
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||||
|
|
||||||
|
/* ADC_WDHT */
|
||||||
|
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||||
|
|
||||||
|
/* ADC_WDLT */
|
||||||
|
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||||
|
|
||||||
|
/* ADC_RSQx */
|
||||||
|
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in routine sequence */
|
||||||
|
#define ADC_RSQ0_RL BITS(20,23) /*!< routine channel sequence length */
|
||||||
|
|
||||||
|
/* ADC_ISQ */
|
||||||
|
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in inserted sequence */
|
||||||
|
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||||
|
|
||||||
|
/* ADC_IDATAx x=0..3*/
|
||||||
|
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
||||||
|
|
||||||
|
/* ADC_RDATA */
|
||||||
|
#define ADC_RDATA_RDATA BITS(0,15) /*!< routine data */
|
||||||
|
|
||||||
|
/* ADC_OVSAMPCTL */
|
||||||
|
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||||
|
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||||
|
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||||
|
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||||
|
|
||||||
|
/* ADC_SSTAT */
|
||||||
|
#define ADC_SSTAT_WDE0 BIT(0) /*!< the mirror image of the WDE bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_EOC0 BIT(1) /*!< the mirror image of the EOC bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_EOIC0 BIT(2) /*!< the mirror image of the EOIC bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_STIC0 BIT(3) /*!< the mirror image of the STIC bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_STRC0 BIT(4) /*!< the mirror image of the STRC bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_ROVF0 BIT(5) /*!< the mirror image of the ROVF bit of ADC0 */
|
||||||
|
#define ADC_SSTAT_WDE1 BIT(8) /*!< the mirror image of the WDE bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_EOC1 BIT(9) /*!< the mirror image of the EOC bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_EOIC1 BIT(10) /*!< the mirror image of the EOIC bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_STIC1 BIT(11) /*!< the mirror image of the STIC bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_STRC1 BIT(12) /*!< the mirror image of the STRC bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_ROVF1 BIT(13) /*!< the mirror image of the ROVF bit of ADC1 */
|
||||||
|
#define ADC_SSTAT_WDE2 BIT(16) /*!< the mirror image of the WDE bit of ADC2 */
|
||||||
|
#define ADC_SSTAT_EOC2 BIT(17) /*!< the mirror image of the EOC bit of ADC2 */
|
||||||
|
#define ADC_SSTAT_EOIC2 BIT(18) /*!< the mirror image of the EOIC bit of ADC2 */
|
||||||
|
#define ADC_SSTAT_STIC2 BIT(19) /*!< the mirror image of the STIC bit of ADC2 */
|
||||||
|
#define ADC_SSTAT_STRC2 BIT(20) /*!< the mirror image of the STRC bit of ADC2 */
|
||||||
|
#define ADC_SSTAT_ROVF2 BIT(21) /*!< the mirror image of the ROVF bit of ADC2 */
|
||||||
|
|
||||||
|
/* ADC_SYNCCTL */
|
||||||
|
#define ADC_SYNCCTL_SYNCM BITS(0,4) /*!< ADC synchronization mode */
|
||||||
|
#define ADC_SYNCCTL_SYNCDLY BITS(8,11) /*!< ADC synchronization delay */
|
||||||
|
#define ADC_SYNCCTL_SYNCDDM BIT(13) /*!< ADC synchronization DMA disable mode */
|
||||||
|
#define ADC_SYNCCTL_SYNCDMA BITS(14,15) /*!< ADC synchronization DMA mode selection */
|
||||||
|
#define ADC_SYNCCTL_ADCCK BITS(16,18) /*!< ADC clock */
|
||||||
|
#define ADC_SYNCCTL_VBATEN BIT(22) /*!< channel 18 (1/4 voltate of external battery) enable of ADC0 */
|
||||||
|
#define ADC_SYNCCTL_TSVREN BIT(23) /*!< channel 16 (temperature sensor) and 17 (internal reference voltage) enable of ADC0 */
|
||||||
|
|
||||||
|
/* ADC_SYNCDATA */
|
||||||
|
#define ADC_SYNCDATA_SYNCDATA0 BITS(0,15) /*!< routine data1 in ADC synchronization mode */
|
||||||
|
#define ADC_SYNCDATA_SYNCDATA1 BITS(16,31) /*!< routine data2 in ADC synchronization mode */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* ADC status flag */
|
||||||
|
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||||
|
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||||
|
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||||
|
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||||
|
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< routine channel start flag */
|
||||||
|
#define ADC_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||||
|
|
||||||
|
/* adc_ctl0 register value */
|
||||||
|
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||||
|
|
||||||
|
/* ADC special function definitions */
|
||||||
|
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||||
|
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted sequence convert automatically */
|
||||||
|
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||||
|
|
||||||
|
/* temperature sensor channel, internal reference voltage channel, VBAT channel */
|
||||||
|
#define ADC_VBAT_CHANNEL_SWITCH ADC_SYNCCTL_VBATEN /*!< VBAT channel */
|
||||||
|
#define ADC_TEMP_VREF_CHANNEL_SWITCH ADC_SYNCCTL_TSVREN /*!< Vref and Vtemp channel */
|
||||||
|
|
||||||
|
/* ADC synchronization mode */
|
||||||
|
#define SYNCCTL_SYNCM(regval) (BITS(0,4) & ((uint32_t)(regval))) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||||
|
#define ADC_SYNC_MODE_INDEPENDENT SYNCCTL_SYNCM(0) /*!< ADC synchronization mode disabled.All the ADCs work independently */
|
||||||
|
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(1) /*!< ADC0 and ADC1 work in combined routine parallel & inserted parallel mode. ADC2 works independently */
|
||||||
|
#define ADC_DAUL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(2) /*!< ADC0 and ADC1 work in combined routine parallel & trigger rotation mode. ADC2 works independently */
|
||||||
|
#define ADC_DAUL_INSERTED_PARALLEL SYNCCTL_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode. ADC2 works independently */
|
||||||
|
#define ADC_DAUL_ROUTINE_PARALLEL SYNCCTL_SYNCM(6) /*!< ADC0 and ADC1 work in routine parallel mode. ADC2 works independently */
|
||||||
|
#define ADC_DAUL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up mode. ADC2 works independently */
|
||||||
|
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode. ADC2 works independently */
|
||||||
|
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_PARALLEL SYNCCTL_SYNCM(17) /*!< all ADCs work in combined routine parallel & inserted parallel mode */
|
||||||
|
#define ADC_ALL_ROUTINE_PARALLEL_INSERTED_ROTATION SYNCCTL_SYNCM(18) /*!< all ADCs work in combined routine parallel & trigger rotation mode */
|
||||||
|
#define ADC_ALL_INSERTED_PARALLEL SYNCCTL_SYNCM(21) /*!< all ADCs work in inserted parallel mode */
|
||||||
|
#define ADC_ALL_ROUTINE_PARALLEL SYNCCTL_SYNCM(22) /*!< all ADCs work in routine parallel mode */
|
||||||
|
#define ADC_ALL_ROUTINE_FOLLOW_UP SYNCCTL_SYNCM(23) /*!< all ADCs work in follow-up mode */
|
||||||
|
#define ADC_ALL_INSERTED_TRRIGGER_ROTATION SYNCCTL_SYNCM(25) /*!< all ADCs work in trigger rotation mode */
|
||||||
|
|
||||||
|
/* ADC data alignment */
|
||||||
|
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||||
|
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||||
|
|
||||||
|
/* external trigger mode for routine and inserted channel */
|
||||||
|
#define EXTERNAL_TRIGGER_DISABLE ((uint32_t)0x00000000U) /*!< external trigger disable */
|
||||||
|
#define EXTERNAL_TRIGGER_RISING ((uint32_t)0x00000001U) /*!< rising edge of external trigger */
|
||||||
|
#define EXTERNAL_TRIGGER_FALLING ((uint32_t)0x00000002U) /*!< falling edge of external trigger */
|
||||||
|
#define EXTERNAL_TRIGGER_RISING_FALLING ((uint32_t)0x00000003U) /*!< rising and falling edge of external trigger */
|
||||||
|
|
||||||
|
/* ADC external trigger select for routine channel */
|
||||||
|
#define CTL1_ETSRC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T1_CH2 CTL1_ETSRC(4) /*!< timer 1 CC2 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T1_CH3 CTL1_ETSRC(5) /*!< timer 1 CC3 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T1_TRGO CTL1_ETSRC(6) /*!< timer 1 TRGO event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T2_CH0 CTL1_ETSRC(7) /*!< timer 2 CC0 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T2_TRGO CTL1_ETSRC(8) /*!< timer 2 TRGO event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T3_CH3 CTL1_ETSRC(9) /*!< timer 3 CC3 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T4_CH0 CTL1_ETSRC(10) /*!< timer 4 CC0 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T4_CH1 CTL1_ETSRC(11) /*!< timer 4 CC1 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T4_CH2 CTL1_ETSRC(12) /*!< timer 4 CC2 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T7_CH0 CTL1_ETSRC(13) /*!< timer 7 CC0 event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_T7_TRGO CTL1_ETSRC(14) /*!< timer 7 TRGO event select */
|
||||||
|
#define ADC_EXTTRIG_ROUTINE_EXTI_11 CTL1_ETSRC(15) /*!< extiline 11 select */
|
||||||
|
|
||||||
|
/* ADC external trigger select for inserted channel */
|
||||||
|
#define CTL1_ETSIC(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(0) /*!< timer0 capture compare 3 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(1) /*!< timer0 TRGO event */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(2) /*!< timer1 capture compare 0 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(3) /*!< timer1 TRGO event */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T2_CH1 CTL1_ETSIC(4) /*!< timer2 capture compare 1 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(5) /*!< timer2 capture compare 3 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T3_CH0 CTL1_ETSIC(6) /*!< timer3 capture compare 0 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T3_CH1 CTL1_ETSIC(7) /*!< timer3 capture compare 1 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(8) /*!< timer3 capture compare 2 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(9) /*!< timer3 capture compare TRGO */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(10) /*!< timer4 capture compare 3 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(11) /*!< timer4 capture compare TRGO */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(12) /*!< timer7 capture compare 1 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T7_CH2 CTL1_ETSIC(13) /*!< timer7 capture compare 2 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(14) /*!< timer7 capture compare 3 */
|
||||||
|
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(15) /*!< external interrupt line 15 */
|
||||||
|
|
||||||
|
/* ADC channel sample time */
|
||||||
|
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||||
|
#define ADC_SAMPLETIME_3 SAMPTX_SPT(0) /*!< 3 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_15 SAMPTX_SPT(1) /*!< 15 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_28 SAMPTX_SPT(2) /*!< 28 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_56 SAMPTX_SPT(3) /*!< 56 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_84 SAMPTX_SPT(4) /*!< 84 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_112 SAMPTX_SPT(5) /*!< 112 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_144 SAMPTX_SPT(6) /*!< 144 sampling cycles */
|
||||||
|
#define ADC_SAMPLETIME_480 SAMPTX_SPT(7) /*!< 480 sampling cycles */
|
||||||
|
|
||||||
|
/* adc_ioffx register value */
|
||||||
|
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||||
|
|
||||||
|
/* adc_wdht register value */
|
||||||
|
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||||
|
|
||||||
|
/* adc_wdlt register value */
|
||||||
|
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||||
|
|
||||||
|
/* adc_rsqx register value */
|
||||||
|
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||||
|
|
||||||
|
/* adc_isq register value */
|
||||||
|
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||||
|
|
||||||
|
/* adc_ovsampctl register value */
|
||||||
|
/* ADC resolution */
|
||||||
|
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< write value to ADC_CTL0_DRES bit field */
|
||||||
|
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||||
|
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||||
|
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||||
|
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||||
|
|
||||||
|
/* oversampling shift */
|
||||||
|
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||||
|
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||||
|
|
||||||
|
/* oversampling ratio */
|
||||||
|
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||||
|
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||||
|
|
||||||
|
/* triggered oversampling */
|
||||||
|
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||||
|
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
||||||
|
|
||||||
|
/* ADC channel sequence definitions */
|
||||||
|
#define ADC_ROUTINE_CHANNEL ((uint8_t)0x01U) /*!< adc routine sequence */
|
||||||
|
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted sequence */
|
||||||
|
#define ADC_ROUTINE_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both routine and inserted sequence */
|
||||||
|
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of routine & inserted sequence */
|
||||||
|
|
||||||
|
/* ADC inserted channel definitions */
|
||||||
|
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||||
|
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||||
|
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||||
|
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||||
|
|
||||||
|
/* ADC channel definitions */
|
||||||
|
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||||
|
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||||
|
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||||
|
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||||
|
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||||
|
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||||
|
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||||
|
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||||
|
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||||
|
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||||
|
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||||
|
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||||
|
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||||
|
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||||
|
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||||
|
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||||
|
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||||
|
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||||
|
#define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */
|
||||||
|
|
||||||
|
/* ADC interrupt flag */
|
||||||
|
#define ADC_INT_WDE ADC_CTL0_WDEIE /*!< analog watchdog event interrupt */
|
||||||
|
#define ADC_INT_EOC ADC_CTL0_EOCIE /*!< end of sequence conversion interrupt */
|
||||||
|
#define ADC_INT_EOIC ADC_CTL0_EOICIE /*!< end of inserted sequence conversion interrupt */
|
||||||
|
#define ADC_INT_ROVF ADC_CTL0_ROVFIE /*!< routine data register overflow */
|
||||||
|
|
||||||
|
/* ADC interrupt flag */
|
||||||
|
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||||
|
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of sequence conversion interrupt */
|
||||||
|
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted sequence conversion interrupt */
|
||||||
|
#define ADC_INT_FLAG_ROVF ADC_STAT_ROVF /*!< routine data register overflow */
|
||||||
|
|
||||||
|
/* configure the ADC clock for all the ADCs */
|
||||||
|
#define SYNCCTL_ADCCK(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||||
|
#define ADC_ADCCK_PCLK2_DIV2 SYNCCTL_ADCCK(0) /*!< PCLK2 div2 */
|
||||||
|
#define ADC_ADCCK_PCLK2_DIV4 SYNCCTL_ADCCK(1) /*!< PCLK2 div4 */
|
||||||
|
#define ADC_ADCCK_PCLK2_DIV6 SYNCCTL_ADCCK(2) /*!< PCLK2 div6 */
|
||||||
|
#define ADC_ADCCK_PCLK2_DIV8 SYNCCTL_ADCCK(3) /*!< PCLK2 div8 */
|
||||||
|
#define ADC_ADCCK_HCLK_DIV5 SYNCCTL_ADCCK(4) /*!< HCLK div5 */
|
||||||
|
#define ADC_ADCCK_HCLK_DIV6 SYNCCTL_ADCCK(5) /*!< HCLK div6 */
|
||||||
|
#define ADC_ADCCK_HCLK_DIV10 SYNCCTL_ADCCK(6) /*!< HCLK div10 */
|
||||||
|
#define ADC_ADCCK_HCLK_DIV20 SYNCCTL_ADCCK(7) /*!< HCLK div20 */
|
||||||
|
|
||||||
|
/* ADC synchronization delay */
|
||||||
|
#define ADC_SYNC_DELAY_5CYCLE ((uint32_t)0x00000000U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 5 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_6CYCLE ((uint32_t)0x00000100U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 6 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_7CYCLE ((uint32_t)0x00000200U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 7 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_8CYCLE ((uint32_t)0x00000300U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 8 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_9CYCLE ((uint32_t)0x00000400U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 9 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_10CYCLE ((uint32_t)0x00000500U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 10 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_11CYCLE ((uint32_t)0x00000600U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 11 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_12CYCLE ((uint32_t)0x00000700U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 12 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_13CYCLE ((uint32_t)0x00000800U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 13 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_14CYCLE ((uint32_t)0x00000900U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 14 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_15CYCLE ((uint32_t)0x00000A00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 15 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_16CYCLE ((uint32_t)0x00000B00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 16 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_17CYCLE ((uint32_t)0x00000C00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 17 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_18CYCLE ((uint32_t)0x00000D00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 18 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_19CYCLE ((uint32_t)0x00000E00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 19 ADC clock cycles. */
|
||||||
|
#define ADC_SYNC_DELAY_20CYCLE ((uint32_t)0x00000F00U) /*!< the delay between 2 sampling phases in ADC synchronization modes to 20 ADC clock cycles. */
|
||||||
|
|
||||||
|
/* ADC synchronization DMA mode selection */
|
||||||
|
#define ADC_SYNC_DMA_DISABLE ((uint32_t)0x00000000U) /*!< ADC synchronization DMA disabled */
|
||||||
|
#define ADC_SYNC_DMA_MODE0 ((uint32_t)0x00004000U) /*!< ADC synchronization DMA mode 0 */
|
||||||
|
#define ADC_SYNC_DMA_MODE1 ((uint32_t)0x00008000U) /*!< ADC synchronization DMA mode 1 */
|
||||||
|
|
||||||
|
/* end of conversion mode */
|
||||||
|
#define ADC_EOC_SET_SEQUENCE ((uint8_t)0x00U) /*!< only at the end of a sequence of routine conversions, the EOC bit is set */
|
||||||
|
#define ADC_EOC_SET_CONVERSION ((uint8_t)0x01U) /*!< at the end of each routine conversion, the EOC bit is set */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization config */
|
||||||
|
/* reset ADC */
|
||||||
|
void adc_deinit(void);
|
||||||
|
/* configure the ADC clock for all the ADCs */
|
||||||
|
void adc_clock_config(uint32_t prescaler);
|
||||||
|
/* enable or disable ADC special function */
|
||||||
|
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
|
||||||
|
/* configure ADC data alignment */
|
||||||
|
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
|
||||||
|
/* enable ADC interface */
|
||||||
|
void adc_enable(uint32_t adc_periph);
|
||||||
|
/* disable ADC interface */
|
||||||
|
void adc_disable(uint32_t adc_periph);
|
||||||
|
/* ADC calibration and reset calibration */
|
||||||
|
void adc_calibration_enable(uint32_t adc_periph);
|
||||||
|
/* configure temperature sensor and internal reference voltage channel or VBAT channel function */
|
||||||
|
void adc_channel_16_to_18(uint32_t function, ControlStatus newvalue);
|
||||||
|
/* configure ADC resolution */
|
||||||
|
void adc_resolution_config(uint32_t adc_periph, uint32_t resolution);
|
||||||
|
/* configure ADC oversample mode */
|
||||||
|
void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio);
|
||||||
|
/* enable ADC oversample mode */
|
||||||
|
void adc_oversample_mode_enable(uint32_t adc_periph);
|
||||||
|
/* disable ADC oversample mode */
|
||||||
|
void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||||
|
|
||||||
|
/* DMA config */
|
||||||
|
/* enable DMA request */
|
||||||
|
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||||
|
/* disable DMA request */
|
||||||
|
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||||
|
/* when DMA=1, the DMA engine issues a request at end of each routine conversion */
|
||||||
|
void adc_dma_request_after_last_enable(uint32_t adc_periph);
|
||||||
|
/* the DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||||
|
void adc_dma_request_after_last_disable(uint32_t adc_periph);
|
||||||
|
|
||||||
|
/* routine sequence and inserted sequence config */
|
||||||
|
/* configure ADC discontinuous mode */
|
||||||
|
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_sequence , uint8_t length);
|
||||||
|
/* configure the length of routine sequence or inserted sequence */
|
||||||
|
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t length);
|
||||||
|
/* configure ADC routine channel */
|
||||||
|
void adc_routine_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||||
|
/* configure ADC inserted channel */
|
||||||
|
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||||
|
/* configure ADC inserted channel offset */
|
||||||
|
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
||||||
|
/* configure ADC external trigger source */
|
||||||
|
void adc_external_trigger_source_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t external_trigger_source);
|
||||||
|
/* enable ADC external trigger */
|
||||||
|
void adc_external_trigger_config(uint32_t adc_periph , uint8_t adc_sequence , uint32_t trigger_mode);
|
||||||
|
/* enable ADC software trigger */
|
||||||
|
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
|
/* configure end of conversion mode */
|
||||||
|
void adc_end_of_conversion_config(uint32_t adc_periph , uint8_t end_selection);
|
||||||
|
|
||||||
|
/* get channel data */
|
||||||
|
/* read ADC routine data register */
|
||||||
|
uint16_t adc_routine_data_read(uint32_t adc_periph);
|
||||||
|
/* read ADC inserted data register */
|
||||||
|
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||||
|
|
||||||
|
/* watchdog config */
|
||||||
|
/* disable ADC analog watchdog single channel */
|
||||||
|
void adc_watchdog_single_channel_disable(uint32_t adc_periph );
|
||||||
|
/* enable ADC analog watchdog single channel */
|
||||||
|
void adc_watchdog_single_channel_enable(uint32_t adc_periph , uint8_t adc_channel);
|
||||||
|
/* configure ADC analog watchdog sequence */
|
||||||
|
void adc_watchdog_sequence_channel_enable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
|
/* disable ADC analog watchdog */
|
||||||
|
void adc_watchdog_disable(uint32_t adc_periph , uint8_t adc_sequence);
|
||||||
|
/* configure ADC analog watchdog threshold */
|
||||||
|
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* get the ADC flag bits */
|
||||||
|
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
|
||||||
|
/* clear the ADC flag bits */
|
||||||
|
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
||||||
|
/* get the bit state of ADCx software start conversion */
|
||||||
|
FlagStatus adc_routine_software_startconv_flag_get(uint32_t adc_periph);
|
||||||
|
/* get the bit state of ADCx software inserted channel start conversion */
|
||||||
|
FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph);
|
||||||
|
/* get the ADC interrupt bits */
|
||||||
|
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||||
|
/* clear the ADC flag */
|
||||||
|
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||||
|
/* enable ADC interrupt */
|
||||||
|
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||||
|
/* disable ADC interrupt */
|
||||||
|
void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||||
|
|
||||||
|
/* ADC synchronization */
|
||||||
|
/* configure the ADC sync mode */
|
||||||
|
void adc_sync_mode_config(uint32_t sync_mode);
|
||||||
|
/* configure the delay between 2 sampling phases in ADC sync modes */
|
||||||
|
void adc_sync_delay_config(uint32_t sample_delay);
|
||||||
|
/* configure ADC sync DMA mode selection */
|
||||||
|
void adc_sync_dma_config(uint32_t dma_mode );
|
||||||
|
/* configure ADC sync DMA engine is disabled after the end of transfer signal from DMA controller is detected */
|
||||||
|
void adc_sync_dma_request_after_last_enable(void);
|
||||||
|
/* configure ADC sync DMA engine issues requests according to the SYNCDMA bits */
|
||||||
|
void adc_sync_dma_request_after_last_disable(void);
|
||||||
|
/* read ADC sync routine data register */
|
||||||
|
uint32_t adc_sync_routine_data_read(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_ADC_H */
|
||||||
@@ -0,0 +1,749 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_can.h
|
||||||
|
\brief definitions for the CAN
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_CAN_H
|
||||||
|
#define GD32F4XX_CAN_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* CAN definitions */
|
||||||
|
#define CAN0 CAN_BASE /*!< CAN0 base address */
|
||||||
|
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */
|
||||||
|
#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */
|
||||||
|
#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/
|
||||||
|
#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */
|
||||||
|
#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */
|
||||||
|
#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */
|
||||||
|
#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */
|
||||||
|
#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */
|
||||||
|
#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */
|
||||||
|
#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */
|
||||||
|
#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */
|
||||||
|
#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */
|
||||||
|
#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */
|
||||||
|
#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */
|
||||||
|
#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */
|
||||||
|
#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */
|
||||||
|
#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */
|
||||||
|
#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */
|
||||||
|
#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */
|
||||||
|
#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */
|
||||||
|
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
||||||
|
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */
|
||||||
|
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
||||||
|
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
||||||
|
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
||||||
|
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */
|
||||||
|
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
||||||
|
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
||||||
|
#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */
|
||||||
|
#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */
|
||||||
|
#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */
|
||||||
|
#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */
|
||||||
|
#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */
|
||||||
|
#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */
|
||||||
|
#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */
|
||||||
|
#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */
|
||||||
|
#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */
|
||||||
|
#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */
|
||||||
|
#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */
|
||||||
|
#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */
|
||||||
|
#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */
|
||||||
|
#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */
|
||||||
|
#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */
|
||||||
|
#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */
|
||||||
|
#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */
|
||||||
|
#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */
|
||||||
|
#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */
|
||||||
|
#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */
|
||||||
|
#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */
|
||||||
|
#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */
|
||||||
|
#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */
|
||||||
|
#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */
|
||||||
|
#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */
|
||||||
|
#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */
|
||||||
|
#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */
|
||||||
|
#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */
|
||||||
|
#define CAN_F23DATA0(canx) REG32((canx) + 0x000002F8U) /*!< CAN filter 23 data 0 register */
|
||||||
|
#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */
|
||||||
|
#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */
|
||||||
|
#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */
|
||||||
|
#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */
|
||||||
|
#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */
|
||||||
|
#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */
|
||||||
|
#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */
|
||||||
|
#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */
|
||||||
|
#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */
|
||||||
|
#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */
|
||||||
|
#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */
|
||||||
|
#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */
|
||||||
|
#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */
|
||||||
|
#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */
|
||||||
|
#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */
|
||||||
|
#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */
|
||||||
|
#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */
|
||||||
|
#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */
|
||||||
|
#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */
|
||||||
|
#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */
|
||||||
|
#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */
|
||||||
|
#define CAN_F17DATA1(canx) REG32((canx) + 0x000002CCU) /*!< CAN filter 17 data 1 register */
|
||||||
|
#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */
|
||||||
|
#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */
|
||||||
|
#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */
|
||||||
|
#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */
|
||||||
|
#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */
|
||||||
|
#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */
|
||||||
|
#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */
|
||||||
|
#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */
|
||||||
|
#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */
|
||||||
|
#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */
|
||||||
|
|
||||||
|
/* CAN transmit mailbox bank */
|
||||||
|
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
||||||
|
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
|
||||||
|
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
|
||||||
|
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
|
||||||
|
|
||||||
|
/* CAN filter bank */
|
||||||
|
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
||||||
|
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
||||||
|
|
||||||
|
/* CAN receive FIFO mailbox bank */
|
||||||
|
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
||||||
|
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
||||||
|
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
||||||
|
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* CAN_CTL */
|
||||||
|
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
|
||||||
|
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
|
||||||
|
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
|
||||||
|
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
|
||||||
|
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
|
||||||
|
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
|
||||||
|
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
|
||||||
|
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
|
||||||
|
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
|
||||||
|
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
|
||||||
|
|
||||||
|
/* CAN_STAT */
|
||||||
|
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
|
||||||
|
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
|
||||||
|
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
|
||||||
|
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||||
|
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
|
||||||
|
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
|
||||||
|
#define CAN_STAT_RS BIT(9) /*!< receiving state */
|
||||||
|
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
|
||||||
|
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
|
||||||
|
|
||||||
|
/* CAN_TSTAT */
|
||||||
|
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
|
||||||
|
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
|
||||||
|
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
|
||||||
|
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
|
||||||
|
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
|
||||||
|
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
|
||||||
|
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
|
||||||
|
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
|
||||||
|
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
|
||||||
|
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
|
||||||
|
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
|
||||||
|
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
|
||||||
|
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
|
||||||
|
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
|
||||||
|
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
|
||||||
|
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
|
||||||
|
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
|
||||||
|
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
|
||||||
|
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
|
||||||
|
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
|
||||||
|
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
|
||||||
|
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
|
||||||
|
|
||||||
|
/* CAN_RFIFO0 */
|
||||||
|
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
|
||||||
|
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
|
||||||
|
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
|
||||||
|
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
|
||||||
|
|
||||||
|
/* CAN_RFIFO1 */
|
||||||
|
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
|
||||||
|
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
|
||||||
|
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
|
||||||
|
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
|
||||||
|
|
||||||
|
/* CAN_INTEN */
|
||||||
|
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
|
||||||
|
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
|
||||||
|
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
|
||||||
|
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
|
||||||
|
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
|
||||||
|
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
|
||||||
|
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
|
||||||
|
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
|
||||||
|
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
|
||||||
|
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
|
||||||
|
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
|
||||||
|
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
||||||
|
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
||||||
|
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
|
||||||
|
|
||||||
|
/* CAN_ERR */
|
||||||
|
#define CAN_ERR_WERR BIT(0) /*!< warning error */
|
||||||
|
#define CAN_ERR_PERR BIT(1) /*!< passive error */
|
||||||
|
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
|
||||||
|
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
|
||||||
|
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
|
||||||
|
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
|
||||||
|
|
||||||
|
/* CAN_BT */
|
||||||
|
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
|
||||||
|
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
|
||||||
|
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
|
||||||
|
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
|
||||||
|
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
|
||||||
|
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
|
||||||
|
|
||||||
|
/* CAN_TMIx */
|
||||||
|
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
|
||||||
|
#define CAN_TMI_FT BIT(1) /*!< frame type */
|
||||||
|
#define CAN_TMI_FF BIT(2) /*!< frame format */
|
||||||
|
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||||
|
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||||
|
|
||||||
|
/* CAN_TMPx */
|
||||||
|
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
|
||||||
|
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
|
||||||
|
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
|
||||||
|
|
||||||
|
/* CAN_TMDATA0x */
|
||||||
|
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
|
||||||
|
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
|
||||||
|
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
|
||||||
|
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
|
||||||
|
|
||||||
|
/* CAN_TMDATA1x */
|
||||||
|
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
|
||||||
|
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
|
||||||
|
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
|
||||||
|
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
|
||||||
|
|
||||||
|
/* CAN_RFIFOMIx */
|
||||||
|
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
|
||||||
|
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
|
||||||
|
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||||
|
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||||
|
|
||||||
|
/* CAN_RFIFOMPx */
|
||||||
|
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
|
||||||
|
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
|
||||||
|
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
|
||||||
|
|
||||||
|
/* CAN_RFIFOMDATA0x */
|
||||||
|
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
|
||||||
|
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
|
||||||
|
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
|
||||||
|
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
|
||||||
|
|
||||||
|
/* CAN_RFIFOMDATA1x */
|
||||||
|
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
|
||||||
|
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
|
||||||
|
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
|
||||||
|
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
|
||||||
|
|
||||||
|
/* CAN_FCTL */
|
||||||
|
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
|
||||||
|
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
|
||||||
|
|
||||||
|
/* CAN_FMCFG */
|
||||||
|
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */
|
||||||
|
|
||||||
|
/* CAN_FSCFG */
|
||||||
|
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */
|
||||||
|
|
||||||
|
/* CAN_FAFIFO */
|
||||||
|
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
|
||||||
|
|
||||||
|
/* CAN_FW */
|
||||||
|
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
|
||||||
|
|
||||||
|
/* CAN_FxDATAy */
|
||||||
|
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* define the CAN bit position and its register index offset */
|
||||||
|
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||||
|
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
||||||
|
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||||
|
|
||||||
|
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||||
|
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
|
||||||
|
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||||
|
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||||
|
|
||||||
|
/* register offset */
|
||||||
|
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
|
||||||
|
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
|
||||||
|
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
|
||||||
|
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
|
||||||
|
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
||||||
|
|
||||||
|
/* CAN flags */
|
||||||
|
typedef enum {
|
||||||
|
/* flags in STAT register */
|
||||||
|
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
||||||
|
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
||||||
|
CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */
|
||||||
|
CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */
|
||||||
|
CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */
|
||||||
|
CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */
|
||||||
|
CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */
|
||||||
|
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
||||||
|
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
||||||
|
/* flags in TSTAT register */
|
||||||
|
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */
|
||||||
|
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */
|
||||||
|
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */
|
||||||
|
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
||||||
|
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
||||||
|
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
||||||
|
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
|
||||||
|
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
|
||||||
|
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
|
||||||
|
CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */
|
||||||
|
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */
|
||||||
|
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */
|
||||||
|
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */
|
||||||
|
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */
|
||||||
|
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */
|
||||||
|
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
|
||||||
|
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
||||||
|
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
||||||
|
/* flags in RFIFO0 register */
|
||||||
|
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
||||||
|
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
||||||
|
/* flags in RFIFO1 register */
|
||||||
|
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
||||||
|
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
||||||
|
/* flags in ERR register */
|
||||||
|
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
||||||
|
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
||||||
|
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
||||||
|
} can_flag_enum;
|
||||||
|
|
||||||
|
/* CAN interrupt flags */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt flags in STAT register */
|
||||||
|
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
||||||
|
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||||
|
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
||||||
|
/* interrupt flags in TSTAT register */
|
||||||
|
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
||||||
|
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
||||||
|
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
||||||
|
/* interrupt flags in RFIFO0 register */
|
||||||
|
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
||||||
|
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
||||||
|
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */
|
||||||
|
/* interrupt flags in RFIFO0 register */
|
||||||
|
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
||||||
|
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
||||||
|
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */
|
||||||
|
/* interrupt flags in ERR register */
|
||||||
|
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
||||||
|
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
||||||
|
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */
|
||||||
|
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
||||||
|
} can_interrupt_flag_enum;
|
||||||
|
|
||||||
|
/* CAN initialize parameters structure */
|
||||||
|
typedef struct {
|
||||||
|
uint8_t working_mode; /*!< CAN working mode */
|
||||||
|
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
||||||
|
uint8_t time_segment_1; /*!< time segment 1 */
|
||||||
|
uint8_t time_segment_2; /*!< time segment 2 */
|
||||||
|
ControlStatus time_triggered; /*!< time triggered communication mode */
|
||||||
|
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
||||||
|
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
||||||
|
ControlStatus auto_retrans; /*!< automatic retransmission mode */
|
||||||
|
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
||||||
|
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
||||||
|
uint16_t prescaler; /*!< baudrate prescaler */
|
||||||
|
} can_parameter_struct;
|
||||||
|
|
||||||
|
/* CAN transmit message structure */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t tx_sfid; /*!< standard format frame identifier */
|
||||||
|
uint32_t tx_efid; /*!< extended format frame identifier */
|
||||||
|
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
||||||
|
uint8_t tx_ft; /*!< type of frame, data or remote */
|
||||||
|
uint8_t tx_dlen; /*!< data length */
|
||||||
|
uint8_t tx_data[8]; /*!< transmit data */
|
||||||
|
} can_transmit_message_struct;
|
||||||
|
|
||||||
|
/* CAN receive message structure */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t rx_sfid; /*!< standard format frame identifier */
|
||||||
|
uint32_t rx_efid; /*!< extended format frame identifier */
|
||||||
|
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
||||||
|
uint8_t rx_ft; /*!< type of frame, data or remote */
|
||||||
|
uint8_t rx_dlen; /*!< data length */
|
||||||
|
uint8_t rx_data[8]; /*!< receive data */
|
||||||
|
uint8_t rx_fi; /*!< filtering index */
|
||||||
|
} can_receive_message_struct;
|
||||||
|
|
||||||
|
/* CAN filter parameters structure */
|
||||||
|
typedef struct {
|
||||||
|
uint16_t filter_list_high; /*!< filter list number high bits */
|
||||||
|
uint16_t filter_list_low; /*!< filter list number low bits */
|
||||||
|
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
||||||
|
uint16_t filter_mask_low; /*!< filter mask number low bits */
|
||||||
|
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
|
||||||
|
uint16_t filter_number; /*!< filter number */
|
||||||
|
uint16_t filter_mode; /*!< filter mode, list or mask */
|
||||||
|
uint16_t filter_bits; /*!< filter scale */
|
||||||
|
ControlStatus filter_enable; /*!< filter work or not */
|
||||||
|
} can_filter_parameter_struct;
|
||||||
|
|
||||||
|
/* CAN errors */
|
||||||
|
typedef enum {
|
||||||
|
CAN_ERROR_NONE = 0, /*!< no error */
|
||||||
|
CAN_ERROR_FILL, /*!< fill error */
|
||||||
|
CAN_ERROR_FORMAT, /*!< format error */
|
||||||
|
CAN_ERROR_ACK, /*!< ACK error */
|
||||||
|
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
|
||||||
|
CAN_ERROR_BITDOMINANT, /*!< bit dominant error */
|
||||||
|
CAN_ERROR_CRC, /*!< CRC error */
|
||||||
|
CAN_ERROR_SOFTWARECFG, /*!< software configuration */
|
||||||
|
} can_error_enum;
|
||||||
|
|
||||||
|
/* transmit states */
|
||||||
|
typedef enum {
|
||||||
|
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
||||||
|
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
||||||
|
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
||||||
|
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
||||||
|
} can_transmit_state_enum;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
CAN_INIT_STRUCT = 0U, /* CAN initialize parameters struct */
|
||||||
|
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
||||||
|
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
||||||
|
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
|
||||||
|
} can_struct_type_enum;
|
||||||
|
|
||||||
|
/* CAN baudrate prescaler */
|
||||||
|
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* CAN bit segment 1 */
|
||||||
|
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||||
|
|
||||||
|
/* CAN bit segment 2 */
|
||||||
|
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
||||||
|
|
||||||
|
/* CAN resynchronization jump width */
|
||||||
|
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
|
||||||
|
|
||||||
|
/* CAN communication mode */
|
||||||
|
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
|
||||||
|
|
||||||
|
/* CAN FDATA high 16 bits */
|
||||||
|
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
|
||||||
|
|
||||||
|
/* CAN FDATA low 16 bits */
|
||||||
|
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* CAN1 filter start bank_number */
|
||||||
|
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
||||||
|
|
||||||
|
/* CAN transmit mailbox extended identifier */
|
||||||
|
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
|
||||||
|
|
||||||
|
/* CAN transmit mailbox standard identifier */
|
||||||
|
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
|
||||||
|
|
||||||
|
/* transmit data byte 0 */
|
||||||
|
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* transmit data byte 1 */
|
||||||
|
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||||
|
|
||||||
|
/* transmit data byte 2 */
|
||||||
|
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||||
|
|
||||||
|
/* transmit data byte 3 */
|
||||||
|
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||||
|
|
||||||
|
/* transmit data byte 4 */
|
||||||
|
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* transmit data byte 5 */
|
||||||
|
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||||
|
|
||||||
|
/* transmit data byte 6 */
|
||||||
|
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||||
|
|
||||||
|
/* transmit data byte 7 */
|
||||||
|
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||||
|
|
||||||
|
/* receive mailbox extended identifier */
|
||||||
|
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
||||||
|
|
||||||
|
/* receive mailbox standard identifier */
|
||||||
|
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
||||||
|
|
||||||
|
/* receive data length */
|
||||||
|
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
|
||||||
|
|
||||||
|
/* the index of the filter by which the frame is passed */
|
||||||
|
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||||
|
|
||||||
|
/* receive data byte 0 */
|
||||||
|
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||||
|
|
||||||
|
/* receive data byte 1 */
|
||||||
|
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||||
|
|
||||||
|
/* receive data byte 2 */
|
||||||
|
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||||
|
|
||||||
|
/* receive data byte 3 */
|
||||||
|
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||||
|
|
||||||
|
/* receive data byte 4 */
|
||||||
|
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||||
|
|
||||||
|
/* receive data byte 5 */
|
||||||
|
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||||
|
|
||||||
|
/* receive data byte 6 */
|
||||||
|
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||||
|
|
||||||
|
/* receive data byte 7 */
|
||||||
|
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||||
|
|
||||||
|
/* error number */
|
||||||
|
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U)
|
||||||
|
|
||||||
|
/* transmit error count */
|
||||||
|
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||||
|
|
||||||
|
/* receive error count */
|
||||||
|
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||||
|
|
||||||
|
/* CAN errors */
|
||||||
|
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||||
|
#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */
|
||||||
|
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
||||||
|
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
||||||
|
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
||||||
|
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */
|
||||||
|
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */
|
||||||
|
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */
|
||||||
|
#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */
|
||||||
|
|
||||||
|
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
|
||||||
|
|
||||||
|
/* CAN communication mode */
|
||||||
|
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
|
||||||
|
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
|
||||||
|
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
|
||||||
|
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
|
||||||
|
|
||||||
|
/* CAN resynchronization jump width */
|
||||||
|
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||||
|
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||||
|
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||||
|
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||||
|
|
||||||
|
/* CAN time segment 1 */
|
||||||
|
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||||
|
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||||
|
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||||
|
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||||
|
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||||
|
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||||
|
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||||
|
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||||
|
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
|
||||||
|
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
|
||||||
|
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
||||||
|
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
|
||||||
|
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
||||||
|
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
||||||
|
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
|
||||||
|
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
||||||
|
|
||||||
|
/* CAN time segment 2 */
|
||||||
|
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||||
|
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||||
|
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||||
|
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||||
|
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||||
|
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||||
|
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||||
|
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||||
|
|
||||||
|
/* CAN mailbox number */
|
||||||
|
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
||||||
|
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
||||||
|
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
||||||
|
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
||||||
|
|
||||||
|
/* CAN frame format */
|
||||||
|
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
||||||
|
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
||||||
|
|
||||||
|
/* CAN receive FIFO */
|
||||||
|
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
||||||
|
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
||||||
|
|
||||||
|
/* frame number of receive FIFO */
|
||||||
|
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
||||||
|
|
||||||
|
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
||||||
|
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
||||||
|
|
||||||
|
/* CAN working mode */
|
||||||
|
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
||||||
|
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
||||||
|
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
||||||
|
|
||||||
|
/* filter bits */
|
||||||
|
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
|
||||||
|
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
|
||||||
|
|
||||||
|
/* filter mode */
|
||||||
|
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
|
||||||
|
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
|
||||||
|
|
||||||
|
/* filter 16 bits mask */
|
||||||
|
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
|
||||||
|
|
||||||
|
/* frame type */
|
||||||
|
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
|
||||||
|
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
|
||||||
|
|
||||||
|
/* CAN timeout */
|
||||||
|
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
|
||||||
|
|
||||||
|
/* CAN mailbox empty status mask */
|
||||||
|
#define CAN_ALL_MAILBOX_EMPTY ((uint32_t)0x1C000000U) /*!< CAN mailbox empty status mask */
|
||||||
|
|
||||||
|
/* interrupt enable bits */
|
||||||
|
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
|
||||||
|
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
|
||||||
|
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
|
||||||
|
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
|
||||||
|
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
|
||||||
|
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
|
||||||
|
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
|
||||||
|
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
|
||||||
|
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
|
||||||
|
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
|
||||||
|
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
|
||||||
|
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
|
||||||
|
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
|
||||||
|
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* deinitialize CAN */
|
||||||
|
void can_deinit(uint32_t can_periph);
|
||||||
|
/* initialize CAN structure */
|
||||||
|
void can_struct_para_init(can_struct_type_enum type, void *p_struct);
|
||||||
|
/* initialize CAN */
|
||||||
|
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
|
||||||
|
/* CAN filter initialization */
|
||||||
|
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
|
||||||
|
|
||||||
|
/* function configuration */
|
||||||
|
/* set can1 filter start bank number */
|
||||||
|
void can1_filter_start_bank(uint8_t start_bank);
|
||||||
|
/* enable functions */
|
||||||
|
/* CAN debug freeze enable */
|
||||||
|
void can_debug_freeze_enable(uint32_t can_periph);
|
||||||
|
/* CAN debug freeze disable */
|
||||||
|
void can_debug_freeze_disable(uint32_t can_periph);
|
||||||
|
/* CAN time trigger mode enable */
|
||||||
|
void can_time_trigger_mode_enable(uint32_t can_periph);
|
||||||
|
/* CAN time trigger mode disable */
|
||||||
|
void can_time_trigger_mode_disable(uint32_t can_periph);
|
||||||
|
|
||||||
|
/* transmit functions */
|
||||||
|
/* transmit CAN message */
|
||||||
|
uint8_t can_message_transmit(uint32_t can_periph, can_transmit_message_struct *transmit_message);
|
||||||
|
/* get CAN transmit state */
|
||||||
|
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
|
||||||
|
/* stop CAN transmission */
|
||||||
|
ErrStatus can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
||||||
|
/* CAN receive message */
|
||||||
|
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
|
||||||
|
/* CAN release FIFO */
|
||||||
|
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
||||||
|
/* CAN receive message length */
|
||||||
|
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
||||||
|
/* CAN working mode */
|
||||||
|
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
||||||
|
/* CAN wakeup from sleep mode */
|
||||||
|
ErrStatus can_wakeup(uint32_t can_periph);
|
||||||
|
|
||||||
|
/* CAN get error type */
|
||||||
|
can_error_enum can_error_get(uint32_t can_periph);
|
||||||
|
/* get CAN receive error number */
|
||||||
|
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
||||||
|
/* get CAN transmit error number */
|
||||||
|
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* CAN get flag state */
|
||||||
|
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
||||||
|
/* CAN clear flag state */
|
||||||
|
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
||||||
|
/* CAN interrupt enable */
|
||||||
|
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
||||||
|
/* CAN interrupt disable */
|
||||||
|
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
||||||
|
/* CAN get interrupt flag state */
|
||||||
|
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||||
|
/* CAN clear interrupt flag state */
|
||||||
|
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_CAN_H */
|
||||||
@@ -0,0 +1,78 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_crc.h
|
||||||
|
\brief definitions for the CRC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_CRC_H
|
||||||
|
#define GD32F4XX_CRC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* CRC definitions */
|
||||||
|
#define CRC CRC_BASE /*!< CRC base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define CRC_DATA REG32(CRC + 0x00000000U) /*!< CRC data register */
|
||||||
|
#define CRC_FDATA REG32(CRC + 0x00000004U) /*!< CRC free data register */
|
||||||
|
#define CRC_CTL REG32(CRC + 0x00000008U) /*!< CRC control register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* CRC_DATA */
|
||||||
|
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||||
|
|
||||||
|
/* CRC_FDATA */
|
||||||
|
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||||
|
|
||||||
|
/* CRC_CTL */
|
||||||
|
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||||
|
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* deinit CRC calculation unit */
|
||||||
|
void crc_deinit(void);
|
||||||
|
|
||||||
|
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||||
|
void crc_data_register_reset(void);
|
||||||
|
/* read the value of the data register */
|
||||||
|
uint32_t crc_data_register_read(void);
|
||||||
|
|
||||||
|
/* read the value of the free data register */
|
||||||
|
uint8_t crc_free_data_register_read(void);
|
||||||
|
/* write data to the free data register */
|
||||||
|
void crc_free_data_register_write(uint8_t free_data);
|
||||||
|
|
||||||
|
/* calculate the CRC value of a 32-bit data */
|
||||||
|
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||||
|
/* calculate the CRC value of an array of 32-bit values */
|
||||||
|
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_CRC_H */
|
||||||
@@ -0,0 +1,182 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_ctc.h
|
||||||
|
\brief definitions for the CTC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_CTC_H
|
||||||
|
#define GD32F4XX_CTC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* CTC definitions */
|
||||||
|
#define CTC CTC_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define CTC_CTL0 REG32((CTC) + 0x00U) /*!< CTC control register 0 */
|
||||||
|
#define CTC_CTL1 REG32((CTC) + 0x04U) /*!< CTC control register 1 */
|
||||||
|
#define CTC_STAT REG32((CTC) + 0x08U) /*!< CTC status register */
|
||||||
|
#define CTC_INTC REG32((CTC) + 0x0CU) /*!< CTC interrupt clear register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* CTC_CTL0 */
|
||||||
|
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||||
|
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||||
|
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||||
|
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||||
|
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||||
|
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||||
|
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||||
|
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||||
|
|
||||||
|
/* CTC_CTL1 */
|
||||||
|
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||||
|
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||||
|
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||||
|
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||||
|
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||||
|
|
||||||
|
/* CTC_STAT */
|
||||||
|
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||||
|
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||||
|
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||||
|
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||||
|
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||||
|
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||||
|
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||||
|
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||||
|
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||||
|
|
||||||
|
/* CTC_INTC */
|
||||||
|
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||||
|
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||||
|
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||||
|
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* hardware automatically trim mode definitions */
|
||||||
|
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||||
|
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||||
|
|
||||||
|
/* reference signal source polarity definitions */
|
||||||
|
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||||
|
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||||
|
|
||||||
|
/* reference signal source selection definitions */
|
||||||
|
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||||
|
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||||
|
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is clock selected */
|
||||||
|
|
||||||
|
/* reference signal source prescaler definitions */
|
||||||
|
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||||
|
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||||
|
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||||
|
|
||||||
|
/* CTC interrupt enable definitions */
|
||||||
|
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||||
|
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||||
|
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||||
|
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||||
|
|
||||||
|
/* CTC interrupt source definitions */
|
||||||
|
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||||
|
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||||
|
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||||
|
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||||
|
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||||
|
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||||
|
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||||
|
|
||||||
|
/* CTC flag definitions */
|
||||||
|
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||||
|
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||||
|
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||||
|
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||||
|
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||||
|
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||||
|
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* reset ctc clock trim controller */
|
||||||
|
void ctc_deinit(void);
|
||||||
|
/* enable CTC trim counter */
|
||||||
|
void ctc_counter_enable(void);
|
||||||
|
/* disable CTC trim counter */
|
||||||
|
void ctc_counter_disable(void);
|
||||||
|
|
||||||
|
/* configure the IRC48M trim value */
|
||||||
|
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||||
|
/* generate software reference source sync pulse */
|
||||||
|
void ctc_software_refsource_pulse_generate(void);
|
||||||
|
/* configure hardware automatically trim mode */
|
||||||
|
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||||
|
|
||||||
|
/* configure reference signal source polarity */
|
||||||
|
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||||
|
/* select reference signal source */
|
||||||
|
void ctc_refsource_signal_select(uint32_t refs);
|
||||||
|
/* configure reference signal source prescaler */
|
||||||
|
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||||
|
/* configure clock trim base limit value */
|
||||||
|
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||||
|
/* configure CTC counter reload value */
|
||||||
|
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||||
|
|
||||||
|
/* read CTC counter capture value when reference sync pulse occurred */
|
||||||
|
uint16_t ctc_counter_capture_value_read(void);
|
||||||
|
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||||
|
FlagStatus ctc_counter_direction_read(void);
|
||||||
|
/* read CTC counter reload value */
|
||||||
|
uint16_t ctc_counter_reload_value_read(void);
|
||||||
|
/* read the IRC48M trim value */
|
||||||
|
uint8_t ctc_irc48m_trim_value_read(void);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* enable the CTC interrupt */
|
||||||
|
void ctc_interrupt_enable(uint32_t interrupt);
|
||||||
|
/* disable the CTC interrupt */
|
||||||
|
void ctc_interrupt_disable(uint32_t interrupt);
|
||||||
|
/* get CTC interrupt flag */
|
||||||
|
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
|
||||||
|
/* clear CTC interrupt flag */
|
||||||
|
void ctc_interrupt_flag_clear(uint32_t int_flag);
|
||||||
|
/* get CTC flag */
|
||||||
|
FlagStatus ctc_flag_get(uint32_t flag);
|
||||||
|
/* clear CTC flag */
|
||||||
|
void ctc_flag_clear(uint32_t flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_CTC_H */
|
||||||
@@ -0,0 +1,277 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dac.h
|
||||||
|
\brief definitions for the DAC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_DAC_H
|
||||||
|
#define GD32F4XX_DAC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* DACx(x=0) definitions */
|
||||||
|
#define DAC0 (DAC_BASE)
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define DAC_CTL0(dacx) REG32((dacx) + 0x00000000U) /*!< DACx control register 0 */
|
||||||
|
#define DAC_SWT(dacx) REG32((dacx) + 0x00000004U) /*!< DACx software trigger register */
|
||||||
|
#define DAC_OUT0_R12DH(dacx) REG32((dacx) + 0x00000008U) /*!< DACx_OUT0 12-bit right-aligned data holding register */
|
||||||
|
#define DAC_OUT0_L12DH(dacx) REG32((dacx) + 0x0000000CU) /*!< DACx_OUT0 12-bit left-aligned data holding register */
|
||||||
|
#define DAC_OUT0_R8DH(dacx) REG32((dacx) + 0x00000010U) /*!< DACx_OUT0 8-bit right-aligned data holding register */
|
||||||
|
#define DAC_OUT1_R12DH(dacx) REG32((dacx) + 0x00000014U) /*!< DACx_OUT1 12-bit right-aligned data holding register */
|
||||||
|
#define DAC_OUT1_L12DH(dacx) REG32((dacx) + 0x00000018U) /*!< DACx_OUT1 12-bit left-aligned data holding register */
|
||||||
|
#define DAC_OUT1_R8DH(dacx) REG32((dacx) + 0x0000001CU) /*!< DACx_OUT1 8-bit right-aligned data holding register */
|
||||||
|
#define DACC_R12DH(dacx) REG32((dacx) + 0x00000020U) /*!< DACx concurrent mode 12-bit right-aligned data holding register */
|
||||||
|
#define DACC_L12DH(dacx) REG32((dacx) + 0x00000024U) /*!< DACx concurrent mode 12-bit left-aligned data holding register */
|
||||||
|
#define DACC_R8DH(dacx) REG32((dacx) + 0x00000028U) /*!< DACx concurrent mode 8-bit right-aligned data holding register */
|
||||||
|
#define DAC_OUT0_DO(dacx) REG32((dacx) + 0x0000002CU) /*!< DACx_OUT0 data output register */
|
||||||
|
#define DAC_OUT1_DO(dacx) REG32((dacx) + 0x00000030U) /*!< DACx_OUT1 data output register */
|
||||||
|
#define DAC_STAT0(dacx) REG32((dacx) + 0x00000034U) /*!< DACx status register 0 */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* DAC_CTL0 */
|
||||||
|
#define DAC_CTL0_DEN0 BIT(0) /*!< DACx_OUT0 enable */
|
||||||
|
#define DAC_CTL0_DBOFF0 BIT(1) /*!< DACx_OUT0 output buffer turn off */
|
||||||
|
#define DAC_CTL0_DTEN0 BIT(2) /*!< DACx_OUT0 trigger enable */
|
||||||
|
#define DAC_CTL0_DTSEL0 BITS(3,5) /*!< DACx_OUT0 trigger selection */
|
||||||
|
#define DAC_CTL0_DWM0 BITS(6,7) /*!< DACx_OUT0 noise wave mode */
|
||||||
|
#define DAC_CTL0_DWBW0 BITS(8,11) /*!< DACx_OUT0 noise wave bit width */
|
||||||
|
#define DAC_CTL0_DDMAEN0 BIT(12) /*!< DACx_OUT0 DMA enable */
|
||||||
|
#define DAC_CTL0_DDUDRIE0 BIT(13) /*!< DACx_OUT0 DMA underrun interrupt enable */
|
||||||
|
|
||||||
|
#define DAC_CTL0_DEN1 BIT(16) /*!< DACx_OUT1 enable */
|
||||||
|
#define DAC_CTL0_DBOFF1 BIT(17) /*!< DACx_OUT1 output buffer turn off */
|
||||||
|
#define DAC_CTL0_DTEN1 BIT(18) /*!< DACx_OUT1 trigger enable */
|
||||||
|
#define DAC_CTL0_DTSEL1 BITS(19,21) /*!< DACx_OUT1 trigger selection */
|
||||||
|
#define DAC_CTL0_DWM1 BITS(22,23) /*!< DACx_OUT1 noise wave mode */
|
||||||
|
#define DAC_CTL0_DWBW1 BITS(24,27) /*!< DACx_OUT1 noise wave bit width */
|
||||||
|
#define DAC_CTL0_DDMAEN1 BIT(28) /*!< DACx_OUT1 DMA enable */
|
||||||
|
#define DAC_CTL0_DDUDRIE1 BIT(29) /*!< DACx_OUT1 DMA underrun interrupt enable */
|
||||||
|
|
||||||
|
/* DAC_SWT */
|
||||||
|
#define DAC_SWT_SWTR0 BIT(0) /*!< DACx_OUT0 software trigger */
|
||||||
|
#define DAC_SWT_SWTR1 BIT(1) /*!< DACx_OUT1 software trigger */
|
||||||
|
|
||||||
|
/* DAC0_OUT0_R12DH */
|
||||||
|
#define DAC_OUT0_DH_R12 BITS(0,11) /*!< DACx_OUT0 12-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DAC0_OUT0_L12DH */
|
||||||
|
#define DAC_OUT0_DH_L12 BITS(4,15) /*!< DACx_OUT0 12-bit left-aligned data */
|
||||||
|
|
||||||
|
/* DAC0_OUT0_R8DH */
|
||||||
|
#define DAC_OUT0_DH_R8 BITS(0,7) /*!< DACx_OUT0 8-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DAC1_OUT1_R12DH */
|
||||||
|
#define DAC_OUT1_DH_R12 BITS(0,11) /*!< DACx_OUT1 12-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DAC1_OUT1_L12DH */
|
||||||
|
#define DAC_OUT1_DH_L12 BITS(4,15) /*!< DACx_OUT1 12-bit left-aligned data */
|
||||||
|
|
||||||
|
/* DAC1_OUT1_R8DH */
|
||||||
|
#define DAC_OUT1_DH_R8 BITS(0,7) /*!< DACx_OUT1 8-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DACC_R12DH */
|
||||||
|
#define DACC_OUT0_DH_R12 BITS(0,11) /*!< DAC concurrent mode DACx_OUT0 12-bit right-aligned data */
|
||||||
|
#define DACC_OUT1_DH_R12 BITS(16,27) /*!< DAC concurrent mode DACx_OUT1 12-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DACC_L12DH */
|
||||||
|
#define DACC_OUT0_DH_L12 BITS(4,15) /*!< DAC concurrent mode DACx_OUT0 12-bit left-aligned data */
|
||||||
|
#define DACC_OUT1_DH_L12 BITS(20,31) /*!< DAC concurrent mode DACx_OUT1 12-bit left-aligned data */
|
||||||
|
|
||||||
|
/* DACC_R8DH */
|
||||||
|
#define DACC_OUT0_DH_R8 BITS(0,7) /*!< DAC concurrent mode DACx_OUT0 8-bit right-aligned data */
|
||||||
|
#define DACC_OUT1_DH_R8 BITS(8,15) /*!< DAC concurrent mode DACx_OUT1 8-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DAC0_OUT0_DO */
|
||||||
|
#define DAC_OUT0_DO_BITS BITS(0,11) /*!< DACx_OUT0 12-bit output data */
|
||||||
|
|
||||||
|
/* DAC1_OUT1_DO */
|
||||||
|
#define DAC_OUT1_DO_BITS BITS(0,11) /*!< DACx_OUT1 12-bit output data */
|
||||||
|
|
||||||
|
/* DAC_STAT0 */
|
||||||
|
#define DAC_STAT0_DDUDR0 BIT(13) /*!< DACx_OUT0 DMA underrun flag */
|
||||||
|
#define DAC_STAT0_DDUDR1 BIT(29) /*!< DACx_OUT1 DMA underrun flag */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* DAC trigger source */
|
||||||
|
#define CTL0_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||||
|
#define DAC_TRIGGER_T5_TRGO CTL0_DTSEL(0) /*!< TIMER5 TRGO */
|
||||||
|
#define DAC_TRIGGER_T7_TRGO CTL0_DTSEL(1) /*!< TIMER7 TRGO */
|
||||||
|
#define DAC_TRIGGER_T6_TRGO CTL0_DTSEL(2) /*!< TIMER6 TRGO */
|
||||||
|
#define DAC_TRIGGER_T4_TRGO CTL0_DTSEL(3) /*!< TIMER4 TRGO */
|
||||||
|
#define DAC_TRIGGER_T1_TRGO CTL0_DTSEL(4) /*!< TIMER1 TRGO */
|
||||||
|
#define DAC_TRIGGER_T3_TRGO CTL0_DTSEL(5) /*!< TIMER3 TRGO */
|
||||||
|
#define DAC_TRIGGER_EXTI_9 CTL0_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||||
|
#define DAC_TRIGGER_SOFTWARE CTL0_DTSEL(7) /*!< software trigger */
|
||||||
|
|
||||||
|
/* DAC noise wave mode */
|
||||||
|
#define CTL0_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||||
|
#define DAC_WAVE_DISABLE CTL0_DWM(0) /*!< wave disabled */
|
||||||
|
#define DAC_WAVE_MODE_LFSR CTL0_DWM(1) /*!< LFSR noise mode */
|
||||||
|
#define DAC_WAVE_MODE_TRIANGLE CTL0_DWM(2) /*!< triangle noise mode */
|
||||||
|
|
||||||
|
/* DAC noise wave bit width */
|
||||||
|
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||||
|
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||||
|
|
||||||
|
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||||
|
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||||
|
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||||
|
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||||
|
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||||
|
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||||
|
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||||
|
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||||
|
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||||
|
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||||
|
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||||
|
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||||
|
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||||
|
|
||||||
|
/* triangle amplitude in DAC triangle noise mode */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||||
|
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||||
|
|
||||||
|
/* DAC data alignment */
|
||||||
|
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< 12-bit right-aligned data */
|
||||||
|
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< 12-bit left-aligned data */
|
||||||
|
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< 8-bit right-aligned data */
|
||||||
|
|
||||||
|
/* DAC output channel definitions */
|
||||||
|
#define DAC_OUT0 ((uint8_t)0x00U) /*!< DACx_OUT0 channel */
|
||||||
|
#define DAC_OUT1 ((uint8_t)0x01U) /*!< DACx_OUT1 channel */
|
||||||
|
|
||||||
|
/* DAC interrupt */
|
||||||
|
#define DAC_INT_DDUDR0 DAC_CTL0_DDUDRIE0 /*!< DACx_OUT0 DMA underrun interrupt */
|
||||||
|
#define DAC_INT_DDUDR1 DAC_CTL0_DDUDRIE1 /*!< DACx_OUT1 DMA underrun interrupt */
|
||||||
|
|
||||||
|
/* DAC interrupt flag */
|
||||||
|
#define DAC_INT_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun interrupt flag */
|
||||||
|
#define DAC_INT_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun interrupt flag */
|
||||||
|
|
||||||
|
/* DAC flags */
|
||||||
|
#define DAC_FLAG_DDUDR0 DAC_STAT0_DDUDR0 /*!< DACx_OUT0 DMA underrun flag */
|
||||||
|
#define DAC_FLAG_DDUDR1 DAC_STAT0_DDUDR1 /*!< DACx_OUT1 DMA underrun flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* DAC initialization functions */
|
||||||
|
/* deinitialize DAC */
|
||||||
|
void dac_deinit(uint32_t dac_periph);
|
||||||
|
/* enable DAC */
|
||||||
|
void dac_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* disable DAC */
|
||||||
|
void dac_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* enable DAC DMA function */
|
||||||
|
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* disable DAC DMA function */
|
||||||
|
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
|
||||||
|
/* DAC buffer functions */
|
||||||
|
/* enable DAC output buffer */
|
||||||
|
void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* disable DAC output buffer */
|
||||||
|
void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
|
||||||
|
/* read and write operation functions */
|
||||||
|
/* get DAC output value */
|
||||||
|
uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* set DAC data holding register value */
|
||||||
|
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data);
|
||||||
|
|
||||||
|
/* DAC trigger configuration */
|
||||||
|
/* enable DAC trigger */
|
||||||
|
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* disable DAC trigger */
|
||||||
|
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
/* configure DAC trigger source */
|
||||||
|
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource);
|
||||||
|
/* enable DAC software trigger */
|
||||||
|
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out);
|
||||||
|
|
||||||
|
/* DAC wave mode configuration */
|
||||||
|
/* configure DAC wave mode */
|
||||||
|
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode);
|
||||||
|
/* configure DAC LFSR noise mode */
|
||||||
|
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits);
|
||||||
|
/* configure DAC triangle noise mode */
|
||||||
|
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude);
|
||||||
|
|
||||||
|
/* DAC concurrent mode configuration */
|
||||||
|
/* enable DAC concurrent mode */
|
||||||
|
void dac_concurrent_enable(uint32_t dac_periph);
|
||||||
|
/* disable DAC concurrent mode */
|
||||||
|
void dac_concurrent_disable(uint32_t dac_periph);
|
||||||
|
/* enable DAC concurrent software trigger */
|
||||||
|
void dac_concurrent_software_trigger_enable(uint32_t dac_periph);
|
||||||
|
/* enable DAC concurrent buffer function */
|
||||||
|
void dac_concurrent_output_buffer_enable(uint32_t dac_periph);
|
||||||
|
/* disable DAC concurrent buffer function */
|
||||||
|
void dac_concurrent_output_buffer_disable(uint32_t dac_periph);
|
||||||
|
/* set DAC concurrent mode data holding register value */
|
||||||
|
void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||||
|
|
||||||
|
/* DAC interrupt and flag functions */
|
||||||
|
/* get DAC flag */
|
||||||
|
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag);
|
||||||
|
/* clear DAC flag */
|
||||||
|
void dac_flag_clear(uint32_t dac_periph, uint32_t flag);
|
||||||
|
/* enable DAC interrupt */
|
||||||
|
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt);
|
||||||
|
/* disable DAC interrupt */
|
||||||
|
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt);
|
||||||
|
/* get DAC interrupt flag */
|
||||||
|
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag);
|
||||||
|
/* clear DAC interrupt flag */
|
||||||
|
void dac_interrupt_flag_clear(uint32_t dac_periph, uint32_t int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_DAC_H */
|
||||||
@@ -0,0 +1,150 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dbg.h
|
||||||
|
\brief definitions for the DBG
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_DBG_H
|
||||||
|
#define GD32F4XX_DBG_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* DBG definitions */
|
||||||
|
#define DBG DBG_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||||
|
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||||
|
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||||
|
#define DBG_CTL2 REG32(DBG + 0x0CU) /*!< DBG control register 2 */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* DBG_ID */
|
||||||
|
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||||
|
|
||||||
|
/* DBG_CTL0 */
|
||||||
|
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||||
|
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||||
|
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||||
|
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||||
|
|
||||||
|
/* DBG_CTL1 */
|
||||||
|
#define DBG_CTL1_TIMER1_HOLD BIT(0) /*!< hold TIMER1 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER2_HOLD BIT(1) /*!< hold TIMER2 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER3_HOLD BIT(2) /*!< hold TIMER3 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER4_HOLD BIT(3) /*!< hold TIMER4 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER5_HOLD BIT(4) /*!< hold TIMER5 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER6_HOLD BIT(5) /*!< hold TIMER6 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER11_HOLD BIT(6) /*!< hold TIMER11 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER12_HOLD BIT(7) /*!< hold TIMER12 counter when core is halted */
|
||||||
|
#define DBG_CTL1_TIMER13_HOLD BIT(8) /*!< hold TIMER13 counter when core is halted */
|
||||||
|
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||||
|
#define DBG_CTL1_WWDGT_HOLD BIT(11) /*!< debug WWDGT kept when core is halted */
|
||||||
|
#define DBG_CTL1_FWDGT_HOLD BIT(12) /*!< debug FWDGT kept when core is halted */
|
||||||
|
#define DBG_CTL1_I2C0_HOLD BIT(21) /*!< hold I2C0 smbus when core is halted */
|
||||||
|
#define DBG_CTL1_I2C1_HOLD BIT(22) /*!< hold I2C1 smbus when core is halted */
|
||||||
|
#define DBG_CTL1_I2C2_HOLD BIT(23) /*!< hold I2C2 smbus when core is halted */
|
||||||
|
#define DBG_CTL1_CAN0_HOLD BIT(25) /*!< debug CAN0 kept when core is halted */
|
||||||
|
#define DBG_CTL1_CAN1_HOLD BIT(26) /*!< debug CAN1 kept when core is halted */
|
||||||
|
|
||||||
|
/* DBG_CTL2 */
|
||||||
|
#define DBG_CTL2_TIMER0_HOLD BIT(0) /*!< hold TIMER0 counter when core is halted */
|
||||||
|
#define DBG_CTL2_TIMER7_HOLD BIT(1) /*!< hold TIMER7 counter when core is halted */
|
||||||
|
#define DBG_CTL2_TIMER8_HOLD BIT(16) /*!< hold TIMER8 counter when core is halted */
|
||||||
|
#define DBG_CTL2_TIMER9_HOLD BIT(17) /*!< hold TIMER9 counter when core is halted */
|
||||||
|
#define DBG_CTL2_TIMER10_HOLD BIT(18) /*!< hold TIMER10 counter when core is halted */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||||
|
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||||
|
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||||
|
|
||||||
|
/* define the peripheral debug hold bit position and its register index offset */
|
||||||
|
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||||
|
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||||
|
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||||
|
|
||||||
|
/* register index */
|
||||||
|
enum dbg_reg_idx
|
||||||
|
{
|
||||||
|
DBG_IDX_CTL0 = 0x04U,
|
||||||
|
DBG_IDX_CTL1 = 0x08U,
|
||||||
|
DBG_IDX_CTL2 = 0x0CU
|
||||||
|
};
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 0U), /*!< hold TIMER1 counter when core is halted */
|
||||||
|
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 1U), /*!< hold TIMER2 counter when core is halted */
|
||||||
|
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 2U), /*!< hold TIMER3 counter when core is halted */
|
||||||
|
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 3U), /*!< hold TIMER4 counter when core is halted */
|
||||||
|
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 4U), /*!< hold TIMER5 counter when core is halted */
|
||||||
|
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 5U), /*!< hold TIMER6 counter when core is halted */
|
||||||
|
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 6U), /*!< hold TIMER11 counter when core is halted */
|
||||||
|
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 7U), /*!< hold TIMER12 counter when core is halted */
|
||||||
|
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 8U), /*!< hold TIMER13 counter when core is halted */
|
||||||
|
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||||
|
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 11U), /*!< debug WWDGT kept when core is halted */
|
||||||
|
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 12U), /*!< debug FWDGT kept when core is halted */
|
||||||
|
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 21U), /*!< hold I2C0 smbus when core is halted */
|
||||||
|
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 22U), /*!< hold I2C1 smbus when core is halted */
|
||||||
|
DBG_I2C2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 23U), /*!< hold I2C2 smbus when core is halted */
|
||||||
|
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 25U), /*!< debug CAN0 kept when core is halted */
|
||||||
|
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 26U), /*!< debug CAN1 kept when core is halted */
|
||||||
|
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 0U), /*!< hold TIMER0 counter when core is halted */
|
||||||
|
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 1U), /*!< hold TIMER7 counter when core is halted */
|
||||||
|
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 16U), /*!< hold TIMER8 counter when core is halted */
|
||||||
|
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 17U), /*!< hold TIMER9 counter when core is halted */
|
||||||
|
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL2, 18U) /*!< hold TIMER10 counter when core is halted */
|
||||||
|
}dbg_periph_enum;
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* deinitialize the DBG */
|
||||||
|
void dbg_deinit(void);
|
||||||
|
/* read DBG_ID code register */
|
||||||
|
uint32_t dbg_id_get(void);
|
||||||
|
|
||||||
|
/* enable low power behavior when the MCU is in debug mode */
|
||||||
|
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||||
|
/* disable low power behavior when the MCU is in debug mode */
|
||||||
|
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||||
|
|
||||||
|
/* enable peripheral behavior when the MCU is in debug mode */
|
||||||
|
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||||
|
/* disable peripheral behavior when the MCU is in debug mode */
|
||||||
|
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||||
|
|
||||||
|
/* enable trace pin assignment */
|
||||||
|
void dbg_trace_pin_enable(void);
|
||||||
|
/* disable trace pin assignment */
|
||||||
|
void dbg_trace_pin_disable(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_DBG_H */
|
||||||
@@ -0,0 +1,236 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dci.h
|
||||||
|
\brief definitions for the DCI
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_DCI_H
|
||||||
|
#define GD32F4XX_DCI_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* DCI definitions */
|
||||||
|
#define DCI DCI_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define DCI_CTL REG32(DCI + 0x00U) /*!< DCI control register */
|
||||||
|
#define DCI_STAT0 REG32(DCI + 0x04U) /*!< DCI status register 0 */
|
||||||
|
#define DCI_STAT1 REG32(DCI + 0x08U) /*!< DCI status register 1 */
|
||||||
|
#define DCI_INTEN REG32(DCI + 0x0CU) /*!< DCI interrupt enable register */
|
||||||
|
#define DCI_INTF REG32(DCI + 0x10U) /*!< DCI interrupt flag register */
|
||||||
|
#define DCI_INTC REG32(DCI + 0x14U) /*!< DCI interrupt clear register */
|
||||||
|
#define DCI_SC REG32(DCI + 0x18U) /*!< DCI synchronization codes register */
|
||||||
|
#define DCI_SCUMSK REG32(DCI + 0x1CU) /*!< DCI synchronization codes unmask register */
|
||||||
|
#define DCI_CWSPOS REG32(DCI + 0x20U) /*!< DCI cropping window start position register */
|
||||||
|
#define DCI_CWSZ REG32(DCI + 0x24U) /*!< DCI cropping window size register */
|
||||||
|
#define DCI_DATA REG32(DCI + 0x28U) /*!< DCI data register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* DCI_CTL */
|
||||||
|
#define DCI_CTL_CAP BIT(0) /*!< capture enable */
|
||||||
|
#define DCI_CTL_SNAP BIT(1) /*!< snapshot mode */
|
||||||
|
#define DCI_CTL_WDEN BIT(2) /*!< window enable */
|
||||||
|
#define DCI_CTL_JM BIT(3) /*!< JPEG mode */
|
||||||
|
#define DCI_CTL_ESM BIT(4) /*!< embedded synchronous mode */
|
||||||
|
#define DCI_CTL_CKS BIT(5) /*!< clock polarity selection */
|
||||||
|
#define DCI_CTL_HPS BIT(6) /*!< horizontal polarity selection */
|
||||||
|
#define DCI_CTL_VPS BIT(7) /*!< vertical polarity selection */
|
||||||
|
#define DCI_CTL_FR BITS(8,9) /*!< frame rate */
|
||||||
|
#define DCI_CTL_DCIF BITS(10,11) /*!< digital camera interface format */
|
||||||
|
#define DCI_CTL_DCIEN BIT(14) /*!< DCI enable */
|
||||||
|
|
||||||
|
/* DCI_STAT0 */
|
||||||
|
#define DCI_STAT0_HS BIT(0) /*!< HS line status */
|
||||||
|
#define DCI_STAT0_VS BIT(1) /*!< VS line status */
|
||||||
|
#define DCI_STAT0_FV BIT(2) /*!< FIFO valid */
|
||||||
|
|
||||||
|
/* DCI_STAT1 */
|
||||||
|
#define DCI_STAT1_EFF BIT(0) /*!< end of frame flag */
|
||||||
|
#define DCI_STAT1_OVRF BIT(1) /*!< FIFO overrun flag */
|
||||||
|
#define DCI_STAT1_ESEF BIT(2) /*!< embedded synchronous error flag */
|
||||||
|
#define DCI_STAT1_VSF BIT(3) /*!< vsync flag */
|
||||||
|
#define DCI_STAT1_ELF BIT(4) /*!< end of line flag */
|
||||||
|
|
||||||
|
/* DCI_INTEN */
|
||||||
|
#define DCI_INTEN_EFIE BIT(0) /*!< end of frame interrupt enable */
|
||||||
|
#define DCI_INTEN_OVRIE BIT(1) /*!< FIFO overrun interrupt enable */
|
||||||
|
#define DCI_INTEN_ESEIE BIT(2) /*!< embedded synchronous error interrupt enable */
|
||||||
|
#define DCI_INTEN_VSIE BIT(3) /*!< vsync interrupt enable */
|
||||||
|
#define DCI_INTEN_ELIE BIT(4) /*!< end of line interrupt enable */
|
||||||
|
|
||||||
|
/* DCI_INTF */
|
||||||
|
#define DCI_INTF_EFIF BIT(0) /*!< end of frame interrupt flag */
|
||||||
|
#define DCI_INTF_OVRIF BIT(1) /*!< FIFO overrun interrupt flag */
|
||||||
|
#define DCI_INTF_ESEIF BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||||
|
#define DCI_INTF_VSIF BIT(3) /*!< vsync interrupt flag */
|
||||||
|
#define DCI_INTF_ELIF BIT(4) /*!< end of line interrupt flag */
|
||||||
|
|
||||||
|
/* DCI_INTC */
|
||||||
|
#define DCI_INTC_EFFC BIT(0) /*!< clear end of frame flag */
|
||||||
|
#define DCI_INTC_OVRFC BIT(1) /*!< clear FIFO overrun flag */
|
||||||
|
#define DCI_INTC_ESEFC BIT(2) /*!< clear embedded synchronous error flag */
|
||||||
|
#define DCI_INTC_VSFC BIT(3) /*!< vsync flag clear */
|
||||||
|
#define DCI_INTC_ELFC BIT(4) /*!< end of line flag clear */
|
||||||
|
|
||||||
|
/* DCI_SC */
|
||||||
|
#define DCI_SC_FS BITS(0,7) /*!< frame start code in embedded synchronous mode */
|
||||||
|
#define DCI_SC_LS BITS(8,15) /*!< line start code in embedded synchronous mode */
|
||||||
|
#define DCI_SC_LE BITS(16,23) /*!< line end code in embedded synchronous mode */
|
||||||
|
#define DCI_SC_FE BITS(24,31) /*!< frame end code in embedded synchronous mode */
|
||||||
|
|
||||||
|
/* DCI_SCUNMSK */
|
||||||
|
#define DCI_SCUMSK_FSM BITS(0,7) /*!< frame start code unmask bits in embedded synchronous mode */
|
||||||
|
#define DCI_SCUMSK_LSM BITS(8,15) /*!< line start code unmask bits in embedded synchronous mode */
|
||||||
|
#define DCI_SCUMSK_LEM BITS(16,23) /*!< line end code unmask bits in embedded synchronous mode */
|
||||||
|
#define DCI_SCUMSK_FEM BITS(24,31) /*!< frame end code unmask bits in embedded synchronous mode */
|
||||||
|
|
||||||
|
/* DCI_CWSPOS */
|
||||||
|
#define DCI_CWSPOS_WHSP BITS(0,13) /*!< window horizontal start position */
|
||||||
|
#define DCI_CWSPOS_WVSP BITS(16,28) /*!< window vertical start position */
|
||||||
|
|
||||||
|
/* DCI_CWSZ */
|
||||||
|
#define DCI_CWSZ_WHSZ BITS(0,13) /*!< window horizontal size */
|
||||||
|
#define DCI_CWSZ_WVSZ BITS(16,29) /*!< window vertical size */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* DCI parameter structure definitions */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t capture_mode; /*!< DCI capture mode: continuous or snapshot */
|
||||||
|
uint32_t clock_polarity; /*!< clock polarity selection */
|
||||||
|
uint32_t hsync_polarity; /*!< horizontal polarity selection */
|
||||||
|
uint32_t vsync_polarity; /*!< vertical polarity selection */
|
||||||
|
uint32_t frame_rate; /*!< frame capture rate */
|
||||||
|
uint32_t interface_format; /*!< digital camera interface format */
|
||||||
|
}dci_parameter_struct;
|
||||||
|
|
||||||
|
#define DCI_CAPTURE_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< continuous capture mode */
|
||||||
|
#define DCI_CAPTURE_MODE_SNAPSHOT DCI_CTL_SNAP /*!< snapshot capture mode */
|
||||||
|
|
||||||
|
#define DCI_CK_POLARITY_FALLING ((uint32_t)0x00000000U) /*!< capture at falling edge */
|
||||||
|
#define DCI_CK_POLARITY_RISING DCI_CTL_CKS /*!< capture at rising edge */
|
||||||
|
|
||||||
|
#define DCI_HSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||||
|
#define DCI_HSYNC_POLARITY_HIGH DCI_CTL_HPS /*!< high level during blanking period */
|
||||||
|
|
||||||
|
#define DCI_VSYNC_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level during blanking period */
|
||||||
|
#define DCI_VSYNC_POLARITY_HIGH DCI_CTL_VPS /*!< high level during blanking period*/
|
||||||
|
|
||||||
|
#define CTL_FR(regval) (BITS(8,9)&((uint32_t)(regval) << 8U))
|
||||||
|
#define DCI_FRAME_RATE_ALL CTL_FR(0) /*!< capture all frames */
|
||||||
|
#define DCI_FRAME_RATE_1_2 CTL_FR(1) /*!< capture one in 2 frames */
|
||||||
|
#define DCI_FRAME_RATE_1_4 CTL_FR(2) /*!< capture one in 4 frames */
|
||||||
|
|
||||||
|
#define CTL_DCIF(regval) (BITS(10,11)&((uint32_t)(regval) << 10U))
|
||||||
|
#define DCI_INTERFACE_FORMAT_8BITS CTL_DCIF(0) /*!< 8-bit data on every pixel clock */
|
||||||
|
#define DCI_INTERFACE_FORMAT_10BITS CTL_DCIF(1) /*!< 10-bit data on every pixel clock */
|
||||||
|
#define DCI_INTERFACE_FORMAT_12BITS CTL_DCIF(2) /*!< 12-bit data on every pixel clock */
|
||||||
|
#define DCI_INTERFACE_FORMAT_14BITS CTL_DCIF(3) /*!< 14-bit data on every pixel clock */
|
||||||
|
|
||||||
|
/* DCI interrupt constants definitions */
|
||||||
|
#define DCI_INT_EF BIT(0) /*!< end of frame interrupt */
|
||||||
|
#define DCI_INT_OVR BIT(1) /*!< FIFO overrun interrupt */
|
||||||
|
#define DCI_INT_ESE BIT(2) /*!< embedded synchronous error interrupt */
|
||||||
|
#define DCI_INT_VSYNC BIT(3) /*!< vsync interrupt */
|
||||||
|
#define DCI_INT_EL BIT(4) /*!< end of line interrupt */
|
||||||
|
|
||||||
|
/* DCI interrupt flag definitions */
|
||||||
|
#define DCI_INT_FLAG_EF BIT(0) /*!< end of frame interrupt flag */
|
||||||
|
#define DCI_INT_FLAG_OVR BIT(1) /*!< FIFO overrun interrupt flag */
|
||||||
|
#define DCI_INT_FLAG_ESE BIT(2) /*!< embedded synchronous error interrupt flag */
|
||||||
|
#define DCI_INT_FLAG_VSYNC BIT(3) /*!< vsync interrupt flag */
|
||||||
|
#define DCI_INT_FLAG_EL BIT(4) /*!< end of line interrupt flag */
|
||||||
|
|
||||||
|
/* DCI flag definitions */
|
||||||
|
#define DCI_FLAG_HS DCI_STAT0_HS /*!< HS line status */
|
||||||
|
#define DCI_FLAG_VS DCI_STAT0_VS /*!< VS line status */
|
||||||
|
#define DCI_FLAG_FV DCI_STAT0_FV /*!< FIFO valid */
|
||||||
|
#define DCI_FLAG_EF (DCI_STAT1_EFF | BIT(31)) /*!< end of frame flag */
|
||||||
|
#define DCI_FLAG_OVR (DCI_STAT1_OVRF | BIT(31)) /*!< FIFO overrun flag */
|
||||||
|
#define DCI_FLAG_ESE (DCI_STAT1_ESEF | BIT(31)) /*!< embedded synchronous error flag */
|
||||||
|
#define DCI_FLAG_VSYNC (DCI_STAT1_VSF | BIT(31)) /*!< vsync flag */
|
||||||
|
#define DCI_FLAG_EL (DCI_STAT1_ELF | BIT(31)) /*!< end of line flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* DCI deinit */
|
||||||
|
void dci_deinit(void);
|
||||||
|
/* initialize DCI registers */
|
||||||
|
void dci_init(dci_parameter_struct* dci_struct);
|
||||||
|
|
||||||
|
/* enable DCI function */
|
||||||
|
void dci_enable(void);
|
||||||
|
/* disable DCI function */
|
||||||
|
void dci_disable(void);
|
||||||
|
/* enable DCI capture */
|
||||||
|
void dci_capture_enable(void);
|
||||||
|
/* disable DCI capture */
|
||||||
|
void dci_capture_disable(void);
|
||||||
|
/* enable DCI jpeg mode */
|
||||||
|
void dci_jpeg_enable(void);
|
||||||
|
/* disable DCI jpeg mode */
|
||||||
|
void dci_jpeg_disable(void);
|
||||||
|
|
||||||
|
/* function configuration */
|
||||||
|
/* enable cropping window function */
|
||||||
|
void dci_crop_window_enable(void);
|
||||||
|
/* disable cropping window function */
|
||||||
|
void dci_crop_window_disable(void);
|
||||||
|
/* configure DCI cropping window */
|
||||||
|
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height);
|
||||||
|
|
||||||
|
/* enable embedded synchronous mode */
|
||||||
|
void dci_embedded_sync_enable(void);
|
||||||
|
/* disable embedded synchronous mode */
|
||||||
|
void dci_embedded_sync_disable(void);
|
||||||
|
/* configure synchronous codes in embedded synchronous mode */
|
||||||
|
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||||
|
/* configure synchronous codes unmask in embedded synchronous mode */
|
||||||
|
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end);
|
||||||
|
|
||||||
|
/* read DCI data register */
|
||||||
|
uint32_t dci_data_read(void);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* get specified flag */
|
||||||
|
FlagStatus dci_flag_get(uint32_t flag);
|
||||||
|
/* enable specified DCI interrupt */
|
||||||
|
void dci_interrupt_enable(uint32_t interrupt);
|
||||||
|
/* disable specified DCI interrupt */
|
||||||
|
void dci_interrupt_disable(uint32_t interrupt);
|
||||||
|
|
||||||
|
|
||||||
|
/* get specified interrupt flag */
|
||||||
|
FlagStatus dci_interrupt_flag_get(uint32_t int_flag);
|
||||||
|
/* clear specified interrupt flag */
|
||||||
|
void dci_interrupt_flag_clear(uint32_t int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_DCI_H */
|
||||||
@@ -0,0 +1,440 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dma.h
|
||||||
|
\brief definitions for the DMA
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_DMA_H
|
||||||
|
#define GD32F4XX_DMA_H
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
extern "C" {
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* DMA definitions */
|
||||||
|
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||||
|
#define DMA1 (DMA_BASE + 0x00000400U) /*!< DMA1 base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define DMA_INTF0(dmax) REG32((dmax) + 0x00000000U) /*!< DMA interrupt flag register 0 */
|
||||||
|
#define DMA_INTF1(dmax) REG32((dmax) + 0x00000004U) /*!< DMA interrupt flag register 1 */
|
||||||
|
#define DMA_INTC0(dmax) REG32((dmax) + 0x00000008U) /*!< DMA interrupt flag clear register 0 */
|
||||||
|
#define DMA_INTC1(dmax) REG32((dmax) + 0x0000000CU) /*!< DMA interrupt flag clear register 1 */
|
||||||
|
|
||||||
|
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x00000010U) /*!< DMA channel 0 control register */
|
||||||
|
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x00000014U) /*!< DMA channel 0 counter register */
|
||||||
|
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x00000018U) /*!< DMA channel 0 peripheral base address register */
|
||||||
|
#define DMA_CH0M0ADDR(dmax) REG32((dmax) + 0x0000001CU) /*!< DMA channel 0 memory 0 base address register */
|
||||||
|
#define DMA_CH0M1ADDR(dmax) REG32((dmax) + 0x00000020U) /*!< DMA channel 0 memory 1 base address register */
|
||||||
|
#define DMA_CH0FCTL(dmax) REG32((dmax) + 0x00000024U) /*!< DMA channel 0 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x00000028U) /*!< DMA channel 1 control register */
|
||||||
|
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x0000002CU) /*!< DMA channel 1 counter register */
|
||||||
|
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x00000030U) /*!< DMA channel 1 peripheral base address register */
|
||||||
|
#define DMA_CH1M0ADDR(dmax) REG32((dmax) + 0x00000034U) /*!< DMA channel 1 memory 0 base address register */
|
||||||
|
#define DMA_CH1M1ADDR(dmax) REG32((dmax) + 0x00000038U) /*!< DMA channel 1 memory 1 base address register */
|
||||||
|
#define DMA_CH1FCTL(dmax) REG32((dmax) + 0x0000003CU) /*!< DMA channel 1 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x00000040U) /*!< DMA channel 2 control register */
|
||||||
|
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x00000044U) /*!< DMA channel 2 counter register */
|
||||||
|
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x00000048U) /*!< DMA channel 2 peripheral base address register */
|
||||||
|
#define DMA_CH2M0ADDR(dmax) REG32((dmax) + 0x0000004CU) /*!< DMA channel 2 memory 0 base address register */
|
||||||
|
#define DMA_CH2M1ADDR(dmax) REG32((dmax) + 0x00000050U) /*!< DMA channel 2 memory 1 base address register */
|
||||||
|
#define DMA_CH2FCTL(dmax) REG32((dmax) + 0x00000054U) /*!< DMA channel 2 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x00000058U) /*!< DMA channel 3 control register */
|
||||||
|
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x0000005CU) /*!< DMA channel 3 counter register */
|
||||||
|
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x00000060U) /*!< DMA channel 3 peripheral base address register */
|
||||||
|
#define DMA_CH3M0ADDR(dmax) REG32((dmax) + 0x00000064U) /*!< DMA channel 3 memory 0 base address register */
|
||||||
|
#define DMA_CH3M1ADDR(dmax) REG32((dmax) + 0x00000068U) /*!< DMA channel 3 memory 1 base address register */
|
||||||
|
#define DMA_CH3FCTL(dmax) REG32((dmax) + 0x0000006CU) /*!< DMA channel 3 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x00000070U) /*!< DMA channel 4 control register */
|
||||||
|
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x00000074U) /*!< DMA channel 4 counter register */
|
||||||
|
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x00000078U) /*!< DMA channel 4 peripheral base address register */
|
||||||
|
#define DMA_CH4M0ADDR(dmax) REG32((dmax) + 0x0000007CU) /*!< DMA channel 4 memory 0 base address register */
|
||||||
|
#define DMA_CH4M1ADDR(dmax) REG32((dmax) + 0x00000080U) /*!< DMA channel 4 memory 1 base address register */
|
||||||
|
#define DMA_CH4FCTL(dmax) REG32((dmax) + 0x00000084U) /*!< DMA channel 4 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x00000088U) /*!< DMA channel 5 control register */
|
||||||
|
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x0000008CU) /*!< DMA channel 5 counter register */
|
||||||
|
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x00000090U) /*!< DMA channel 5 peripheral base address register */
|
||||||
|
#define DMA_CH5M0ADDR(dmax) REG32((dmax) + 0x00000094U) /*!< DMA channel 5 memory 0 base address register */
|
||||||
|
#define DMA_CH5M1ADDR(dmax) REG32((dmax) + 0x00000098U) /*!< DMA channel 5 memory 1 base address register */
|
||||||
|
#define DMA_CH5FCTL(dmax) REG32((dmax) + 0x0000009CU) /*!< DMA channel 5 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x000000A0U) /*!< DMA channel 6 control register */
|
||||||
|
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x000000A4U) /*!< DMA channel 6 counter register */
|
||||||
|
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x000000A8U) /*!< DMA channel 6 peripheral base address register */
|
||||||
|
#define DMA_CH6M0ADDR(dmax) REG32((dmax) + 0x000000ACU) /*!< DMA channel 6 memory 0 base address register */
|
||||||
|
#define DMA_CH6M1ADDR(dmax) REG32((dmax) + 0x000000B0U) /*!< DMA channel 6 memory 1 base address register */
|
||||||
|
#define DMA_CH6FCTL(dmax) REG32((dmax) + 0x000000B4U) /*!< DMA channel 6 FIFO control register */
|
||||||
|
|
||||||
|
#define DMA_CH7CTL(dmax) REG32((dmax) + 0x000000B8U) /*!< DMA channel 7 control register */
|
||||||
|
#define DMA_CH7CNT(dmax) REG32((dmax) + 0x000000BCU) /*!< DMA channel 7 counter register */
|
||||||
|
#define DMA_CH7PADDR(dmax) REG32((dmax) + 0x000000C0U) /*!< DMA channel 7 peripheral base address register */
|
||||||
|
#define DMA_CH7M0ADDR(dmax) REG32((dmax) + 0x000000C4U) /*!< DMA channel 7 memory 0 base address register */
|
||||||
|
#define DMA_CH7M1ADDR(dmax) REG32((dmax) + 0x000000C8U) /*!< DMA channel 7 memory 1 base address register */
|
||||||
|
#define DMA_CH7FCTL(dmax) REG32((dmax) + 0x000000CCU) /*!< DMA channel 7 FIFO control register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* DMA_INTF */
|
||||||
|
#define DMA_INTF_FEEIF BIT(0) /*!< FIFO error and exception flag */
|
||||||
|
#define DMA_INTF_SDEIF BIT(2) /*!< single data mode exception flag */
|
||||||
|
#define DMA_INTF_TAEIF BIT(3) /*!< transfer access error flag */
|
||||||
|
#define DMA_INTF_HTFIF BIT(4) /*!< half transfer finish flag */
|
||||||
|
#define DMA_INTF_FTFIF BIT(5) /*!< full transger finish flag */
|
||||||
|
|
||||||
|
/* DMA_INTC */
|
||||||
|
#define DMA_INTC_FEEIFC BIT(0) /*!< clear FIFO error and exception flag */
|
||||||
|
#define DMA_INTC_SDEIFC BIT(2) /*!< clear single data mode exception flag */
|
||||||
|
#define DMA_INTC_TAEIFC BIT(3) /*!< clear single data mode exception flag */
|
||||||
|
#define DMA_INTC_HTFIFC BIT(4) /*!< clear half transfer finish flag */
|
||||||
|
#define DMA_INTC_FTFIFC BIT(5) /*!< clear full transger finish flag */
|
||||||
|
|
||||||
|
/* DMA_CHxCTL,x=0..7 */
|
||||||
|
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||||
|
#define DMA_CHXCTL_SDEIE BIT(1) /*!< enable bit for channel x single data mode exception interrupt */
|
||||||
|
#define DMA_CHXCTL_TAEIE BIT(2) /*!< enable bit for channel x tranfer access error interrupt */
|
||||||
|
#define DMA_CHXCTL_HTFIE BIT(3) /*!< enable bit for channel x half transfer finish interrupt */
|
||||||
|
#define DMA_CHXCTL_FTFIE BIT(4) /*!< enable bit for channel x full transfer finish interrupt */
|
||||||
|
#define DMA_CHXCTL_TFCS BIT(5) /*!< transfer flow controller select */
|
||||||
|
#define DMA_CHXCTL_TM BITS(6,7) /*!< transfer mode */
|
||||||
|
#define DMA_CHXCTL_CMEN BIT(8) /*!< circulation mode */
|
||||||
|
#define DMA_CHXCTL_PNAGA BIT(9) /*!< next address generation algorithm of peripheral */
|
||||||
|
#define DMA_CHXCTL_MNAGA BIT(10) /*!< next address generation algorithm of memory */
|
||||||
|
#define DMA_CHXCTL_PWIDTH BITS(11,12) /*!< transfer width of peipheral */
|
||||||
|
#define DMA_CHXCTL_MWIDTH BITS(13,14) /*!< transfer width of memory */
|
||||||
|
#define DMA_CHXCTL_PAIF BIT(15) /*!< peripheral address increment fixed */
|
||||||
|
#define DMA_CHXCTL_PRIO BITS(16,17) /*!< priority level */
|
||||||
|
#define DMA_CHXCTL_SBMEN BIT(18) /*!< switch-buffer mode enable */
|
||||||
|
#define DMA_CHXCTL_MBS BIT(19) /*!< memory buffer select */
|
||||||
|
#define DMA_CHXCTL_PBURST BITS(21,22) /*!< transfer burst type of peripheral */
|
||||||
|
#define DMA_CHXCTL_MBURST BITS(23,24) /*!< transfer burst type of memory */
|
||||||
|
#define DMA_CHXCTL_PERIEN BITS(25,27) /*!< peripheral enable */
|
||||||
|
|
||||||
|
/* DMA_CHxCNT,x=0..7 */
|
||||||
|
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||||
|
|
||||||
|
/* DMA_CHxPADDR,x=0..7 */
|
||||||
|
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||||
|
|
||||||
|
/* DMA_CHxM0ADDR,x=0..7 */
|
||||||
|
#define DMA_CHXM0ADDR_M0ADDR BITS(0,31) /*!< memory 0 base address */
|
||||||
|
|
||||||
|
/* DMA_CHxM1ADDR,x=0..7 */
|
||||||
|
#define DMA_CHXM1ADDR_M0ADDR BITS(0,31) /*!< memory 1 base address */
|
||||||
|
|
||||||
|
/* DMA_CHxFCTL,x=0..7 */
|
||||||
|
#define DMA_CHXFCTL_FCCV BITS(0,1) /*!< FIFO counter critical value */
|
||||||
|
#define DMA_CHXFCTL_MDMEN BIT(2) /*!< multi-data mode enable */
|
||||||
|
#define DMA_CHXFCTL_FCNT BITS(3,5) /*!< FIFO counter */
|
||||||
|
#define DMA_CHXFCTL_FEEIE BIT(7) /*!< FIFO exception interrupt enable */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* DMA channel select */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DMA_CH0 = 0, /*!< DMA Channel 0 */
|
||||||
|
DMA_CH1, /*!< DMA Channel 1 */
|
||||||
|
DMA_CH2, /*!< DMA Channel 2 */
|
||||||
|
DMA_CH3, /*!< DMA Channel 3 */
|
||||||
|
DMA_CH4, /*!< DMA Channel 4 */
|
||||||
|
DMA_CH5, /*!< DMA Channel 5 */
|
||||||
|
DMA_CH6, /*!< DMA Channel 6 */
|
||||||
|
DMA_CH7 /*!< DMA Channel 7 */
|
||||||
|
} dma_channel_enum;
|
||||||
|
|
||||||
|
/* DMA peripheral select */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DMA_SUBPERI0 = 0, /*!< DMA Peripheral 0 */
|
||||||
|
DMA_SUBPERI1, /*!< DMA Peripheral 1 */
|
||||||
|
DMA_SUBPERI2, /*!< DMA Peripheral 2 */
|
||||||
|
DMA_SUBPERI3, /*!< DMA Peripheral 3 */
|
||||||
|
DMA_SUBPERI4, /*!< DMA Peripheral 4 */
|
||||||
|
DMA_SUBPERI5, /*!< DMA Peripheral 5 */
|
||||||
|
DMA_SUBPERI6, /*!< DMA Peripheral 6 */
|
||||||
|
DMA_SUBPERI7 /*!< DMA Peripheral 7 */
|
||||||
|
} dma_subperipheral_enum;
|
||||||
|
|
||||||
|
/* DMA multidata mode initialize struct */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t periph_addr; /*!< peripheral base address */
|
||||||
|
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||||
|
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||||
|
|
||||||
|
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||||
|
uint32_t memory_width; /*!< transfer data size of memory */
|
||||||
|
uint32_t memory_inc; /*!< memory increasing mode */
|
||||||
|
|
||||||
|
uint32_t memory_burst_width; /*!< multi data mode enable */
|
||||||
|
uint32_t periph_burst_width; /*!< multi data mode enable */
|
||||||
|
uint32_t critical_value; /*!< FIFO critical */
|
||||||
|
|
||||||
|
uint32_t circular_mode; /*!< DMA circular mode */
|
||||||
|
uint32_t direction; /*!< channel data transfer direction */
|
||||||
|
uint32_t number; /*!< channel transfer number */
|
||||||
|
uint32_t priority; /*!< channel priority level */
|
||||||
|
}dma_multi_data_parameter_struct;
|
||||||
|
|
||||||
|
/* DMA singledata mode initialize struct */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t periph_addr; /*!< peripheral base address */
|
||||||
|
uint32_t periph_inc; /*!< peripheral increasing mode */
|
||||||
|
|
||||||
|
uint32_t memory0_addr; /*!< memory 0 base address */
|
||||||
|
uint32_t memory_inc; /*!< memory increasing mode */
|
||||||
|
|
||||||
|
uint32_t periph_memory_width; /*!< transfer data size of peripheral */
|
||||||
|
|
||||||
|
uint32_t circular_mode; /*!< DMA circular mode */
|
||||||
|
uint32_t direction; /*!< channel data transfer direction */
|
||||||
|
uint32_t number; /*!< channel transfer number */
|
||||||
|
uint32_t priority; /*!< channel priority level */
|
||||||
|
} dma_single_data_parameter_struct;
|
||||||
|
|
||||||
|
#define DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /*!< DMA channel flag shift */
|
||||||
|
|
||||||
|
/* DMA_register address */
|
||||||
|
#define DMA_CHCTL(dma,channel) REG32(((dma) + 0x10U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||||
|
#define DMA_CHCNT(dma,channel) REG32(((dma) + 0x14U) + 0x18U*(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||||
|
#define DMA_CHPADDR(dma,channel) REG32(((dma) + 0x18U) + 0x18U*(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||||
|
#define DMA_CHM0ADDR(dma,channel) REG32(((dma) + 0x1CU) + 0x18U*(channel)) /*!< the address of DMA channel CHXM0ADDR register */
|
||||||
|
#define DMA_CHM1ADDR(dma,channel) REG32(((dma) + 0x20U) + 0x18U*(channel)) /*!< the address of DMA channel CHXM1ADDR register */
|
||||||
|
#define DMA_CHFCTL(dma,channel) REG32(((dma) + 0x24U) + 0x18U*(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||||
|
|
||||||
|
/* peripheral select */
|
||||||
|
#define CHCTL_PERIEN(regval) (BITS(25,27) & ((uint32_t)(regval) << 25))
|
||||||
|
#define DMA_PERIPH_0_SELECT CHCTL_PERIEN(0) /*!< peripheral 0 select */
|
||||||
|
#define DMA_PERIPH_1_SELECT CHCTL_PERIEN(1) /*!< peripheral 1 select */
|
||||||
|
#define DMA_PERIPH_2_SELECT CHCTL_PERIEN(2) /*!< peripheral 2 select */
|
||||||
|
#define DMA_PERIPH_3_SELECT CHCTL_PERIEN(3) /*!< peripheral 3 select */
|
||||||
|
#define DMA_PERIPH_4_SELECT CHCTL_PERIEN(4) /*!< peripheral 4 select */
|
||||||
|
#define DMA_PERIPH_5_SELECT CHCTL_PERIEN(5) /*!< peripheral 5 select */
|
||||||
|
#define DMA_PERIPH_6_SELECT CHCTL_PERIEN(6) /*!< peripheral 6 select */
|
||||||
|
#define DMA_PERIPH_7_SELECT CHCTL_PERIEN(7) /*!< peripheral 7 select */
|
||||||
|
|
||||||
|
/* burst type of memory */
|
||||||
|
#define CHCTL_MBURST(regval) (BITS(23,24) & ((uint32_t)(regval) << 23))
|
||||||
|
#define DMA_MEMORY_BURST_SINGLE CHCTL_MBURST(0) /*!< single burst */
|
||||||
|
#define DMA_MEMORY_BURST_4_BEAT CHCTL_MBURST(1) /*!< 4-beat burst */
|
||||||
|
#define DMA_MEMORY_BURST_8_BEAT CHCTL_MBURST(2) /*!< 8-beat burst */
|
||||||
|
#define DMA_MEMORY_BURST_16_BEAT CHCTL_MBURST(3) /*!< 16-beat burst */
|
||||||
|
|
||||||
|
/* burst type of peripheral */
|
||||||
|
#define CHCTL_PBURST(regval) (BITS(21,22) & ((uint32_t)(regval) << 21))
|
||||||
|
#define DMA_PERIPH_BURST_SINGLE CHCTL_PBURST(0) /*!< single burst */
|
||||||
|
#define DMA_PERIPH_BURST_4_BEAT CHCTL_PBURST(1) /*!< 4-beat burst */
|
||||||
|
#define DMA_PERIPH_BURST_8_BEAT CHCTL_PBURST(2) /*!< 8-beat burst */
|
||||||
|
#define DMA_PERIPH_BURST_16_BEAT CHCTL_PBURST(3) /*!< 16-beat burst */
|
||||||
|
|
||||||
|
/* channel priority level */
|
||||||
|
#define CHCTL_PRIO(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||||
|
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
|
||||||
|
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
|
||||||
|
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
|
||||||
|
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
|
||||||
|
|
||||||
|
/* transfer data width of memory */
|
||||||
|
#define CHCTL_MWIDTH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||||
|
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data width of memory is 8-bit */
|
||||||
|
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data width of memory is 16-bit */
|
||||||
|
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data width of memory is 32-bit */
|
||||||
|
|
||||||
|
/* transfer data width of peripheral */
|
||||||
|
#define CHCTL_PWIDTH(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||||
|
#define DMA_PERIPH_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data width of peripheral is 8-bit */
|
||||||
|
#define DMA_PERIPH_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data width of peripheral is 16-bit */
|
||||||
|
#define DMA_PERIPH_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data width of peripheral is 32-bit */
|
||||||
|
|
||||||
|
/* channel transfer mode */
|
||||||
|
#define CHCTL_TM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||||
|
#define DMA_PERIPH_TO_MEMORY CHCTL_TM(0) /*!< read from peripheral and write to memory */
|
||||||
|
#define DMA_MEMORY_TO_PERIPH CHCTL_TM(1) /*!< read from memory and write to peripheral */
|
||||||
|
#define DMA_MEMORY_TO_MEMORY CHCTL_TM(2) /*!< read from memory and write to memory */
|
||||||
|
|
||||||
|
/* FIFO counter critical value */
|
||||||
|
#define CHFCTL_FCCV(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define DMA_FIFO_1_WORD CHFCTL_FCCV(0) /*!< critical value 1 word */
|
||||||
|
#define DMA_FIFO_2_WORD CHFCTL_FCCV(1) /*!< critical value 2 word */
|
||||||
|
#define DMA_FIFO_3_WORD CHFCTL_FCCV(2) /*!< critical value 3 word */
|
||||||
|
#define DMA_FIFO_4_WORD CHFCTL_FCCV(3) /*!< critical value 4 word */
|
||||||
|
|
||||||
|
/* memory select */
|
||||||
|
#define DMA_MEMORY_0 ((uint32_t)0x00000000U) /*!< select memory 0 */
|
||||||
|
#define DMA_MEMORY_1 ((uint32_t)0x00000001U) /*!< select memory 1 */
|
||||||
|
|
||||||
|
/* DMA circular mode */
|
||||||
|
#define DMA_CIRCULAR_MODE_ENABLE ((uint32_t)0x00000000U) /*!< circular mode enable */
|
||||||
|
#define DMA_CIRCULAR_MODE_DISABLE ((uint32_t)0x00000001U) /*!< circular mode disable */
|
||||||
|
|
||||||
|
/* DMA flow controller select */
|
||||||
|
#define DMA_FLOW_CONTROLLER_DMA ((uint32_t)0x00000000U) /*!< DMA is the flow controler */
|
||||||
|
#define DMA_FLOW_CONTROLLER_PERI ((uint32_t)0x00000001U) /*!< peripheral is the flow controler */
|
||||||
|
|
||||||
|
/* peripheral increasing mode */
|
||||||
|
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is increasing address mode */
|
||||||
|
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is fixed address mode */
|
||||||
|
#define DMA_PERIPH_INCREASE_FIX ((uint32_t)0x00000002U) /*!< next address of peripheral is increasing fixed */
|
||||||
|
|
||||||
|
/* memory increasing mode */
|
||||||
|
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000000U) /*!< next address of memory is increasing address mode */
|
||||||
|
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000001U) /*!< next address of memory is fixed address mode */
|
||||||
|
|
||||||
|
/* FIFO status */
|
||||||
|
#define DMA_FIFO_STATUS_NODATA ((uint32_t)0x00000000U) /*!< the data in the FIFO less than 1 word */
|
||||||
|
#define DMA_FIFO_STATUS_1_WORD ((uint32_t)0x00000001U) /*!< the data in the FIFO more than 1 word, less than 2 words */
|
||||||
|
#define DMA_FIFO_STATUS_2_WORD ((uint32_t)0x00000002U) /*!< the data in the FIFO more than 2 word, less than 3 words */
|
||||||
|
#define DMA_FIFO_STATUS_3_WORD ((uint32_t)0x00000003U) /*!< the data in the FIFO more than 3 word, less than 4 words */
|
||||||
|
#define DMA_FIFO_STATUS_EMPTY ((uint32_t)0x00000004U) /*!< the data in the FIFO is empty */
|
||||||
|
#define DMA_FIFO_STATUS_FULL ((uint32_t)0x00000005U) /*!< the data in the FIFO is full */
|
||||||
|
|
||||||
|
/* DMA reset value */
|
||||||
|
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||||
|
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||||
|
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||||
|
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||||
|
#define DMA_CHINTF_RESET_VALUE ((uint32_t)0x0000003DU) /*!< clear DMA channel CHXINTFS register */
|
||||||
|
#define DMA_CHFCTL_RESET_VALUE ((uint32_t)0x00000021U) /*!< the reset value of DMA channel CHXFCTL register */
|
||||||
|
|
||||||
|
/* DMA_INTF register */
|
||||||
|
/* interrupt flag bits */
|
||||||
|
#define DMA_INT_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||||
|
#define DMA_INT_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||||
|
#define DMA_INT_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||||
|
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||||
|
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||||
|
|
||||||
|
/* flag bits */
|
||||||
|
#define DMA_FLAG_FEE DMA_INTF_FEEIF /*!< FIFO error and exception flag */
|
||||||
|
#define DMA_FLAG_SDE DMA_INTF_SDEIF /*!< single data mode exception flag */
|
||||||
|
#define DMA_FLAG_TAE DMA_INTF_TAEIF /*!< transfer access error flag */
|
||||||
|
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag */
|
||||||
|
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag */
|
||||||
|
|
||||||
|
/* DMA_CHxCTL register */
|
||||||
|
/* interrupt enable bits */
|
||||||
|
#define DMA_INT_SDE DMA_CHXCTL_SDEIE /*!< enable bit for channel x single data mode exception interrupt */
|
||||||
|
#define DMA_INT_TAE DMA_CHXCTL_TAEIE /*!< enable bit for channel x tranfer access error interrupt */
|
||||||
|
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel x half transfer finish interrupt */
|
||||||
|
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel x full transfer finish interrupt */
|
||||||
|
#define DMA_INT_FEE DMA_CHXFCTL_FEEIE /*!< FIFO exception interrupt enable */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* DMA deinitialization and initialization functions */
|
||||||
|
/* deinitialize DMA a channel registers */
|
||||||
|
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
/* initialize the DMA single data mode parameters struct with the default values */
|
||||||
|
void dma_single_data_para_struct_init(dma_single_data_parameter_struct* init_struct);
|
||||||
|
/* initialize the DMA multi data mode parameters struct with the default values */
|
||||||
|
void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct* init_struct);
|
||||||
|
/* DMA single data mode initialize */
|
||||||
|
void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct* init_struct);
|
||||||
|
/* DMA multi data mode initialize */
|
||||||
|
void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct* init_struct);
|
||||||
|
|
||||||
|
/* DMA configuration functions */
|
||||||
|
/* set DMA peripheral base address */
|
||||||
|
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||||
|
/* set DMA Memory base address */
|
||||||
|
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address);
|
||||||
|
|
||||||
|
/* set the number of remaining data to be transferred by the DMA */
|
||||||
|
void dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx, uint32_t number);
|
||||||
|
/* get the number of remaining data to be transferred by the DMA */
|
||||||
|
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
|
||||||
|
/* configure priority level of DMA channel */
|
||||||
|
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||||
|
|
||||||
|
/* configure transfer burst beats of memory */
|
||||||
|
void dma_memory_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat);
|
||||||
|
/* configure transfer burst beats of peripheral */
|
||||||
|
void dma_periph_burst_beats_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat);
|
||||||
|
/* configure transfer data size of memory */
|
||||||
|
void dma_memory_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize);
|
||||||
|
/* configure transfer data size of peripheral */
|
||||||
|
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize);
|
||||||
|
|
||||||
|
/* configure next address increasement algorithm of memory */
|
||||||
|
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||||
|
/* configure next address increasement algorithm of peripheral */
|
||||||
|
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm);
|
||||||
|
|
||||||
|
/* enable DMA circulation mode */
|
||||||
|
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
/* disable DMA circulation mode */
|
||||||
|
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
/* enable DMA channel */
|
||||||
|
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
/* disable DMA channel */
|
||||||
|
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
|
||||||
|
/* configure the direction of data transfer on the channel */
|
||||||
|
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction);
|
||||||
|
|
||||||
|
/* DMA switch buffer mode config */
|
||||||
|
void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select);
|
||||||
|
/* DMA using memory get */
|
||||||
|
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
|
||||||
|
/* DMA channel peripheral select */
|
||||||
|
void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph);
|
||||||
|
/* DMA flow controller configure */
|
||||||
|
void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller);
|
||||||
|
/* DMA flow controller enable */
|
||||||
|
void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue);
|
||||||
|
/* DMA FIFO status get */
|
||||||
|
uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||||
|
|
||||||
|
/* flag and interrupt functions */
|
||||||
|
/* check DMA flag is set or not */
|
||||||
|
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||||
|
/* clear DMA a channel flag */
|
||||||
|
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||||
|
/* enable DMA interrupt */
|
||||||
|
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||||
|
/* disable DMA interrupt */
|
||||||
|
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||||
|
/* check DMA flag is set or not */
|
||||||
|
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||||
|
/* clear DMA a channel flag */
|
||||||
|
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt);
|
||||||
|
|
||||||
|
#if defined(__cplusplus)
|
||||||
|
}
|
||||||
|
#endif /* __cplusplus */
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_DMA_H */
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,810 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_exmc.h
|
||||||
|
\brief definitions for the EXMC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_EXMC_H
|
||||||
|
#define GD32F4XX_EXMC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* EXMC definitions */
|
||||||
|
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||||
|
#define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */
|
||||||
|
#define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */
|
||||||
|
#define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */
|
||||||
|
#define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
/* NOR/PSRAM */
|
||||||
|
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */
|
||||||
|
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */
|
||||||
|
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */
|
||||||
|
|
||||||
|
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */
|
||||||
|
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */
|
||||||
|
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */
|
||||||
|
|
||||||
|
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */
|
||||||
|
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */
|
||||||
|
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */
|
||||||
|
|
||||||
|
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */
|
||||||
|
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */
|
||||||
|
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */
|
||||||
|
|
||||||
|
/* NAND/PC card */
|
||||||
|
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */
|
||||||
|
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */
|
||||||
|
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */
|
||||||
|
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */
|
||||||
|
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */
|
||||||
|
|
||||||
|
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */
|
||||||
|
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */
|
||||||
|
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */
|
||||||
|
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */
|
||||||
|
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */
|
||||||
|
|
||||||
|
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */
|
||||||
|
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */
|
||||||
|
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */
|
||||||
|
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */
|
||||||
|
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */
|
||||||
|
|
||||||
|
/* SDRAM */
|
||||||
|
#define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */
|
||||||
|
#define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */
|
||||||
|
|
||||||
|
#define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */
|
||||||
|
#define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */
|
||||||
|
|
||||||
|
#define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */
|
||||||
|
#define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */
|
||||||
|
#define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */
|
||||||
|
#define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */
|
||||||
|
|
||||||
|
/* SQPI PSRAM */
|
||||||
|
#define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */
|
||||||
|
#define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */
|
||||||
|
#define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */
|
||||||
|
#define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */
|
||||||
|
#define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* EXMC_SNCTLx,x=0..3 */
|
||||||
|
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||||
|
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */
|
||||||
|
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||||
|
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||||
|
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||||
|
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
|
||||||
|
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||||
|
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||||
|
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||||
|
#define EXMC_SNCTL_WEN BIT(12) /*!< write enable */
|
||||||
|
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||||
|
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||||
|
#define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */
|
||||||
|
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
||||||
|
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */
|
||||||
|
#define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */
|
||||||
|
|
||||||
|
/* EXMC_SNTCFGx,x=0..3 */
|
||||||
|
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
||||||
|
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||||
|
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
|
||||||
|
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||||
|
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||||
|
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
|
||||||
|
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||||
|
|
||||||
|
/* EXMC_SNWTCFGx,x=0..3 */
|
||||||
|
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
|
||||||
|
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||||
|
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
|
||||||
|
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
|
||||||
|
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||||
|
|
||||||
|
/* EXMC_NPCTLx,x=1..3 */
|
||||||
|
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
|
||||||
|
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
|
||||||
|
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
|
||||||
|
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
|
||||||
|
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
|
||||||
|
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
|
||||||
|
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
|
||||||
|
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
|
||||||
|
|
||||||
|
/* EXMC_NPINTENx,x=1..3 */
|
||||||
|
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
|
||||||
|
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
|
||||||
|
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
|
||||||
|
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
|
||||||
|
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
|
||||||
|
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
|
||||||
|
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
|
||||||
|
|
||||||
|
/* EXMC_NPCTCFGx,x=1..3 */
|
||||||
|
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
|
||||||
|
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
|
||||||
|
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
|
||||||
|
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
|
||||||
|
|
||||||
|
/* EXMC_NPATCFGx,x=1..3 */
|
||||||
|
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
|
||||||
|
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
|
||||||
|
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
|
||||||
|
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
|
||||||
|
|
||||||
|
/* EXMC_PIOTCFG3 */
|
||||||
|
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
|
||||||
|
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
|
||||||
|
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
|
||||||
|
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
|
||||||
|
|
||||||
|
/* EXMC_NECCx,x=1..2 */
|
||||||
|
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
|
||||||
|
|
||||||
|
/* EXMC_SDCTLx,x=0..1 */
|
||||||
|
#define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */
|
||||||
|
#define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */
|
||||||
|
#define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */
|
||||||
|
#define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */
|
||||||
|
#define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */
|
||||||
|
#define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */
|
||||||
|
#define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */
|
||||||
|
#define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */
|
||||||
|
#define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */
|
||||||
|
|
||||||
|
/* EXMC_SDTCFGx,x=0..1 */
|
||||||
|
#define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */
|
||||||
|
#define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */
|
||||||
|
#define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */
|
||||||
|
#define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */
|
||||||
|
#define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */
|
||||||
|
#define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */
|
||||||
|
#define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */
|
||||||
|
|
||||||
|
/* EXMC_SDCMD */
|
||||||
|
#define EXMC_SDCMD_CMD BITS(0,2) /*!< command */
|
||||||
|
#define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */
|
||||||
|
#define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */
|
||||||
|
#define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */
|
||||||
|
#define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */
|
||||||
|
|
||||||
|
/* EXMC_SDARI */
|
||||||
|
#define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */
|
||||||
|
#define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */
|
||||||
|
#define EXMC_SDARI_REIE BIT(14) /*!< refresh error interrupt enable */
|
||||||
|
|
||||||
|
/* EXMC_SDSTAT */
|
||||||
|
#define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */
|
||||||
|
#define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */
|
||||||
|
#define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */
|
||||||
|
#define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */
|
||||||
|
|
||||||
|
/* EXMC_SDRSCTL */
|
||||||
|
#define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */
|
||||||
|
#define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */
|
||||||
|
#define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */
|
||||||
|
|
||||||
|
/* EXMC_SINIT */
|
||||||
|
#define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */
|
||||||
|
#define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */
|
||||||
|
#define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */
|
||||||
|
#define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */
|
||||||
|
|
||||||
|
/* EXMC_SRCMD */
|
||||||
|
#define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */
|
||||||
|
#define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */
|
||||||
|
#define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */
|
||||||
|
#define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */
|
||||||
|
|
||||||
|
/* EXMC_SWCMD */
|
||||||
|
#define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */
|
||||||
|
#define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */
|
||||||
|
#define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */
|
||||||
|
#define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */
|
||||||
|
|
||||||
|
/* EXMC_SIDL */
|
||||||
|
#define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */
|
||||||
|
|
||||||
|
/* EXMC_SIDH */
|
||||||
|
#define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* EXMC NOR/SRAM timing initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t asyn_access_mode; /*!< asynchronous access mode */
|
||||||
|
uint32_t syn_data_latency; /*!< configure the data latency */
|
||||||
|
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
|
||||||
|
uint32_t bus_latency; /*!< configure the bus latency */
|
||||||
|
uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */
|
||||||
|
uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */
|
||||||
|
uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */
|
||||||
|
}exmc_norsram_timing_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC NOR/SRAM initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||||
|
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
|
||||||
|
uint32_t extended_mode; /*!< enable or disable the extended mode */
|
||||||
|
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||||
|
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
|
||||||
|
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||||
|
uint32_t nwait_config; /*!< NWAIT signal configuration */
|
||||||
|
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
|
||||||
|
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||||
|
uint32_t burst_mode; /*!< enable or disable the burst mode */
|
||||||
|
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||||
|
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||||
|
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||||
|
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing
|
||||||
|
parameters for read if the extendedmode is used. */
|
||||||
|
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */
|
||||||
|
}exmc_norsram_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC NAND/PC card timing initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||||
|
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
|
||||||
|
uint32_t waittime; /*!< configure the minimum wait time */
|
||||||
|
uint32_t setuptime; /*!< configure the address setup time */
|
||||||
|
}exmc_nand_pccard_timing_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC NAND initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||||
|
uint32_t ecc_size; /*!< the page size for the ECC calculation */
|
||||||
|
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||||
|
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||||
|
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
|
||||||
|
uint32_t databus_width; /*!< the NAND flash databus width */
|
||||||
|
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||||
|
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||||
|
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||||
|
}exmc_nand_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC PC card initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||||
|
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||||
|
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||||
|
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */
|
||||||
|
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */
|
||||||
|
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
||||||
|
}exmc_pccard_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC SDRAM timing initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t row_to_column_delay; /*!< configure the row to column delay */
|
||||||
|
uint32_t row_precharge_delay; /*!< configure the row precharge delay */
|
||||||
|
uint32_t write_recovery_delay; /*!< configure the write recovery delay */
|
||||||
|
uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */
|
||||||
|
uint32_t row_address_select_delay; /*!< configure the row address select delay */
|
||||||
|
uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */
|
||||||
|
uint32_t load_mode_register_delay; /*!< configure the load mode register delay */
|
||||||
|
}exmc_sdram_timing_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC SDRAM initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t sdram_device; /*!< device of SDRAM */
|
||||||
|
uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */
|
||||||
|
uint32_t burst_read_switch; /*!< enable or disable the burst read */
|
||||||
|
uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */
|
||||||
|
uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */
|
||||||
|
uint32_t cas_latency; /*!< configure the SDRAM CAS latency */
|
||||||
|
uint32_t internal_bank_number; /*!< the number of internal bank */
|
||||||
|
uint32_t data_width; /*!< the databus width of SDRAM memory */
|
||||||
|
uint32_t row_address_width; /*!< the bit width of a row address */
|
||||||
|
uint32_t column_address_width; /*!< the bit width of a column address */
|
||||||
|
exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */
|
||||||
|
}exmc_sdram_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC SDRAM command initialize structure */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t mode_register_content; /*!< the SDRAM mode register content */
|
||||||
|
uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */
|
||||||
|
uint32_t bank_select; /*!< the bank which command will be sent to */
|
||||||
|
uint32_t command; /*!< the commands that will be sent to SDRAM */
|
||||||
|
}exmc_sdram_command_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC SQPISRAM initialize structure */
|
||||||
|
typedef struct{
|
||||||
|
uint32_t sample_polarity; /*!< read data sample polarity */
|
||||||
|
uint32_t id_length; /*!< SPI PSRAM ID length */
|
||||||
|
uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */
|
||||||
|
uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */
|
||||||
|
}exmc_sqpipsram_parameter_struct;
|
||||||
|
|
||||||
|
/* EXMC register address */
|
||||||
|
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
||||||
|
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
||||||
|
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
||||||
|
|
||||||
|
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */
|
||||||
|
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */
|
||||||
|
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */
|
||||||
|
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */
|
||||||
|
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */
|
||||||
|
|
||||||
|
#define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */
|
||||||
|
#define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */
|
||||||
|
|
||||||
|
/* CRAM page size */
|
||||||
|
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||||
|
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
|
||||||
|
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
|
||||||
|
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
|
||||||
|
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
|
||||||
|
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
|
||||||
|
|
||||||
|
/* NOR bank memory data bus width */
|
||||||
|
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||||
|
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
|
||||||
|
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
|
||||||
|
|
||||||
|
/* NOR bank memory type */
|
||||||
|
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||||
|
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||||
|
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||||
|
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||||
|
|
||||||
|
/* asynchronous access mode */
|
||||||
|
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||||
|
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
|
||||||
|
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
|
||||||
|
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
|
||||||
|
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
|
||||||
|
|
||||||
|
/* data latency for NOR flash */
|
||||||
|
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||||
|
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
|
||||||
|
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
|
||||||
|
|
||||||
|
/* synchronous clock divide ratio */
|
||||||
|
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
|
||||||
|
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
|
||||||
|
|
||||||
|
/* ECC size */
|
||||||
|
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||||
|
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */
|
||||||
|
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */
|
||||||
|
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */
|
||||||
|
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */
|
||||||
|
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */
|
||||||
|
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */
|
||||||
|
|
||||||
|
/* ALE to RE delay */
|
||||||
|
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
|
||||||
|
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
|
||||||
|
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
|
||||||
|
|
||||||
|
/* CLE to RE delay */
|
||||||
|
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
|
||||||
|
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
|
||||||
|
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
|
||||||
|
|
||||||
|
/* NAND bank memory data bus width */
|
||||||
|
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||||
|
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */
|
||||||
|
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */
|
||||||
|
|
||||||
|
/* SDRAM pipeline delay */
|
||||||
|
#define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13))
|
||||||
|
#define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */
|
||||||
|
#define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */
|
||||||
|
#define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */
|
||||||
|
|
||||||
|
/* SDRAM clock configuration */
|
||||||
|
#define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10))
|
||||||
|
#define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */
|
||||||
|
#define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */
|
||||||
|
#define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */
|
||||||
|
|
||||||
|
/* CAS latency */
|
||||||
|
#define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7))
|
||||||
|
#define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */
|
||||||
|
#define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */
|
||||||
|
#define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */
|
||||||
|
|
||||||
|
/* SDRAM data bus width */
|
||||||
|
#define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||||
|
#define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */
|
||||||
|
#define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */
|
||||||
|
#define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */
|
||||||
|
|
||||||
|
/* SDRAM row address bit width */
|
||||||
|
#define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||||
|
#define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */
|
||||||
|
#define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */
|
||||||
|
#define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */
|
||||||
|
|
||||||
|
/* SDRAM column address bit width */
|
||||||
|
#define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */
|
||||||
|
#define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */
|
||||||
|
#define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */
|
||||||
|
#define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */
|
||||||
|
|
||||||
|
/* SDRAM number of successive auto-refresh */
|
||||||
|
#define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */
|
||||||
|
|
||||||
|
/* SDRAM command selection */
|
||||||
|
#define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||||
|
#define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */
|
||||||
|
#define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */
|
||||||
|
#define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */
|
||||||
|
#define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */
|
||||||
|
#define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */
|
||||||
|
#define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */
|
||||||
|
#define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */
|
||||||
|
|
||||||
|
/* SDRAM the delayed sample clock of read data */
|
||||||
|
#define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||||
|
#define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */
|
||||||
|
#define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */
|
||||||
|
#define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */
|
||||||
|
#define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */
|
||||||
|
#define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */
|
||||||
|
#define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */
|
||||||
|
#define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */
|
||||||
|
#define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */
|
||||||
|
#define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */
|
||||||
|
#define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */
|
||||||
|
#define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */
|
||||||
|
#define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */
|
||||||
|
#define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */
|
||||||
|
#define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */
|
||||||
|
#define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */
|
||||||
|
#define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */
|
||||||
|
|
||||||
|
/* SPI PSRAM ID length */
|
||||||
|
#define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29))
|
||||||
|
#define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */
|
||||||
|
|
||||||
|
/* SPI PSRAM bit number of address phase */
|
||||||
|
#define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24))
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */
|
||||||
|
|
||||||
|
/* SPI PSRAM bit number of command phase */
|
||||||
|
#define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||||
|
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */
|
||||||
|
#define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */
|
||||||
|
|
||||||
|
/* SPI PSRAM read command mode */
|
||||||
|
#define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||||
|
#define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */
|
||||||
|
|
||||||
|
/* SPI PSRAM write command mode */
|
||||||
|
#define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||||
|
#define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */
|
||||||
|
#define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */
|
||||||
|
|
||||||
|
/* EXMC NOR/SRAM bank region definition */
|
||||||
|
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||||
|
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
|
||||||
|
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
|
||||||
|
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
|
||||||
|
|
||||||
|
/* EXMC consecutive clock */
|
||||||
|
#define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */
|
||||||
|
#define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */
|
||||||
|
|
||||||
|
/* EXMC NOR/SRAM write mode */
|
||||||
|
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
|
||||||
|
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
|
||||||
|
|
||||||
|
/* EXMC NWAIT signal configuration */
|
||||||
|
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
|
||||||
|
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
|
||||||
|
|
||||||
|
/* EXMC NWAIT signal polarity configuration */
|
||||||
|
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||||
|
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
|
||||||
|
|
||||||
|
/* EXMC NAND/PC card bank definition */
|
||||||
|
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */
|
||||||
|
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */
|
||||||
|
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */
|
||||||
|
|
||||||
|
/* EXMC SDRAM bank definition */
|
||||||
|
#define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */
|
||||||
|
#define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */
|
||||||
|
|
||||||
|
/* EXMC SDRAM internal banks */
|
||||||
|
#define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */
|
||||||
|
#define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */
|
||||||
|
|
||||||
|
/* SDRAM device0 selection */
|
||||||
|
#define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */
|
||||||
|
#define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */
|
||||||
|
|
||||||
|
/* SDRAM device1 selection */
|
||||||
|
#define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */
|
||||||
|
#define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */
|
||||||
|
|
||||||
|
/* SDRAM device status */
|
||||||
|
#define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */
|
||||||
|
#define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */
|
||||||
|
#define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */
|
||||||
|
|
||||||
|
/* sample cycle of read data */
|
||||||
|
#define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||||
|
#define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */
|
||||||
|
|
||||||
|
/* read data sample polarity */
|
||||||
|
#define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */
|
||||||
|
#define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */
|
||||||
|
|
||||||
|
/* SQPI SRAM command flag */
|
||||||
|
#define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */
|
||||||
|
#define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */
|
||||||
|
|
||||||
|
/* EXMC flag bits */
|
||||||
|
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
|
||||||
|
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
|
||||||
|
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
|
||||||
|
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
|
||||||
|
#define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */
|
||||||
|
#define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */
|
||||||
|
|
||||||
|
/* EXMC interrupt flag bits */
|
||||||
|
#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */
|
||||||
|
#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */
|
||||||
|
#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */
|
||||||
|
#define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* NOR/SRAM */
|
||||||
|
/* deinitialize EXMC NOR/SRAM region */
|
||||||
|
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
|
||||||
|
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||||
|
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||||
|
/* initialize EXMC NOR/SRAM region */
|
||||||
|
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||||
|
/* enable EXMC NOR/SRAM region */
|
||||||
|
void exmc_norsram_enable(uint32_t exmc_norsram_region);
|
||||||
|
/* disable EXMC NOR/SRAM region */
|
||||||
|
void exmc_norsram_disable(uint32_t exmc_norsram_region);
|
||||||
|
/* NAND */
|
||||||
|
/* deinitialize EXMC NAND bank */
|
||||||
|
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
||||||
|
/* initialize exmc_nand_parameter_struct with the default values */
|
||||||
|
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||||
|
/* initialize EXMC NAND bank */
|
||||||
|
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||||
|
/* enable EXMC NAND bank */
|
||||||
|
void exmc_nand_enable(uint32_t exmc_nand_bank);
|
||||||
|
/* disable EXMC NAND bank */
|
||||||
|
void exmc_nand_disable(uint32_t exmc_nand_bank);
|
||||||
|
/* PC card */
|
||||||
|
/* deinitialize EXMC PC card bank */
|
||||||
|
void exmc_pccard_deinit(void);
|
||||||
|
/* initialize exmc_pccard_parameter_struct with the default values */
|
||||||
|
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||||
|
/* initialize EXMC PC card bank */
|
||||||
|
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||||
|
/* enable EXMC PC card bank */
|
||||||
|
void exmc_pccard_enable(void);
|
||||||
|
/* disable EXMC PC card bank */
|
||||||
|
void exmc_pccard_disable(void);
|
||||||
|
/* SDRAM */
|
||||||
|
/* deinitialize EXMC SDRAM device */
|
||||||
|
void exmc_sdram_deinit(uint32_t exmc_sdram_device);
|
||||||
|
/* initialize exmc_sdram_parameter_struct with the default values */
|
||||||
|
void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||||
|
/* initialize EXMC SDRAM device */
|
||||||
|
void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct);
|
||||||
|
/* initialize exmc_sdram_command_parameter_struct with the default values */
|
||||||
|
void exmc_sdram_struct_command_para_init(exmc_sdram_command_parameter_struct *exmc_sdram_command_init_struct);
|
||||||
|
/* SQPIPSRAM */
|
||||||
|
/* deinitialize EXMC SQPIPSRAM */
|
||||||
|
void exmc_sqpipsram_deinit(void);
|
||||||
|
/* initialize exmc_sqpipsram_parameter_struct with the default values */
|
||||||
|
void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||||
|
/* initialize EXMC SQPIPSRAM */
|
||||||
|
void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct);
|
||||||
|
|
||||||
|
/* function configuration */
|
||||||
|
/* NOR/SRAM */
|
||||||
|
/* configure consecutive clock */
|
||||||
|
void exmc_norsram_consecutive_clock_config(uint32_t clock_mode);
|
||||||
|
/* configure CRAM page size */
|
||||||
|
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
|
||||||
|
/* NAND */
|
||||||
|
/* enable or disable the EXMC NAND ECC function */
|
||||||
|
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
|
||||||
|
/* get the EXMC ECC value */
|
||||||
|
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
|
||||||
|
/* SDRAM */
|
||||||
|
/* enable or disable read sample */
|
||||||
|
void exmc_sdram_readsample_enable(ControlStatus newvalue);
|
||||||
|
/* configure the delayed sample clock of read data */
|
||||||
|
void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk);
|
||||||
|
/* configure the SDRAM memory command */
|
||||||
|
void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct);
|
||||||
|
/* set auto-refresh interval */
|
||||||
|
void exmc_sdram_refresh_count_set(uint32_t exmc_count);
|
||||||
|
/* set the number of successive auto-refresh command */
|
||||||
|
void exmc_sdram_autorefresh_number_set(uint32_t exmc_number);
|
||||||
|
/* configure the write protection function */
|
||||||
|
void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue);
|
||||||
|
/* get the status of SDRAM device0 or device1 */
|
||||||
|
uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device);
|
||||||
|
/* SQPIPSRAM */
|
||||||
|
/* set the read command */
|
||||||
|
void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code);
|
||||||
|
/* set the write command */
|
||||||
|
void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code);
|
||||||
|
/* send SPI read ID command */
|
||||||
|
void exmc_sqpipsram_read_id_command_send(void);
|
||||||
|
/* send SPI special command which does not have address and data phase */
|
||||||
|
void exmc_sqpipsram_write_cmd_send(void);
|
||||||
|
/* get the EXMC SPI ID low data */
|
||||||
|
uint32_t exmc_sqpipsram_low_id_get(void);
|
||||||
|
/* get the EXMC SPI ID high data */
|
||||||
|
uint32_t exmc_sqpipsram_high_id_get(void);
|
||||||
|
/* get the bit value of EXMC send write command bit or read ID command */
|
||||||
|
FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* enable EXMC interrupt */
|
||||||
|
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt);
|
||||||
|
/* disable EXMC interrupt */
|
||||||
|
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt);
|
||||||
|
/* get EXMC flag status */
|
||||||
|
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag);
|
||||||
|
/* clear EXMC flag status */
|
||||||
|
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag);
|
||||||
|
/* get EXMC interrupt flag */
|
||||||
|
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt);
|
||||||
|
/* clear EXMC interrupt flag */
|
||||||
|
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_EXMC_H */
|
||||||
@@ -0,0 +1,271 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_exti.h
|
||||||
|
\brief definitions for the EXTI
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_EXTI_H
|
||||||
|
#define GD32F4XX_EXTI_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* EXTI definitions */
|
||||||
|
#define EXTI EXTI_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
|
||||||
|
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
|
||||||
|
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
|
||||||
|
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
|
||||||
|
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
|
||||||
|
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* EXTI_INTEN */
|
||||||
|
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||||
|
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||||
|
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||||
|
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||||
|
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||||
|
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||||
|
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||||
|
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||||
|
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||||
|
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||||
|
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||||
|
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||||
|
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||||
|
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||||
|
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||||
|
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||||
|
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||||
|
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||||
|
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||||
|
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||||
|
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||||
|
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||||
|
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||||
|
|
||||||
|
/* EXTI_EVEN */
|
||||||
|
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||||
|
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||||
|
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||||
|
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||||
|
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||||
|
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||||
|
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||||
|
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||||
|
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||||
|
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||||
|
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||||
|
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||||
|
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||||
|
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||||
|
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||||
|
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||||
|
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||||
|
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||||
|
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||||
|
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||||
|
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||||
|
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||||
|
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||||
|
|
||||||
|
/* EXTI_RTEN */
|
||||||
|
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||||
|
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||||
|
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||||
|
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||||
|
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||||
|
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||||
|
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||||
|
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||||
|
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||||
|
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||||
|
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||||
|
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||||
|
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||||
|
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||||
|
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||||
|
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||||
|
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||||
|
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||||
|
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||||
|
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||||
|
#define EXTI_RTEN_RTEN20 BIT(20) /*!< rising edge from line 20 */
|
||||||
|
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||||
|
#define EXTI_RTEN_RTEN22 BIT(22) /*!< rising edge from line 22 */
|
||||||
|
|
||||||
|
/* EXTI_FTEN */
|
||||||
|
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||||
|
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||||
|
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||||
|
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||||
|
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||||
|
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||||
|
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||||
|
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||||
|
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||||
|
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||||
|
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||||
|
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||||
|
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||||
|
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||||
|
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||||
|
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||||
|
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||||
|
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||||
|
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||||
|
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||||
|
#define EXTI_FTEN_FTEN20 BIT(20) /*!< falling edge from line 20 */
|
||||||
|
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||||
|
#define EXTI_FTEN_FTEN22 BIT(22) /*!< falling edge from line 22 */
|
||||||
|
|
||||||
|
/* EXTI_SWIEV */
|
||||||
|
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||||
|
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||||
|
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||||
|
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||||
|
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||||
|
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||||
|
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||||
|
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||||
|
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||||
|
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||||
|
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||||
|
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||||
|
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||||
|
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||||
|
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||||
|
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||||
|
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||||
|
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||||
|
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||||
|
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||||
|
#define EXTI_SWIEV_SWIEV20 BIT(20) /*!< software interrupt/event request from line 20 */
|
||||||
|
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||||
|
#define EXTI_SWIEV_SWIEV22 BIT(22) /*!< software interrupt/event request from line 22 */
|
||||||
|
|
||||||
|
/* EXTI_PD */
|
||||||
|
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||||
|
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||||
|
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||||
|
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||||
|
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||||
|
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||||
|
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||||
|
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||||
|
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||||
|
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||||
|
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||||
|
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||||
|
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||||
|
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||||
|
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||||
|
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||||
|
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||||
|
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||||
|
#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
|
||||||
|
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||||
|
#define EXTI_PD_PD20 BIT(20) /*!< interrupt pending status from line 20 */
|
||||||
|
#define EXTI_PD_PD21 BIT(21) /*!< interrupt pending status from line 21 */
|
||||||
|
#define EXTI_PD_PD22 BIT(22) /*!< interrupt pending status from line 22 */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* EXTI line number */
|
||||||
|
typedef enum {
|
||||||
|
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||||
|
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||||
|
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||||
|
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||||
|
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||||
|
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||||
|
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||||
|
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||||
|
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||||
|
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||||
|
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||||
|
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||||
|
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||||
|
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||||
|
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||||
|
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||||
|
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||||
|
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||||
|
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||||
|
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||||
|
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||||
|
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||||
|
EXTI_22 = BIT(22) /*!< EXTI line 22 */
|
||||||
|
} exti_line_enum;
|
||||||
|
|
||||||
|
/* external interrupt and event */
|
||||||
|
typedef enum {
|
||||||
|
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||||
|
EXTI_EVENT /*!< EXTI event mode */
|
||||||
|
} exti_mode_enum;
|
||||||
|
|
||||||
|
/* interrupt trigger mode */
|
||||||
|
typedef enum {
|
||||||
|
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||||
|
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||||
|
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||||
|
EXTI_TRIG_NONE /*!< none EXTI edge trigger */
|
||||||
|
} exti_trig_type_enum;
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* deinitialize the EXTI */
|
||||||
|
void exti_deinit(void);
|
||||||
|
/* initialize the EXTI line x */
|
||||||
|
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||||
|
/* enable the interrupts from EXTI line x */
|
||||||
|
void exti_interrupt_enable(exti_line_enum linex);
|
||||||
|
/* disable the interrupts from EXTI line x */
|
||||||
|
void exti_interrupt_disable(exti_line_enum linex);
|
||||||
|
/* enable the events from EXTI line x */
|
||||||
|
void exti_event_enable(exti_line_enum linex);
|
||||||
|
/* disable the events from EXTI line x */
|
||||||
|
void exti_event_disable(exti_line_enum linex);
|
||||||
|
/* enable the software interrupt event from EXTI line x */
|
||||||
|
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||||
|
/* disable the software interrupt event from EXTI line x */
|
||||||
|
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* get EXTI line x interrupt pending flag */
|
||||||
|
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||||
|
/* clear EXTI line x interrupt pending flag */
|
||||||
|
void exti_flag_clear(exti_line_enum linex);
|
||||||
|
/* get EXTI line x interrupt pending flag */
|
||||||
|
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||||
|
/* clear EXTI line x interrupt pending flag */
|
||||||
|
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_EXTI_H */
|
||||||
@@ -0,0 +1,415 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_fmc.h
|
||||||
|
\brief definitions for the FMC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_FMC_H
|
||||||
|
#define GD32F4XX_FMC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* FMC and option byte definition */
|
||||||
|
#define FMC FMC_BASE /*!< FMC register base address */
|
||||||
|
#define OB OB_BASE /*!< option byte base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define FMC_WS REG32((FMC) + 0x00000000U) /*!< FMC wait state register */
|
||||||
|
#define FMC_KEY REG32((FMC) + 0x00000004U) /*!< FMC unlock key register */
|
||||||
|
#define FMC_OBKEY REG32((FMC) + 0x00000008U) /*!< FMC option byte unlock key register */
|
||||||
|
#define FMC_STAT REG32((FMC) + 0x0000000CU) /*!< FMC status register */
|
||||||
|
#define FMC_CTL REG32((FMC) + 0x00000010U) /*!< FMC control register */
|
||||||
|
#define FMC_OBCTL0 REG32((FMC) + 0x00000014U) /*!< FMC option byte control register 0 */
|
||||||
|
#define FMC_OBCTL1 REG32((FMC) + 0x00000018U) /*!< FMC option byte control register 1 */
|
||||||
|
#define FMC_PECFG REG32((FMC) + 0x00000020U) /*!< FMC page erase configuration register */
|
||||||
|
#define FMC_PEKEY REG32((FMC) + 0x00000024U) /*!< FMC unlock page erase key register */
|
||||||
|
#define FMC_WSEN REG32((FMC) + 0x000000FCU) /*!< FMC wait state enable register */
|
||||||
|
#define FMC_PID REG32((FMC) + 0x00000100U) /*!< FMC product ID register */
|
||||||
|
|
||||||
|
#define OB_WP1 REG32((OB) + 0x00000008U) /*!< option byte write protection 1 */
|
||||||
|
#define OB_USER REG32((OB) + 0x00010000U) /*!< option byte user value*/
|
||||||
|
#define OB_SPC REG32((OB) + 0x00010001U) /*!< option byte security protection value */
|
||||||
|
#define OB_WP0 REG32((OB) + 0x00010008U) /*!< option byte write protection 0 */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* FMC_WS */
|
||||||
|
#define FMC_WC_WSCNT BITS(0,3) /*!< wait state counter */
|
||||||
|
|
||||||
|
/* FMC_KEY */
|
||||||
|
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash key bits */
|
||||||
|
|
||||||
|
/* FMC_OBKEY */
|
||||||
|
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option byte key bits */
|
||||||
|
|
||||||
|
/* FMC_STAT */
|
||||||
|
#define FMC_STAT_END BIT(0) /*!< end of operation flag bit */
|
||||||
|
#define FMC_STAT_OPERR BIT(1) /*!< flash operation error flag bit */
|
||||||
|
#define FMC_STAT_WPERR BIT(4) /*!< erase/Program protection error flag bit */
|
||||||
|
#define FMC_STAT_PGMERR BIT(6) /*!< program size not match error flag bit */
|
||||||
|
#define FMC_STAT_PGSERR BIT(7) /*!< program sequence error flag bit */
|
||||||
|
#define FMC_STAT_RDDERR BIT(8) /*!< read D-bus protection error flag bit */
|
||||||
|
#define FMC_STAT_BUSY BIT(16) /*!< flash busy flag bit */
|
||||||
|
|
||||||
|
/* FMC_CTL */
|
||||||
|
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||||
|
#define FMC_CTL_SER BIT(1) /*!< main flash sector erase command bit */
|
||||||
|
#define FMC_CTL_MER0 BIT(2) /*!< main flash mass erase for bank0 command bit */
|
||||||
|
#define FMC_CTL_SN BITS(3,7) /*!< select which sector number to be erased */
|
||||||
|
#define FMC_CTL_PSZ BITS(8,9) /*!< program size bit */
|
||||||
|
#define FMC_CTL_MER1 BIT(15) /*!< main flash mass erase for bank1 command bit */
|
||||||
|
#define FMC_CTL_START BIT(16) /*!< send erase command to FMC bit */
|
||||||
|
#define FMC_CTL_ENDIE BIT(24) /*!< end of operation interrupt enable bit */
|
||||||
|
#define FMC_CTL_ERRIE BIT(25) /*!< error interrupt enable bit */
|
||||||
|
#define FMC_CTL_LK BIT(31) /*!< FMC_CTL lock bit */
|
||||||
|
|
||||||
|
/* FMC_OBCTL0 */
|
||||||
|
#define FMC_OBCTL0_OB_LK BIT(0) /*!< FMC_OBCTL0 lock bit */
|
||||||
|
#define FMC_OBCTL0_OB_START BIT(1) /*!< send option byte change command to FMC bit */
|
||||||
|
#define FMC_OBCTL0_BOR_TH BITS(2,3) /*!< option byte BOR threshold value */
|
||||||
|
#define FMC_OBCTL0_BB BIT(4) /*!< option byte boot bank value */
|
||||||
|
#define FMC_OBCTL0_NWDG_HW BIT(5) /*!< option byte watchdog value */
|
||||||
|
#define FMC_OBCTL0_NRST_DPSLP BIT(6) /*!< option byte deepsleep reset value */
|
||||||
|
#define FMC_OBCTL0_NRST_STDBY BIT(7) /*!< option byte standby reset value */
|
||||||
|
#define FMC_OBCTL0_SPC BITS(8,15) /*!< option byte Security Protection code */
|
||||||
|
#define FMC_OBCTL0_WP0 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
||||||
|
#define FMC_OBCTL0_DBS BIT(30) /*!< double banks or single bank selection when flash size is 1M bytes */
|
||||||
|
#define FMC_OBCTL0_DRP BIT(31) /*!< D-bus read protection bit */
|
||||||
|
|
||||||
|
/* FMC_OBCTL1 */
|
||||||
|
#define FMC_OBCTL1_WP1 BITS(16,27) /*!< erase/program protection of each sector when DRP is 0 */
|
||||||
|
|
||||||
|
/* FMC_PECFG */
|
||||||
|
#define FMC_PE_EN BIT(31) /*!< the enable bit of page erase function */
|
||||||
|
#define FMC_PE_ADDR BITS(0,28) /*!< page erase address */
|
||||||
|
|
||||||
|
/* FMC_PEKEY */
|
||||||
|
#define FMC_PE_KEY BITS(0,31) /*!< FMC_PECFG unlock key value */
|
||||||
|
|
||||||
|
/* FMC_WSEN */
|
||||||
|
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||||
|
|
||||||
|
/* FMC_PID */
|
||||||
|
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* fmc state */
|
||||||
|
typedef enum {
|
||||||
|
FMC_READY = 0, /*!< the operation has been completed */
|
||||||
|
FMC_BUSY, /*!< the operation is in progress */
|
||||||
|
FMC_RDDERR, /*!< read D-bus protection error */
|
||||||
|
FMC_PGSERR, /*!< program sequence error */
|
||||||
|
FMC_PGMERR, /*!< program size not match error */
|
||||||
|
FMC_WPERR, /*!< erase/program protection error */
|
||||||
|
FMC_OPERR, /*!< operation error */
|
||||||
|
FMC_TOERR /*!< timeout error */
|
||||||
|
} fmc_state_enum;
|
||||||
|
|
||||||
|
/* unlock key */
|
||||||
|
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||||
|
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||||
|
#define UNLOCK_PE_KEY ((uint32_t)0xA9B8C7D6U) /*!< unlock page erase function key */
|
||||||
|
|
||||||
|
#define OB_UNLOCK_KEY0 ((uint32_t)0x08192A3BU) /*!< ob unlock key 0 */
|
||||||
|
#define OB_UNLOCK_KEY1 ((uint32_t)0x4C5D6E7FU) /*!< ob unlock key 1 */
|
||||||
|
|
||||||
|
/* option byte write protection */
|
||||||
|
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||||
|
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||||
|
|
||||||
|
/* FMC wait state counter */
|
||||||
|
#define WC_WSCNT(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||||
|
#define WS_WSCNT_0 WC_WSCNT(0) /*!< FMC 0 wait */
|
||||||
|
#define WS_WSCNT_1 WC_WSCNT(1) /*!< FMC 1 wait */
|
||||||
|
#define WS_WSCNT_2 WC_WSCNT(2) /*!< FMC 2 wait */
|
||||||
|
#define WS_WSCNT_3 WC_WSCNT(3) /*!< FMC 3 wait */
|
||||||
|
#define WS_WSCNT_4 WC_WSCNT(4) /*!< FMC 4 wait */
|
||||||
|
#define WS_WSCNT_5 WC_WSCNT(5) /*!< FMC 5 wait */
|
||||||
|
#define WS_WSCNT_6 WC_WSCNT(6) /*!< FMC 6 wait */
|
||||||
|
#define WS_WSCNT_7 WC_WSCNT(7) /*!< FMC 7 wait */
|
||||||
|
#define WS_WSCNT_8 WC_WSCNT(8) /*!< FMC 8 wait */
|
||||||
|
#define WS_WSCNT_9 WC_WSCNT(9) /*!< FMC 9 wait */
|
||||||
|
#define WS_WSCNT_10 WC_WSCNT(10) /*!< FMC 10 wait */
|
||||||
|
#define WS_WSCNT_11 WC_WSCNT(11) /*!< FMC 11 wait */
|
||||||
|
#define WS_WSCNT_12 WC_WSCNT(12) /*!< FMC 12 wait */
|
||||||
|
#define WS_WSCNT_13 WC_WSCNT(13) /*!< FMC 13 wait */
|
||||||
|
#define WS_WSCNT_14 WC_WSCNT(14) /*!< FMC 14 wait */
|
||||||
|
#define WS_WSCNT_15 WC_WSCNT(15) /*!< FMC 15 wait */
|
||||||
|
|
||||||
|
/* option byte BOR threshold value */
|
||||||
|
#define OBCTL0_BOR_TH(regval) (BITS(2,3) & ((uint32_t)(regval))<< 2)
|
||||||
|
#define OB_BOR_TH_VALUE3 OBCTL0_BOR_TH(0) /*!< BOR threshold value 3 */
|
||||||
|
#define OB_BOR_TH_VALUE2 OBCTL0_BOR_TH(1) /*!< BOR threshold value 2 */
|
||||||
|
#define OB_BOR_TH_VALUE1 OBCTL0_BOR_TH(2) /*!< BOR threshold value 1 */
|
||||||
|
#define OB_BOR_TH_OFF OBCTL0_BOR_TH(3) /*!< no BOR function */
|
||||||
|
|
||||||
|
/* option byte boot bank value */
|
||||||
|
#define OBCTL0_BB(regval) (BIT(4) & ((uint32_t)(regval)<<4))
|
||||||
|
#define OB_BB_DISABLE OBCTL0_BB(0) /*!< boot from bank0 */
|
||||||
|
#define OB_BB_ENABLE OBCTL0_BB(1) /*!< boot from bank1 or bank0 if bank1 is void */
|
||||||
|
|
||||||
|
/* option byte software/hardware free watch dog timer */
|
||||||
|
#define OBCTL0_NWDG_HW(regval) (BIT(5) & ((uint32_t)(regval))<< 5)
|
||||||
|
#define OB_FWDGT_SW OBCTL0_NWDG_HW(1) /*!< software free watchdog */
|
||||||
|
#define OB_FWDGT_HW OBCTL0_NWDG_HW(0) /*!< hardware free watchdog */
|
||||||
|
|
||||||
|
/* option byte reset or not entering deep sleep mode */
|
||||||
|
#define OBCTL0_NRST_DPSLP(regval) (BIT(6) & ((uint32_t)(regval))<< 6)
|
||||||
|
#define OB_DEEPSLEEP_NRST OBCTL0_NRST_DPSLP(1) /*!< no reset when entering deepsleep mode */
|
||||||
|
#define OB_DEEPSLEEP_RST OBCTL0_NRST_DPSLP(0) /*!< generate a reset instead of entering deepsleep mode */
|
||||||
|
|
||||||
|
/* option byte reset or not entering standby mode */
|
||||||
|
#define OBCTL0_NRST_STDBY(regval) (BIT(7) & ((uint32_t)(regval))<< 7)
|
||||||
|
#define OB_STDBY_NRST OBCTL0_NRST_STDBY(1) /*!< no reset when entering deepsleep mode */
|
||||||
|
#define OB_STDBY_RST OBCTL0_NRST_STDBY(0) /*!< generate a reset instead of entering standby mode */
|
||||||
|
|
||||||
|
/* read protect configure */
|
||||||
|
#define FMC_NSPC ((uint8_t)0xAAU) /*!< no security protection */
|
||||||
|
#define FMC_LSPC ((uint8_t)0xABU) /*!< low security protection */
|
||||||
|
#define FMC_HSPC ((uint8_t)0xCCU) /*!< high security protection */
|
||||||
|
|
||||||
|
/* option bytes write protection */
|
||||||
|
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
||||||
|
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
||||||
|
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
||||||
|
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
||||||
|
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
||||||
|
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
||||||
|
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
||||||
|
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
||||||
|
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
||||||
|
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
||||||
|
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
||||||
|
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
||||||
|
#define OB_WP_12 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 12 */
|
||||||
|
#define OB_WP_13 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 13 */
|
||||||
|
#define OB_WP_14 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 14 */
|
||||||
|
#define OB_WP_15 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 15 */
|
||||||
|
#define OB_WP_16 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 16 */
|
||||||
|
#define OB_WP_17 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 17 */
|
||||||
|
#define OB_WP_18 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 18 */
|
||||||
|
#define OB_WP_19 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 19 */
|
||||||
|
#define OB_WP_20 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 20 */
|
||||||
|
#define OB_WP_21 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 21 */
|
||||||
|
#define OB_WP_22 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 22 */
|
||||||
|
#define OB_WP_23_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 23~27 */
|
||||||
|
#define OB_WP_ALL ((uint32_t)0x0FFF0FFFU) /*!< erase/program protection of all sectors */
|
||||||
|
|
||||||
|
/* option bytes D-bus read protection */
|
||||||
|
#define OB_DRP_0 ((uint32_t)0x00000001U) /*!< D-bus read protection protection of sector 0 */
|
||||||
|
#define OB_DRP_1 ((uint32_t)0x00000002U) /*!< D-bus read protection protection of sector 1 */
|
||||||
|
#define OB_DRP_2 ((uint32_t)0x00000004U) /*!< D-bus read protection protection of sector 2 */
|
||||||
|
#define OB_DRP_3 ((uint32_t)0x00000008U) /*!< D-bus read protection protection of sector 3 */
|
||||||
|
#define OB_DRP_4 ((uint32_t)0x00000010U) /*!< D-bus read protection protection of sector 4 */
|
||||||
|
#define OB_DRP_5 ((uint32_t)0x00000020U) /*!< D-bus read protection protection of sector 5 */
|
||||||
|
#define OB_DRP_6 ((uint32_t)0x00000040U) /*!< D-bus read protection protection of sector 6 */
|
||||||
|
#define OB_DRP_7 ((uint32_t)0x00000080U) /*!< D-bus read protection protection of sector 7 */
|
||||||
|
#define OB_DRP_8 ((uint32_t)0x00000100U) /*!< D-bus read protection protection of sector 8 */
|
||||||
|
#define OB_DRP_9 ((uint32_t)0x00000200U) /*!< D-bus read protection protection of sector 9 */
|
||||||
|
#define OB_DRP_10 ((uint32_t)0x00000400U) /*!< D-bus read protection protection of sector 10 */
|
||||||
|
#define OB_DRP_11 ((uint32_t)0x00000800U) /*!< D-bus read protection protection of sector 11 */
|
||||||
|
#define OB_DRP_12 ((uint32_t)0x00010000U) /*!< D-bus read protection protection of sector 12 */
|
||||||
|
#define OB_DRP_13 ((uint32_t)0x00020000U) /*!< D-bus read protection protection of sector 13 */
|
||||||
|
#define OB_DRP_14 ((uint32_t)0x00040000U) /*!< D-bus read protection protection of sector 14 */
|
||||||
|
#define OB_DRP_15 ((uint32_t)0x00080000U) /*!< D-bus read protection protection of sector 15 */
|
||||||
|
#define OB_DRP_16 ((uint32_t)0x00100000U) /*!< D-bus read protection protection of sector 16 */
|
||||||
|
#define OB_DRP_17 ((uint32_t)0x00200000U) /*!< D-bus read protection protection of sector 17 */
|
||||||
|
#define OB_DRP_18 ((uint32_t)0x00400000U) /*!< D-bus read protection protection of sector 18 */
|
||||||
|
#define OB_DRP_19 ((uint32_t)0x00800000U) /*!< D-bus read protection protection of sector 19 */
|
||||||
|
#define OB_DRP_20 ((uint32_t)0x01000000U) /*!< D-bus read protection protection of sector 20 */
|
||||||
|
#define OB_DRP_21 ((uint32_t)0x02000000U) /*!< D-bus read protection protection of sector 21 */
|
||||||
|
#define OB_DRP_22 ((uint32_t)0x04000000U) /*!< D-bus read protection protection of sector 22 */
|
||||||
|
#define OB_DRP_23_27 ((uint32_t)0x08000000U) /*!< D-bus read protection protection of sector 23~27 */
|
||||||
|
#define OB_DRP_ALL ((uint32_t)0x0FFF0FFFU) /*!< D-bus read protection protection of all sectors */
|
||||||
|
|
||||||
|
/* double banks or single bank selection when flash size is 1M bytes */
|
||||||
|
#define OBCTL0_DBS(regval) (BIT(30) & ((uint32_t)(regval) << 30U))
|
||||||
|
#define OB_DBS_DISABLE OBCTL0_DBS(0) /*!< single bank when flash size is 1M bytes */
|
||||||
|
#define OB_DBS_ENABLE OBCTL0_DBS(1) /*!< double bank when flash size is 1M bytes */
|
||||||
|
|
||||||
|
/* option bytes D-bus read protection mode */
|
||||||
|
#define OBCTL0_DRP(regval) (BIT(31) & ((uint32_t)(regval) << 31U))
|
||||||
|
#define OB_DRP_DISABLE OBCTL0_DRP(0) /*!< the WPx bits used as erase/program protection of each sector */
|
||||||
|
#define OB_DRP_ENABLE OBCTL0_DRP(1) /*!< the WPx bits used as erase/program protection and D-bus read protection of each sector */
|
||||||
|
|
||||||
|
/* FMC sectors */
|
||||||
|
#define CTL_SN(regval) (BITS(3,7) & ((uint32_t)(regval))<< 3)
|
||||||
|
#define CTL_SECTOR_NUMBER_0 CTL_SN(0) /*!< sector 0 */
|
||||||
|
#define CTL_SECTOR_NUMBER_1 CTL_SN(1) /*!< sector 1 */
|
||||||
|
#define CTL_SECTOR_NUMBER_2 CTL_SN(2) /*!< sector 2 */
|
||||||
|
#define CTL_SECTOR_NUMBER_3 CTL_SN(3) /*!< sector 3 */
|
||||||
|
#define CTL_SECTOR_NUMBER_4 CTL_SN(4) /*!< sector 4 */
|
||||||
|
#define CTL_SECTOR_NUMBER_5 CTL_SN(5) /*!< sector 5 */
|
||||||
|
#define CTL_SECTOR_NUMBER_6 CTL_SN(6) /*!< sector 6 */
|
||||||
|
#define CTL_SECTOR_NUMBER_7 CTL_SN(7) /*!< sector 7 */
|
||||||
|
#define CTL_SECTOR_NUMBER_8 CTL_SN(8) /*!< sector 8 */
|
||||||
|
#define CTL_SECTOR_NUMBER_9 CTL_SN(9) /*!< sector 9 */
|
||||||
|
#define CTL_SECTOR_NUMBER_10 CTL_SN(10) /*!< sector 10 */
|
||||||
|
#define CTL_SECTOR_NUMBER_11 CTL_SN(11) /*!< sector 11 */
|
||||||
|
#define CTL_SECTOR_NUMBER_24 CTL_SN(12) /*!< sector 24 */
|
||||||
|
#define CTL_SECTOR_NUMBER_25 CTL_SN(13) /*!< sector 25 */
|
||||||
|
#define CTL_SECTOR_NUMBER_26 CTL_SN(14) /*!< sector 26 */
|
||||||
|
#define CTL_SECTOR_NUMBER_27 CTL_SN(15) /*!< sector 27 */
|
||||||
|
#define CTL_SECTOR_NUMBER_12 CTL_SN(16) /*!< sector 12 */
|
||||||
|
#define CTL_SECTOR_NUMBER_13 CTL_SN(17) /*!< sector 13 */
|
||||||
|
#define CTL_SECTOR_NUMBER_14 CTL_SN(18) /*!< sector 14 */
|
||||||
|
#define CTL_SECTOR_NUMBER_15 CTL_SN(19) /*!< sector 15 */
|
||||||
|
#define CTL_SECTOR_NUMBER_16 CTL_SN(20) /*!< sector 16 */
|
||||||
|
#define CTL_SECTOR_NUMBER_17 CTL_SN(21) /*!< sector 17 */
|
||||||
|
#define CTL_SECTOR_NUMBER_18 CTL_SN(22) /*!< sector 18 */
|
||||||
|
#define CTL_SECTOR_NUMBER_19 CTL_SN(23) /*!< sector 19 */
|
||||||
|
#define CTL_SECTOR_NUMBER_20 CTL_SN(24) /*!< sector 20 */
|
||||||
|
#define CTL_SECTOR_NUMBER_21 CTL_SN(25) /*!< sector 21 */
|
||||||
|
#define CTL_SECTOR_NUMBER_22 CTL_SN(26) /*!< sector 22 */
|
||||||
|
#define CTL_SECTOR_NUMBER_23 CTL_SN(27) /*!< sector 23 */
|
||||||
|
|
||||||
|
|
||||||
|
/* FMC program size */
|
||||||
|
#define CTL_PSZ(regval) (BITS(8,9) & ((uint32_t)(regval))<< 8U)
|
||||||
|
#define CTL_PSZ_BYTE CTL_PSZ(0) /*!< FMC program by byte access */
|
||||||
|
#define CTL_PSZ_HALF_WORD CTL_PSZ(1) /*!< FMC program by half-word access */
|
||||||
|
#define CTL_PSZ_WORD CTL_PSZ(2) /*!< FMC program by word access */
|
||||||
|
|
||||||
|
/* FMC interrupt enable */
|
||||||
|
#define FMC_INT_END ((uint32_t)0x01000000U) /*!< enable FMC end of program interrupt */
|
||||||
|
#define FMC_INT_ERR ((uint32_t)0x02000000U) /*!< enable FMC error interrupt */
|
||||||
|
|
||||||
|
/* FMC flags */
|
||||||
|
#define FMC_FLAG_END FMC_STAT_END /*!< FMC end of operation flag bit */
|
||||||
|
#define FMC_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error flag bit */
|
||||||
|
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error flag bit */
|
||||||
|
#define FMC_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error flag bit */
|
||||||
|
#define FMC_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error flag bit */
|
||||||
|
#define FMC_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error flag bit */
|
||||||
|
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||||
|
|
||||||
|
/* FMC interrupt flags */
|
||||||
|
#define FMC_INT_FLAG_END FMC_STAT_END /*!< FMC end of operation interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_OPERR FMC_STAT_OPERR /*!< FMC operation error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC erase/program protection error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_PGMERR FMC_STAT_PGMERR /*!< FMC program size not match error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_PGSERR FMC_STAT_PGSERR /*!< FMC program sequence error interrupt flag */
|
||||||
|
#define FMC_INT_FLAG_RDDERR FMC_STAT_RDDERR /*!< FMC read D-bus protection error interrupt flag */
|
||||||
|
|
||||||
|
|
||||||
|
/* FMC time out */
|
||||||
|
#define FMC_TIMEOUT_COUNT ((uint32_t)0x4FFFFFFFU) /*!< count to judge of FMC timeout */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* FMC main memory programming functions */
|
||||||
|
/* set the FMC wait state counter */
|
||||||
|
void fmc_wscnt_set(uint32_t wscnt);
|
||||||
|
/* unlock the main FMC operation */
|
||||||
|
void fmc_unlock(void);
|
||||||
|
/* lock the main FMC operation */
|
||||||
|
void fmc_lock(void);
|
||||||
|
#if defined (GD32F425) || defined (GD32F427) || defined (GD32F470)
|
||||||
|
/* FMC erase page */
|
||||||
|
fmc_state_enum fmc_page_erase(uint32_t page_addr);
|
||||||
|
#endif
|
||||||
|
/* FMC erase sector */
|
||||||
|
fmc_state_enum fmc_sector_erase(uint32_t fmc_sector);
|
||||||
|
/* FMC erase whole chip */
|
||||||
|
fmc_state_enum fmc_mass_erase(void);
|
||||||
|
/* FMC erase whole bank0 */
|
||||||
|
fmc_state_enum fmc_bank0_erase(void);
|
||||||
|
/* FMC erase whole bank1 */
|
||||||
|
fmc_state_enum fmc_bank1_erase(void);
|
||||||
|
/* FMC program a word at the corresponding address */
|
||||||
|
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||||
|
/* FMC program a half word at the corresponding address */
|
||||||
|
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||||
|
/* FMC program a byte at the corresponding address */
|
||||||
|
fmc_state_enum fmc_byte_program(uint32_t address, uint8_t data);
|
||||||
|
|
||||||
|
/* FMC option bytes programming functions */
|
||||||
|
/* unlock the option byte operation */
|
||||||
|
void ob_unlock(void);
|
||||||
|
/* lock the option byte operation */
|
||||||
|
void ob_lock(void);
|
||||||
|
/* send option byte change command */
|
||||||
|
void ob_start(void);
|
||||||
|
/* erase option byte */
|
||||||
|
void ob_erase(void);
|
||||||
|
/* enable write protect */
|
||||||
|
ErrStatus ob_write_protection_enable(uint32_t ob_wp);
|
||||||
|
/* disable write protect */
|
||||||
|
ErrStatus ob_write_protection_disable(uint32_t ob_wp);
|
||||||
|
/* enable erase/program protection and D-bus read protection */
|
||||||
|
void ob_drp_enable(uint32_t ob_drp);
|
||||||
|
/* disable erase/program protection and D-bus read protection */
|
||||||
|
void ob_drp_disable(void);
|
||||||
|
/* configure security protection level */
|
||||||
|
void ob_security_protection_config(uint8_t ob_spc);
|
||||||
|
/* program the FMC user option byte */
|
||||||
|
void ob_user_write(uint32_t ob_fwdgt, uint32_t ob_deepsleep, uint32_t ob_stdby);
|
||||||
|
/* program the option byte BOR threshold value */
|
||||||
|
void ob_user_bor_threshold(uint32_t ob_bor_th);
|
||||||
|
/* configure the boot mode */
|
||||||
|
void ob_boot_mode_config(uint32_t boot_mode);
|
||||||
|
#if defined (GD32F450) || defined (GD32F470)
|
||||||
|
/* configure the double bank select */
|
||||||
|
void ob_double_bank_select(uint32_t double_bank);
|
||||||
|
#endif
|
||||||
|
/* get the FMC user option byte */
|
||||||
|
uint8_t ob_user_get(void);
|
||||||
|
/* get the FMC option byte write protection */
|
||||||
|
uint16_t ob_write_protection0_get(void);
|
||||||
|
/* get the FMC option byte write protection */
|
||||||
|
uint16_t ob_write_protection1_get(void);
|
||||||
|
/* get the FMC erase/program protection and D-bus read protection option bytes value */
|
||||||
|
uint16_t ob_drp0_get(void);
|
||||||
|
/* get the FMC erase/program protection and D-bus read protection option bytes value */
|
||||||
|
uint16_t ob_drp1_get(void);
|
||||||
|
/* get option byte security protection code value */
|
||||||
|
FlagStatus ob_spc_get(void);
|
||||||
|
/* get the FMC option byte BOR threshold value */
|
||||||
|
uint8_t ob_user_bor_threshold_get(void);
|
||||||
|
|
||||||
|
/* FMC interrupts and flags management functions */
|
||||||
|
/* get flag set or reset */
|
||||||
|
FlagStatus fmc_flag_get(uint32_t fmc_flag);
|
||||||
|
/* clear the FMC pending flag */
|
||||||
|
void fmc_flag_clear(uint32_t fmc_flag);
|
||||||
|
/* enable FMC interrupt */
|
||||||
|
void fmc_interrupt_enable(uint32_t fmc_int);
|
||||||
|
/* disable FMC interrupt */
|
||||||
|
void fmc_interrupt_disable(uint32_t fmc_int);
|
||||||
|
/* get FMC interrupt flag set or reset */
|
||||||
|
FlagStatus fmc_interrupt_flag_get(uint32_t fmc_int_flag);
|
||||||
|
/* clear the FMC interrupt flag */
|
||||||
|
void fmc_interrupt_flag_clear(uint32_t fmc_int_flag);
|
||||||
|
/* get the FMC state */
|
||||||
|
fmc_state_enum fmc_state_get(void);
|
||||||
|
/* check whether FMC is ready or not */
|
||||||
|
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_FMC_H */
|
||||||
@@ -0,0 +1,111 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_fwdgt.h
|
||||||
|
\brief definitions for the FWDGT
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_FWDGT_H
|
||||||
|
#define GD32F4XX_FWDGT_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* FWDGT definitions */
|
||||||
|
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||||
|
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
|
||||||
|
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
|
||||||
|
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* FWDGT_CTL */
|
||||||
|
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||||
|
|
||||||
|
/* FWDGT_PSC */
|
||||||
|
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||||
|
|
||||||
|
/* FWDGT_RLD */
|
||||||
|
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||||
|
|
||||||
|
/* FWDGT_STAT */
|
||||||
|
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||||
|
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* psc register value */
|
||||||
|
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||||
|
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||||
|
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||||
|
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||||
|
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||||
|
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||||
|
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||||
|
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||||
|
|
||||||
|
/* control value */
|
||||||
|
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||||
|
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||||
|
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||||
|
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||||
|
|
||||||
|
/* FWDGT timeout value */
|
||||||
|
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||||
|
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||||
|
|
||||||
|
/* FWDGT flag definitions */
|
||||||
|
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||||
|
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||||
|
|
||||||
|
/* write value to FWDGT_RLD_RLD bit field */
|
||||||
|
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||||
|
void fwdgt_write_enable(void);
|
||||||
|
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||||
|
void fwdgt_write_disable(void);
|
||||||
|
/* start the free watchdog timer counter */
|
||||||
|
void fwdgt_enable(void);
|
||||||
|
|
||||||
|
/* configure the free watchdog timer counter prescaler value */
|
||||||
|
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||||
|
/* configure the free watchdog timer counter reload value */
|
||||||
|
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||||
|
/* reload the counter of FWDGT */
|
||||||
|
void fwdgt_counter_reload(void);
|
||||||
|
/* configure counter reload value, and prescaler divider value */
|
||||||
|
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value);
|
||||||
|
|
||||||
|
/* get flag state of FWDGT */
|
||||||
|
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_FWDGT_H */
|
||||||
@@ -0,0 +1,406 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_gpio.h
|
||||||
|
\brief definitions for the GPIO
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_GPIO_H
|
||||||
|
#define GD32F4XX_GPIO_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions */
|
||||||
|
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||||
|
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||||
|
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||||
|
#define GPIOD (GPIO_BASE + 0x00000C00U)
|
||||||
|
#define GPIOE (GPIO_BASE + 0x00001000U)
|
||||||
|
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||||
|
#define GPIOG (GPIO_BASE + 0x00001800U)
|
||||||
|
#define GPIOH (GPIO_BASE + 0x00001C00U)
|
||||||
|
#define GPIOI (GPIO_BASE + 0x00002000U)
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
|
||||||
|
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
|
||||||
|
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
|
||||||
|
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||||
|
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||||
|
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||||
|
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operate register */
|
||||||
|
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||||
|
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||||
|
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||||
|
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
|
||||||
|
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* GPIO_CTL */
|
||||||
|
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||||
|
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||||
|
|
||||||
|
/* GPIO_OMODE */
|
||||||
|
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||||
|
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||||
|
|
||||||
|
/* GPIO_OSPD */
|
||||||
|
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||||
|
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||||
|
|
||||||
|
/* GPIO_PUD */
|
||||||
|
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||||
|
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||||
|
|
||||||
|
/* GPIO_ISTAT */
|
||||||
|
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||||
|
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||||
|
|
||||||
|
/* GPIO_OCTL */
|
||||||
|
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output control bit */
|
||||||
|
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output control bit */
|
||||||
|
|
||||||
|
/* GPIO_BOP */
|
||||||
|
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||||
|
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||||
|
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||||
|
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||||
|
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||||
|
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||||
|
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||||
|
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||||
|
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||||
|
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||||
|
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||||
|
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||||
|
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||||
|
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||||
|
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||||
|
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||||
|
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||||
|
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||||
|
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||||
|
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||||
|
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||||
|
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||||
|
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||||
|
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||||
|
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||||
|
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||||
|
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||||
|
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||||
|
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||||
|
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||||
|
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||||
|
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||||
|
|
||||||
|
/* GPIO_LOCK */
|
||||||
|
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||||
|
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||||
|
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||||
|
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||||
|
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||||
|
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||||
|
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||||
|
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||||
|
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||||
|
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||||
|
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||||
|
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||||
|
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||||
|
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||||
|
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||||
|
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||||
|
#define GPIO_LOCK_LKK BIT(16) /*!< pin lock sequence key */
|
||||||
|
|
||||||
|
/* GPIO_AFSEL0 */
|
||||||
|
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||||
|
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||||
|
|
||||||
|
/* GPIO_AFSEL1 */
|
||||||
|
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||||
|
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||||
|
|
||||||
|
/* GPIO_BC */
|
||||||
|
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||||
|
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||||
|
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||||
|
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||||
|
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||||
|
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||||
|
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||||
|
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||||
|
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||||
|
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||||
|
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||||
|
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||||
|
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||||
|
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||||
|
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||||
|
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||||
|
|
||||||
|
/* GPIO_TG */
|
||||||
|
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||||
|
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||||
|
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||||
|
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||||
|
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||||
|
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||||
|
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||||
|
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||||
|
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||||
|
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||||
|
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||||
|
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||||
|
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||||
|
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||||
|
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||||
|
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
typedef FlagStatus bit_status;
|
||||||
|
|
||||||
|
/* output mode definitions */
|
||||||
|
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||||
|
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||||
|
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||||
|
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||||
|
|
||||||
|
/* pull-up/ pull-down definitions */
|
||||||
|
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||||
|
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||||
|
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||||
|
|
||||||
|
/* GPIO pin definitions */
|
||||||
|
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||||
|
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||||
|
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||||
|
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||||
|
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||||
|
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||||
|
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||||
|
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||||
|
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||||
|
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||||
|
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||||
|
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||||
|
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||||
|
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||||
|
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||||
|
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||||
|
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||||
|
|
||||||
|
/* GPIO mode configuration values */
|
||||||
|
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||||
|
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
|
||||||
|
|
||||||
|
/* GPIO pull-up/ pull-down values */
|
||||||
|
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||||
|
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
|
||||||
|
|
||||||
|
/* GPIO output speed values */
|
||||||
|
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||||
|
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
|
||||||
|
|
||||||
|
/* GPIO output type */
|
||||||
|
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||||
|
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||||
|
|
||||||
|
/* GPIO output max speed level */
|
||||||
|
#define OSPD_OSPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define GPIO_OSPEED_LEVEL0 OSPD_OSPD(0) /*!< output max speed level 0 */
|
||||||
|
#define GPIO_OSPEED_LEVEL1 OSPD_OSPD(1) /*!< output max speed level 1 */
|
||||||
|
#define GPIO_OSPEED_LEVEL2 OSPD_OSPD(2) /*!< output max speed level 2 */
|
||||||
|
#define GPIO_OSPEED_LEVEL3 OSPD_OSPD(3) /*!< output max speed level 3 */
|
||||||
|
|
||||||
|
/* GPIO output max speed value */
|
||||||
|
#define GPIO_OSPEED_2MHZ GPIO_OSPEED_LEVEL0 /*!< output max speed 2MHz */
|
||||||
|
#define GPIO_OSPEED_25MHZ GPIO_OSPEED_LEVEL1 /*!< output max speed 25MHz */
|
||||||
|
#define GPIO_OSPEED_50MHZ GPIO_OSPEED_LEVEL2 /*!< output max speed 50MHz */
|
||||||
|
#define GPIO_OSPEED_MAX GPIO_OSPEED_LEVEL3 /*!< GPIO very high output speed, max speed more than 50MHz */
|
||||||
|
|
||||||
|
/* GPIO alternate function values */
|
||||||
|
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||||
|
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
|
||||||
|
|
||||||
|
/* GPIO alternate function */
|
||||||
|
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||||
|
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||||
|
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||||
|
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||||
|
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||||
|
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected */
|
||||||
|
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected */
|
||||||
|
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected */
|
||||||
|
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected */
|
||||||
|
#define GPIO_AF_8 AF(8) /*!< alternate function 8 selected */
|
||||||
|
#define GPIO_AF_9 AF(9) /*!< alternate function 9 selected */
|
||||||
|
#define GPIO_AF_10 AF(10) /*!< alternate function 10 selected */
|
||||||
|
#define GPIO_AF_11 AF(11) /*!< alternate function 11 selected */
|
||||||
|
#define GPIO_AF_12 AF(12) /*!< alternate function 12 selected */
|
||||||
|
#define GPIO_AF_13 AF(13) /*!< alternate function 13 selected */
|
||||||
|
#define GPIO_AF_14 AF(14) /*!< alternate function 14 selected */
|
||||||
|
#define GPIO_AF_15 AF(15) /*!< alternate function 15 selected */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* reset GPIO port */
|
||||||
|
void gpio_deinit(uint32_t gpio_periph);
|
||||||
|
/* set GPIO mode */
|
||||||
|
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||||
|
/* set GPIO output type and speed */
|
||||||
|
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||||
|
|
||||||
|
/* set GPIO pin bit */
|
||||||
|
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
/* reset GPIO pin bit */
|
||||||
|
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
/* write data to the specified GPIO pin */
|
||||||
|
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||||
|
/* write data to the specified GPIO port */
|
||||||
|
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||||
|
|
||||||
|
/* get GPIO pin input status */
|
||||||
|
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
/* get GPIO port input status */
|
||||||
|
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||||
|
/* get GPIO pin output status */
|
||||||
|
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
/* get GPIO port output status */
|
||||||
|
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||||
|
|
||||||
|
/* set GPIO alternate function */
|
||||||
|
void gpio_af_set(uint32_t gpio_periph, uint32_t alt_func_num, uint32_t pin);
|
||||||
|
/* lock GPIO pin bit */
|
||||||
|
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
|
||||||
|
/* toggle GPIO pin status */
|
||||||
|
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||||
|
/* toggle GPIO port status */
|
||||||
|
void gpio_port_toggle(uint32_t gpio_periph);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_GPIO_H */
|
||||||
@@ -0,0 +1,409 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_i2c.h
|
||||||
|
\brief definitions for the I2C
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_I2C_H
|
||||||
|
#define GD32F4XX_I2C_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* I2Cx(x=0,1,2) definitions */
|
||||||
|
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||||
|
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||||
|
#define I2C2 (I2C_BASE + 0x00000800U) /*!< I2C2 base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||||
|
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||||
|
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
|
||||||
|
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
|
||||||
|
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||||
|
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||||
|
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||||
|
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||||
|
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||||
|
#define I2C_FCTL(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C filter control register */
|
||||||
|
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* I2Cx_CTL0 */
|
||||||
|
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||||
|
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||||
|
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||||
|
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||||
|
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||||
|
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||||
|
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||||
|
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||||
|
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||||
|
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||||
|
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||||
|
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||||
|
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||||
|
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||||
|
|
||||||
|
/* I2Cx_CTL1 */
|
||||||
|
#define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */
|
||||||
|
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||||
|
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||||
|
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||||
|
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||||
|
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||||
|
|
||||||
|
/* I2Cx_SADDR0 */
|
||||||
|
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||||
|
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||||
|
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||||
|
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||||
|
|
||||||
|
/* I2Cx_SADDR1 */
|
||||||
|
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||||
|
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||||
|
|
||||||
|
/* I2Cx_DATA */
|
||||||
|
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||||
|
|
||||||
|
/* I2Cx_STAT0 */
|
||||||
|
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||||
|
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||||
|
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||||
|
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||||
|
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||||
|
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||||
|
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||||
|
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||||
|
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||||
|
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||||
|
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||||
|
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||||
|
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||||
|
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||||
|
|
||||||
|
/* I2Cx_STAT1 */
|
||||||
|
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||||
|
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||||
|
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||||
|
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||||
|
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||||
|
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||||
|
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||||
|
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||||
|
|
||||||
|
/* I2Cx_CKCFG */
|
||||||
|
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */
|
||||||
|
#define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */
|
||||||
|
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||||
|
|
||||||
|
/* I2Cx_RT */
|
||||||
|
#define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */
|
||||||
|
|
||||||
|
/* I2Cx_FCTL */
|
||||||
|
#define I2C_FCTL_DF BITS(0,3) /*!< digital noise filter */
|
||||||
|
#define I2C_FCTL_AFD BIT(4) /*!< analog noise filter disable */
|
||||||
|
|
||||||
|
/* I2Cx_SAMCS */
|
||||||
|
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
|
||||||
|
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
|
||||||
|
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
|
||||||
|
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
|
||||||
|
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
|
||||||
|
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||||
|
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||||
|
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||||
|
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
|
||||||
|
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
|
||||||
|
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
|
||||||
|
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* define the I2C bit position and its register index offset */
|
||||||
|
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||||
|
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||||
|
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||||
|
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||||
|
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||||
|
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||||
|
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||||
|
|
||||||
|
/* register offset */
|
||||||
|
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
|
||||||
|
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
|
||||||
|
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
|
||||||
|
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
|
||||||
|
|
||||||
|
/* I2C flags */
|
||||||
|
typedef enum {
|
||||||
|
/* flags in STAT0 register */
|
||||||
|
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||||
|
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||||
|
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||||
|
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||||
|
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||||
|
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||||
|
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||||
|
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||||
|
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||||
|
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||||
|
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||||
|
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||||
|
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||||
|
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||||
|
/* flags in STAT1 register */
|
||||||
|
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||||
|
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||||
|
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||||
|
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||||
|
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||||
|
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||||
|
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||||
|
/* flags in SAMCS register */
|
||||||
|
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||||
|
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||||
|
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||||
|
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||||
|
} i2c_flag_enum;
|
||||||
|
|
||||||
|
/* I2C interrupt flags */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt flags in CTL1 register */
|
||||||
|
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */
|
||||||
|
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||||
|
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||||
|
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||||
|
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||||
|
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||||
|
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||||
|
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */
|
||||||
|
/* interrupt flags in SAMCS register */
|
||||||
|
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||||
|
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||||
|
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||||
|
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||||
|
} i2c_interrupt_flag_enum;
|
||||||
|
|
||||||
|
/* I2C interrupt */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt in CTL1 register */
|
||||||
|
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */
|
||||||
|
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */
|
||||||
|
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */
|
||||||
|
/* interrupt in SAMCS register */
|
||||||
|
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */
|
||||||
|
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */
|
||||||
|
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */
|
||||||
|
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */
|
||||||
|
} i2c_interrupt_enum;
|
||||||
|
|
||||||
|
/* the digital noise filter can filter spikes's length */
|
||||||
|
typedef enum {
|
||||||
|
I2C_DF_DISABLE = 0, /*!< disable digital noise filter */
|
||||||
|
I2C_DF_1PCLK, /*!< enable digital noise filter and the maximum filtered spiker's length 1 PCLK1 */
|
||||||
|
I2C_DF_2PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 2 PCLK1 */
|
||||||
|
I2C_DF_3PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 3 PCLK1 */
|
||||||
|
I2C_DF_4PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 4 PCLK1 */
|
||||||
|
I2C_DF_5PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 5 PCLK1 */
|
||||||
|
I2C_DF_6PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 6 PCLK1 */
|
||||||
|
I2C_DF_7PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 7 PCLK1 */
|
||||||
|
I2C_DF_8PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 8 PCLK1 */
|
||||||
|
I2C_DF_9PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 9 PCLK1 */
|
||||||
|
I2C_DF_10PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 10 PCLK1 */
|
||||||
|
I2C_DF_11PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 11 PCLK1 */
|
||||||
|
I2C_DF_12PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 12 PCLK1 */
|
||||||
|
I2C_DF_13PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 13 PCLK1 */
|
||||||
|
I2C_DF_14PCLKS, /*!< enable digital noise filter and the maximum filtered spiker's length 14 PCLK1 */
|
||||||
|
I2C_DF_15PCLKS /*!< enable digital noise filter and the maximum filtered spiker's length 15 PCLK1 */
|
||||||
|
} i2c_digital_filter_enum;
|
||||||
|
|
||||||
|
/* SMBus/I2C mode switch and SMBus type selection */
|
||||||
|
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||||
|
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||||
|
|
||||||
|
/* SMBus/I2C mode switch and SMBus type selection */
|
||||||
|
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||||
|
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||||
|
|
||||||
|
/* I2C transfer direction */
|
||||||
|
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||||
|
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||||
|
|
||||||
|
/* whether or not to send an ACK */
|
||||||
|
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||||
|
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||||
|
|
||||||
|
/* I2C POAP position*/
|
||||||
|
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||||
|
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||||
|
|
||||||
|
/* whether or not to stretch SCL low */
|
||||||
|
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */
|
||||||
|
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */
|
||||||
|
|
||||||
|
/* whether or not to response to a general call */
|
||||||
|
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||||
|
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||||
|
|
||||||
|
/* software reset I2C */
|
||||||
|
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||||
|
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||||
|
|
||||||
|
/* I2C DMA mode configure */
|
||||||
|
/* DMA mode switch */
|
||||||
|
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */
|
||||||
|
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */
|
||||||
|
|
||||||
|
/* flag indicating DMA last transfer */
|
||||||
|
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||||
|
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||||
|
|
||||||
|
/* I2C PEC configure */
|
||||||
|
/* PEC enable */
|
||||||
|
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||||
|
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||||
|
|
||||||
|
/* PEC transfer */
|
||||||
|
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||||
|
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */
|
||||||
|
|
||||||
|
/* I2C SMBus configure */
|
||||||
|
/* issue or not alert through SMBA pin */
|
||||||
|
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||||
|
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||||
|
|
||||||
|
/* ARP protocol in SMBus switch */
|
||||||
|
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */
|
||||||
|
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */
|
||||||
|
|
||||||
|
/* transmit I2C data */
|
||||||
|
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* receive I2C data */
|
||||||
|
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||||
|
|
||||||
|
/* I2C duty cycle in fast mode */
|
||||||
|
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode */
|
||||||
|
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode */
|
||||||
|
|
||||||
|
/* address mode for the I2C slave */
|
||||||
|
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
|
||||||
|
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* reset I2C */
|
||||||
|
void i2c_deinit(uint32_t i2c_periph);
|
||||||
|
/* configure I2C clock */
|
||||||
|
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||||
|
/* configure I2C address */
|
||||||
|
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||||
|
|
||||||
|
/* application function declarations */
|
||||||
|
/* select SMBus type */
|
||||||
|
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||||
|
/* whether or not to send an ACK */
|
||||||
|
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||||
|
/* configure I2C POAP position */
|
||||||
|
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||||
|
/* master sends slave address */
|
||||||
|
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||||
|
/* enable dual-address mode */
|
||||||
|
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||||
|
/* disable dual-address mode */
|
||||||
|
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||||
|
/* enable I2C */
|
||||||
|
void i2c_enable(uint32_t i2c_periph);
|
||||||
|
/* disable I2C */
|
||||||
|
void i2c_disable(uint32_t i2c_periph);
|
||||||
|
/* generate a START condition on I2C bus */
|
||||||
|
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||||
|
/* generate a STOP condition on I2C bus */
|
||||||
|
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||||
|
/* I2C transmit data function */
|
||||||
|
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||||
|
/* I2C receive data function */
|
||||||
|
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||||
|
/* configure I2C DMA mode */
|
||||||
|
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||||
|
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||||
|
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||||
|
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||||
|
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||||
|
/* whether or not to response to a general call */
|
||||||
|
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||||
|
/* configure software reset of I2C */
|
||||||
|
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||||
|
/* configure I2C PEC calculation */
|
||||||
|
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||||
|
/* configure whether to transfer PEC value */
|
||||||
|
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||||
|
/* get packet error checking value */
|
||||||
|
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||||
|
/* configure I2C alert through SMBA pin */
|
||||||
|
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||||
|
/* configure I2C ARP protocol in SMBus */
|
||||||
|
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||||
|
/* disable analog noise filter */
|
||||||
|
void i2c_analog_noise_filter_disable(uint32_t i2c_periph);
|
||||||
|
/* enable analog noise filter */
|
||||||
|
void i2c_analog_noise_filter_enable(uint32_t i2c_periph);
|
||||||
|
/* configure digital noise filter */
|
||||||
|
void i2c_digital_noise_filter_config(uint32_t i2c_periph, i2c_digital_filter_enum dfilterpara);
|
||||||
|
/* enable SAM_V interface */
|
||||||
|
void i2c_sam_enable(uint32_t i2c_periph);
|
||||||
|
/* disable SAM_V interface */
|
||||||
|
void i2c_sam_disable(uint32_t i2c_periph);
|
||||||
|
/* enable SAM_V interface timeout detect */
|
||||||
|
void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||||
|
/* disable SAM_V interface timeout detect */
|
||||||
|
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* get I2C flag status */
|
||||||
|
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||||
|
/* clear I2C flag status */
|
||||||
|
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||||
|
/* enable I2C interrupt */
|
||||||
|
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||||
|
/* disable I2C interrupt */
|
||||||
|
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||||
|
/* get I2C interrupt flag status */
|
||||||
|
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||||
|
/* clear I2C interrupt flag status */
|
||||||
|
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_I2C_H */
|
||||||
@@ -0,0 +1,378 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_ipa.h
|
||||||
|
\brief definitions for the IPA
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_IPA_H
|
||||||
|
#define GD32F4XX_IPA_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* IPA definitions */
|
||||||
|
#define IPA IPA_BASE /*!< IPA base address */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* registers definitions */
|
||||||
|
#define IPA_CTL REG32(IPA + 0x00000000U) /*!< IPA control register */
|
||||||
|
#define IPA_INTF REG32(IPA + 0x00000004U) /*!< IPA interrupt flag register */
|
||||||
|
#define IPA_INTC REG32(IPA + 0x00000008U) /*!< IPA interrupt flag clear register */
|
||||||
|
#define IPA_FMADDR REG32(IPA + 0x0000000CU) /*!< IPA foreground memory base address register */
|
||||||
|
#define IPA_FLOFF REG32(IPA + 0x00000010U) /*!< IPA foreground line offset register */
|
||||||
|
#define IPA_BMADDR REG32(IPA + 0x00000014U) /*!< IPA background memory base address register */
|
||||||
|
#define IPA_BLOFF REG32(IPA + 0x00000018U) /*!< IPA background line offset register */
|
||||||
|
#define IPA_FPCTL REG32(IPA + 0x0000001CU) /*!< IPA foreground pixel control register */
|
||||||
|
#define IPA_FPV REG32(IPA + 0x00000020U) /*!< IPA foreground pixel value register */
|
||||||
|
#define IPA_BPCTL REG32(IPA + 0x00000024U) /*!< IPA background pixel control register */
|
||||||
|
#define IPA_BPV REG32(IPA + 0x00000028U) /*!< IPA background pixel value register */
|
||||||
|
#define IPA_FLMADDR REG32(IPA + 0x0000002CU) /*!< IPA foreground LUT memory base address register */
|
||||||
|
#define IPA_BLMADDR REG32(IPA + 0x00000030U) /*!< IPA background LUT memory base address register */
|
||||||
|
#define IPA_DPCTL REG32(IPA + 0x00000034U) /*!< IPA destination pixel control register */
|
||||||
|
#define IPA_DPV REG32(IPA + 0x00000038U) /*!< IPA destination pixel value register */
|
||||||
|
#define IPA_DMADDR REG32(IPA + 0x0000003CU) /*!< IPA destination memory base address register */
|
||||||
|
#define IPA_DLOFF REG32(IPA + 0x00000040U) /*!< IPA destination line offset register */
|
||||||
|
#define IPA_IMS REG32(IPA + 0x00000044U) /*!< IPA image size register */
|
||||||
|
#define IPA_LM REG32(IPA + 0x00000048U) /*!< IPA line mark register */
|
||||||
|
#define IPA_ITCTL REG32(IPA + 0x0000004CU) /*!< IPA inter-timer control register */
|
||||||
|
|
||||||
|
/* IPA_CTL */
|
||||||
|
#define IPA_CTL_TEN BIT(0) /*!< transfer enable */
|
||||||
|
#define IPA_CTL_THU BIT(1) /*!< transfer hang up */
|
||||||
|
#define IPA_CTL_TST BIT(2) /*!< transfer stop */
|
||||||
|
#define IPA_CTL_TAEIE BIT(8) /*!< enable bit for transfer access error interrupt */
|
||||||
|
#define IPA_CTL_FTFIE BIT(9) /*!< enable bit for full transfer finish interrup */
|
||||||
|
#define IPA_CTL_TLMIE BIT(10) /*!< enable bit for transfer line mark interrupt */
|
||||||
|
#define IPA_CTL_LACIE BIT(11) /*!< enable bit for LUT access conflict interrupt */
|
||||||
|
#define IPA_CTL_LLFIE BIT(12) /*!< enable bit for LUT loading finish interrupt */
|
||||||
|
#define IPA_CTL_WCFIE BIT(13) /*!< enable bit for wrong configuration interrupt */
|
||||||
|
#define IPA_CTL_PFCM BITS(16,17) /*!< pixel format convert mode */
|
||||||
|
|
||||||
|
/* IPA_INTF */
|
||||||
|
#define IPA_INTF_TAEIF BIT(0) /*!< transfer access error interrupt flag */
|
||||||
|
#define IPA_INTF_FTFIF BIT(1) /*!< full transfer finish interrupt flag */
|
||||||
|
#define IPA_INTF_TLMIF BIT(2) /*!< transfer line mark interrupt flag */
|
||||||
|
#define IPA_INTF_LACIF BIT(3) /*!< LUT access conflict interrupt flag */
|
||||||
|
#define IPA_INTF_LLFIF BIT(4) /*!< LUT loading finish interrupt flag */
|
||||||
|
#define IPA_INTF_WCFIF BIT(5) /*!< wrong configuration interrupt flag */
|
||||||
|
|
||||||
|
/* IPA_INTC */
|
||||||
|
#define IPA_INTC_TAEIFC BIT(0) /*!< clear bit for transfer access error interrupt flag */
|
||||||
|
#define IPA_INTC_FTFIFC BIT(1) /*!< clear bit for full transfer finish interrupt flag */
|
||||||
|
#define IPA_INTC_TLMIFC BIT(2) /*!< clear bit for transfer line mark interrupt flag */
|
||||||
|
#define IPA_INTC_LACIFC BIT(3) /*!< clear bit for LUT access conflict interrupt flag */
|
||||||
|
#define IPA_INTC_LLFIFC BIT(4) /*!< clear bit for LUT loading finish interrupt flag */
|
||||||
|
#define IPA_INTC_WCFIFC BIT(5) /*!< clear bit for wrong configuration interrupt flag */
|
||||||
|
|
||||||
|
/* IPA_FMADDR */
|
||||||
|
#define IPA_FMADDR_FMADDR BITS(0,31) /*!< foreground memory base address */
|
||||||
|
|
||||||
|
/* IPA_FLOFF */
|
||||||
|
#define IPA_FLOFF_FLOFF BITS(0,13) /*!< foreground line offset */
|
||||||
|
|
||||||
|
/* IPA_BMADDR */
|
||||||
|
#define IPA_BMADDR_BMADDR BITS(0,31) /*!< background memory base address */
|
||||||
|
|
||||||
|
/* IPA_BLOFF */
|
||||||
|
#define IPA_BLOFF_BLOFF BITS(0,13) /*!< background line offset */
|
||||||
|
|
||||||
|
/* IPA_FPCTL */
|
||||||
|
#define IPA_FPCTL_FPF BITS(0,3) /*!< foreground pixel format */
|
||||||
|
#define IPA_FPCTL_FLPF BIT(4) /*!< foreground LUT pixel format */
|
||||||
|
#define IPA_FPCTL_FLLEN BIT(5) /*!< foreground LUT loading enable */
|
||||||
|
#define IPA_FPCTL_FCNP BITS(8,15) /*!< foreground LUT number of pixel */
|
||||||
|
#define IPA_FPCTL_FAVCA BITS(16,17) /*!< foreground alpha value calculation algorithm */
|
||||||
|
#define IPA_FPCTL_FPDAV BITS(24,31) /*!< foreground pre- defined alpha value */
|
||||||
|
|
||||||
|
/* IPA_FPV */
|
||||||
|
#define IPA_FPV_FPDBV BITS(0,7) /*!< foreground pre-defined red value */
|
||||||
|
#define IPA_FPV_FPDGV BITS(8,15) /*!< foreground pre-defined green value */
|
||||||
|
#define IPA_FPV_FPDRV BITS(16,23) /*!< foreground pre-defined red value */
|
||||||
|
|
||||||
|
/* IPA_BPCTL */
|
||||||
|
#define IPA_BPCTL_BPF BITS(0,3) /*!< background pixel format */
|
||||||
|
#define IPA_BPCTL_BLPF BIT(4) /*!< background LUT pixel format */
|
||||||
|
#define IPA_BPCTL_BLLEN BIT(5) /*!< background LUT loading enable */
|
||||||
|
#define IPA_BPCTL_BCNP BITS(8,15) /*!< background LUT number of pixel */
|
||||||
|
#define IPA_BPCTL_BAVCA BITS(16,17) /*!< background alpha value calculation algorithm */
|
||||||
|
#define IPA_BPCTL_BPDAV BITS(24,31) /*!< background pre- defined alpha value */
|
||||||
|
|
||||||
|
/* IPA_BPV */
|
||||||
|
#define IPA_BPV_BPDBV BITS(0,7) /*!< background pre-defined blue value */
|
||||||
|
#define IPA_BPV_BPDGV BITS(8,15) /*!< background pre-defined green value */
|
||||||
|
#define IPA_BPV_BPDRV BITS(16,23) /*!< background pre-defined red value */
|
||||||
|
|
||||||
|
/* IPA_FLMADDR */
|
||||||
|
#define IPA_FLMADDR_FLMADDR BITS(0,31) /*!< foreground LUT memory base address */
|
||||||
|
|
||||||
|
/* IPA_BLMADDR */
|
||||||
|
#define IPA_BLMADDR_BLMADDR BITS(0,31) /*!< background LUT memory base address */
|
||||||
|
|
||||||
|
/* IPA_DPCTL */
|
||||||
|
#define IPA_DPCTL_DPF BITS(0,2) /*!< destination pixel control register */
|
||||||
|
|
||||||
|
/* IPA_DPV */
|
||||||
|
/* destination pixel format ARGB8888 */
|
||||||
|
#define IPA_DPV_DPDBV_0 BITS(0,7) /*!< destination pre-defined blue value */
|
||||||
|
#define IPA_DPV_DPDGV_0 BITS(8,15) /*!< destination pre-defined green value */
|
||||||
|
#define IPA_DPV_DPDRV_0 BITS(16,23) /*!< destination pre-defined red value */
|
||||||
|
#define IPA_DPV_DPDAV_0 BITS(24,31) /*!< destination pre-defined alpha value */
|
||||||
|
|
||||||
|
/* destination pixel format RGB8888 */
|
||||||
|
#define IPA_DPV_DPDBV_1 BITS(0,7) /*!< destination pre-defined blue value */
|
||||||
|
#define IPA_DPV_DPDGV_1 BITS(8,15) /*!< destination pre-defined green value */
|
||||||
|
#define IPA_DPV_DPDRV_1 BITS(16,23) /*!< destination pre-defined red value */
|
||||||
|
|
||||||
|
/* destination pixel format RGB565 */
|
||||||
|
#define IPA_DPV_DPDBV_2 BITS(0,4) /*!< destination pre-defined blue value */
|
||||||
|
#define IPA_DPV_DPDGV_2 BITS(5,10) /*!< destination pre-defined green value */
|
||||||
|
#define IPA_DPV_DPDRV_2 BITS(11,15) /*!< destination pre-defined red value */
|
||||||
|
|
||||||
|
/* destination pixel format ARGB1555 */
|
||||||
|
#define IPA_DPV_DPDBV_3 BITS(0,4) /*!< destination pre-defined blue value */
|
||||||
|
#define IPA_DPV_DPDGV_3 BITS(5,9) /*!< destination pre-defined green value */
|
||||||
|
#define IPA_DPV_DPDRV_3 BITS(10,14) /*!< destination pre-defined red value */
|
||||||
|
#define IPA_DPV_DPDAV_3 BIT(15) /*!< destination pre-defined alpha value */
|
||||||
|
|
||||||
|
/* destination pixel format ARGB4444 */
|
||||||
|
#define IPA_DPV_DPDBV_4 BITS(0,3) /*!< destination pre-defined blue value */
|
||||||
|
#define IPA_DPV_DPDGV_4 BITS(4,7) /*!< destination pre-defined green value */
|
||||||
|
#define IPA_DPV_DPDRV_4 BITS(8,11) /*!< destination pre-defined red value */
|
||||||
|
#define IPA_DPV_DPDAV_4 BITS(12,15) /*!< destination pre-defined alpha value */
|
||||||
|
|
||||||
|
/* IPA_DMADDR */
|
||||||
|
#define IPA_DMADDR_DMADDR BITS(0,31) /*!< destination memory base address */
|
||||||
|
|
||||||
|
/* IPA_DLOFF */
|
||||||
|
#define IPA_DLOFF_DLOFF BITS(0,13) /*!< destination line offset */
|
||||||
|
|
||||||
|
/* IPA_IMS */
|
||||||
|
#define IPA_IMS_HEIGHT BITS(0,15) /*!< height of the image to be processed */
|
||||||
|
#define IPA_IMS_WIDTH BITS(16,29) /*!< width of the image to be processed */
|
||||||
|
|
||||||
|
/* IPA_LM */
|
||||||
|
#define IPA_LM_LM BITS(0,15) /*!< line mark */
|
||||||
|
|
||||||
|
/* IPA_ITCTL */
|
||||||
|
#define IPA_ITCTL_ITEN BIT(0) /*!< inter-timer enable */
|
||||||
|
#define IPA_ITCTL_NCCI BITS(8,15) /*!< number of clock cycles interval */
|
||||||
|
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* IPA foreground parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t foreground_memaddr; /*!< foreground memory base address */
|
||||||
|
uint32_t foreground_lineoff; /*!< foreground line offset */
|
||||||
|
uint32_t foreground_prealpha; /*!< foreground pre-defined alpha value */
|
||||||
|
uint32_t foreground_alpha_algorithm; /*!< foreground alpha value calculation algorithm */
|
||||||
|
uint32_t foreground_pf; /*!< foreground pixel format */
|
||||||
|
uint32_t foreground_prered; /*!< foreground pre-defined red value */
|
||||||
|
uint32_t foreground_pregreen; /*!< foreground pre-defined green value */
|
||||||
|
uint32_t foreground_preblue; /*!< foreground pre-defined blue value */
|
||||||
|
} ipa_foreground_parameter_struct;
|
||||||
|
|
||||||
|
/* IPA background parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t background_memaddr; /*!< background memory base address */
|
||||||
|
uint32_t background_lineoff; /*!< background line offset */
|
||||||
|
uint32_t background_prealpha; /*!< background pre-defined alpha value */
|
||||||
|
uint32_t background_alpha_algorithm; /*!< background alpha value calculation algorithm */
|
||||||
|
uint32_t background_pf; /*!< background pixel format */
|
||||||
|
uint32_t background_prered; /*!< background pre-defined red value */
|
||||||
|
uint32_t background_pregreen; /*!< background pre-defined green value */
|
||||||
|
uint32_t background_preblue; /*!< background pre-defined blue value */
|
||||||
|
} ipa_background_parameter_struct;
|
||||||
|
|
||||||
|
/* IPA destination parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t destination_memaddr; /*!< destination memory base address */
|
||||||
|
uint32_t destination_lineoff; /*!< destination line offset */
|
||||||
|
uint32_t destination_prealpha; /*!< destination pre-defined alpha value */
|
||||||
|
uint32_t destination_pf; /*!< destination pixel format */
|
||||||
|
uint32_t destination_prered; /*!< destination pre-defined red value */
|
||||||
|
uint32_t destination_pregreen; /*!< destination pre-defined green value */
|
||||||
|
uint32_t destination_preblue; /*!< destination pre-defined blue value */
|
||||||
|
uint32_t image_width; /*!< width of the image to be processed */
|
||||||
|
uint32_t image_height; /*!< height of the image to be processed */
|
||||||
|
} ipa_destination_parameter_struct;
|
||||||
|
|
||||||
|
/* destination pixel format */
|
||||||
|
typedef enum {
|
||||||
|
IPA_DPF_ARGB8888, /*!< destination pixel format ARGB8888 */
|
||||||
|
IPA_DPF_RGB888, /*!< destination pixel format RGB888 */
|
||||||
|
IPA_DPF_RGB565, /*!< destination pixel format RGB565 */
|
||||||
|
IPA_DPF_ARGB1555, /*!< destination pixel format ARGB1555 */
|
||||||
|
IPA_DPF_ARGB4444 /*!< destination pixel format ARGB4444 */
|
||||||
|
} ipa_dpf_enum;
|
||||||
|
|
||||||
|
/* LUT pixel format */
|
||||||
|
#define IPA_LUT_PF_ARGB8888 ((uint8_t)0x00U) /*!< LUT pixel format ARGB8888 */
|
||||||
|
#define IPA_LUT_PF_RGB888 ((uint8_t)0x01U) /*!< LUT pixel format RGB888 */
|
||||||
|
|
||||||
|
/* Inter-timer */
|
||||||
|
#define IPA_INTER_TIMER_DISABLE ((uint8_t)0x00U) /*!< inter-timer disable */
|
||||||
|
#define IPA_INTER_TIMER_ENABLE ((uint8_t)0x01U) /*!< inter-timer enable */
|
||||||
|
|
||||||
|
/* IPA pixel format convert mode */
|
||||||
|
#define CTL_PFCM(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||||
|
#define IPA_FGTODE CTL_PFCM(0) /*!< foreground memory to destination memory without pixel format convert */
|
||||||
|
#define IPA_FGTODE_PF_CONVERT CTL_PFCM(1) /*!< foreground memory to destination memory with pixel format convert */
|
||||||
|
#define IPA_FGBGTODE CTL_PFCM(2) /*!< blending foreground and background memory to destination memory */
|
||||||
|
#define IPA_FILL_UP_DE CTL_PFCM(3) /*!< fill up destination memory with specific color */
|
||||||
|
|
||||||
|
/* foreground alpha value calculation algorithm */
|
||||||
|
#define FPCTL_FAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||||
|
#define IPA_FG_ALPHA_MODE_0 FPCTL_FAVCA(0) /*!< no effect */
|
||||||
|
#define IPA_FG_ALPHA_MODE_1 FPCTL_FAVCA(1) /*!< FPDAV[7:0] is selected as the foreground alpha value */
|
||||||
|
#define IPA_FG_ALPHA_MODE_2 FPCTL_FAVCA(2) /*!< FPDAV[7:0] multiplied by read alpha value */
|
||||||
|
|
||||||
|
/* background alpha value calculation algorithm */
|
||||||
|
#define BPCTL_BAVCA(regval) (BITS(16,17) & ((uint32_t)(regval) << 16))
|
||||||
|
#define IPA_BG_ALPHA_MODE_0 BPCTL_BAVCA(0) /*!< no effect */
|
||||||
|
#define IPA_BG_ALPHA_MODE_1 BPCTL_BAVCA(1) /*!< BPDAV[7:0] is selected as the background alpha value */
|
||||||
|
#define IPA_BG_ALPHA_MODE_2 BPCTL_BAVCA(2) /*!< BPDAV[7:0] multiplied by read alpha value */
|
||||||
|
|
||||||
|
/* foreground pixel format */
|
||||||
|
#define FPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||||
|
#define FOREGROUND_PPF_ARGB8888 FPCTL_PPF(0) /*!< foreground pixel format ARGB8888 */
|
||||||
|
#define FOREGROUND_PPF_RGB888 FPCTL_PPF(1) /*!< foreground pixel format RGB888 */
|
||||||
|
#define FOREGROUND_PPF_RGB565 FPCTL_PPF(2) /*!< foreground pixel format RGB565 */
|
||||||
|
#define FOREGROUND_PPF_ARG1555 FPCTL_PPF(3) /*!< foreground pixel format ARGB1555 */
|
||||||
|
#define FOREGROUND_PPF_ARGB4444 FPCTL_PPF(4) /*!< foreground pixel format ARGB4444 */
|
||||||
|
#define FOREGROUND_PPF_L8 FPCTL_PPF(5) /*!< foreground pixel format L8 */
|
||||||
|
#define FOREGROUND_PPF_AL44 FPCTL_PPF(6) /*!< foreground pixel format AL44 */
|
||||||
|
#define FOREGROUND_PPF_AL88 FPCTL_PPF(7) /*!< foreground pixel format AL88 */
|
||||||
|
#define FOREGROUND_PPF_L4 FPCTL_PPF(8) /*!< foreground pixel format L4 */
|
||||||
|
#define FOREGROUND_PPF_A8 FPCTL_PPF(9) /*!< foreground pixel format A8 */
|
||||||
|
#define FOREGROUND_PPF_A4 FPCTL_PPF(10) /*!< foreground pixel format A4 */
|
||||||
|
|
||||||
|
/* background pixel format */
|
||||||
|
#define BPCTL_PPF(regval) (BITS(0,3) & ((uint32_t)(regval)))
|
||||||
|
#define BACKGROUND_PPF_ARGB8888 BPCTL_PPF(0) /*!< background pixel format ARGB8888 */
|
||||||
|
#define BACKGROUND_PPF_RGB888 BPCTL_PPF(1) /*!< background pixel format RGB888 */
|
||||||
|
#define BACKGROUND_PPF_RGB565 BPCTL_PPF(2) /*!< background pixel format RGB565 */
|
||||||
|
#define BACKGROUND_PPF_ARG1555 BPCTL_PPF(3) /*!< background pixel format ARGB1555 */
|
||||||
|
#define BACKGROUND_PPF_ARGB4444 BPCTL_PPF(4) /*!< background pixel format ARGB4444 */
|
||||||
|
#define BACKGROUND_PPF_L8 BPCTL_PPF(5) /*!< background pixel format L8 */
|
||||||
|
#define BACKGROUND_PPF_AL44 BPCTL_PPF(6) /*!< background pixel format AL44 */
|
||||||
|
#define BACKGROUND_PPF_AL88 BPCTL_PPF(7) /*!< background pixel format AL88 */
|
||||||
|
#define BACKGROUND_PPF_L4 BPCTL_PPF(8) /*!< background pixel format L4 */
|
||||||
|
#define BACKGROUND_PPF_A8 BPCTL_PPF(9) /*!< background pixel format A8 */
|
||||||
|
#define BACKGROUND_PPF_A4 BPCTL_PPF(10) /*!< background pixel format A4 */
|
||||||
|
|
||||||
|
/* IPA flags */
|
||||||
|
#define IPA_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
|
||||||
|
#define IPA_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
|
||||||
|
#define IPA_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
|
||||||
|
#define IPA_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
|
||||||
|
#define IPA_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
|
||||||
|
#define IPA_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
|
||||||
|
|
||||||
|
/* IPA interrupt enable or disable */
|
||||||
|
#define IPA_INT_TAE IPA_CTL_TAEIE /*!< transfer access error interrupt */
|
||||||
|
#define IPA_INT_FTF IPA_CTL_FTFIE /*!< full transfer finish interrupt */
|
||||||
|
#define IPA_INT_TLM IPA_CTL_TLMIE /*!< transfer line mark interrupt */
|
||||||
|
#define IPA_INT_LAC IPA_CTL_LACIE /*!< LUT access conflict interrupt */
|
||||||
|
#define IPA_INT_LLF IPA_CTL_LLFIE /*!< LUT loading finish interrupt */
|
||||||
|
#define IPA_INT_WCF IPA_CTL_WCFIE /*!< wrong configuration interrupt */
|
||||||
|
|
||||||
|
/* IPA interrupt flags */
|
||||||
|
#define IPA_INT_FLAG_TAE IPA_INTF_TAEIF /*!< transfer access error interrupt flag */
|
||||||
|
#define IPA_INT_FLAG_FTF IPA_INTF_FTFIF /*!< full transfer finish interrupt flag */
|
||||||
|
#define IPA_INT_FLAG_TLM IPA_INTF_TLMIF /*!< transfer line mark interrupt flag */
|
||||||
|
#define IPA_INT_FLAG_LAC IPA_INTF_LACIF /*!< LUT access conflict interrupt flag */
|
||||||
|
#define IPA_INT_FLAG_LLF IPA_INTF_LLFIF /*!< LUT loading finish interrupt flag */
|
||||||
|
#define IPA_INT_FLAG_WCF IPA_INTF_WCFIF /*!< wrong configuration interrupt flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* functions enable or disable, pixel format convert mode set */
|
||||||
|
/* deinitialize IPA */
|
||||||
|
void ipa_deinit(void);
|
||||||
|
/* enable IPA transfer */
|
||||||
|
void ipa_transfer_enable(void);
|
||||||
|
/* enable IPA transfer hang up */
|
||||||
|
void ipa_transfer_hangup_enable(void);
|
||||||
|
/* disable IPA transfer hang up */
|
||||||
|
void ipa_transfer_hangup_disable(void);
|
||||||
|
/* enable IPA transfer stop */
|
||||||
|
void ipa_transfer_stop_enable(void);
|
||||||
|
/* disable IPA transfer stop */
|
||||||
|
void ipa_transfer_stop_disable(void);
|
||||||
|
/* enable IPA foreground LUT loading */
|
||||||
|
void ipa_foreground_lut_loading_enable(void);
|
||||||
|
/* enable IPA background LUT loading */
|
||||||
|
void ipa_background_lut_loading_enable(void);
|
||||||
|
/* set pixel format convert mode, the function is invalid when the IPA transfer is enabled */
|
||||||
|
void ipa_pixel_format_convert_mode_set(uint32_t pfcm);
|
||||||
|
|
||||||
|
/* structure initialization, foreground, background, destination and LUT initialization */
|
||||||
|
/* initialize the structure of IPA foreground parameter struct with the default values, it is
|
||||||
|
suggested that call this function after an ipa_foreground_parameter_struct structure is defined */
|
||||||
|
void ipa_foreground_struct_para_init(ipa_foreground_parameter_struct *foreground_struct);
|
||||||
|
/* initialize foreground parameters */
|
||||||
|
void ipa_foreground_init(ipa_foreground_parameter_struct *foreground_struct);
|
||||||
|
/* initialize the structure of IPA background parameter struct with the default values, it is
|
||||||
|
suggested that call this function after an ipa_background_parameter_struct structure is defined */
|
||||||
|
void ipa_background_struct_para_init(ipa_background_parameter_struct *background_struct);
|
||||||
|
/* initialize background parameters */
|
||||||
|
void ipa_background_init(ipa_background_parameter_struct *background_struct);
|
||||||
|
/* initialize the structure of IPA destination parameter struct with the default values, it is
|
||||||
|
suggested that call this function after an ipa_destination_parameter_struct structure is defined */
|
||||||
|
void ipa_destination_struct_para_init(ipa_destination_parameter_struct *destination_struct);
|
||||||
|
/* initialize destination parameters */
|
||||||
|
void ipa_destination_init(ipa_destination_parameter_struct *destination_struct);
|
||||||
|
/* initialize IPA foreground LUT parameters */
|
||||||
|
void ipa_foreground_lut_init(uint8_t fg_lut_num, uint8_t fg_lut_pf, uint32_t fg_lut_addr);
|
||||||
|
/* initialize IPA background LUT parameters */
|
||||||
|
void ipa_background_lut_init(uint8_t bg_lut_num, uint8_t bg_lut_pf, uint32_t bg_lut_addr);
|
||||||
|
|
||||||
|
/* configuration functions */
|
||||||
|
/* configure IPA line mark */
|
||||||
|
void ipa_line_mark_config(uint16_t line_num);
|
||||||
|
/* inter-timer enable or disable */
|
||||||
|
void ipa_inter_timer_config(uint8_t timer_cfg);
|
||||||
|
/* configure the number of clock cycles interval */
|
||||||
|
void ipa_interval_clock_num_config(uint8_t clk_num);
|
||||||
|
|
||||||
|
/* flag and interrupt functions */
|
||||||
|
/* get IPA flag status in IPA_INTF register */
|
||||||
|
FlagStatus ipa_flag_get(uint32_t flag);
|
||||||
|
/* clear IPA flag in IPA_INTF register */
|
||||||
|
void ipa_flag_clear(uint32_t flag);
|
||||||
|
/* enable IPA interrupt */
|
||||||
|
void ipa_interrupt_enable(uint32_t int_flag);
|
||||||
|
/* disable IPA interrupt */
|
||||||
|
void ipa_interrupt_disable(uint32_t int_flag);
|
||||||
|
/* get IPA interrupt flag */
|
||||||
|
FlagStatus ipa_interrupt_flag_get(uint32_t int_flag);
|
||||||
|
/* clear IPA interrupt flag */
|
||||||
|
void ipa_interrupt_flag_clear(uint32_t int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_IPA_H */
|
||||||
@@ -0,0 +1,184 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_iref.h
|
||||||
|
\brief definitions for the IREF
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_IREF_H
|
||||||
|
#define GD32F4XX_IREF_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* IREF definitions */
|
||||||
|
#define IREF IREF_BASE /*!< IREF base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define IREF_CTL REG32(IREF + 0x300U) /*!< IREF control register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* IREF_CTL */
|
||||||
|
#define IREF_CTL_CSDT BITS(0,5) /*!< current step data */
|
||||||
|
#define IREF_CTL_SCMOD BIT(7) /*!< sink current mode */
|
||||||
|
#define IREF_CTL_CPT BITS(8,12) /*!< current precision trim */
|
||||||
|
#define IREF_CTL_SSEL BIT(14) /*!< step selection */
|
||||||
|
#define IREF_CTL_CREN BIT(15) /*!< current reference enable */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* IREF current precision trim */
|
||||||
|
#define CTL_CPT(regval) (BITS(8,12) & ((uint32_t)(regval) << 8))
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_0 CTL_CPT(0) /*!< IREF current precision trim 0 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_1 CTL_CPT(1) /*!< IREF current precision trim 1 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_2 CTL_CPT(2) /*!< IREF current precision trim 2 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_3 CTL_CPT(3) /*!< IREF current precision trim 3 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_4 CTL_CPT(4) /*!< IREF current precision trim 4 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_5 CTL_CPT(5) /*!< IREF current precision trim 5 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_6 CTL_CPT(6) /*!< IREF current precision trim 6 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_7 CTL_CPT(7) /*!< IREF current precision trim 7 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_8 CTL_CPT(8) /*!< IREF current precision trim 8 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_9 CTL_CPT(9) /*!< IREF current precision trim 9 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_10 CTL_CPT(10) /*!< IREF current precision trim 10 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_11 CTL_CPT(11) /*!< IREF current precision trim 11 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_12 CTL_CPT(12) /*!< IREF current precision trim 12 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_13 CTL_CPT(13) /*!< IREF current precision trim 13 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_14 CTL_CPT(14) /*!< IREF current precision trim 14 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_15 CTL_CPT(15) /*!< IREF current precision trim 15 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_16 CTL_CPT(16) /*!< IREF current precision trim 16 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_17 CTL_CPT(17) /*!< IREF current precision trim 17 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_18 CTL_CPT(18) /*!< IREF current precision trim 18 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_19 CTL_CPT(19) /*!< IREF current precision trim 19 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_20 CTL_CPT(20) /*!< IREF current precision trim 20 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_21 CTL_CPT(21) /*!< IREF current precision trim 21 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_22 CTL_CPT(22) /*!< IREF current precision trim 22 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_23 CTL_CPT(23) /*!< IREF current precision trim 23 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_24 CTL_CPT(24) /*!< IREF current precision trim 24 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_25 CTL_CPT(25) /*!< IREF current precision trim 25 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_26 CTL_CPT(26) /*!< IREF current precision trim 26 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_27 CTL_CPT(27) /*!< IREF current precision trim 27 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_28 CTL_CPT(28) /*!< IREF current precision trim 28 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_29 CTL_CPT(29) /*!< IREF current precision trim 29 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_30 CTL_CPT(30) /*!< IREF current precision trim 30 */
|
||||||
|
#define IREF_CUR_PRECISION_TRIM_31 CTL_CPT(31) /*!< IREF current precision trim 31 */
|
||||||
|
|
||||||
|
/* IREF current step */
|
||||||
|
#define CTL_CSDT(regval) (BITS(0,5) & ((uint32_t)(regval) << 0))
|
||||||
|
#define IREF_CUR_STEP_DATA_0 CTL_CSDT(0) /*!< IREF current step data 0 */
|
||||||
|
#define IREF_CUR_STEP_DATA_1 CTL_CSDT(1) /*!< IREF current step data 1 */
|
||||||
|
#define IREF_CUR_STEP_DATA_2 CTL_CSDT(2) /*!< IREF current step data 2 */
|
||||||
|
#define IREF_CUR_STEP_DATA_3 CTL_CSDT(3) /*!< IREF current step data 3 */
|
||||||
|
#define IREF_CUR_STEP_DATA_4 CTL_CSDT(4) /*!< IREF current step data 4 */
|
||||||
|
#define IREF_CUR_STEP_DATA_5 CTL_CSDT(5) /*!< IREF current step data 5 */
|
||||||
|
#define IREF_CUR_STEP_DATA_6 CTL_CSDT(6) /*!< IREF current step data 6 */
|
||||||
|
#define IREF_CUR_STEP_DATA_7 CTL_CSDT(7) /*!< IREF current step data 7 */
|
||||||
|
#define IREF_CUR_STEP_DATA_8 CTL_CSDT(8) /*!< IREF current step data 8 */
|
||||||
|
#define IREF_CUR_STEP_DATA_9 CTL_CSDT(9) /*!< IREF current step data 9 */
|
||||||
|
#define IREF_CUR_STEP_DATA_10 CTL_CSDT(10) /*!< IREF current step data 10 */
|
||||||
|
#define IREF_CUR_STEP_DATA_11 CTL_CSDT(11) /*!< IREF current step data 11 */
|
||||||
|
#define IREF_CUR_STEP_DATA_12 CTL_CSDT(12) /*!< IREF current step data 12 */
|
||||||
|
#define IREF_CUR_STEP_DATA_13 CTL_CSDT(13) /*!< IREF current step data 13 */
|
||||||
|
#define IREF_CUR_STEP_DATA_14 CTL_CSDT(14) /*!< IREF current step data 14 */
|
||||||
|
#define IREF_CUR_STEP_DATA_15 CTL_CSDT(15) /*!< IREF current step data 15 */
|
||||||
|
#define IREF_CUR_STEP_DATA_16 CTL_CSDT(16) /*!< IREF current step data 16 */
|
||||||
|
#define IREF_CUR_STEP_DATA_17 CTL_CSDT(17) /*!< IREF current step data 17 */
|
||||||
|
#define IREF_CUR_STEP_DATA_18 CTL_CSDT(18) /*!< IREF current step data 18 */
|
||||||
|
#define IREF_CUR_STEP_DATA_19 CTL_CSDT(19) /*!< IREF current step data 19 */
|
||||||
|
#define IREF_CUR_STEP_DATA_20 CTL_CSDT(20) /*!< IREF current step data 20 */
|
||||||
|
#define IREF_CUR_STEP_DATA_21 CTL_CSDT(21) /*!< IREF current step data 21 */
|
||||||
|
#define IREF_CUR_STEP_DATA_22 CTL_CSDT(22) /*!< IREF current step data 22 */
|
||||||
|
#define IREF_CUR_STEP_DATA_23 CTL_CSDT(23) /*!< IREF current step data 23 */
|
||||||
|
#define IREF_CUR_STEP_DATA_24 CTL_CSDT(24) /*!< IREF current step data 24 */
|
||||||
|
#define IREF_CUR_STEP_DATA_25 CTL_CSDT(25) /*!< IREF current step data 25 */
|
||||||
|
#define IREF_CUR_STEP_DATA_26 CTL_CSDT(26) /*!< IREF current step data 26 */
|
||||||
|
#define IREF_CUR_STEP_DATA_27 CTL_CSDT(27) /*!< IREF current step data 27 */
|
||||||
|
#define IREF_CUR_STEP_DATA_28 CTL_CSDT(28) /*!< IREF current step data 28 */
|
||||||
|
#define IREF_CUR_STEP_DATA_29 CTL_CSDT(29) /*!< IREF current step data 29 */
|
||||||
|
#define IREF_CUR_STEP_DATA_30 CTL_CSDT(30) /*!< IREF current step data 30 */
|
||||||
|
#define IREF_CUR_STEP_DATA_31 CTL_CSDT(31) /*!< IREF current step data 31 */
|
||||||
|
#define IREF_CUR_STEP_DATA_32 CTL_CSDT(32) /*!< IREF current step data 32 */
|
||||||
|
#define IREF_CUR_STEP_DATA_33 CTL_CSDT(33) /*!< IREF current step data 33 */
|
||||||
|
#define IREF_CUR_STEP_DATA_34 CTL_CSDT(34) /*!< IREF current step data 34 */
|
||||||
|
#define IREF_CUR_STEP_DATA_35 CTL_CSDT(35) /*!< IREF current step data 35 */
|
||||||
|
#define IREF_CUR_STEP_DATA_36 CTL_CSDT(36) /*!< IREF current step data 36 */
|
||||||
|
#define IREF_CUR_STEP_DATA_37 CTL_CSDT(37) /*!< IREF current step data 37 */
|
||||||
|
#define IREF_CUR_STEP_DATA_38 CTL_CSDT(38) /*!< IREF current step data 38 */
|
||||||
|
#define IREF_CUR_STEP_DATA_39 CTL_CSDT(39) /*!< IREF current step data 39 */
|
||||||
|
#define IREF_CUR_STEP_DATA_40 CTL_CSDT(40) /*!< IREF current step data 40 */
|
||||||
|
#define IREF_CUR_STEP_DATA_41 CTL_CSDT(41) /*!< IREF current step data 41 */
|
||||||
|
#define IREF_CUR_STEP_DATA_42 CTL_CSDT(42) /*!< IREF current step data 42 */
|
||||||
|
#define IREF_CUR_STEP_DATA_43 CTL_CSDT(43) /*!< IREF current step data 43 */
|
||||||
|
#define IREF_CUR_STEP_DATA_44 CTL_CSDT(44) /*!< IREF current step data 44 */
|
||||||
|
#define IREF_CUR_STEP_DATA_45 CTL_CSDT(45) /*!< IREF current step data 45 */
|
||||||
|
#define IREF_CUR_STEP_DATA_46 CTL_CSDT(46) /*!< IREF current step data 46 */
|
||||||
|
#define IREF_CUR_STEP_DATA_47 CTL_CSDT(47) /*!< IREF current step data 47 */
|
||||||
|
#define IREF_CUR_STEP_DATA_48 CTL_CSDT(48) /*!< IREF current step data 48 */
|
||||||
|
#define IREF_CUR_STEP_DATA_49 CTL_CSDT(49) /*!< IREF current step data 49 */
|
||||||
|
#define IREF_CUR_STEP_DATA_50 CTL_CSDT(50) /*!< IREF current step data 50 */
|
||||||
|
#define IREF_CUR_STEP_DATA_51 CTL_CSDT(51) /*!< IREF current step data 51 */
|
||||||
|
#define IREF_CUR_STEP_DATA_52 CTL_CSDT(52) /*!< IREF current step data 52 */
|
||||||
|
#define IREF_CUR_STEP_DATA_53 CTL_CSDT(53) /*!< IREF current step data 53 */
|
||||||
|
#define IREF_CUR_STEP_DATA_54 CTL_CSDT(54) /*!< IREF current step data 54 */
|
||||||
|
#define IREF_CUR_STEP_DATA_55 CTL_CSDT(55) /*!< IREF current step data 54 */
|
||||||
|
#define IREF_CUR_STEP_DATA_56 CTL_CSDT(56) /*!< IREF current step data 54 */
|
||||||
|
#define IREF_CUR_STEP_DATA_57 CTL_CSDT(57) /*!< IREF current step data 57 */
|
||||||
|
#define IREF_CUR_STEP_DATA_58 CTL_CSDT(58) /*!< IREF current step data 58 */
|
||||||
|
#define IREF_CUR_STEP_DATA_59 CTL_CSDT(59) /*!< IREF current step data 59 */
|
||||||
|
#define IREF_CUR_STEP_DATA_60 CTL_CSDT(60) /*!< IREF current step data 60 */
|
||||||
|
#define IREF_CUR_STEP_DATA_61 CTL_CSDT(61) /*!< IREF current step data 61 */
|
||||||
|
#define IREF_CUR_STEP_DATA_62 CTL_CSDT(62) /*!< IREF current step data 62 */
|
||||||
|
#define IREF_CUR_STEP_DATA_63 CTL_CSDT(63) /*!< IREF current step data 63 */
|
||||||
|
|
||||||
|
/* IREF mode selection */
|
||||||
|
#define IREF_STEP(regval) (BIT(14) & ((uint32_t)(regval) << 14))
|
||||||
|
#define IREF_MODE_LOW_POWER IREF_STEP(0) /*!< low power, 1uA step */
|
||||||
|
#define IREF_MODE_HIGH_CURRENT IREF_STEP(1) /*!< high current, 8uA step */
|
||||||
|
|
||||||
|
/* IREF sink current mode*/
|
||||||
|
#define IREF_CURRENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||||
|
#define IREF_SOURCE_CURRENT IREF_CURRENT(0) /*!< IREF source current */
|
||||||
|
#define IREF_SINK_CURRENT IREF_CURRENT(1) /*!< IREF sink current */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* deinitialize IREF */
|
||||||
|
void iref_deinit(void);
|
||||||
|
/* enable IREF */
|
||||||
|
void iref_enable(void);
|
||||||
|
/* disable IREF */
|
||||||
|
void iref_disable(void);
|
||||||
|
|
||||||
|
/* set IREF mode*/
|
||||||
|
void iref_mode_set(uint32_t step);
|
||||||
|
/* set IREF sink current mode*/
|
||||||
|
void iref_sink_set(uint32_t sinkmode);
|
||||||
|
/* set IREF current precision trim value */
|
||||||
|
void iref_precision_trim_value_set(uint32_t precisiontrim);
|
||||||
|
/* set IREF step data*/
|
||||||
|
void iref_step_data_config(uint32_t stepdata);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_IREF_H */
|
||||||
@@ -0,0 +1,90 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_misc.h
|
||||||
|
\brief definitions for the MISC
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_MISC_H
|
||||||
|
#define GD32F4XX_MISC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* set the RAM and FLASH base address */
|
||||||
|
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
|
||||||
|
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
|
||||||
|
|
||||||
|
/* set the NVIC vector table offset mask */
|
||||||
|
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80)
|
||||||
|
|
||||||
|
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||||
|
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||||
|
|
||||||
|
/* priority group - define the pre-emption priority and the subpriority */
|
||||||
|
#define NVIC_PRIGROUP_PRE0_SUB4 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 4 bits for subpriority */
|
||||||
|
#define NVIC_PRIGROUP_PRE1_SUB3 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 3 bits for subpriority */
|
||||||
|
#define NVIC_PRIGROUP_PRE2_SUB2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 2 bits for subpriority */
|
||||||
|
#define NVIC_PRIGROUP_PRE3_SUB1 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 1 bits for subpriority */
|
||||||
|
#define NVIC_PRIGROUP_PRE4_SUB0 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 0 bits for subpriority */
|
||||||
|
|
||||||
|
/* choose the method to enter or exit the lowpower mode */
|
||||||
|
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||||
|
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||||
|
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||||
|
|
||||||
|
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT
|
||||||
|
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP
|
||||||
|
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND
|
||||||
|
|
||||||
|
/* choose the systick clock source */
|
||||||
|
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||||
|
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* set the priority group */
|
||||||
|
void nvic_priority_group_set(uint32_t nvic_prigroup);
|
||||||
|
|
||||||
|
/* enable NVIC request */
|
||||||
|
void nvic_irq_enable(IRQn_Type nvic_irq, uint8_t nvic_irq_pre_priority, uint8_t nvic_irq_sub_priority);
|
||||||
|
/* disable NVIC request */
|
||||||
|
void nvic_irq_disable(IRQn_Type nvic_irq);
|
||||||
|
|
||||||
|
/* set the NVIC vector table base address */
|
||||||
|
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||||
|
|
||||||
|
/* set the state of the low power mode */
|
||||||
|
void system_lowpower_set(uint8_t lowpower_mode);
|
||||||
|
/* reset the state of the low power mode */
|
||||||
|
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||||
|
|
||||||
|
/* set the systick clock source */
|
||||||
|
void systick_clksource_set(uint32_t systick_clksource);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_MISC_H */
|
||||||
@@ -0,0 +1,203 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_pmu.h
|
||||||
|
\brief definitions for the PMU
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_PMU_H
|
||||||
|
#define GD32F4XX_PMU_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* PMU definitions */
|
||||||
|
#define PMU PMU_BASE /*!< PMU base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */
|
||||||
|
#define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* PMU_CTL */
|
||||||
|
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||||
|
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||||
|
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||||
|
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||||
|
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||||
|
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||||
|
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||||
|
#define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */
|
||||||
|
#define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */
|
||||||
|
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||||
|
#define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */
|
||||||
|
#define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */
|
||||||
|
#define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */
|
||||||
|
|
||||||
|
/* PMU_CS */
|
||||||
|
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||||
|
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||||
|
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||||
|
#define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */
|
||||||
|
#define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */
|
||||||
|
#define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */
|
||||||
|
#define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */
|
||||||
|
#define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */
|
||||||
|
#define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */
|
||||||
|
#define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* PMU ldo definitions */
|
||||||
|
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */
|
||||||
|
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */
|
||||||
|
|
||||||
|
/* PMU low voltage detector threshold definitions */
|
||||||
|
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||||
|
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||||
|
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||||
|
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||||
|
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||||
|
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||||
|
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||||
|
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||||
|
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||||
|
|
||||||
|
/* PMU low-driver mode when use low power LDO */
|
||||||
|
#define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10))
|
||||||
|
#define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */
|
||||||
|
#define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */
|
||||||
|
|
||||||
|
/* PMU low-driver mode when use normal power LDO */
|
||||||
|
#define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11))
|
||||||
|
#define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */
|
||||||
|
#define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */
|
||||||
|
|
||||||
|
/* PMU LDO output voltage select definitions */
|
||||||
|
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||||
|
#define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */
|
||||||
|
#define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */
|
||||||
|
#define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */
|
||||||
|
|
||||||
|
|
||||||
|
/* PMU high-driver mode switch */
|
||||||
|
#define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17))
|
||||||
|
#define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */
|
||||||
|
#define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */
|
||||||
|
|
||||||
|
/* PMU low-driver mode enable in deep-sleep mode */
|
||||||
|
#define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||||
|
#define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */
|
||||||
|
#define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */
|
||||||
|
|
||||||
|
/* PMU backup SRAM LDO on or off */
|
||||||
|
#define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9))
|
||||||
|
#define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */
|
||||||
|
#define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */
|
||||||
|
|
||||||
|
/* PMU low power mode ready flag definitions */
|
||||||
|
#define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18))
|
||||||
|
#define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */
|
||||||
|
#define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */
|
||||||
|
|
||||||
|
/* PMU flag definitions */
|
||||||
|
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||||
|
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||||
|
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */
|
||||||
|
#define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */
|
||||||
|
#define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */
|
||||||
|
#define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */
|
||||||
|
#define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */
|
||||||
|
#define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */
|
||||||
|
|
||||||
|
/* PMU flag reset definitions */
|
||||||
|
#define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */
|
||||||
|
#define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */
|
||||||
|
|
||||||
|
/* PMU command constants definitions */
|
||||||
|
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||||
|
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* reset PMU registers */
|
||||||
|
void pmu_deinit(void);
|
||||||
|
|
||||||
|
/* LVD functions */
|
||||||
|
/* select low voltage detector threshold */
|
||||||
|
void pmu_lvd_select(uint32_t lvdt_n);
|
||||||
|
/* disable PMU lvd */
|
||||||
|
void pmu_lvd_disable(void);
|
||||||
|
|
||||||
|
/* LDO functions */
|
||||||
|
/* select LDO output voltage */
|
||||||
|
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||||
|
|
||||||
|
/* functions of low-driver mode and high-driver mode */
|
||||||
|
/* enable high-driver mode */
|
||||||
|
void pmu_highdriver_mode_enable(void);
|
||||||
|
/* disable high-driver mode */
|
||||||
|
void pmu_highdriver_mode_disable(void);
|
||||||
|
/* switch high-driver mode */
|
||||||
|
void pmu_highdriver_switch_select(uint32_t highdr_switch);
|
||||||
|
/* enable low-driver mode in deep-sleep */
|
||||||
|
void pmu_lowdriver_mode_enable(void);
|
||||||
|
/* disable low-driver mode in deep-sleep */
|
||||||
|
void pmu_lowdriver_mode_disable(void);
|
||||||
|
/* in deep-sleep mode, driver mode when use low power LDO */
|
||||||
|
void pmu_lowpower_driver_config(uint32_t mode);
|
||||||
|
/* in deep-sleep mode, driver mode when use normal power LDO */
|
||||||
|
void pmu_normalpower_driver_config(uint32_t mode);
|
||||||
|
|
||||||
|
/* set PMU mode */
|
||||||
|
/* PMU work in sleep mode */
|
||||||
|
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||||
|
/* PMU work in deepsleep mode */
|
||||||
|
void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd);
|
||||||
|
/* PMU work in standby mode */
|
||||||
|
void pmu_to_standbymode(void);
|
||||||
|
/* enable PMU wakeup pin */
|
||||||
|
void pmu_wakeup_pin_enable(void);
|
||||||
|
/* disable PMU wakeup pin */
|
||||||
|
void pmu_wakeup_pin_disable(void);
|
||||||
|
|
||||||
|
/* backup related functions */
|
||||||
|
/* backup SRAM LDO on */
|
||||||
|
void pmu_backup_ldo_config(uint32_t bkp_ldo);
|
||||||
|
/* enable write access to the registers in backup domain */
|
||||||
|
void pmu_backup_write_enable(void);
|
||||||
|
/* disable write access to the registers in backup domain */
|
||||||
|
void pmu_backup_write_disable(void);
|
||||||
|
|
||||||
|
/* flag functions */
|
||||||
|
/* get flag state */
|
||||||
|
FlagStatus pmu_flag_get(uint32_t flag);
|
||||||
|
/* clear flag bit */
|
||||||
|
void pmu_flag_clear(uint32_t flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_PMU_H */
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,638 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_rtc.c
|
||||||
|
\brief definitions for the RTC
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_RTC_H
|
||||||
|
#define GD32F4XX_RTC_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* RTC definitions */
|
||||||
|
#define RTC RTC_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define RTC_TIME REG32((RTC) + 0x00U) /*!< RTC time of day register */
|
||||||
|
#define RTC_DATE REG32((RTC) + 0x04U) /*!< RTC date register */
|
||||||
|
#define RTC_CTL REG32((RTC) + 0x08U) /*!< RTC control register */
|
||||||
|
#define RTC_STAT REG32((RTC) + 0x0CU) /*!< RTC status register */
|
||||||
|
#define RTC_PSC REG32((RTC) + 0x10U) /*!< RTC time prescaler register */
|
||||||
|
#define RTC_WUT REG32((RTC) + 0x14U) /*!< RTC wakeup timer regiser */
|
||||||
|
#define RTC_COSC REG32((RTC) + 0x18U) /*!< RTC coarse calibration register */
|
||||||
|
#define RTC_ALRM0TD REG32((RTC) + 0x1CU) /*!< RTC alarm 0 time and date register */
|
||||||
|
#define RTC_ALRM1TD REG32((RTC) + 0x20U) /*!< RTC alarm 1 time and date register */
|
||||||
|
#define RTC_WPK REG32((RTC) + 0x24U) /*!< RTC write protection key register */
|
||||||
|
#define RTC_SS REG32((RTC) + 0x28U) /*!< RTC sub second register */
|
||||||
|
#define RTC_SHIFTCTL REG32((RTC) + 0x2CU) /*!< RTC shift function control register */
|
||||||
|
#define RTC_TTS REG32((RTC) + 0x30U) /*!< RTC time of timestamp register */
|
||||||
|
#define RTC_DTS REG32((RTC) + 0x34U) /*!< RTC date of timestamp register */
|
||||||
|
#define RTC_SSTS REG32((RTC) + 0x38U) /*!< RTC sub second of timestamp register */
|
||||||
|
#define RTC_HRFC REG32((RTC) + 0x3CU) /*!< RTC high resolution frequency compensation registor */
|
||||||
|
#define RTC_TAMP REG32((RTC) + 0x40U) /*!< RTC tamper register */
|
||||||
|
#define RTC_ALRM0SS REG32((RTC) + 0x44U) /*!< RTC alarm 0 sub second register */
|
||||||
|
#define RTC_ALRM1SS REG32((RTC) + 0x48U) /*!< RTC alarm 1 sub second register */
|
||||||
|
#define RTC_BKP0 REG32((RTC) + 0x50U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP1 REG32((RTC) + 0x54U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP2 REG32((RTC) + 0x58U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP3 REG32((RTC) + 0x5CU) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP4 REG32((RTC) + 0x60U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP5 REG32((RTC) + 0x64U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP6 REG32((RTC) + 0x68U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP7 REG32((RTC) + 0x6CU) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP8 REG32((RTC) + 0x70U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP9 REG32((RTC) + 0x74U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP10 REG32((RTC) + 0x78U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP11 REG32((RTC) + 0x7CU) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP12 REG32((RTC) + 0x80U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP13 REG32((RTC) + 0x84U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP14 REG32((RTC) + 0x88U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP15 REG32((RTC) + 0x8CU) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP16 REG32((RTC) + 0x90U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP17 REG32((RTC) + 0x94U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP18 REG32((RTC) + 0x98U) /*!< RTC backup register */
|
||||||
|
#define RTC_BKP19 REG32((RTC) + 0x9CU) /*!< RTC backup register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* RTC_TIME */
|
||||||
|
#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
|
||||||
|
#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||||
|
#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||||
|
#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||||
|
#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||||
|
#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||||
|
#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
|
||||||
|
|
||||||
|
/* RTC_DATE */
|
||||||
|
#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||||
|
#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||||
|
#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
|
||||||
|
#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
|
||||||
|
#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
|
||||||
|
#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
|
||||||
|
#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
|
||||||
|
|
||||||
|
/* RTC_CTL */
|
||||||
|
#define RTC_CTL_WTCS BITS(0,2) /*!< auto wakeup timer clock selection */
|
||||||
|
#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
|
||||||
|
#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
|
||||||
|
#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
|
||||||
|
#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
|
||||||
|
#define RTC_CTL_CCEN BIT(7) /*!< coarse calibration function enable */
|
||||||
|
#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm0 function enable */
|
||||||
|
#define RTC_CTL_ALRM1EN BIT(9) /*!< alarm1 function enable */
|
||||||
|
#define RTC_CTL_WTEN BIT(10) /*!< auto wakeup timer function enable */
|
||||||
|
#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
|
||||||
|
#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm0 interrupt enable */
|
||||||
|
#define RTC_CTL_ALRM1IE BIT(13) /*!< RTC alarm1 interrupt enable */
|
||||||
|
#define RTC_CTL_WTIE BIT(14) /*!< auto wakeup timer interrupt enable */
|
||||||
|
#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
|
||||||
|
#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
|
||||||
|
#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
|
||||||
|
#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
|
||||||
|
#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
|
||||||
|
#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
|
||||||
|
#define RTC_CTL_OS BITS(21,22) /*!< output selection */
|
||||||
|
#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
|
||||||
|
|
||||||
|
/* RTC_STAT */
|
||||||
|
#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm0 configuration can be write flag */
|
||||||
|
#define RTC_STAT_ALRM1WF BIT(1) /*!< alarm1 configuration can be write flag */
|
||||||
|
#define RTC_STAT_WTWF BIT(2) /*!< wakeup timer can be write flag */
|
||||||
|
#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
|
||||||
|
#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
|
||||||
|
#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
|
||||||
|
#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
|
||||||
|
#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
|
||||||
|
#define RTC_STAT_ALRM0F BIT(8) /*!< alarm0 occurs flag */
|
||||||
|
#define RTC_STAT_ALRM1F BIT(9) /*!< alarm1 occurs flag */
|
||||||
|
#define RTC_STAT_WTF BIT(10) /*!< wakeup timer occurs flag */
|
||||||
|
#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
|
||||||
|
#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
|
||||||
|
#define RTC_STAT_TP0F BIT(13) /*!< RTC tamper 0 detected flag */
|
||||||
|
#define RTC_STAT_TP1F BIT(14) /*!< RTC tamper 1 detected flag */
|
||||||
|
#define RTC_STAT_SCPF BIT(16) /*!< smooth calibration pending flag */
|
||||||
|
|
||||||
|
/* RTC_PSC */
|
||||||
|
#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
|
||||||
|
#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
|
||||||
|
|
||||||
|
/* RTC_WUT */
|
||||||
|
#define RTC_WUT_WTRV BITS(0,15) /*!< auto wakeup timer reloads value */
|
||||||
|
|
||||||
|
/* RTC_COSC */
|
||||||
|
#define RTC_COSC_COSS BITS(0,4) /*!< coarse calibration step */
|
||||||
|
#define RTC_COSC_COSD BIT(7) /*!< coarse calibration direction */
|
||||||
|
|
||||||
|
/* RTC_ALRMxTD */
|
||||||
|
#define RTC_ALRMXTD_SCU BITS(0,3) /*!< second units in BCD code */
|
||||||
|
#define RTC_ALRMXTD_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||||
|
#define RTC_ALRMXTD_MSKS BIT(7) /*!< alarm second mask bit */
|
||||||
|
#define RTC_ALRMXTD_MNU BITS(8,11) /*!< minutes units in BCD code */
|
||||||
|
#define RTC_ALRMXTD_MNT BITS(12,14) /*!< minutes tens in BCD code */
|
||||||
|
#define RTC_ALRMXTD_MSKM BIT(15) /*!< alarm minutes mask bit */
|
||||||
|
#define RTC_ALRMXTD_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||||
|
#define RTC_ALRMXTD_HRT BITS(20,21) /*!< hour units in BCD code */
|
||||||
|
#define RTC_ALRMXTD_PM BIT(22) /*!< AM/PM flag */
|
||||||
|
#define RTC_ALRMXTD_MSKH BIT(23) /*!< alarm hour mask bit */
|
||||||
|
#define RTC_ALRMXTD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
|
||||||
|
#define RTC_ALRMXTD_DAYT BITS(28,29) /*!< date tens in BCD code */
|
||||||
|
#define RTC_ALRMXTD_DOWS BIT(30) /*!< day of week selection */
|
||||||
|
#define RTC_ALRMXTD_MSKD BIT(31) /*!< alarm date mask bit */
|
||||||
|
|
||||||
|
/* RTC_WPK */
|
||||||
|
#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
|
||||||
|
|
||||||
|
/* RTC_SS */
|
||||||
|
#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
|
||||||
|
|
||||||
|
/* RTC_SHIFTCTL */
|
||||||
|
#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
|
||||||
|
#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
|
||||||
|
|
||||||
|
/* RTC_TTS */
|
||||||
|
#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
|
||||||
|
#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */
|
||||||
|
#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||||
|
#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||||
|
#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||||
|
#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||||
|
#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
|
||||||
|
|
||||||
|
/* RTC_DTS */
|
||||||
|
#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||||
|
#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||||
|
#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
|
||||||
|
#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
|
||||||
|
#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
|
||||||
|
|
||||||
|
/* RTC_SSTS */
|
||||||
|
#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
|
||||||
|
|
||||||
|
/* RTC_HRFC */
|
||||||
|
#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
|
||||||
|
#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
|
||||||
|
#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */
|
||||||
|
#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
|
||||||
|
|
||||||
|
/* RTC_TAMP */
|
||||||
|
#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
|
||||||
|
#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
|
||||||
|
#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */
|
||||||
|
#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */
|
||||||
|
#define RTC_TAMP_TP1EG BIT(4) /*!< Tamper 1 event trigger edge for RTC tamp 1 input */
|
||||||
|
#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
|
||||||
|
#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
|
||||||
|
#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
|
||||||
|
#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
|
||||||
|
#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
|
||||||
|
#define RTC_TAMP_TP0SEL BIT(16) /*!< Tamper 0 function input mapping selection */
|
||||||
|
#define RTC_TAMP_TSSEL BIT(17) /*!< Timestamp input mapping selection */
|
||||||
|
#define RTC_TAMP_AOT BIT(18) /*!< RTC_ALARM output Type */
|
||||||
|
|
||||||
|
/* RTC_ALRM0SS */
|
||||||
|
#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm0 sub second value */
|
||||||
|
#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
|
||||||
|
|
||||||
|
/* RTC_ALRM1SS */
|
||||||
|
#define RTC_ALRM1SS_SSC BITS(0,14) /*!< alarm1 sub second value */
|
||||||
|
#define RTC_ALRM1SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* structure for initialization of the RTC */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
|
||||||
|
uint8_t month; /*!< RTC month value */
|
||||||
|
uint8_t date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
|
||||||
|
uint8_t day_of_week; /*!< RTC weekday value */
|
||||||
|
uint8_t hour; /*!< RTC hour value */
|
||||||
|
uint8_t minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint8_t second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint16_t factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
|
||||||
|
uint16_t factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
|
||||||
|
uint32_t am_pm; /*!< RTC AM/PM value */
|
||||||
|
uint32_t display_format; /*!< RTC time notation */
|
||||||
|
}rtc_parameter_struct;
|
||||||
|
|
||||||
|
/* structure for RTC alarm configuration */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t alarm_mask; /*!< RTC alarm mask */
|
||||||
|
uint32_t weekday_or_date; /*!< specify RTC alarm is on date or weekday */
|
||||||
|
uint8_t alarm_day; /*!< RTC alarm date or weekday value*/
|
||||||
|
uint8_t alarm_hour; /*!< RTC alarm hour value */
|
||||||
|
uint8_t alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint8_t alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint32_t am_pm; /*!< RTC alarm AM/PM value */
|
||||||
|
}rtc_alarm_struct;
|
||||||
|
|
||||||
|
/* structure for RTC time-stamp configuration */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t timestamp_month; /*!< RTC time-stamp month value */
|
||||||
|
uint8_t timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
|
||||||
|
uint8_t timestamp_day; /*!< RTC time-stamp weekday value */
|
||||||
|
uint8_t timestamp_hour; /*!< RTC time-stamp hour value */
|
||||||
|
uint8_t timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint8_t timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
|
||||||
|
uint32_t am_pm; /*!< RTC time-stamp AM/PM value */
|
||||||
|
}rtc_timestamp_struct;
|
||||||
|
|
||||||
|
/* structure for RTC tamper configuration */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t tamper_source; /*!< RTC tamper source */
|
||||||
|
uint32_t tamper_trigger; /*!< RTC tamper trigger */
|
||||||
|
uint32_t tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
|
||||||
|
uint32_t tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
|
||||||
|
ControlStatus tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
|
||||||
|
uint32_t tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
|
||||||
|
ControlStatus tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
|
||||||
|
}rtc_tamper_struct;
|
||||||
|
|
||||||
|
/* time register value */
|
||||||
|
#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TIME_SC bit field */
|
||||||
|
#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
|
||||||
|
|
||||||
|
#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TIME_MN bit field */
|
||||||
|
#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
|
||||||
|
|
||||||
|
#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TIME_HR bit field */
|
||||||
|
#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
|
||||||
|
|
||||||
|
#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
|
||||||
|
#define RTC_PM RTC_TIME_PM /*!< PM format */
|
||||||
|
|
||||||
|
/* date register value */
|
||||||
|
#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DATE_DAY bit field */
|
||||||
|
#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
|
||||||
|
|
||||||
|
#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DATE_MON bit field */
|
||||||
|
#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
|
||||||
|
#define RTC_JAN ((uint8_t)0x01U) /*!< janurary */
|
||||||
|
#define RTC_FEB ((uint8_t)0x02U) /*!< february */
|
||||||
|
#define RTC_MAR ((uint8_t)0x03U) /*!< march */
|
||||||
|
#define RTC_APR ((uint8_t)0x04U) /*!< april */
|
||||||
|
#define RTC_MAY ((uint8_t)0x05U) /*!< may */
|
||||||
|
#define RTC_JUN ((uint8_t)0x06U) /*!< june */
|
||||||
|
#define RTC_JUL ((uint8_t)0x07U) /*!< july */
|
||||||
|
#define RTC_AUG ((uint8_t)0x08U) /*!< august */
|
||||||
|
#define RTC_SEP ((uint8_t)0x09U) /*!< september */
|
||||||
|
#define RTC_OCT ((uint8_t)0x10U) /*!< october */
|
||||||
|
#define RTC_NOV ((uint8_t)0x11U) /*!< november */
|
||||||
|
#define RTC_DEC ((uint8_t)0x12U) /*!< december */
|
||||||
|
|
||||||
|
#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DATE_DOW bit field */
|
||||||
|
#define GET_DATE_DOW(regval) GET_BITS((uint32_t)(regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
|
||||||
|
#define RTC_MONDAY ((uint8_t)0x01) /*!< monday */
|
||||||
|
#define RTC_TUESDAY ((uint8_t)0x02) /*!< tuesday */
|
||||||
|
#define RTC_WEDSDAY ((uint8_t)0x03) /*!< wednesday */
|
||||||
|
#define RTC_THURSDAY ((uint8_t)0x04) /*!< thursday */
|
||||||
|
#define RTC_FRIDAY ((uint8_t)0x05) /*!< friday */
|
||||||
|
#define RTC_SATURDAY ((uint8_t)0x06) /*!< saturday */
|
||||||
|
#define RTC_SUNDAY ((uint8_t)0x07) /*!< sunday */
|
||||||
|
|
||||||
|
#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_DATE_YR bit field */
|
||||||
|
#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
|
||||||
|
|
||||||
|
/* ctl register value */
|
||||||
|
#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21)) /*!< write value to RTC_CTL_OS bit field */
|
||||||
|
#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
|
||||||
|
#define RTC_OS_ALARM0 CTL_OS(1) /*!< enable alarm0 flag output */
|
||||||
|
#define RTC_OS_ALARM1 CTL_OS(2) /*!< enable alarm1 flag output */
|
||||||
|
#define RTC_OS_WAKEUP CTL_OS(3) /*!< enable wakeup flag output */
|
||||||
|
|
||||||
|
#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
|
||||||
|
#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */
|
||||||
|
#define RTC_ALARM0_HIGH RTC_OS_ALARM0 /*!< enable alarm0 flag output with high level */
|
||||||
|
#define RTC_ALARM0_LOW (RTC_OS_ALARM0 | RTC_CTL_OPOL) /*!< enable alarm0 flag output with low level*/
|
||||||
|
#define RTC_ALARM1_HIGH RTC_OS_ALARM1 /*!< enable alarm1 flag output with high level */
|
||||||
|
#define RTC_ALARM1_LOW (RTC_OS_ALARM1 | RTC_CTL_OPOL) /*!< enable alarm1 flag output with low level*/
|
||||||
|
#define RTC_WAKEUP_HIGH RTC_OS_WAKEUP /*!< enable wakeup flag output with high level */
|
||||||
|
#define RTC_WAKEUP_LOW (RTC_OS_WAKEUP | RTC_CTL_OPOL) /*!< enable wakeup flag output with low level*/
|
||||||
|
|
||||||
|
#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
|
||||||
|
#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
|
||||||
|
|
||||||
|
#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
|
||||||
|
#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
|
||||||
|
|
||||||
|
/* psc register value */
|
||||||
|
#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_PSC_FACTOR_S bit field */
|
||||||
|
#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
|
||||||
|
|
||||||
|
#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_PSC_FACTOR_A bit field */
|
||||||
|
#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
|
||||||
|
|
||||||
|
/* alrmtd register value */
|
||||||
|
#define ALRMTD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMTD_SC bit field */
|
||||||
|
#define GET_ALRMTD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRMTD_SC bit field */
|
||||||
|
|
||||||
|
#define ALRMTD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_ALRMTD_MN bit field */
|
||||||
|
#define GET_ALRMTD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRMTD_MN bit field */
|
||||||
|
|
||||||
|
#define ALRMTD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_ALRMTD_HR bit field */
|
||||||
|
#define GET_ALRMTD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRMTD_HR bit field */
|
||||||
|
|
||||||
|
#define ALRMTD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMTD_DAY bit field */
|
||||||
|
#define GET_ALRMTD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRMTD_DAY bit field */
|
||||||
|
|
||||||
|
#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
|
||||||
|
#define RTC_ALARM_DATE_MASK RTC_ALRMXTD_MSKD /*!< alarm date mask */
|
||||||
|
#define RTC_ALARM_HOUR_MASK RTC_ALRMXTD_MSKH /*!< alarm hour mask */
|
||||||
|
#define RTC_ALARM_MINUTE_MASK RTC_ALRMXTD_MSKM /*!< alarm minute mask */
|
||||||
|
#define RTC_ALARM_SECOND_MASK RTC_ALRMXTD_MSKS /*!< alarm second mask */
|
||||||
|
#define RTC_ALARM_ALL_MASK (RTC_ALRMXTD_MSKD|RTC_ALRMXTD_MSKH|RTC_ALRMXTD_MSKM|RTC_ALRMXTD_MSKS) /*!< alarm all mask */
|
||||||
|
|
||||||
|
#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
|
||||||
|
#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRMXTD_DOWS /*!< alarm weekday format selected */
|
||||||
|
|
||||||
|
/* wpk register value */
|
||||||
|
#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_WPK_WPK bit field */
|
||||||
|
|
||||||
|
/* ss register value */
|
||||||
|
#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SS_SSC bit field */
|
||||||
|
|
||||||
|
/* shiftctl register value */
|
||||||
|
#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
|
||||||
|
|
||||||
|
#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
|
||||||
|
#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
|
||||||
|
|
||||||
|
/* tts register value */
|
||||||
|
#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_TTS_SC bit field */
|
||||||
|
#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
|
||||||
|
|
||||||
|
#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TTS_MN bit field */
|
||||||
|
#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
|
||||||
|
|
||||||
|
#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16)) /*!< write value to RTC_TTS_HR bit field */
|
||||||
|
#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
|
||||||
|
|
||||||
|
/* dts register value */
|
||||||
|
#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_DTS_DAY bit field */
|
||||||
|
#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
|
||||||
|
|
||||||
|
#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_DTS_MON bit field */
|
||||||
|
#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
|
||||||
|
|
||||||
|
#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_DTS_DOW bit field */
|
||||||
|
#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
|
||||||
|
|
||||||
|
/* ssts register value */
|
||||||
|
#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_SSTS_SSC bit field */
|
||||||
|
|
||||||
|
/* hrfc register value */
|
||||||
|
#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0)) /*!< write value to RTC_HRFC_CMSK bit field */
|
||||||
|
|
||||||
|
#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
|
||||||
|
#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
|
||||||
|
#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
|
||||||
|
|
||||||
|
#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
|
||||||
|
#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
|
||||||
|
|
||||||
|
/* tamp register value */
|
||||||
|
#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) /*!< write value to RTC_TAMP_FREQ bit field */
|
||||||
|
#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
|
||||||
|
#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
|
||||||
|
|
||||||
|
#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< write value to RTC_TAMP_FLT bit field */
|
||||||
|
#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
|
||||||
|
#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
|
||||||
|
#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
|
||||||
|
#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
|
||||||
|
|
||||||
|
#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) /*!< write value to RTC_TAMP_PRCH bit field */
|
||||||
|
#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
|
||||||
|
#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
|
||||||
|
#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
|
||||||
|
#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
|
||||||
|
|
||||||
|
#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
|
||||||
|
#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
|
||||||
|
|
||||||
|
#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
|
||||||
|
#define RTC_TAMPER_TRIGGER_EDGE_FALLING RTC_TAMP_TP0EG /*!< tamper detection is in falling edge mode */
|
||||||
|
#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
|
||||||
|
#define RTC_TAMPER_TRIGGER_LEVEL_HIGH RTC_TAMP_TP0EG /*!< tamper detection is in high level mode */
|
||||||
|
|
||||||
|
#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
|
||||||
|
|
||||||
|
#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
|
||||||
|
#define RTC_ALARM_OUTPUT_PP RTC_TAMP_AOT /*!< RTC alarm output push-pull mode */
|
||||||
|
|
||||||
|
/* ALRMXSS register value */
|
||||||
|
#define ALRMXSS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0)) /*!< write value to RTC_ALRMXSS_SSC bit field */
|
||||||
|
|
||||||
|
#define ALRMXSS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) /*!< write value to RTC_ALRMXSS_MASKSSC bit field */
|
||||||
|
#define RTC_MASKSSC_0_14 ALRMXSS_MASKSSC(0) /*!< mask alarm subsecond configuration */
|
||||||
|
#define RTC_MASKSSC_1_14 ALRMXSS_MASKSSC(1) /*!< mask RTC_ALRMXSS_SSC[14:1], and RTC_ALRMXSS_SSC[0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_2_14 ALRMXSS_MASKSSC(2) /*!< mask RTC_ALRMXSS_SSC[14:2], and RTC_ALRMXSS_SSC[1:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_3_14 ALRMXSS_MASKSSC(3) /*!< mask RTC_ALRMXSS_SSC[14:3], and RTC_ALRMXSS_SSC[2:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_4_14 ALRMXSS_MASKSSC(4) /*!< mask RTC_ALRMXSS_SSC[14:4]], and RTC_ALRMXSS_SSC[3:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_5_14 ALRMXSS_MASKSSC(5) /*!< mask RTC_ALRMXSS_SSC[14:5], and RTC_ALRMXSS_SSC[4:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_6_14 ALRMXSS_MASKSSC(6) /*!< mask RTC_ALRMXSS_SSC[14:6], and RTC_ALRMXSS_SSC[5:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_7_14 ALRMXSS_MASKSSC(7) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_8_14 ALRMXSS_MASKSSC(8) /*!< mask RTC_ALRMXSS_SSC[14:7], and RTC_ALRMXSS_SSC[6:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_9_14 ALRMXSS_MASKSSC(9) /*!< mask RTC_ALRMXSS_SSC[14:9], and RTC_ALRMXSS_SSC[8:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_10_14 ALRMXSS_MASKSSC(10) /*!< mask RTC_ALRMXSS_SSC[14:10], and RTC_ALRMXSS_SSC[9:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_11_14 ALRMXSS_MASKSSC(11) /*!< mask RTC_ALRMXSS_SSC[14:11], and RTC_ALRMXSS_SSC[10:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_12_14 ALRMXSS_MASKSSC(12) /*!< mask RTC_ALRMXSS_SSC[14:12], and RTC_ALRMXSS_SSC[11:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_13_14 ALRMXSS_MASKSSC(13) /*!< mask RTC_ALRMXSS_SSC[14:13], and RTC_ALRMXSS_SSC[12:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_14 ALRMXSS_MASKSSC(14) /*!< mask RTC_ALRMXSS_SSC[14], and RTC_ALRMXSS_SSC[13:0] is to be compared */
|
||||||
|
#define RTC_MASKSSC_NONE ALRMXSS_MASKSSC(15) /*!< mask none, and RTC_ALRMXSS_SSC[14:0] is to be compared */
|
||||||
|
|
||||||
|
/* RTC interrupt source */
|
||||||
|
#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
|
||||||
|
#define RTC_INT_ALARM0 RTC_CTL_ALRM0IE /*!< RTC alarm0 interrupt enable */
|
||||||
|
#define RTC_INT_ALARM1 RTC_CTL_ALRM1IE /*!< RTC alarm1 interrupt enable */
|
||||||
|
#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
|
||||||
|
#define RTC_INT_WAKEUP RTC_CTL_WTIE /*!< RTC wakeup timer interrupt enable */
|
||||||
|
|
||||||
|
/* write protect key */
|
||||||
|
#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
|
||||||
|
#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
|
||||||
|
#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
|
||||||
|
|
||||||
|
/* registers reset value */
|
||||||
|
#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
|
||||||
|
#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
|
||||||
|
#define RTC_STAT_RESET ((uint32_t)0x00000000U) /*!< RTC_STAT register reset value */
|
||||||
|
#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
|
||||||
|
#define RTC_WUT_RESET ((uint32_t)0x0000FFFFU) /*!< RTC_WUT register reset value */
|
||||||
|
|
||||||
|
/* RTC alarm */
|
||||||
|
#define RTC_ALARM0 ((uint8_t)0x01U) /*!< RTC alarm 0 */
|
||||||
|
#define RTC_ALARM1 ((uint8_t)0x02U) /*!< RTC alarm 1 */
|
||||||
|
|
||||||
|
/* RTC coarse calibration direction */
|
||||||
|
#define CALIB_INCREASE ((uint8_t)0x01U) /*!< RTC coarse calibration increase */
|
||||||
|
#define CALIB_DECREASE ((uint8_t)0x02U) /*!< RTC coarse calibration decrease */
|
||||||
|
|
||||||
|
/* RTC wakeup timer clock */
|
||||||
|
#define CTL_WTCS(regval) (BITS(0,2) & ((regval)<< 0))
|
||||||
|
#define WAKEUP_RTCCK_DIV16 CTL_WTCS(0) /*!< wakeup timer clock is RTC clock divided by 16 */
|
||||||
|
#define WAKEUP_RTCCK_DIV8 CTL_WTCS(1) /*!< wakeup timer clock is RTC clock divided by 8 */
|
||||||
|
#define WAKEUP_RTCCK_DIV4 CTL_WTCS(2) /*!< wakeup timer clock is RTC clock divided by 4 */
|
||||||
|
#define WAKEUP_RTCCK_DIV2 CTL_WTCS(3) /*!< wakeup timer clock is RTC clock divided by 2 */
|
||||||
|
#define WAKEUP_CKSPRE CTL_WTCS(4) /*!< wakeup timer clock is ckapre */
|
||||||
|
#define WAKEUP_CKSPRE_2EXP16 CTL_WTCS(6) /*!< wakeup timer clock is ckapre and wakeup timer add 2exp16 */
|
||||||
|
|
||||||
|
/* RTC_AF pin */
|
||||||
|
#define RTC_AF0_TIMESTAMP ((uint32_t)0x00000000) /*!< RTC_AF0 use for timestamp */
|
||||||
|
#define RTC_AF1_TIMESTAMP RTC_TAMP_TSSEL /*!< RTC_AF1 use for timestamp */
|
||||||
|
#define RTC_AF0_TAMPER0 ((uint32_t)0x00000000) /*!< RTC_AF0 use for tamper0 */
|
||||||
|
#define RTC_AF1_TAMPER0 RTC_TAMP_TP0SEL /*!< RTC_AF1 use for tamper0 */
|
||||||
|
|
||||||
|
/* RTC flags */
|
||||||
|
#define RTC_FLAG_ALRM0W RTC_STAT_ALRM0WF /*!< alarm0 configuration can be write flag */
|
||||||
|
#define RTC_FLAG_ALRM1W RTC_STAT_ALRM1WF /*!< alarm1 configuration can be write flag */
|
||||||
|
#define RTC_FLAG_WTW RTC_STAT_WTWF /*!< wakeup timer can be write flag */
|
||||||
|
#define RTC_FLAG_SOP RTC_STAT_SOPF /*!< shift function operation pending flag */
|
||||||
|
#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year configuration mark status flag */
|
||||||
|
#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< register synchronization flag */
|
||||||
|
#define RTC_FLAG_INIT RTC_STAT_INITF /*!< initialization state flag */
|
||||||
|
#define RTC_FLAG_ALRM0 RTC_STAT_ALRM0F /*!< alarm0 occurs flag */
|
||||||
|
#define RTC_FLAG_ALRM1 RTC_STAT_ALRM1F /*!< alarm1 occurs flag */
|
||||||
|
#define RTC_FLAG_WT RTC_STAT_WTF /*!< wakeup timer occurs flag */
|
||||||
|
#define RTC_FLAG_TS RTC_STAT_TSF /*!< time-stamp flag */
|
||||||
|
#define RTC_FLAG_TSOVR RTC_STAT_TSOVRF /*!< time-stamp overflow flag */
|
||||||
|
#define RTC_FLAG_TP0 RTC_STAT_TP0F /*!< RTC tamper 0 detected flag */
|
||||||
|
#define RTC_FLAG_TP1 RTC_STAT_TP1F /*!< RTC tamper 1 detected flag */
|
||||||
|
#define RTC_STAT_SCP RTC_STAT_SCPF /*!< smooth calibration pending flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* reset most of the RTC registers */
|
||||||
|
ErrStatus rtc_deinit(void);
|
||||||
|
/* initialize RTC registers */
|
||||||
|
ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
|
||||||
|
/* enter RTC init mode */
|
||||||
|
ErrStatus rtc_init_mode_enter(void);
|
||||||
|
/* exit RTC init mode */
|
||||||
|
void rtc_init_mode_exit(void);
|
||||||
|
/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
|
||||||
|
ErrStatus rtc_register_sync_wait(void);
|
||||||
|
|
||||||
|
/* get current time and date */
|
||||||
|
void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
|
||||||
|
/* get current subsecond value */
|
||||||
|
uint32_t rtc_subsecond_get(void);
|
||||||
|
|
||||||
|
/* configure RTC alarm */
|
||||||
|
void rtc_alarm_config(uint8_t rtc_alarm, rtc_alarm_struct* rtc_alarm_time);
|
||||||
|
/* configure subsecond of RTC alarm */
|
||||||
|
void rtc_alarm_subsecond_config(uint8_t rtc_alarm, uint32_t mask_subsecond, uint32_t subsecond);
|
||||||
|
/* get RTC alarm */
|
||||||
|
void rtc_alarm_get(uint8_t rtc_alarm,rtc_alarm_struct* rtc_alarm_time);
|
||||||
|
/* get RTC alarm subsecond */
|
||||||
|
uint32_t rtc_alarm_subsecond_get(uint8_t rtc_alarm);
|
||||||
|
/* enable RTC alarm */
|
||||||
|
void rtc_alarm_enable(uint8_t rtc_alarm);
|
||||||
|
/* disable RTC alarm */
|
||||||
|
ErrStatus rtc_alarm_disable(uint8_t rtc_alarm);
|
||||||
|
|
||||||
|
/* enable RTC time-stamp */
|
||||||
|
void rtc_timestamp_enable(uint32_t edge);
|
||||||
|
/* disable RTC time-stamp */
|
||||||
|
void rtc_timestamp_disable(void);
|
||||||
|
/* get RTC timestamp time and date */
|
||||||
|
void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
|
||||||
|
/* get RTC time-stamp subsecond */
|
||||||
|
uint32_t rtc_timestamp_subsecond_get(void);
|
||||||
|
/* RTC time-stamp pin map */
|
||||||
|
void rtc_timestamp_pin_map(uint32_t rtc_af);
|
||||||
|
|
||||||
|
/* enable RTC tamper */
|
||||||
|
void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
|
||||||
|
/* disable RTC tamper */
|
||||||
|
void rtc_tamper_disable(uint32_t source);
|
||||||
|
/* RTC tamper0 pin map */
|
||||||
|
void rtc_tamper0_pin_map(uint32_t rtc_af);
|
||||||
|
|
||||||
|
/* enable specified RTC interrupt */
|
||||||
|
void rtc_interrupt_enable(uint32_t interrupt);
|
||||||
|
/* disble specified RTC interrupt */
|
||||||
|
void rtc_interrupt_disable(uint32_t interrupt);
|
||||||
|
/* check specified flag */
|
||||||
|
FlagStatus rtc_flag_get(uint32_t flag);
|
||||||
|
/* clear specified flag */
|
||||||
|
void rtc_flag_clear(uint32_t flag);
|
||||||
|
|
||||||
|
/* configure RTC alarm output source */
|
||||||
|
void rtc_alarm_output_config(uint32_t source, uint32_t mode);
|
||||||
|
/* configure RTC calibration output source */
|
||||||
|
void rtc_calibration_output_config(uint32_t source);
|
||||||
|
|
||||||
|
/* adjust the daylight saving time by adding or substracting one hour from the current time */
|
||||||
|
void rtc_hour_adjust(uint32_t operation);
|
||||||
|
/* adjust RTC second or subsecond value of current time */
|
||||||
|
ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
|
||||||
|
|
||||||
|
/* enable RTC bypass shadow registers function */
|
||||||
|
void rtc_bypass_shadow_enable(void);
|
||||||
|
/* disable RTC bypass shadow registers function */
|
||||||
|
void rtc_bypass_shadow_disable(void);
|
||||||
|
|
||||||
|
/* enable RTC reference clock detection function */
|
||||||
|
ErrStatus rtc_refclock_detection_enable(void);
|
||||||
|
/* disable RTC reference clock detection function */
|
||||||
|
ErrStatus rtc_refclock_detection_disable(void);
|
||||||
|
|
||||||
|
/* enable RTC wakeup timer */
|
||||||
|
void rtc_wakeup_enable(void);
|
||||||
|
/* disable RTC wakeup timer */
|
||||||
|
ErrStatus rtc_wakeup_disable(void);
|
||||||
|
/* set auto wakeup timer clock */
|
||||||
|
ErrStatus rtc_wakeup_clock_set(uint8_t wakeup_clock);
|
||||||
|
/* set auto wakeup timer value */
|
||||||
|
ErrStatus rtc_wakeup_timer_set(uint16_t wakeup_timer);
|
||||||
|
/* get auto wakeup timer value */
|
||||||
|
uint16_t rtc_wakeup_timer_get(void);
|
||||||
|
|
||||||
|
/* configure RTC smooth calibration */
|
||||||
|
ErrStatus rtc_smooth_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
|
||||||
|
/* enable RTC coarse calibration */
|
||||||
|
ErrStatus rtc_coarse_calibration_enable(void);
|
||||||
|
/* disable RTC coarse calibration */
|
||||||
|
ErrStatus rtc_coarse_calibration_disable(void);
|
||||||
|
/* configure RTC coarse calibration direction and step */
|
||||||
|
ErrStatus rtc_coarse_calibration_config(uint8_t direction, uint8_t step);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_RTC_H */
|
||||||
@@ -0,0 +1,431 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_sdio.h
|
||||||
|
\brief definitions for the SDIO
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_SDIO_H
|
||||||
|
#define GD32F4XX_SDIO_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* SDIO definitions */
|
||||||
|
#define SDIO SDIO_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define SDIO_PWRCTL REG32(SDIO + 0x00000000U) /*!< SDIO power control register */
|
||||||
|
#define SDIO_CLKCTL REG32(SDIO + 0x00000004U) /*!< SDIO clock control register */
|
||||||
|
#define SDIO_CMDAGMT REG32(SDIO + 0x00000008U) /*!< SDIO command argument register */
|
||||||
|
#define SDIO_CMDCTL REG32(SDIO + 0x0000000CU) /*!< SDIO command control register */
|
||||||
|
#define SDIO_RSPCMDIDX REG32(SDIO + 0x00000010U) /*!< SDIO command index response register */
|
||||||
|
#define SDIO_RESP0 REG32(SDIO + 0x00000014U) /*!< SDIO response register 0 */
|
||||||
|
#define SDIO_RESP1 REG32(SDIO + 0x00000018U) /*!< SDIO response register 1 */
|
||||||
|
#define SDIO_RESP2 REG32(SDIO + 0x0000001CU) /*!< SDIO response register 2 */
|
||||||
|
#define SDIO_RESP3 REG32(SDIO + 0x00000020U) /*!< SDIO response register 3 */
|
||||||
|
#define SDIO_DATATO REG32(SDIO + 0x00000024U) /*!< SDIO data timeout register */
|
||||||
|
#define SDIO_DATALEN REG32(SDIO + 0x00000028U) /*!< SDIO data length register */
|
||||||
|
#define SDIO_DATACTL REG32(SDIO + 0x0000002CU) /*!< SDIO data control register */
|
||||||
|
#define SDIO_DATACNT REG32(SDIO + 0x00000030U) /*!< SDIO data counter register */
|
||||||
|
#define SDIO_STAT REG32(SDIO + 0x00000034U) /*!< SDIO status register */
|
||||||
|
#define SDIO_INTC REG32(SDIO + 0x00000038U) /*!< SDIO interrupt clear register */
|
||||||
|
#define SDIO_INTEN REG32(SDIO + 0x0000003CU) /*!< SDIO interrupt enable register */
|
||||||
|
#define SDIO_FIFOCNT REG32(SDIO + 0x00000048U) /*!< SDIO FIFO counter register */
|
||||||
|
#define SDIO_FIFO REG32(SDIO + 0x00000080U) /*!< SDIO FIFO data register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* SDIO_PWRCTL */
|
||||||
|
#define SDIO_PWRCTL_PWRCTL BITS(0,1) /*!< SDIO power control bits */
|
||||||
|
|
||||||
|
/* SDIO_CLKCTL */
|
||||||
|
#define SDIO_CLKCTL_DIV BITS(0,7) /*!< clock division */
|
||||||
|
#define SDIO_CLKCTL_CLKEN BIT(8) /*!< SDIO_CLK clock output enable bit */
|
||||||
|
#define SDIO_CLKCTL_CLKPWRSAV BIT(9) /*!< SDIO_CLK clock dynamic switch on/off for power saving */
|
||||||
|
#define SDIO_CLKCTL_CLKBYP BIT(10) /*!< clock bypass enable bit */
|
||||||
|
#define SDIO_CLKCTL_BUSMODE BITS(11,12) /*!< SDIO card bus mode control bit */
|
||||||
|
#define SDIO_CLKCTL_CLKEDGE BIT(13) /*!< SDIO_CLK clock edge selection bit */
|
||||||
|
#define SDIO_CLKCTL_HWCLKEN BIT(14) /*!< hardware clock control enable bit */
|
||||||
|
#define SDIO_CLKCTL_DIV8 BIT(31) /*!< MSB of clock division */
|
||||||
|
|
||||||
|
/* SDIO_CMDAGMT */
|
||||||
|
#define SDIO_CMDAGMT_CMDAGMT BITS(0,31) /*!< SDIO card command argument */
|
||||||
|
|
||||||
|
/* SDIO_CMDCTL */
|
||||||
|
#define SDIO_CMDCTL_CMDIDX BITS(0,5) /*!< command index */
|
||||||
|
#define SDIO_CMDCTL_CMDRESP BITS(6,7) /*!< command response type bits */
|
||||||
|
#define SDIO_CMDCTL_INTWAIT BIT(8) /*!< interrupt wait instead of timeout */
|
||||||
|
#define SDIO_CMDCTL_WAITDEND BIT(9) /*!< wait for ends of data transfer */
|
||||||
|
#define SDIO_CMDCTL_CSMEN BIT(10) /*!< command state machine(CSM) enable bit */
|
||||||
|
#define SDIO_CMDCTL_SUSPEND BIT(11) /*!< SD I/O suspend command(SD I/O only) */
|
||||||
|
#define SDIO_CMDCTL_ENCMDC BIT(12) /*!< CMD completion signal enabled (CE-ATA only) */
|
||||||
|
#define SDIO_CMDCTL_NINTEN BIT(13) /*!< no CE-ATA interrupt (CE-ATA only) */
|
||||||
|
#define SDIO_CMDCTL_ATAEN BIT(14) /*!< CE-ATA command enable(CE-ATA only) */
|
||||||
|
|
||||||
|
/* SDIO_DATATO */
|
||||||
|
#define SDIO_DATATO_DATATO BITS(0,31) /*!< data timeout period */
|
||||||
|
|
||||||
|
/* SDIO_DATALEN */
|
||||||
|
#define SDIO_DATALEN_DATALEN BITS(0,24) /*!< data transfer length */
|
||||||
|
|
||||||
|
/* SDIO_DATACTL */
|
||||||
|
#define SDIO_DATACTL_DATAEN BIT(0) /*!< data transfer enabled bit */
|
||||||
|
#define SDIO_DATACTL_DATADIR BIT(1) /*!< data transfer direction */
|
||||||
|
#define SDIO_DATACTL_TRANSMOD BIT(2) /*!< data transfer mode */
|
||||||
|
#define SDIO_DATACTL_DMAEN BIT(3) /*!< DMA enable bit */
|
||||||
|
#define SDIO_DATACTL_BLKSZ BITS(4,7) /*!< data block size */
|
||||||
|
#define SDIO_DATACTL_RWEN BIT(8) /*!< read wait mode enabled(SD I/O only) */
|
||||||
|
#define SDIO_DATACTL_RWSTOP BIT(9) /*!< read wait stop(SD I/O only) */
|
||||||
|
#define SDIO_DATACTL_RWTYPE BIT(10) /*!< read wait type(SD I/O only) */
|
||||||
|
#define SDIO_DATACTL_IOEN BIT(11) /*!< SD I/O specific function enable(SD I/O only) */
|
||||||
|
|
||||||
|
/* SDIO_STAT */
|
||||||
|
#define SDIO_STAT_CCRCERR BIT(0) /*!< command response received (CRC check failed) */
|
||||||
|
#define SDIO_STAT_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) */
|
||||||
|
#define SDIO_STAT_CMDTMOUT BIT(2) /*!< command response timeout */
|
||||||
|
#define SDIO_STAT_DTTMOUT BIT(3) /*!< data timeout */
|
||||||
|
#define SDIO_STAT_TXURE BIT(4) /*!< transmit FIFO underrun error occurs */
|
||||||
|
#define SDIO_STAT_RXORE BIT(5) /*!< received FIFO overrun error occurs */
|
||||||
|
#define SDIO_STAT_CMDRECV BIT(6) /*!< command response received (CRC check passed) */
|
||||||
|
#define SDIO_STAT_CMDSEND BIT(7) /*!< command sent (no response required) */
|
||||||
|
#define SDIO_STAT_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) */
|
||||||
|
#define SDIO_STAT_STBITE BIT(9) /*!< start bit error in the bus */
|
||||||
|
#define SDIO_STAT_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) */
|
||||||
|
#define SDIO_STAT_CMDRUN BIT(11) /*!< command transmission in progress */
|
||||||
|
#define SDIO_STAT_TXRUN BIT(12) /*!< data transmission in progress */
|
||||||
|
#define SDIO_STAT_RXRUN BIT(13) /*!< data reception in progress */
|
||||||
|
#define SDIO_STAT_TFH BIT(14) /*!< transmit FIFO is half empty: at least 8 words can be written into the FIFO */
|
||||||
|
#define SDIO_STAT_RFH BIT(15) /*!< receive FIFO is half full: at least 8 words can be read in the FIFO */
|
||||||
|
#define SDIO_STAT_TFF BIT(16) /*!< transmit FIFO is full */
|
||||||
|
#define SDIO_STAT_RFF BIT(17) /*!< receive FIFO is full */
|
||||||
|
#define SDIO_STAT_TFE BIT(18) /*!< transmit FIFO is empty */
|
||||||
|
#define SDIO_STAT_RFE BIT(19) /*!< receive FIFO is empty */
|
||||||
|
#define SDIO_STAT_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO */
|
||||||
|
#define SDIO_STAT_RXDTVAL BIT(21) /*!< data is valid in receive FIFO */
|
||||||
|
#define SDIO_STAT_SDIOINT BIT(22) /*!< SD I/O interrupt received */
|
||||||
|
#define SDIO_STAT_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) */
|
||||||
|
|
||||||
|
/* SDIO_INTC */
|
||||||
|
#define SDIO_INTC_CCRCERRC BIT(0) /*!< CCRCERR flag clear bit */
|
||||||
|
#define SDIO_INTC_DTCRCERRC BIT(1) /*!< DTCRCERR flag clear bit */
|
||||||
|
#define SDIO_INTC_CMDTMOUTC BIT(2) /*!< CMDTMOUT flag clear bit */
|
||||||
|
#define SDIO_INTC_DTTMOUTC BIT(3) /*!< DTTMOUT flag clear bit */
|
||||||
|
#define SDIO_INTC_TXUREC BIT(4) /*!< TXURE flag clear bit */
|
||||||
|
#define SDIO_INTC_RXOREC BIT(5) /*!< RXORE flag clear bit */
|
||||||
|
#define SDIO_INTC_CMDRECVC BIT(6) /*!< CMDRECV flag clear bit */
|
||||||
|
#define SDIO_INTC_CMDSENDC BIT(7) /*!< CMDSEND flag clear bit */
|
||||||
|
#define SDIO_INTC_DTENDC BIT(8) /*!< DTEND flag clear bit */
|
||||||
|
#define SDIO_INTC_STBITEC BIT(9) /*!< STBITE flag clear bit */
|
||||||
|
#define SDIO_INTC_DTBLKENDC BIT(10) /*!< DTBLKEND flag clear bit */
|
||||||
|
#define SDIO_INTC_SDIOINTC BIT(22) /*!< SDIOINT flag clear bit */
|
||||||
|
#define SDIO_INTC_ATAENDC BIT(23) /*!< ATAEND flag clear bit */
|
||||||
|
|
||||||
|
/* SDIO_INTEN */
|
||||||
|
#define SDIO_INTEN_CCRCERRIE BIT(0) /*!< command response CRC fail interrupt enable */
|
||||||
|
#define SDIO_INTEN_DTCRCERRIE BIT(1) /*!< data CRC fail interrupt enable */
|
||||||
|
#define SDIO_INTEN_CMDTMOUTIE BIT(2) /*!< command response timeout interrupt enable */
|
||||||
|
#define SDIO_INTEN_DTTMOUTIE BIT(3) /*!< data timeout interrupt enable */
|
||||||
|
#define SDIO_INTEN_TXUREIE BIT(4) /*!< transmit FIFO underrun error interrupt enable */
|
||||||
|
#define SDIO_INTEN_RXOREIE BIT(5) /*!< received FIFO overrun error interrupt enable */
|
||||||
|
#define SDIO_INTEN_CMDRECVIE BIT(6) /*!< command response received interrupt enable */
|
||||||
|
#define SDIO_INTEN_CMDSENDIE BIT(7) /*!< command sent interrupt enable */
|
||||||
|
#define SDIO_INTEN_DTENDIE BIT(8) /*!< data end interrupt enable */
|
||||||
|
#define SDIO_INTEN_STBITEIE BIT(9) /*!< start bit error interrupt enable */
|
||||||
|
#define SDIO_INTEN_DTBLKENDIE BIT(10) /*!< data block end interrupt enable */
|
||||||
|
#define SDIO_INTEN_CMDRUNIE BIT(11) /*!< command transmission interrupt enable */
|
||||||
|
#define SDIO_INTEN_TXRUNIE BIT(12) /*!< data transmission interrupt enable */
|
||||||
|
#define SDIO_INTEN_RXRUNIE BIT(13) /*!< data reception interrupt enable */
|
||||||
|
#define SDIO_INTEN_TFHIE BIT(14) /*!< transmit FIFO half empty interrupt enable */
|
||||||
|
#define SDIO_INTEN_RFHIE BIT(15) /*!< receive FIFO half full interrupt enable */
|
||||||
|
#define SDIO_INTEN_TFFIE BIT(16) /*!< transmit FIFO full interrupt enable */
|
||||||
|
#define SDIO_INTEN_RFFIE BIT(17) /*!< receive FIFO full interrupt enable */
|
||||||
|
#define SDIO_INTEN_TFEIE BIT(18) /*!< transmit FIFO empty interrupt enable */
|
||||||
|
#define SDIO_INTEN_RFEIE BIT(19) /*!< receive FIFO empty interrupt enable */
|
||||||
|
#define SDIO_INTEN_TXDTVALIE BIT(20) /*!< data valid in transmit FIFO interrupt enable */
|
||||||
|
#define SDIO_INTEN_RXDTVALIE BIT(21) /*!< data valid in receive FIFO interrupt enable */
|
||||||
|
#define SDIO_INTEN_SDIOINTIE BIT(22) /*!< SD I/O interrupt received interrupt enable */
|
||||||
|
#define SDIO_INTEN_ATAENDIE BIT(23) /*!< CE-ATA command completion signal received interrupt enable */
|
||||||
|
|
||||||
|
/* SDIO_FIFO */
|
||||||
|
#define SDIO_FIFO_FIFODT BITS(0,31) /*!< receive FIFO data or transmit FIFO data */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* SDIO flags */
|
||||||
|
#define SDIO_FLAG_CCRCERR BIT(0) /*!< command response received (CRC check failed) flag */
|
||||||
|
#define SDIO_FLAG_DTCRCERR BIT(1) /*!< data block sent/received (CRC check failed) flag */
|
||||||
|
#define SDIO_FLAG_CMDTMOUT BIT(2) /*!< command response timeout flag */
|
||||||
|
#define SDIO_FLAG_DTTMOUT BIT(3) /*!< data timeout flag */
|
||||||
|
#define SDIO_FLAG_TXURE BIT(4) /*!< transmit FIFO underrun error occurs flag */
|
||||||
|
#define SDIO_FLAG_RXORE BIT(5) /*!< received FIFO overrun error occurs flag */
|
||||||
|
#define SDIO_FLAG_CMDRECV BIT(6) /*!< command response received (CRC check passed) flag */
|
||||||
|
#define SDIO_FLAG_CMDSEND BIT(7) /*!< command sent (no response required) flag */
|
||||||
|
#define SDIO_FLAG_DTEND BIT(8) /*!< data end (data counter, SDIO_DATACNT, is zero) flag */
|
||||||
|
#define SDIO_FLAG_STBITE BIT(9) /*!< start bit error in the bus flag */
|
||||||
|
#define SDIO_FLAG_DTBLKEND BIT(10) /*!< data block sent/received (CRC check passed) flag */
|
||||||
|
#define SDIO_FLAG_CMDRUN BIT(11) /*!< command transmission in progress flag */
|
||||||
|
#define SDIO_FLAG_TXRUN BIT(12) /*!< data transmission in progress flag */
|
||||||
|
#define SDIO_FLAG_RXRUN BIT(13) /*!< data reception in progress flag */
|
||||||
|
#define SDIO_FLAG_TFH BIT(14) /*!< transmit FIFO is half empty flag: at least 8 words can be written into the FIFO */
|
||||||
|
#define SDIO_FLAG_RFH BIT(15) /*!< receive FIFO is half full flag: at least 8 words can be read in the FIFO */
|
||||||
|
#define SDIO_FLAG_TFF BIT(16) /*!< transmit FIFO is full flag */
|
||||||
|
#define SDIO_FLAG_RFF BIT(17) /*!< receive FIFO is full flag */
|
||||||
|
#define SDIO_FLAG_TFE BIT(18) /*!< transmit FIFO is empty flag */
|
||||||
|
#define SDIO_FLAG_RFE BIT(19) /*!< receive FIFO is empty flag */
|
||||||
|
#define SDIO_FLAG_TXDTVAL BIT(20) /*!< data is valid in transmit FIFO flag */
|
||||||
|
#define SDIO_FLAG_RXDTVAL BIT(21) /*!< data is valid in receive FIFO flag */
|
||||||
|
#define SDIO_FLAG_SDIOINT BIT(22) /*!< SD I/O interrupt received flag */
|
||||||
|
#define SDIO_FLAG_ATAEND BIT(23) /*!< CE-ATA command completion signal received (only for CMD61) flag */
|
||||||
|
|
||||||
|
/* SDIO interrupt enable or disable */
|
||||||
|
#define SDIO_INT_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt */
|
||||||
|
#define SDIO_INT_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt */
|
||||||
|
#define SDIO_INT_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt */
|
||||||
|
#define SDIO_INT_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt */
|
||||||
|
#define SDIO_INT_TXURE BIT(4) /*!< SDIO TXURE interrupt */
|
||||||
|
#define SDIO_INT_RXORE BIT(5) /*!< SDIO RXORE interrupt */
|
||||||
|
#define SDIO_INT_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt */
|
||||||
|
#define SDIO_INT_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt */
|
||||||
|
#define SDIO_INT_DTEND BIT(8) /*!< SDIO DTEND interrupt */
|
||||||
|
#define SDIO_INT_STBITE BIT(9) /*!< SDIO STBITE interrupt */
|
||||||
|
#define SDIO_INT_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt */
|
||||||
|
#define SDIO_INT_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt */
|
||||||
|
#define SDIO_INT_TXRUN BIT(12) /*!< SDIO TXRUN interrupt */
|
||||||
|
#define SDIO_INT_RXRUN BIT(13) /*!< SDIO RXRUN interrupt */
|
||||||
|
#define SDIO_INT_TFH BIT(14) /*!< SDIO TFH interrupt */
|
||||||
|
#define SDIO_INT_RFH BIT(15) /*!< SDIO RFH interrupt */
|
||||||
|
#define SDIO_INT_TFF BIT(16) /*!< SDIO TFF interrupt */
|
||||||
|
#define SDIO_INT_RFF BIT(17) /*!< SDIO RFF interrupt */
|
||||||
|
#define SDIO_INT_TFE BIT(18) /*!< SDIO TFE interrupt */
|
||||||
|
#define SDIO_INT_RFE BIT(19) /*!< SDIO RFE interrupt */
|
||||||
|
#define SDIO_INT_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt */
|
||||||
|
#define SDIO_INT_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt */
|
||||||
|
#define SDIO_INT_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt */
|
||||||
|
#define SDIO_INT_ATAEND BIT(23) /*!< SDIO ATAEND interrupt */
|
||||||
|
|
||||||
|
/* SDIO interrupt flags */
|
||||||
|
#define SDIO_INT_FLAG_CCRCERR BIT(0) /*!< SDIO CCRCERR interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_DTCRCERR BIT(1) /*!< SDIO DTCRCERR interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_CMDTMOUT BIT(2) /*!< SDIO CMDTMOUT interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_DTTMOUT BIT(3) /*!< SDIO DTTMOUT interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TXURE BIT(4) /*!< SDIO TXURE interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RXORE BIT(5) /*!< SDIO RXORE interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_CMDRECV BIT(6) /*!< SDIO CMDRECV interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_CMDSEND BIT(7) /*!< SDIO CMDSEND interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_DTEND BIT(8) /*!< SDIO DTEND interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_STBITE BIT(9) /*!< SDIO STBITE interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_DTBLKEND BIT(10) /*!< SDIO DTBLKEND interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_CMDRUN BIT(11) /*!< SDIO CMDRUN interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TXRUN BIT(12) /*!< SDIO TXRUN interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RXRUN BIT(13) /*!< SDIO RXRUN interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TFH BIT(14) /*!< SDIO TFH interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RFH BIT(15) /*!< SDIO RFH interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TFF BIT(16) /*!< SDIO TFF interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RFF BIT(17) /*!< SDIO RFF interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TFE BIT(18) /*!< SDIO TFE interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RFE BIT(19) /*!< SDIO RFE interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_TXDTVAL BIT(20) /*!< SDIO TXDTVAL interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_RXDTVAL BIT(21) /*!< SDIO RXDTVAL interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_SDIOINT BIT(22) /*!< SDIO SDIOINT interrupt flag */
|
||||||
|
#define SDIO_INT_FLAG_ATAEND BIT(23) /*!< SDIO ATAEND interrupt flag */
|
||||||
|
|
||||||
|
/* SDIO power control */
|
||||||
|
#define PWRCTL_PWRCTL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||||
|
#define SDIO_POWER_OFF PWRCTL_PWRCTL(0) /*!< SDIO power off */
|
||||||
|
#define SDIO_POWER_ON PWRCTL_PWRCTL(3) /*!< SDIO power on */
|
||||||
|
|
||||||
|
/* SDIO card bus mode control */
|
||||||
|
#define CLKCTL_BUSMODE(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||||
|
#define SDIO_BUSMODE_1BIT CLKCTL_BUSMODE(0) /*!< 1-bit SDIO card bus mode */
|
||||||
|
#define SDIO_BUSMODE_4BIT CLKCTL_BUSMODE(1) /*!< 4-bit SDIO card bus mode */
|
||||||
|
#define SDIO_BUSMODE_8BIT CLKCTL_BUSMODE(2) /*!< 8-bit SDIO card bus mode */
|
||||||
|
|
||||||
|
/* SDIO_CLK clock edge selection */
|
||||||
|
#define SDIO_SDIOCLKEDGE_RISING (uint32_t)0x00000000U /*!< select the rising edge of the SDIOCLK to generate SDIO_CLK */
|
||||||
|
#define SDIO_SDIOCLKEDGE_FALLING SDIO_CLKCTL_CLKEDGE /*!< select the falling edge of the SDIOCLK to generate SDIO_CLK */
|
||||||
|
|
||||||
|
/* clock bypass enable or disable */
|
||||||
|
#define SDIO_CLOCKBYPASS_DISABLE (uint32_t)0x00000000U /*!< no bypass */
|
||||||
|
#define SDIO_CLOCKBYPASS_ENABLE SDIO_CLKCTL_CLKBYP /*!< clock bypass */
|
||||||
|
|
||||||
|
/* SDIO_CLK clock dynamic switch on/off for power saving */
|
||||||
|
#define SDIO_CLOCKPWRSAVE_DISABLE (uint32_t)0x00000000U /*!< SDIO_CLK clock is always on */
|
||||||
|
#define SDIO_CLOCKPWRSAVE_ENABLE SDIO_CLKCTL_CLKPWRSAV /*!< SDIO_CLK closed when bus is idle */
|
||||||
|
|
||||||
|
/* SDIO command response type */
|
||||||
|
#define CMDCTL_CMDRESP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||||
|
#define SDIO_RESPONSETYPE_NO CMDCTL_CMDRESP(0) /*!< no response */
|
||||||
|
#define SDIO_RESPONSETYPE_SHORT CMDCTL_CMDRESP(1) /*!< short response */
|
||||||
|
#define SDIO_RESPONSETYPE_LONG CMDCTL_CMDRESP(3) /*!< long response */
|
||||||
|
|
||||||
|
/* command state machine wait type */
|
||||||
|
#define SDIO_WAITTYPE_NO (uint32_t)0x00000000U /*!< not wait interrupt */
|
||||||
|
#define SDIO_WAITTYPE_INTERRUPT SDIO_CMDCTL_INTWAIT /*!< wait interrupt */
|
||||||
|
#define SDIO_WAITTYPE_DATAEND SDIO_CMDCTL_WAITDEND /*!< wait the end of data transfer */
|
||||||
|
|
||||||
|
#define SDIO_RESPONSE0 (uint32_t)0x00000000U /*!< card response[31:0]/card response[127:96] */
|
||||||
|
#define SDIO_RESPONSE1 (uint32_t)0x00000001U /*!< card response[95:64] */
|
||||||
|
#define SDIO_RESPONSE2 (uint32_t)0x00000002U /*!< card response[63:32] */
|
||||||
|
#define SDIO_RESPONSE3 (uint32_t)0x00000003U /*!< card response[31:1], plus bit 0 */
|
||||||
|
|
||||||
|
/* SDIO data block size */
|
||||||
|
#define DATACTL_BLKSZ(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||||
|
#define SDIO_DATABLOCKSIZE_1BYTE DATACTL_BLKSZ(0) /*!< block size = 1 byte */
|
||||||
|
#define SDIO_DATABLOCKSIZE_2BYTES DATACTL_BLKSZ(1) /*!< block size = 2 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_4BYTES DATACTL_BLKSZ(2) /*!< block size = 4 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_8BYTES DATACTL_BLKSZ(3) /*!< block size = 8 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_16BYTES DATACTL_BLKSZ(4) /*!< block size = 16 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_32BYTES DATACTL_BLKSZ(5) /*!< block size = 32 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_64BYTES DATACTL_BLKSZ(6) /*!< block size = 64 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_128BYTES DATACTL_BLKSZ(7) /*!< block size = 128 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_256BYTES DATACTL_BLKSZ(8) /*!< block size = 256 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_512BYTES DATACTL_BLKSZ(9) /*!< block size = 512 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_1024BYTES DATACTL_BLKSZ(10) /*!< block size = 1024 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_2048BYTES DATACTL_BLKSZ(11) /*!< block size = 2048 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_4096BYTES DATACTL_BLKSZ(12) /*!< block size = 4096 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_8192BYTES DATACTL_BLKSZ(13) /*!< block size = 8192 bytes */
|
||||||
|
#define SDIO_DATABLOCKSIZE_16384BYTES DATACTL_BLKSZ(14) /*!< block size = 16384 bytes */
|
||||||
|
|
||||||
|
/* SDIO data transfer mode */
|
||||||
|
#define SDIO_TRANSMODE_BLOCK (uint32_t)0x00000000U /*!< block transfer */
|
||||||
|
#define SDIO_TRANSMODE_STREAM SDIO_DATACTL_TRANSMOD /*!< stream transfer or SDIO multibyte transfer */
|
||||||
|
|
||||||
|
/* SDIO data transfer direction */
|
||||||
|
#define SDIO_TRANSDIRECTION_TOCARD (uint32_t)0x00000000U /*!< write data to card */
|
||||||
|
#define SDIO_TRANSDIRECTION_TOSDIO SDIO_DATACTL_DATADIR /*!< read data from card */
|
||||||
|
|
||||||
|
/* SDIO read wait type */
|
||||||
|
#define SDIO_READWAITTYPE_DAT2 (uint32_t)0x00000000U /*!< read wait control using SDIO_DAT[2] */
|
||||||
|
#define SDIO_READWAITTYPE_CLK SDIO_DATACTL_RWTYPE /*!< read wait control by stopping SDIO_CLK */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* de/initialization functions, hardware clock, bus mode, power_state and SDIO clock configuration */
|
||||||
|
/* deinitialize the SDIO */
|
||||||
|
void sdio_deinit(void);
|
||||||
|
/* configure the SDIO clock */
|
||||||
|
void sdio_clock_config(uint32_t clock_edge, uint32_t clock_bypass, uint32_t clock_powersave, uint16_t clock_division);
|
||||||
|
/* enable hardware clock control */
|
||||||
|
void sdio_hardware_clock_enable(void);
|
||||||
|
/* disable hardware clock control */
|
||||||
|
void sdio_hardware_clock_disable(void);
|
||||||
|
/* set different SDIO card bus mode */
|
||||||
|
void sdio_bus_mode_set(uint32_t bus_mode);
|
||||||
|
/* set the SDIO power state */
|
||||||
|
void sdio_power_state_set(uint32_t power_state);
|
||||||
|
/* get the SDIO power state */
|
||||||
|
uint32_t sdio_power_state_get(void);
|
||||||
|
/* enable SDIO_CLK clock output */
|
||||||
|
void sdio_clock_enable(void);
|
||||||
|
/* disable SDIO_CLK clock output */
|
||||||
|
void sdio_clock_disable(void);
|
||||||
|
|
||||||
|
/* configure the command index, argument, response type, wait type and CSM to send command functions */
|
||||||
|
/* configure the command and response */
|
||||||
|
void sdio_command_response_config(uint32_t cmd_index, uint32_t cmd_argument, uint32_t response_type);
|
||||||
|
/* set the command state machine wait type */
|
||||||
|
void sdio_wait_type_set(uint32_t wait_type);
|
||||||
|
/* enable the CSM(command state machine) */
|
||||||
|
void sdio_csm_enable(void);
|
||||||
|
/* disable the CSM(command state machine) */
|
||||||
|
void sdio_csm_disable(void);
|
||||||
|
/* get the last response command index */
|
||||||
|
uint8_t sdio_command_index_get(void);
|
||||||
|
/* get the response for the last received command */
|
||||||
|
uint32_t sdio_response_get(uint32_t sdio_responsex);
|
||||||
|
|
||||||
|
/* configure the data timeout, length, block size, transfer mode, direction and DSM for data transfer functions */
|
||||||
|
/* configure the data timeout, data length and data block size */
|
||||||
|
void sdio_data_config(uint32_t data_timeout, uint32_t data_length, uint32_t data_blocksize);
|
||||||
|
/* configure the data transfer mode and direction */
|
||||||
|
void sdio_data_transfer_config(uint32_t transfer_mode, uint32_t transfer_direction);
|
||||||
|
/* enable the DSM(data state machine) for data transfer */
|
||||||
|
void sdio_dsm_enable(void);
|
||||||
|
/* disable the DSM(data state machine) */
|
||||||
|
void sdio_dsm_disable(void);
|
||||||
|
/* write data(one word) to the transmit FIFO */
|
||||||
|
void sdio_data_write(uint32_t data);
|
||||||
|
/* read data(one word) from the receive FIFO */
|
||||||
|
uint32_t sdio_data_read(void);
|
||||||
|
/* get the number of remaining data bytes to be transferred to card */
|
||||||
|
uint32_t sdio_data_counter_get(void);
|
||||||
|
/* get the number of words remaining to be written or read from FIFO */
|
||||||
|
uint32_t sdio_fifo_counter_get(void);
|
||||||
|
/* enable the DMA request for SDIO */
|
||||||
|
void sdio_dma_enable(void);
|
||||||
|
/* disable the DMA request for SDIO */
|
||||||
|
void sdio_dma_disable(void);
|
||||||
|
|
||||||
|
/* flag and interrupt functions */
|
||||||
|
/* get the flags state of SDIO */
|
||||||
|
FlagStatus sdio_flag_get(uint32_t flag);
|
||||||
|
/* clear the pending flags of SDIO */
|
||||||
|
void sdio_flag_clear(uint32_t flag);
|
||||||
|
/* enable the SDIO interrupt */
|
||||||
|
void sdio_interrupt_enable(uint32_t int_flag);
|
||||||
|
/* disable the SDIO interrupt */
|
||||||
|
void sdio_interrupt_disable(uint32_t int_flag);
|
||||||
|
/* get the interrupt flags state of SDIO */
|
||||||
|
FlagStatus sdio_interrupt_flag_get(uint32_t int_flag);
|
||||||
|
/* clear the interrupt pending flags of SDIO */
|
||||||
|
void sdio_interrupt_flag_clear(uint32_t int_flag);
|
||||||
|
|
||||||
|
/* SD I/O card functions */
|
||||||
|
/* enable the read wait mode(SD I/O only) */
|
||||||
|
void sdio_readwait_enable(void);
|
||||||
|
/* disable the read wait mode(SD I/O only) */
|
||||||
|
void sdio_readwait_disable(void);
|
||||||
|
/* enable the function that stop the read wait process(SD I/O only) */
|
||||||
|
void sdio_stop_readwait_enable(void);
|
||||||
|
/* disable the function that stop the read wait process(SD I/O only) */
|
||||||
|
void sdio_stop_readwait_disable(void);
|
||||||
|
/* set the read wait type(SD I/O only) */
|
||||||
|
void sdio_readwait_type_set(uint32_t readwait_type);
|
||||||
|
/* enable the SD I/O mode specific operation(SD I/O only) */
|
||||||
|
void sdio_operation_enable(void);
|
||||||
|
/* disable the SD I/O mode specific operation(SD I/O only) */
|
||||||
|
void sdio_operation_disable(void);
|
||||||
|
/* enable the SD I/O suspend operation(SD I/O only) */
|
||||||
|
void sdio_suspend_enable(void);
|
||||||
|
/* disable the SD I/O suspend operation(SD I/O only) */
|
||||||
|
void sdio_suspend_disable(void);
|
||||||
|
|
||||||
|
/* CE-ATA functions */
|
||||||
|
/* enable the CE-ATA command(CE-ATA only) */
|
||||||
|
void sdio_ceata_command_enable(void);
|
||||||
|
/* disable the CE-ATA command(CE-ATA only) */
|
||||||
|
void sdio_ceata_command_disable(void);
|
||||||
|
/* enable the CE-ATA interrupt(CE-ATA only) */
|
||||||
|
void sdio_ceata_interrupt_enable(void);
|
||||||
|
/* disable the CE-ATA interrupt(CE-ATA only) */
|
||||||
|
void sdio_ceata_interrupt_disable(void);
|
||||||
|
/* enable the CE-ATA command completion signal(CE-ATA only) */
|
||||||
|
void sdio_ceata_command_completion_enable(void);
|
||||||
|
/* disable the CE-ATA command completion signal(CE-ATA only) */
|
||||||
|
void sdio_ceata_command_completion_disable(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_SDIO_H */
|
||||||
@@ -0,0 +1,372 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_spi.h
|
||||||
|
\brief definitions for the SPI
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_SPI_H
|
||||||
|
#define GD32F4XX_SPI_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* SPIx(x=0,1,2,3,4,5) definitions */
|
||||||
|
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||||
|
#define SPI1 SPI_BASE
|
||||||
|
#define SPI2 (SPI_BASE + 0x00000400U)
|
||||||
|
#define SPI3 (SPI_BASE + 0x0000FC00U)
|
||||||
|
#define SPI4 (SPI_BASE + 0x00011800U)
|
||||||
|
#define SPI5 (SPI_BASE + 0x00011C00U)
|
||||||
|
|
||||||
|
/* I2Sx_ADD(x=1,2) definitions */
|
||||||
|
#define I2S1_ADD I2S_ADD_BASE
|
||||||
|
#define I2S2_ADD (I2S_ADD_BASE + 0x00000C00U)
|
||||||
|
|
||||||
|
/* SPI registers definitions */
|
||||||
|
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||||
|
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||||
|
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||||
|
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||||
|
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||||
|
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||||
|
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||||
|
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||||
|
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||||
|
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register */
|
||||||
|
|
||||||
|
/* I2S_ADD registers definitions */
|
||||||
|
#define I2S_ADD_CTL0(i2sx_add) REG32((i2sx_add) + 0x00000000U) /*!< I2S_ADD control register 0 */
|
||||||
|
#define I2S_ADD_CTL1(i2sx_add) REG32((i2sx_add) + 0x00000004U) /*!< I2S_ADD control register 1*/
|
||||||
|
#define I2S_ADD_STAT(i2sx_add) REG32((i2sx_add) + 0x00000008U) /*!< I2S_ADD status register */
|
||||||
|
#define I2S_ADD_DATA(i2sx_add) REG32((i2sx_add) + 0x0000000CU) /*!< I2S_ADD data register */
|
||||||
|
#define I2S_ADD_CRCPOLY(i2sx_add) REG32((i2sx_add) + 0x00000010U) /*!< I2S_ADD CRC polynomial register */
|
||||||
|
#define I2S_ADD_RCRC(i2sx_add) REG32((i2sx_add) + 0x00000014U) /*!< I2S_ADD receive CRC register */
|
||||||
|
#define I2S_ADD_TCRC(i2sx_add) REG32((i2sx_add) + 0x00000018U) /*!< I2S_ADD transmit CRC register */
|
||||||
|
#define I2S_ADD_I2SCTL(i2sx_add) REG32((i2sx_add) + 0x0000001CU) /*!< I2S_ADD I2S control register */
|
||||||
|
#define I2S_ADD_I2SPSC(i2sx_add) REG32((i2sx_add) + 0x00000020U) /*!< I2S_ADD I2S clock prescaler register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* SPI_CTL0 */
|
||||||
|
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/
|
||||||
|
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||||
|
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||||
|
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||||
|
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||||
|
#define SPI_CTL0_LF BIT(7) /*!< lsb first mode */
|
||||||
|
#define SPI_CTL0_SWNSS BIT(8) /*!< nss pin selection in nss software mode */
|
||||||
|
#define SPI_CTL0_SWNSSEN BIT(9) /*!< nss software mode selection */
|
||||||
|
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||||
|
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||||
|
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||||
|
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||||
|
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||||
|
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||||
|
|
||||||
|
/* SPI_CTL1 */
|
||||||
|
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */
|
||||||
|
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */
|
||||||
|
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive nss output */
|
||||||
|
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||||
|
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||||
|
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||||
|
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||||
|
|
||||||
|
/* SPI_STAT */
|
||||||
|
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||||
|
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||||
|
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||||
|
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||||
|
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||||
|
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||||
|
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||||
|
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||||
|
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||||
|
|
||||||
|
/* SPI_DATA */
|
||||||
|
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||||
|
|
||||||
|
/* SPI_CRCPOLY */
|
||||||
|
#define SPI_CRCPOLY_CPR BITS(0,15) /*!< CRC polynomial register */
|
||||||
|
|
||||||
|
/* SPI_RCRC */
|
||||||
|
#define SPI_RCRC_RCR BITS(0,15) /*!< RX CRC register */
|
||||||
|
|
||||||
|
/* SPI_TCRC */
|
||||||
|
#define SPI_TCRC_TCR BITS(0,15) /*!< TX CRC register */
|
||||||
|
|
||||||
|
/* SPI_I2SCTL */
|
||||||
|
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||||
|
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||||
|
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||||
|
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||||
|
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||||
|
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||||
|
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||||
|
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||||
|
|
||||||
|
/* SPI_I2S_PSC */
|
||||||
|
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||||
|
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||||
|
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||||
|
|
||||||
|
/* SPI_SPI_QCTL(only SPI5) */
|
||||||
|
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||||
|
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* SPI and I2S parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t device_mode; /*!< SPI master or slave */
|
||||||
|
uint32_t trans_mode; /*!< SPI transtype */
|
||||||
|
uint32_t frame_size; /*!< SPI frame size */
|
||||||
|
uint32_t nss; /*!< SPI nss control by handware or software */
|
||||||
|
uint32_t endian; /*!< SPI big endian or little endian */
|
||||||
|
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||||
|
uint32_t prescale; /*!< SPI prescale factor */
|
||||||
|
} spi_parameter_struct;
|
||||||
|
|
||||||
|
/* SPI mode definitions */
|
||||||
|
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||||
|
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||||
|
|
||||||
|
/* SPI bidirectional transfer direction */
|
||||||
|
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||||
|
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||||
|
|
||||||
|
/* SPI transmit type */
|
||||||
|
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||||
|
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||||
|
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||||
|
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||||
|
|
||||||
|
/* SPI frame size */
|
||||||
|
#define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */
|
||||||
|
#define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */
|
||||||
|
|
||||||
|
/* SPI NSS control mode */
|
||||||
|
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI nss control by sofrware */
|
||||||
|
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI nss control by hardware */
|
||||||
|
|
||||||
|
/* SPI transmit way */
|
||||||
|
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||||
|
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||||
|
|
||||||
|
/* SPI clock polarity and phase */
|
||||||
|
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||||
|
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||||
|
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||||
|
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL|SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||||
|
|
||||||
|
/* SPI clock prescale factor */
|
||||||
|
#define CTL0_PSC(regval) (BITS(3,5)&((uint32_t)(regval)<<3))
|
||||||
|
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */
|
||||||
|
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */
|
||||||
|
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */
|
||||||
|
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */
|
||||||
|
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */
|
||||||
|
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */
|
||||||
|
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */
|
||||||
|
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */
|
||||||
|
|
||||||
|
/* I2S audio sample rate */
|
||||||
|
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||||
|
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||||
|
|
||||||
|
/* I2S frame format */
|
||||||
|
#define I2SCTL_DTLEN(regval) (BITS(1,2)&((uint32_t)(regval)<<1))
|
||||||
|
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||||
|
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||||
|
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||||
|
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2)|SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||||
|
|
||||||
|
/* I2S master clock output */
|
||||||
|
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||||
|
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||||
|
|
||||||
|
/* I2S operation mode */
|
||||||
|
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9)&((uint32_t)(regval)<<8))
|
||||||
|
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||||
|
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||||
|
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||||
|
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||||
|
|
||||||
|
/* I2S standard */
|
||||||
|
#define I2SCTL_I2SSTD(regval) (BITS(4,5)&((uint32_t)(regval)<<4))
|
||||||
|
#define I2S_STD_PHILIPS I2SCTL_I2SSTD(0) /*!< I2S philips standard */
|
||||||
|
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||||
|
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||||
|
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||||
|
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||||
|
|
||||||
|
/* I2S clock polarity */
|
||||||
|
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||||
|
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||||
|
|
||||||
|
/* SPI DMA constants definitions */
|
||||||
|
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||||
|
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||||
|
|
||||||
|
/* SPI CRC constants definitions */
|
||||||
|
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||||
|
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||||
|
|
||||||
|
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||||
|
#define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */
|
||||||
|
#define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */
|
||||||
|
#define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */
|
||||||
|
|
||||||
|
/* SPI/I2S interrupt flag constants definitions */
|
||||||
|
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||||
|
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||||
|
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||||
|
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||||
|
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||||
|
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||||
|
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||||
|
|
||||||
|
/* SPI/I2S flag definitions */
|
||||||
|
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||||
|
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||||
|
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||||
|
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||||
|
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||||
|
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||||
|
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||||
|
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||||
|
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||||
|
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||||
|
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||||
|
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||||
|
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||||
|
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* deinitialize SPI and I2S */
|
||||||
|
void spi_i2s_deinit(uint32_t spi_periph);
|
||||||
|
/* initialize the parameters of SPI struct with default values */
|
||||||
|
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||||
|
/* initialize SPI parameter */
|
||||||
|
void spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||||
|
/* enable SPI */
|
||||||
|
void spi_enable(uint32_t spi_periph);
|
||||||
|
/* disable SPI */
|
||||||
|
void spi_disable(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* initialize I2S parameter */
|
||||||
|
void i2s_init(uint32_t spi_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl);
|
||||||
|
/* configure I2S prescale */
|
||||||
|
void i2s_psc_config(uint32_t spi_periph, uint32_t i2s_audiosample, uint32_t i2s_frameformat, uint32_t i2s_mckout);
|
||||||
|
/* enable I2S */
|
||||||
|
void i2s_enable(uint32_t spi_periph);
|
||||||
|
/* disable I2S */
|
||||||
|
void i2s_disable(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* NSS functions */
|
||||||
|
/* enable SPI nss output */
|
||||||
|
void spi_nss_output_enable(uint32_t spi_periph);
|
||||||
|
/* disable SPI nss output */
|
||||||
|
void spi_nss_output_disable(uint32_t spi_periph);
|
||||||
|
/* SPI nss pin high level in software mode */
|
||||||
|
void spi_nss_internal_high(uint32_t spi_periph);
|
||||||
|
/* SPI nss pin low level in software mode */
|
||||||
|
void spi_nss_internal_low(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* SPI DMA functions */
|
||||||
|
/* enable SPI DMA send or receive */
|
||||||
|
void spi_dma_enable(uint32_t spi_periph, uint8_t spi_dma);
|
||||||
|
/* diable SPI DMA send or receive */
|
||||||
|
void spi_dma_disable(uint32_t spi_periph, uint8_t spi_dma);
|
||||||
|
|
||||||
|
/* SPI/I2S transfer configure functions */
|
||||||
|
/* configure SPI/I2S data frame format */
|
||||||
|
void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||||
|
/* SPI transmit data */
|
||||||
|
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||||
|
/* SPI receive data */
|
||||||
|
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||||
|
/* configure SPI bidirectional transfer direction */
|
||||||
|
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||||
|
/* configure i2s full duplex mode */
|
||||||
|
void i2s_full_duplex_mode_config(uint32_t i2s_add_periph, uint32_t i2s_mode, uint32_t i2s_standard, uint32_t i2s_ckpl, uint32_t i2s_frameformat);
|
||||||
|
/* clear TI Mode Format Error flag status */
|
||||||
|
void spi_i2s_format_error_clear(uint32_t spi_periph, uint32_t flag);
|
||||||
|
|
||||||
|
/* SPI CRC functions */
|
||||||
|
/* set SPI CRC polynomial */
|
||||||
|
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||||
|
/* get SPI CRC polynomial */
|
||||||
|
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||||
|
/* turn on SPI CRC function */
|
||||||
|
void spi_crc_on(uint32_t spi_periph);
|
||||||
|
/* turn off SPI CRC function */
|
||||||
|
void spi_crc_off(uint32_t spi_periph);
|
||||||
|
/* SPI next data is CRC value */
|
||||||
|
void spi_crc_next(uint32_t spi_periph);
|
||||||
|
/* get SPI CRC send value or receive value */
|
||||||
|
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t spi_crc);
|
||||||
|
/* clear SPI CRC error flag status */
|
||||||
|
void spi_crc_error_clear(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* SPI TI mode functions */
|
||||||
|
/* enable SPI TI mode */
|
||||||
|
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||||
|
/* disable SPI TI mode */
|
||||||
|
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* quad wire SPI functions */
|
||||||
|
/* enable quad wire SPI */
|
||||||
|
void spi_quad_enable(uint32_t spi_periph);
|
||||||
|
/* disable quad wire SPI */
|
||||||
|
void spi_quad_disable(uint32_t spi_periph);
|
||||||
|
/* enable quad wire SPI write */
|
||||||
|
void spi_quad_write_enable(uint32_t spi_periph);
|
||||||
|
/* enable quad wire SPI read */
|
||||||
|
void spi_quad_read_enable(uint32_t spi_periph);
|
||||||
|
|
||||||
|
/* flag and interrupt functions */
|
||||||
|
/* get SPI and I2S flag status */
|
||||||
|
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||||
|
/* enable SPI and I2S interrupt */
|
||||||
|
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
/* disable SPI and I2S interrupt */
|
||||||
|
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
/* get SPI and I2S interrupt status*/
|
||||||
|
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_SPI_H */
|
||||||
@@ -0,0 +1,179 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_syscfg.h
|
||||||
|
\brief definitions for the SYSCFG
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_SYSCFG_H
|
||||||
|
#define GD32F4XX_SYSCFG_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* SYSCFG definitions */
|
||||||
|
#define SYSCFG SYSCFG_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
|
||||||
|
#define SYSCFG_CFG1 REG32(SYSCFG + 0x04U) /*!< system configuration register 1 */
|
||||||
|
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
|
||||||
|
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
|
||||||
|
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
|
||||||
|
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
|
||||||
|
#define SYSCFG_CPSCTL REG32(SYSCFG + 0x20U) /*!< system I/O compensation control register */
|
||||||
|
|
||||||
|
/* SYSCFG_CFG0 bits definitions */
|
||||||
|
#define SYSCFG_CFG0_BOOT_MODE BITS(0,2) /*!< SYSCFG memory remap config */
|
||||||
|
#define SYSCFG_CFG0_FMC_SWP BIT(8) /*!< FMC memory swap config */
|
||||||
|
#define SYSCFG_CFG0_EXMC_SWP BITS(10,11) /*!< EXMC memory swap config */
|
||||||
|
|
||||||
|
/* SYSCFG_CFG1 bits definitions */
|
||||||
|
#define SYSCFG_CFG1_ENET_PHY_SEL BIT(23) /*!< Ethernet PHY selection config */
|
||||||
|
|
||||||
|
/* SYSCFG_EXTISS0 bits definitions */
|
||||||
|
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
|
||||||
|
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
|
||||||
|
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
|
||||||
|
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
|
||||||
|
|
||||||
|
/* SYSCFG_EXTISS1 bits definitions */
|
||||||
|
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
|
||||||
|
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
|
||||||
|
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
|
||||||
|
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
|
||||||
|
|
||||||
|
/* SYSCFG_EXTISS2 bits definitions */
|
||||||
|
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
|
||||||
|
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
|
||||||
|
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
|
||||||
|
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
|
||||||
|
|
||||||
|
/* SYSCFG_EXTISS3 bits definitions */
|
||||||
|
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
|
||||||
|
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
|
||||||
|
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
|
||||||
|
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
|
||||||
|
|
||||||
|
/* SYSCFG_CPSCTL bits definitions */
|
||||||
|
#define SYSCFG_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */
|
||||||
|
#define SYSCFG_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* boot mode definitions */
|
||||||
|
#define SYSCFG_BOOTMODE_FLASH ((uint8_t)0x00U) /*!< main flash memory remap */
|
||||||
|
#define SYSCFG_BOOTMODE_BOOTLOADER ((uint8_t)0x01U) /*!< boot loader remap */
|
||||||
|
#define SYSCFG_BOOTMODE_EXMC_SRAM ((uint8_t)0x02U) /*!< SRAM/NOR 0 and 1 of EXMC remap */
|
||||||
|
#define SYSCFG_BOOTMODE_SRAM ((uint8_t)0x03U) /*!< SRAM0 of on-chip SRAM remap */
|
||||||
|
#define SYSCFG_BOOTMODE_EXMC_SDRAM ((uint8_t)0x04U) /*!< SDRAM bank0 of EXMC remap */
|
||||||
|
|
||||||
|
/* FMC swap definitions */
|
||||||
|
#define SYSCFG_FMC_SWP_BANK0 ((uint32_t)0x00000000U) /*!< main flash Bank 0 is mapped at address 0x08000000 */
|
||||||
|
#define SYSCFG_FMC_SWP_BANK1 ((uint32_t)0x00000100U) /*!< main flash Bank 1 is mapped at address 0x08000000 */
|
||||||
|
|
||||||
|
/* EXMC swap enable/disable */
|
||||||
|
#define SYSCFG_EXMC_SWP_ENABLE ((uint32_t)0x00000400U) /*!< SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card */
|
||||||
|
#define SYSCFG_EXMC_SWP_DISABLE ((uint32_t)0x00000000U) /*!< no memory mapping swap */
|
||||||
|
|
||||||
|
/* EXTI source select definition */
|
||||||
|
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select GPIOx pin 0~3 */
|
||||||
|
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select GPIOx pin 4~7 */
|
||||||
|
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select GPIOx pin 8~11 */
|
||||||
|
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select GPIOx pin 12~15 */
|
||||||
|
|
||||||
|
/* EXTI source select mask bits definition */
|
||||||
|
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
|
||||||
|
|
||||||
|
/* EXTI source select jumping step definition */
|
||||||
|
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
|
||||||
|
|
||||||
|
/* EXTI source select moving step definition */
|
||||||
|
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP*((pin)%EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
|
||||||
|
|
||||||
|
/* EXTI source port definitions */
|
||||||
|
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOD ((uint8_t)0x03U) /*!< EXTI GPIOD configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOE ((uint8_t)0x04U) /*!< EXTI GPIOE configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOG ((uint8_t)0x06U) /*!< EXTI GPIOG configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOH ((uint8_t)0x07U) /*!< EXTI GPIOH configuration */
|
||||||
|
#define EXTI_SOURCE_GPIOI ((uint8_t)0x08U) /*!< EXTI GPIOI configuration */
|
||||||
|
|
||||||
|
/* EXTI source pin definitions */
|
||||||
|
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
|
||||||
|
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
|
||||||
|
|
||||||
|
/* ethernet PHY selection */
|
||||||
|
#define SYSCFG_ENET_PHY_MII ((uint32_t)0x00000000U) /*!< MII is selected for the Ethernet MAC */
|
||||||
|
#define SYSCFG_ENET_PHY_RMII ((uint32_t)0x00800000U) /*!< RMII is selected for the Ethernet MAC */
|
||||||
|
|
||||||
|
/* I/O compensation cell enable/disable */
|
||||||
|
#define SYSCFG_COMPENSATION_ENABLE ((uint32_t)0x00000001U) /*!< I/O compensation cell enable */
|
||||||
|
#define SYSCFG_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell disable */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* deinit syscfg module */
|
||||||
|
void syscfg_deinit(void);
|
||||||
|
|
||||||
|
/* function configuration */
|
||||||
|
/* configure the boot mode */
|
||||||
|
void syscfg_bootmode_config(uint8_t syscfg_bootmode);
|
||||||
|
/* configure FMC memory mapping swap */
|
||||||
|
void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap);
|
||||||
|
/* configure the EXMC swap */
|
||||||
|
void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap);
|
||||||
|
/* configure the GPIO pin as EXTI Line */
|
||||||
|
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
|
||||||
|
/* configure the PHY interface for the ethernet MAC */
|
||||||
|
void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface);
|
||||||
|
/* configure the I/O compensation cell */
|
||||||
|
void syscfg_compensation_config(uint32_t syscfg_compensation);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* check the I/O compensation cell is ready or not */
|
||||||
|
FlagStatus syscfg_flag_get(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_SYSCFG_H */
|
||||||
@@ -0,0 +1,776 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_timer.h
|
||||||
|
\brief definitions for the TIMER
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_TIMER_H
|
||||||
|
#define GD32F4XX_TIMER_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* TIMERx(x=0..13) definitions */
|
||||||
|
#define TIMER0 (TIMER_BASE + 0x00010000U)
|
||||||
|
#define TIMER1 (TIMER_BASE + 0x00000000U)
|
||||||
|
#define TIMER2 (TIMER_BASE + 0x00000400U)
|
||||||
|
#define TIMER3 (TIMER_BASE + 0x00000800U)
|
||||||
|
#define TIMER4 (TIMER_BASE + 0x00000C00U)
|
||||||
|
#define TIMER5 (TIMER_BASE + 0x00001000U)
|
||||||
|
#define TIMER6 (TIMER_BASE + 0x00001400U)
|
||||||
|
#define TIMER7 (TIMER_BASE + 0x00010400U)
|
||||||
|
#define TIMER8 (TIMER_BASE + 0x00014000U)
|
||||||
|
#define TIMER9 (TIMER_BASE + 0x00014400U)
|
||||||
|
#define TIMER10 (TIMER_BASE + 0x00014800U)
|
||||||
|
#define TIMER11 (TIMER_BASE + 0x00001800U)
|
||||||
|
#define TIMER12 (TIMER_BASE + 0x00001C00U)
|
||||||
|
#define TIMER13 (TIMER_BASE + 0x00002000U)
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
|
||||||
|
#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
|
||||||
|
#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
|
||||||
|
#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
|
||||||
|
#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
|
||||||
|
#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
|
||||||
|
#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
|
||||||
|
#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
|
||||||
|
#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
|
||||||
|
#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
|
||||||
|
#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
|
||||||
|
#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
|
||||||
|
#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
|
||||||
|
#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
|
||||||
|
#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
|
||||||
|
#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
|
||||||
|
#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
|
||||||
|
#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */
|
||||||
|
#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
|
||||||
|
#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
|
||||||
|
#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */
|
||||||
|
#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* TIMER_CTL0 */
|
||||||
|
#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
|
||||||
|
#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
|
||||||
|
#define TIMER_CTL0_UPS BIT(2) /*!< update source */
|
||||||
|
#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
|
||||||
|
#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
|
||||||
|
#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
|
||||||
|
#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
|
||||||
|
#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
|
||||||
|
|
||||||
|
/* TIMER_CTL1 */
|
||||||
|
#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */
|
||||||
|
#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
|
||||||
|
#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
|
||||||
|
#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
|
||||||
|
#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
|
||||||
|
#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
|
||||||
|
#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
|
||||||
|
#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
|
||||||
|
#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
|
||||||
|
#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
|
||||||
|
#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
|
||||||
|
#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
|
||||||
|
|
||||||
|
/* TIMER_SMCFG */
|
||||||
|
#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
|
||||||
|
#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
|
||||||
|
#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
|
||||||
|
#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
|
||||||
|
#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
|
||||||
|
#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
|
||||||
|
#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
|
||||||
|
|
||||||
|
/* TIMER_DMAINTEN */
|
||||||
|
#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */
|
||||||
|
#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
|
||||||
|
#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */
|
||||||
|
#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
|
||||||
|
|
||||||
|
/* TIMER_INTF */
|
||||||
|
#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
|
||||||
|
#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */
|
||||||
|
#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */
|
||||||
|
#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */
|
||||||
|
#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */
|
||||||
|
#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
|
||||||
|
#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
|
||||||
|
#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
|
||||||
|
#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */
|
||||||
|
#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */
|
||||||
|
#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */
|
||||||
|
#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */
|
||||||
|
|
||||||
|
/* TIMER_SWEVG */
|
||||||
|
#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
|
||||||
|
#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
|
||||||
|
#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
|
||||||
|
#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
|
||||||
|
#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
|
||||||
|
#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
|
||||||
|
#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
|
||||||
|
#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
|
||||||
|
|
||||||
|
/* TIMER_CHCTL0 */
|
||||||
|
/* output compare mode */
|
||||||
|
#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
|
||||||
|
#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
|
||||||
|
#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
|
||||||
|
#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */
|
||||||
|
#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
|
||||||
|
#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
|
||||||
|
#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
|
||||||
|
#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
|
||||||
|
#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */
|
||||||
|
#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
|
||||||
|
/* input capture mode */
|
||||||
|
#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
|
||||||
|
#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
|
||||||
|
#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
|
||||||
|
#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
|
||||||
|
|
||||||
|
/* TIMER_CHCTL1 */
|
||||||
|
/* output compare mode */
|
||||||
|
#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
|
||||||
|
#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
|
||||||
|
#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
|
||||||
|
#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */
|
||||||
|
#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
|
||||||
|
#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
|
||||||
|
#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
|
||||||
|
#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
|
||||||
|
#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */
|
||||||
|
#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
|
||||||
|
/* input capture mode */
|
||||||
|
#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
|
||||||
|
#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
|
||||||
|
#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
|
||||||
|
#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
|
||||||
|
|
||||||
|
/* TIMER_CHCTL2 */
|
||||||
|
#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */
|
||||||
|
#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */
|
||||||
|
#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
|
||||||
|
#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
|
||||||
|
#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */
|
||||||
|
#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */
|
||||||
|
#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
|
||||||
|
#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
|
||||||
|
#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */
|
||||||
|
#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */
|
||||||
|
#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
|
||||||
|
#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
|
||||||
|
#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */
|
||||||
|
#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */
|
||||||
|
|
||||||
|
/* TIMER_CNT */
|
||||||
|
#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */
|
||||||
|
#define TIMER_CNT_CNT32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) timer counter */
|
||||||
|
|
||||||
|
/* TIMER_PSC */
|
||||||
|
#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
|
||||||
|
|
||||||
|
/* TIMER_CAR */
|
||||||
|
#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */
|
||||||
|
#define TIMER_CAR_CARL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) counter auto reload value */
|
||||||
|
|
||||||
|
/* TIMER_CREP */
|
||||||
|
#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
|
||||||
|
|
||||||
|
/* TIMER_CH0CV */
|
||||||
|
#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */
|
||||||
|
#define TIMER_CH0CV_CH0VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 0 */
|
||||||
|
|
||||||
|
/* TIMER_CH1CV */
|
||||||
|
#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */
|
||||||
|
#define TIMER_CH1CV_CH1VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 1 */
|
||||||
|
|
||||||
|
/* TIMER_CH2CV */
|
||||||
|
#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */
|
||||||
|
#define TIMER_CH2CV_CH2VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 2 */
|
||||||
|
|
||||||
|
/* TIMER_CH3CV */
|
||||||
|
#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */
|
||||||
|
#define TIMER_CH3CV_CH3VAL32 BITS(0,31) /*!< 32 bit(TIMER1,TIMER4) capture/compare value of channel 3 */
|
||||||
|
|
||||||
|
/* TIMER_CCHP */
|
||||||
|
#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
|
||||||
|
#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
|
||||||
|
#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
|
||||||
|
#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
|
||||||
|
#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
|
||||||
|
#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
|
||||||
|
#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
|
||||||
|
#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
|
||||||
|
|
||||||
|
/* TIMER_DMACFG */
|
||||||
|
#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
|
||||||
|
#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
|
||||||
|
|
||||||
|
/* TIMER_DMATB */
|
||||||
|
#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
|
||||||
|
|
||||||
|
/* TIMER_IRMP */
|
||||||
|
#define TIMER1_IRMP_ITI1_RMP BITS(10,11) /*!< TIMER1 internal trigger input 1 remap */
|
||||||
|
#define TIMER4_IRMP_CI3_RMP BITS(6,7) /*!< TIMER4 channel 3 input remap */
|
||||||
|
#define TIMER10_IRMP_ITI1_RMP BITS(0,1) /*!< TIMER10 internal trigger input 1 remap */
|
||||||
|
|
||||||
|
/* TIMER_CFG */
|
||||||
|
#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */
|
||||||
|
#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* TIMER init parameter struct definitions*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t prescaler; /*!< prescaler value */
|
||||||
|
uint16_t alignedmode; /*!< aligned mode */
|
||||||
|
uint16_t counterdirection; /*!< counter direction */
|
||||||
|
uint16_t clockdivision; /*!< clock division value */
|
||||||
|
uint32_t period; /*!< period value */
|
||||||
|
uint8_t repetitioncounter; /*!< the counter repetition value */
|
||||||
|
}timer_parameter_struct;
|
||||||
|
|
||||||
|
/* break parameter struct definitions*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t runoffstate; /*!< run mode off-state */
|
||||||
|
uint16_t ideloffstate; /*!< idle mode off-state */
|
||||||
|
uint16_t deadtime; /*!< dead time */
|
||||||
|
uint16_t breakpolarity; /*!< break polarity */
|
||||||
|
uint16_t outputautostate; /*!< output automatic enable */
|
||||||
|
uint16_t protectmode; /*!< complementary register protect control */
|
||||||
|
uint16_t breakstate; /*!< break enable */
|
||||||
|
}timer_break_parameter_struct;
|
||||||
|
|
||||||
|
/* channel output parameter struct definitions */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t outputstate; /*!< channel output state */
|
||||||
|
uint16_t outputnstate; /*!< channel complementary output state */
|
||||||
|
uint16_t ocpolarity; /*!< channel output polarity */
|
||||||
|
uint16_t ocnpolarity; /*!< channel complementary output polarity */
|
||||||
|
uint16_t ocidlestate; /*!< idle state of channel output */
|
||||||
|
uint16_t ocnidlestate; /*!< idle state of channel complementary output */
|
||||||
|
}timer_oc_parameter_struct;
|
||||||
|
|
||||||
|
/* channel input parameter struct definitions */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t icpolarity; /*!< channel input polarity */
|
||||||
|
uint16_t icselection; /*!< channel input mode selection */
|
||||||
|
uint16_t icprescaler; /*!< channel input capture prescaler */
|
||||||
|
uint16_t icfilter; /*!< channel input capture filter control */
|
||||||
|
}timer_ic_parameter_struct;
|
||||||
|
|
||||||
|
/* TIMER interrupt enable or disable */
|
||||||
|
#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
|
||||||
|
#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
|
||||||
|
#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
|
||||||
|
#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
|
||||||
|
#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
|
||||||
|
#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
|
||||||
|
#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
|
||||||
|
#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
|
||||||
|
|
||||||
|
/* TIMER flag */
|
||||||
|
#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
|
||||||
|
#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
|
||||||
|
#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
|
||||||
|
#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
|
||||||
|
#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
|
||||||
|
#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
|
||||||
|
#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
|
||||||
|
#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
|
||||||
|
#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
|
||||||
|
#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
|
||||||
|
#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
|
||||||
|
#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
|
||||||
|
|
||||||
|
/* TIMER interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
|
||||||
|
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
|
||||||
|
|
||||||
|
/* TIMER DMA source enable */
|
||||||
|
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
|
||||||
|
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
|
||||||
|
#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */
|
||||||
|
#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */
|
||||||
|
#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */
|
||||||
|
#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */
|
||||||
|
#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */
|
||||||
|
|
||||||
|
/* channel DMA request source selection */
|
||||||
|
#define TIMER_DMAREQUEST_UPDATEEVENT ((uint8_t)0x00U) /*!< DMA request of channel y is sent when update event occurs */
|
||||||
|
#define TIMER_DMAREQUEST_CHANNELEVENT ((uint8_t)0x01U) /*!< DMA request of channel y is sent when channel y event occurs */
|
||||||
|
|
||||||
|
/* DMA access base address */
|
||||||
|
#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
|
||||||
|
#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
|
||||||
|
#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
|
||||||
|
#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
|
||||||
|
#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
|
||||||
|
#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
|
||||||
|
#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
|
||||||
|
#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
|
||||||
|
#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
|
||||||
|
#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
|
||||||
|
#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
|
||||||
|
#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
|
||||||
|
#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
|
||||||
|
#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
|
||||||
|
#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
|
||||||
|
#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
|
||||||
|
#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
|
||||||
|
#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
|
||||||
|
#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
|
||||||
|
#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
|
||||||
|
#define TIMER_DMACFG_DMATA_DMATB DMACFG_DMATA(19) /*!< DMA transfer address is TIMER_DMATB */
|
||||||
|
|
||||||
|
/* DMA access burst length */
|
||||||
|
#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
|
||||||
|
#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
|
||||||
|
#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
|
||||||
|
#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
|
||||||
|
|
||||||
|
/* TIMER software event generation source */
|
||||||
|
#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
|
||||||
|
#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
|
||||||
|
#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
|
||||||
|
#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
|
||||||
|
#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
|
||||||
|
#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
|
||||||
|
#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
|
||||||
|
#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
|
||||||
|
|
||||||
|
/* center-aligned mode selection */
|
||||||
|
#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
|
||||||
|
#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
|
||||||
|
#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
|
||||||
|
#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
|
||||||
|
#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
|
||||||
|
|
||||||
|
/* TIMER prescaler reload mode */
|
||||||
|
#define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */
|
||||||
|
#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */
|
||||||
|
|
||||||
|
/* count direction */
|
||||||
|
#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
|
||||||
|
#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */
|
||||||
|
|
||||||
|
/* specify division ratio between TIMER clock and dead-time and sampling clock */
|
||||||
|
#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||||
|
#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */
|
||||||
|
#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */
|
||||||
|
#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
|
||||||
|
|
||||||
|
/* single pulse mode */
|
||||||
|
#define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */
|
||||||
|
#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */
|
||||||
|
|
||||||
|
/* update source */
|
||||||
|
#define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */
|
||||||
|
#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
|
||||||
|
|
||||||
|
/* run mode off-state configure */
|
||||||
|
#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||||
|
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */
|
||||||
|
|
||||||
|
/* idle mode off-state configure */
|
||||||
|
#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||||
|
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
|
||||||
|
|
||||||
|
/* break input polarity */
|
||||||
|
#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
|
||||||
|
#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */
|
||||||
|
|
||||||
|
/* output automatic enable */
|
||||||
|
#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */
|
||||||
|
#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
|
||||||
|
|
||||||
|
/* complementary register protect control */
|
||||||
|
#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||||
|
#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
|
||||||
|
#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
|
||||||
|
#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
|
||||||
|
#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
|
||||||
|
|
||||||
|
/* break input enable */
|
||||||
|
#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */
|
||||||
|
#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
|
||||||
|
|
||||||
|
/* TIMER channel n(n=0,1,2,3) */
|
||||||
|
#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */
|
||||||
|
#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */
|
||||||
|
#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */
|
||||||
|
#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */
|
||||||
|
|
||||||
|
/* channel enable state*/
|
||||||
|
#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */
|
||||||
|
#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */
|
||||||
|
|
||||||
|
/* channel complementary output enable state*/
|
||||||
|
#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
|
||||||
|
#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
|
||||||
|
|
||||||
|
/* channel output polarity */
|
||||||
|
#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
|
||||||
|
#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
|
||||||
|
|
||||||
|
/* channel complementary output polarity */
|
||||||
|
#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
|
||||||
|
#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
|
||||||
|
|
||||||
|
/* idle state of channel output */
|
||||||
|
#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */
|
||||||
|
#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */
|
||||||
|
|
||||||
|
/* idle state of channel complementary output */
|
||||||
|
#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
|
||||||
|
#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
|
||||||
|
|
||||||
|
/* channel output compare mode */
|
||||||
|
#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */
|
||||||
|
#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */
|
||||||
|
#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */
|
||||||
|
#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */
|
||||||
|
#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
|
||||||
|
#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
|
||||||
|
#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
|
||||||
|
#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
|
||||||
|
|
||||||
|
/* channel output compare shadow enable */
|
||||||
|
#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
|
||||||
|
#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
|
||||||
|
|
||||||
|
/* channel output compare fast enable */
|
||||||
|
#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */
|
||||||
|
#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */
|
||||||
|
|
||||||
|
/* channel output compare clear enable */
|
||||||
|
#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
|
||||||
|
#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
|
||||||
|
|
||||||
|
/* channel control shadow register update control */
|
||||||
|
#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */
|
||||||
|
#define TIMER_UPDATECTL_CCUTRI ((uint32_t)0x00000001U) /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */
|
||||||
|
|
||||||
|
/* channel input capture polarity */
|
||||||
|
#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
|
||||||
|
#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
|
||||||
|
#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */
|
||||||
|
|
||||||
|
/* TIMER input capture selection */
|
||||||
|
#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
|
||||||
|
#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
|
||||||
|
#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
|
||||||
|
|
||||||
|
/* channel input capture prescaler */
|
||||||
|
#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
|
||||||
|
#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
|
||||||
|
#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/
|
||||||
|
#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
|
||||||
|
|
||||||
|
/* trigger selection */
|
||||||
|
#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||||
|
#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
|
||||||
|
#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */
|
||||||
|
|
||||||
|
/* master mode control */
|
||||||
|
#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||||
|
#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */
|
||||||
|
#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
|
||||||
|
#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
|
||||||
|
|
||||||
|
/* slave mode control */
|
||||||
|
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
|
||||||
|
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
|
||||||
|
#define TIMER_QUAD_DECODER_MODE0 SMCFG_SMC(1) /*!< quadrature decoder mode 0 */
|
||||||
|
#define TIMER_QUAD_DECODER_MODE1 SMCFG_SMC(2) /*!< quadrature decoder mode 1 */
|
||||||
|
#define TIMER_QUAD_DECODER_MODE2 SMCFG_SMC(3) /*!< quadrature decoder mode 2 */
|
||||||
|
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
|
||||||
|
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
|
||||||
|
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
|
||||||
|
#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
|
||||||
|
|
||||||
|
/* master slave mode selection */
|
||||||
|
#define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */
|
||||||
|
#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */
|
||||||
|
|
||||||
|
/* external trigger prescaler */
|
||||||
|
#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
|
||||||
|
#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
|
||||||
|
#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
|
||||||
|
#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
|
||||||
|
#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
|
||||||
|
|
||||||
|
/* external trigger polarity */
|
||||||
|
#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
|
||||||
|
#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */
|
||||||
|
|
||||||
|
/* channel 0 trigger input selection */
|
||||||
|
#define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */
|
||||||
|
#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */
|
||||||
|
|
||||||
|
/* timer1 internal trigger input1 remap */
|
||||||
|
#define TIMER1_IRMP(regval) (BITS(10, 11) & ((uint32_t)(regval) << 10U))
|
||||||
|
#define TIMER1_ITI1_RMP_TIMER7_TRGO TIMER1_IRMP(0) /*!< timer1 internal trigger input 1 remap to TIMER7_TRGO */
|
||||||
|
#define TIMER1_ITI1_RMP_ETHERNET_PTP TIMER1_IRMP(1) /*!< timer1 internal trigger input 1 remap to ethernet PTP */
|
||||||
|
#define TIMER1_ITI1_RMP_USB_FS_SOF TIMER1_IRMP(2) /*!< timer1 internal trigger input 1 remap to USB FS SOF */
|
||||||
|
#define TIMER1_ITI1_RMP_USB_HS_SOF TIMER1_IRMP(3) /*!< timer1 internal trigger input 1 remap to USB HS SOF */
|
||||||
|
|
||||||
|
/* timer4 channel 3 input remap */
|
||||||
|
#define TIMER4_IRMP(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U))
|
||||||
|
#define TIMER4_CI3_RMP_GPIO TIMER4_IRMP(0) /*!< timer4 channel 3 input remap to GPIO pin */
|
||||||
|
#define TIMER4_CI3_RMP_IRC32K TIMER4_IRMP(1) /*!< timer4 channel 3 input remap to IRC32K */
|
||||||
|
#define TIMER4_CI3_RMP_LXTAL TIMER4_IRMP(2) /*!< timer4 channel 3 input remap to LXTAL */
|
||||||
|
#define TIMER4_CI3_RMP_RTC_WAKEUP_INT TIMER4_IRMP(3) /*!< timer4 channel 3 input remap to RTC wakeup interrupt */
|
||||||
|
|
||||||
|
/* timer10 internal trigger input1 remap */
|
||||||
|
#define TIMER10_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U))
|
||||||
|
#define TIMER10_ITI1_RMP_GPIO TIMER10_IRMP(0) /*!< timer10 internal trigger input1 remap based on GPIO setting */
|
||||||
|
#define TIMER10_ITI1_RMP_RTC_HXTAL_DIV TIMER10_IRMP(2) /*!< timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register) */
|
||||||
|
|
||||||
|
/* timerx(x=0,1,2,13,14,15,16) write cc register selection */
|
||||||
|
#define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */
|
||||||
|
#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
|
||||||
|
|
||||||
|
/* the output value selection */
|
||||||
|
#define TIMER_OUTSEL_ENABLE ((uint16_t)0x0001U) /*!< output value selection enable */
|
||||||
|
#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* TIMER timebase*/
|
||||||
|
/* deinit a TIMER */
|
||||||
|
void timer_deinit(uint32_t timer_periph);
|
||||||
|
/* initialize TIMER init parameter struct */
|
||||||
|
void timer_struct_para_init(timer_parameter_struct* initpara);
|
||||||
|
/* initialize TIMER counter */
|
||||||
|
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
|
||||||
|
/* enable a TIMER */
|
||||||
|
void timer_enable(uint32_t timer_periph);
|
||||||
|
/* disable a TIMER */
|
||||||
|
void timer_disable(uint32_t timer_periph);
|
||||||
|
/* enable the auto reload shadow function */
|
||||||
|
void timer_auto_reload_shadow_enable(uint32_t timer_periph);
|
||||||
|
/* disable the auto reload shadow function */
|
||||||
|
void timer_auto_reload_shadow_disable(uint32_t timer_periph);
|
||||||
|
/* enable the update event */
|
||||||
|
void timer_update_event_enable(uint32_t timer_periph);
|
||||||
|
/* disable the update event */
|
||||||
|
void timer_update_event_disable(uint32_t timer_periph);
|
||||||
|
/* set TIMER counter alignment mode */
|
||||||
|
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
|
||||||
|
/* set TIMER counter up direction */
|
||||||
|
void timer_counter_up_direction(uint32_t timer_periph);
|
||||||
|
/* set TIMER counter down direction */
|
||||||
|
void timer_counter_down_direction(uint32_t timer_periph);
|
||||||
|
/* configure TIMER prescaler */
|
||||||
|
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
|
||||||
|
/* configure TIMER repetition register value */
|
||||||
|
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
|
||||||
|
/* configure TIMER autoreload register value */
|
||||||
|
void timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload);
|
||||||
|
/* configure TIMER counter register value */
|
||||||
|
void timer_counter_value_config(uint32_t timer_periph , uint32_t counter);
|
||||||
|
/* read TIMER counter value */
|
||||||
|
uint32_t timer_counter_read(uint32_t timer_periph);
|
||||||
|
/* read TIMER prescaler value */
|
||||||
|
uint16_t timer_prescaler_read(uint32_t timer_periph);
|
||||||
|
/* configure TIMER single pulse mode */
|
||||||
|
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
|
||||||
|
/* configure TIMER update source */
|
||||||
|
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
|
||||||
|
|
||||||
|
/* timer DMA and event*/
|
||||||
|
/* enable the TIMER DMA */
|
||||||
|
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
|
||||||
|
/* disable the TIMER DMA */
|
||||||
|
void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
|
||||||
|
/* channel DMA request source selection */
|
||||||
|
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
|
||||||
|
/* configure the TIMER DMA transfer */
|
||||||
|
void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth);
|
||||||
|
/* software generate events */
|
||||||
|
void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
|
||||||
|
|
||||||
|
/* TIMER channel complementary protection */
|
||||||
|
/* initialize TIMER break parameter struct */
|
||||||
|
void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
|
||||||
|
/* configure TIMER break function */
|
||||||
|
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
|
||||||
|
/* enable TIMER break function */
|
||||||
|
void timer_break_enable(uint32_t timer_periph);
|
||||||
|
/* disable TIMER break function */
|
||||||
|
void timer_break_disable(uint32_t timer_periph);
|
||||||
|
/* enable TIMER output automatic function */
|
||||||
|
void timer_automatic_output_enable(uint32_t timer_periph);
|
||||||
|
/* disable TIMER output automatic function */
|
||||||
|
void timer_automatic_output_disable(uint32_t timer_periph);
|
||||||
|
/* enable or disable TIMER primary output function */
|
||||||
|
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||||
|
/* enable or disable channel capture/compare control shadow register */
|
||||||
|
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||||
|
/* configure TIMER channel control shadow register update control */
|
||||||
|
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
|
||||||
|
|
||||||
|
/* TIMER channel output */
|
||||||
|
/* initialize TIMER channel output parameter struct */
|
||||||
|
void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
|
||||||
|
/* configure TIMER channel output function */
|
||||||
|
void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara);
|
||||||
|
/* configure TIMER channel output compare mode */
|
||||||
|
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode);
|
||||||
|
/* configure TIMER channel output pulse value */
|
||||||
|
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
|
||||||
|
/* configure TIMER channel output shadow function */
|
||||||
|
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
|
||||||
|
/* configure TIMER channel output fast function */
|
||||||
|
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
|
||||||
|
/* configure TIMER channel output clear function */
|
||||||
|
void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear);
|
||||||
|
/* configure TIMER channel output polarity */
|
||||||
|
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
|
||||||
|
/* configure TIMER channel complementary output polarity */
|
||||||
|
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
|
||||||
|
/* configure TIMER channel enable state */
|
||||||
|
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
|
||||||
|
/* configure TIMER channel complementary output enable state */
|
||||||
|
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
|
||||||
|
|
||||||
|
/* TIMER channel input */
|
||||||
|
/* initialize TIMER channel input parameter struct */
|
||||||
|
void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
|
||||||
|
/* configure TIMER input capture parameter */
|
||||||
|
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
|
||||||
|
/* configure TIMER channel input capture prescaler value */
|
||||||
|
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
|
||||||
|
/* read TIMER channel capture compare register value */
|
||||||
|
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
|
||||||
|
/* configure TIMER input pwm capture function */
|
||||||
|
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
|
||||||
|
/* configure TIMER hall sensor mode */
|
||||||
|
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
|
||||||
|
|
||||||
|
/* TIMER master and slave */
|
||||||
|
/* select TIMER input trigger source */
|
||||||
|
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
|
||||||
|
/* select TIMER master mode output trigger source */
|
||||||
|
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
|
||||||
|
/* select TIMER slave mode */
|
||||||
|
void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode);
|
||||||
|
/* configure TIMER master slave mode */
|
||||||
|
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
|
||||||
|
/* configure TIMER external trigger input */
|
||||||
|
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||||
|
/* configure TIMER quadrature decoder mode */
|
||||||
|
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
|
||||||
|
/* configure TIMER internal clock mode */
|
||||||
|
void timer_internal_clock_config(uint32_t timer_periph);
|
||||||
|
/* configure TIMER the internal trigger as external clock input */
|
||||||
|
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
|
||||||
|
/* configure TIMER the external trigger as external clock input */
|
||||||
|
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter);
|
||||||
|
/* configure TIMER the external clock mode 0 */
|
||||||
|
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||||
|
/* configure TIMER the external clock mode 1 */
|
||||||
|
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||||
|
/* disable TIMER the external clock mode 1 */
|
||||||
|
void timer_external_clock_mode1_disable(uint32_t timer_periph);
|
||||||
|
/* configure TIMER channel remap function */
|
||||||
|
void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap);
|
||||||
|
|
||||||
|
/* TIMER configure */
|
||||||
|
/* configure TIMER write CHxVAL register selection */
|
||||||
|
void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
|
||||||
|
/* configure TIMER output value selection */
|
||||||
|
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
|
||||||
|
|
||||||
|
/* TIMER interrupt and flag*/
|
||||||
|
/* get TIMER flags */
|
||||||
|
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
|
||||||
|
/* clear TIMER flags */
|
||||||
|
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
|
||||||
|
/* enable the TIMER interrupt */
|
||||||
|
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* disable the TIMER interrupt */
|
||||||
|
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* get timer interrupt flag */
|
||||||
|
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
/* clear TIMER interrupt flag */
|
||||||
|
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_TIMER_H */
|
||||||
@@ -0,0 +1,373 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_tli.h
|
||||||
|
\brief definitions for the TLI
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_TLI_H
|
||||||
|
#define GD32F4XX_TLI_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* TLI definitions */
|
||||||
|
#define TLI TLI_BASE /*!< TLI base address */
|
||||||
|
/* TLI layer definitions */
|
||||||
|
#define LAYER0 TLI_BASE /*!< TLI layer0 base address */
|
||||||
|
#define LAYER1 (TLI_BASE + 0x00000080U) /*!< TLI layer1 base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define TLI_SPSZ REG32(TLI + 0x00000008U) /*!< TLI synchronous pulse size register */
|
||||||
|
#define TLI_BPSZ REG32(TLI + 0x0000000CU) /*!< TLI back-porch size register */
|
||||||
|
#define TLI_ASZ REG32(TLI + 0x00000010U) /*!< TLI active size register */
|
||||||
|
#define TLI_TSZ REG32(TLI + 0x00000014U) /*!< TLI total size register */
|
||||||
|
#define TLI_CTL REG32(TLI + 0x00000018U) /*!< TLI control register */
|
||||||
|
#define TLI_RL REG32(TLI + 0x00000024U) /*!< TLI reload Layer register */
|
||||||
|
#define TLI_BGC REG32(TLI + 0x0000002CU) /*!< TLI background color register */
|
||||||
|
#define TLI_INTEN REG32(TLI + 0x00000034U) /*!< TLI interrupt enable register */
|
||||||
|
#define TLI_INTF REG32(TLI + 0x00000038U) /*!< TLI interrupt flag register */
|
||||||
|
#define TLI_INTC REG32(TLI + 0x0000003CU) /*!< TLI interrupt flag clear register */
|
||||||
|
#define TLI_LM REG32(TLI + 0x00000040U) /*!< TLI line mark register */
|
||||||
|
#define TLI_CPPOS REG32(TLI + 0x00000044U) /*!< TLI current pixel position register */
|
||||||
|
#define TLI_STAT REG32(TLI + 0x00000048U) /*!< TLI status register */
|
||||||
|
#define TLI_LxCTL(layerx) REG32((layerx) + 0x00000084U) /*!< TLI layer x control register */
|
||||||
|
#define TLI_LxHPOS(layerx) REG32((layerx) + 0x00000088U) /*!< TLI layer x horizontal position parameters register */
|
||||||
|
#define TLI_LxVPOS(layerx) REG32((layerx) + 0x0000008CU) /*!< TLI layer x vertical position parameters register */
|
||||||
|
#define TLI_LxCKEY(layerx) REG32((layerx) + 0x00000090U) /*!< TLI layer x color key register */
|
||||||
|
#define TLI_LxPPF(layerx) REG32((layerx) + 0x00000094U) /*!< TLI layer x packeted pixel format register */
|
||||||
|
#define TLI_LxSA(layerx) REG32((layerx) + 0x00000098U) /*!< TLI layer x specified alpha register */
|
||||||
|
#define TLI_LxDC(layerx) REG32((layerx) + 0x0000009CU) /*!< TLI layer x default color register */
|
||||||
|
#define TLI_LxBLEND(layerx) REG32((layerx) + 0x000000A0U) /*!< TLI layer x blending register */
|
||||||
|
#define TLI_LxFBADDR(layerx) REG32((layerx) + 0x000000ACU) /*!< TLI layer x frame base address register */
|
||||||
|
#define TLI_LxFLLEN(layerx) REG32((layerx) + 0x000000B0U) /*!< TLI layer x frame line length register */
|
||||||
|
#define TLI_LxFTLN(layerx) REG32((layerx) + 0x000000B4U) /*!< TLI layer x frame total line number register */
|
||||||
|
#define TLI_LxLUT(layerx) REG32((layerx) + 0x000000C4U) /*!< TLI layer x look up table register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* TLI_SPSZ */
|
||||||
|
#define TLI_SPSZ_VPSZ BITS(0,11) /*!< size of the vertical synchronous pulse */
|
||||||
|
#define TLI_SPSZ_HPSZ BITS(16,27) /*!< size of the horizontal synchronous pulse */
|
||||||
|
|
||||||
|
/* TLI_BPSZ */
|
||||||
|
#define TLI_BPSZ_VBPSZ BITS(0,11) /*!< size of the vertical back porch plus synchronous pulse */
|
||||||
|
#define TLI_BPSZ_HBPSZ BITS(16,27) /*!< size of the horizontal back porch plus synchronous pulse */
|
||||||
|
|
||||||
|
/* TLI_ASZ */
|
||||||
|
#define TLI_ASZ_VASZ BITS(0,11) /*!< size of the vertical active area width plus back porch and synchronous pulse */
|
||||||
|
#define TLI_ASZ_HASZ BITS(16,27) /*!< size of the horizontal active area width plus back porch and synchronous pulse */
|
||||||
|
|
||||||
|
/* TLI_TSZ */
|
||||||
|
#define TLI_TSZ_VTSZ BITS(0,11) /*!< vertical total size of the display, including active area, back porch, synchronous pulse and front porch */
|
||||||
|
#define TLI_TSZ_HTSZ BITS(16,27) /*!< horizontal total size of the display, including active area, back porch, synchronous pulse and front porch */
|
||||||
|
|
||||||
|
/* TLI_CTL */
|
||||||
|
#define TLI_CTL_TLIEN BIT(0) /*!< TLI enable bit */
|
||||||
|
#define TLI_CTL_BDB BITS(4,6) /*!< blue channel dither bits number */
|
||||||
|
#define TLI_CTL_GDB BITS(8,10) /*!< green channel dither bits number */
|
||||||
|
#define TLI_CTL_RDB BITS(12,14) /*!< red channel dither bits number */
|
||||||
|
#define TLI_CTL_DFEN BIT(16) /*!< dither function enable */
|
||||||
|
#define TLI_CTL_CLKPS BIT(28) /*!< pixel clock polarity selection */
|
||||||
|
#define TLI_CTL_DEPS BIT(29) /*!< data enable polarity selection */
|
||||||
|
#define TLI_CTL_VPPS BIT(30) /*!< vertical pulse polarity selection */
|
||||||
|
#define TLI_CTL_HPPS BIT(31) /*!< horizontal pulse polarity selection */
|
||||||
|
|
||||||
|
/* TLI_RL */
|
||||||
|
#define TLI_RL_RQR BIT(0) /*!< request reload */
|
||||||
|
#define TLI_RL_FBR BIT(1) /*!< frame blank reload */
|
||||||
|
|
||||||
|
/* TLI_BGC */
|
||||||
|
#define TLI_BGC_BVB BITS(0,7) /*!< background value blue */
|
||||||
|
#define TLI_BGC_BVG BITS(8,15) /*!< background value green */
|
||||||
|
#define TLI_BGC_BVR BITS(16,23) /*!< background value red */
|
||||||
|
|
||||||
|
/* TLI_INTEN */
|
||||||
|
#define TLI_INTEN_LMIE BIT(0) /*!< line mark interrupt enable */
|
||||||
|
#define TLI_INTEN_FEIE BIT(1) /*!< FIFO error interrupt enable */
|
||||||
|
#define TLI_INTEN_TEIE BIT(2) /*!< transaction error interrupt enable */
|
||||||
|
#define TLI_INTEN_LCRIE BIT(3) /*!< layer configuration reloaded interrupt enable */
|
||||||
|
|
||||||
|
/* TLI_INTF */
|
||||||
|
#define TLI_INTF_LMF BIT(0) /*!< line mark flag */
|
||||||
|
#define TLI_INTF_FEF BIT(1) /*!< FIFO error flag */
|
||||||
|
#define TLI_INTF_TEF BIT(2) /*!< transaction error flag */
|
||||||
|
#define TLI_INTF_LCRF BIT(3) /*!< layer configuration reloaded flag */
|
||||||
|
|
||||||
|
/* TLI_INTC */
|
||||||
|
#define TLI_INTC_LMC BIT(0) /*!< line mark flag clear */
|
||||||
|
#define TLI_INTC_FEC BIT(1) /*!< FIFO error flag clear */
|
||||||
|
#define TLI_INTC_TEC BIT(2) /*!< transaction error flag clear */
|
||||||
|
#define TLI_INTC_LCRC BIT(3) /*!< layer configuration reloaded flag clear */
|
||||||
|
|
||||||
|
/* TLI_LM */
|
||||||
|
#define TLI_LM_LM BITS(0,10) /*!< line mark value */
|
||||||
|
|
||||||
|
/* TLI_CPPOS */
|
||||||
|
#define TLI_CPPOS_VPOS BITS(0,15) /*!< vertical position */
|
||||||
|
#define TLI_CPPOS_HPOS BITS(16,31) /*!< horizontal position */
|
||||||
|
|
||||||
|
/* TLI_STAT */
|
||||||
|
#define TLI_STAT_VDE BIT(0) /*!< current VDE status */
|
||||||
|
#define TLI_STAT_HDE BIT(1) /*!< current HDE status */
|
||||||
|
#define TLI_STAT_VS BIT(2) /*!< current VS status of the TLI */
|
||||||
|
#define TLI_STAT_HS BIT(3) /*!< current HS status of the TLI */
|
||||||
|
|
||||||
|
/* TLI_LxCTL */
|
||||||
|
#define TLI_LxCTL_LEN BIT(0) /*!< layer enable */
|
||||||
|
#define TLI_LxCTL_CKEYEN BIT(1) /*!< color keying enable */
|
||||||
|
#define TLI_LxCTL_LUTEN BIT(4) /*!< LUT enable */
|
||||||
|
|
||||||
|
/* TLI_LxHPOS */
|
||||||
|
#define TLI_LxHPOS_WLP BITS(0,11) /*!< window left position */
|
||||||
|
#define TLI_LxHPOS_WRP BITS(16,27) /*!< window right position */
|
||||||
|
|
||||||
|
/* TLI_LxVPOS */
|
||||||
|
#define TLI_LxVPOS_WTP BITS(0,11) /*!< window top position */
|
||||||
|
#define TLI_LxVPOS_WBP BITS(16,27) /*!< window bottom position */
|
||||||
|
|
||||||
|
/* TLI_LxCKEY */
|
||||||
|
#define TLI_LxCKEY_CKEYB BITS(0,7) /*!< color key blue */
|
||||||
|
#define TLI_LxCKEY_CKEYG BITS(8,15) /*!< color key green */
|
||||||
|
#define TLI_LxCKEY_CKEYR BITS(16,23) /*!< color key red */
|
||||||
|
|
||||||
|
/* TLI_LxPPF */
|
||||||
|
#define TLI_LxPPF_PPF BITS(0,2) /*!< packeted pixel format */
|
||||||
|
|
||||||
|
/* TLI_LxSA */
|
||||||
|
#define TLI_LxSA_SA BITS(0,7) /*!< specified alpha */
|
||||||
|
|
||||||
|
/* TLI_LxDC */
|
||||||
|
#define TLI_LxDC_DCB BITS(0,7) /*!< the default color blue */
|
||||||
|
#define TLI_LxDC_DCG BITS(8,15) /*!< the default color green */
|
||||||
|
#define TLI_LxDC_DCR BITS(16,23) /*!< the default color red */
|
||||||
|
#define TLI_LxDC_DCA BITS(24,31) /*!< the default color alpha */
|
||||||
|
|
||||||
|
/* TLI_LxBLEND */
|
||||||
|
#define TLI_LxBLEND_ACF2 BITS(0,2) /*!< alpha calculation factor 2 of blending method */
|
||||||
|
#define TLI_LxBLEND_ACF1 BITS(8,10) /*!< alpha calculation factor 1 of blending method */
|
||||||
|
|
||||||
|
/* TLI_LxFBADDR */
|
||||||
|
#define TLI_LxFBADDR_FBADD BITS(0,31) /*!< frame buffer base address */
|
||||||
|
|
||||||
|
/* TLI_LxFLLEN */
|
||||||
|
#define TLI_LxFLLEN_FLL BITS(0,13) /*!< frame line length */
|
||||||
|
#define TLI_LxFLLEN_STDOFF BITS(16,29) /*!< frame buffer stride offset */
|
||||||
|
|
||||||
|
/* TLI_LxFTLN */
|
||||||
|
#define TLI_LxFTLN_FTLN BITS(0,10) /*!< frame total line number */
|
||||||
|
|
||||||
|
/* TLI_LxLUT */
|
||||||
|
#define TLI_LxLUT_TB BITS(0,7) /*!< blue channel of a LUT entry */
|
||||||
|
#define TLI_LxLUT_TG BITS(8,15) /*!< green channel of a LUT entry */
|
||||||
|
#define TLI_LxLUT_TR BITS(16,23) /*!< red channel of a LUT entry */
|
||||||
|
#define TLI_LxLUT_TADD BITS(24,31) /*!< look up table write address */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* TLI parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint16_t synpsz_vpsz; /*!< size of the vertical synchronous pulse */
|
||||||
|
uint16_t synpsz_hpsz; /*!< size of the horizontal synchronous pulse */
|
||||||
|
uint16_t backpsz_vbpsz; /*!< size of the vertical back porch plus synchronous pulse */
|
||||||
|
uint16_t backpsz_hbpsz; /*!< size of the horizontal back porch plus synchronous pulse */
|
||||||
|
uint32_t activesz_vasz; /*!< size of the vertical active area width plus back porch and synchronous pulse */
|
||||||
|
uint32_t activesz_hasz; /*!< size of the horizontal active area width plus back porch and synchronous pulse */
|
||||||
|
uint32_t totalsz_vtsz; /*!< vertical total size of the display */
|
||||||
|
uint32_t totalsz_htsz; /*!< horizontal total size of the display */
|
||||||
|
uint32_t backcolor_red; /*!< background value red */
|
||||||
|
uint32_t backcolor_green; /*!< background value green */
|
||||||
|
uint32_t backcolor_blue; /*!< background value blue */
|
||||||
|
uint32_t signalpolarity_hs; /*!< horizontal pulse polarity selection */
|
||||||
|
uint32_t signalpolarity_vs; /*!< vertical pulse polarity selection */
|
||||||
|
uint32_t signalpolarity_de; /*!< data enable polarity selection */
|
||||||
|
uint32_t signalpolarity_pixelck; /*!< pixel clock polarity selection */
|
||||||
|
} tli_parameter_struct;
|
||||||
|
|
||||||
|
/* TLI layer parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint16_t layer_window_rightpos; /*!< window right position */
|
||||||
|
uint16_t layer_window_leftpos; /*!< window left position */
|
||||||
|
uint16_t layer_window_bottompos; /*!< window bottom position */
|
||||||
|
uint16_t layer_window_toppos; /*!< window top position */
|
||||||
|
uint32_t layer_ppf; /*!< packeted pixel format */
|
||||||
|
uint8_t layer_sa; /*!< specified alpha */
|
||||||
|
uint8_t layer_default_alpha; /*!< the default color alpha */
|
||||||
|
uint8_t layer_default_red; /*!< the default color red */
|
||||||
|
uint8_t layer_default_green; /*!< the default color green */
|
||||||
|
uint8_t layer_default_blue; /*!< the default color blue */
|
||||||
|
uint32_t layer_acf1; /*!< alpha calculation factor 1 of blending method */
|
||||||
|
uint32_t layer_acf2; /*!< alpha calculation factor 2 of blending method */
|
||||||
|
uint32_t layer_frame_bufaddr; /*!< frame buffer base address */
|
||||||
|
uint16_t layer_frame_buf_stride_offset; /*!< frame buffer stride offset */
|
||||||
|
uint16_t layer_frame_line_length; /*!< frame line length */
|
||||||
|
uint16_t layer_frame_total_line_number; /*!< frame total line number */
|
||||||
|
} tli_layer_parameter_struct;
|
||||||
|
|
||||||
|
/* TLI layer LUT parameter struct definitions */
|
||||||
|
typedef struct {
|
||||||
|
uint32_t layer_table_addr; /*!< look up table write address */
|
||||||
|
uint8_t layer_lut_channel_red; /*!< red channel of a LUT entry */
|
||||||
|
uint8_t layer_lut_channel_green; /*!< green channel of a LUT entry */
|
||||||
|
uint8_t layer_lut_channel_blue; /*!< blue channel of a LUT entry */
|
||||||
|
} tli_layer_lut_parameter_struct;
|
||||||
|
|
||||||
|
/* packeted pixel format */
|
||||||
|
typedef enum {
|
||||||
|
LAYER_PPF_ARGB8888 = 0U, /*!< layerx pixel format ARGB8888 */
|
||||||
|
LAYER_PPF_RGB888, /*!< layerx pixel format RGB888 */
|
||||||
|
LAYER_PPF_RGB565, /*!< layerx pixel format RGB565 */
|
||||||
|
LAYER_PPF_ARGB1555, /*!< layerx pixel format ARGB1555 */
|
||||||
|
LAYER_PPF_ARGB4444, /*!< layerx pixel format ARGB4444 */
|
||||||
|
LAYER_PPF_L8, /*!< layerx pixel format L8 */
|
||||||
|
LAYER_PPF_AL44, /*!< layerx pixel format AL44 */
|
||||||
|
LAYER_PPF_AL88 /*!< layerx pixel format AL88 */
|
||||||
|
} tli_layer_ppf_enum;
|
||||||
|
|
||||||
|
/* TLI flags */
|
||||||
|
#define TLI_FLAG_VDE TLI_STAT_VDE /*!< current VDE status */
|
||||||
|
#define TLI_FLAG_HDE TLI_STAT_HDE /*!< current HDE status */
|
||||||
|
#define TLI_FLAG_VS TLI_STAT_VS /*!< current VS status of the TLI */
|
||||||
|
#define TLI_FLAG_HS TLI_STAT_HS /*!< current HS status of the TLI */
|
||||||
|
#define TLI_FLAG_LM BIT(0) | BIT(31) /*!< line mark interrupt flag */
|
||||||
|
#define TLI_FLAG_FE BIT(1) | BIT(31) /*!< FIFO error interrupt flag */
|
||||||
|
#define TLI_FLAG_TE BIT(2) | BIT(31) /*!< transaction error interrupt flag */
|
||||||
|
#define TLI_FLAG_LCR BIT(3) | BIT(31) /*!< layer configuration reloaded interrupt flag */
|
||||||
|
|
||||||
|
/* TLI interrupt enable or disable */
|
||||||
|
#define TLI_INT_LM BIT(0) /*!< line mark interrupt */
|
||||||
|
#define TLI_INT_FE BIT(1) /*!< FIFO error interrupt */
|
||||||
|
#define TLI_INT_TE BIT(2) /*!< transaction error interrupt */
|
||||||
|
#define TLI_INT_LCR BIT(3) /*!< layer configuration reloaded interrupt */
|
||||||
|
|
||||||
|
/* TLI interrupt flag */
|
||||||
|
#define TLI_INT_FLAG_LM BIT(0) /*!< line mark interrupt flag */
|
||||||
|
#define TLI_INT_FLAG_FE BIT(1) /*!< FIFO error interrupt flag */
|
||||||
|
#define TLI_INT_FLAG_TE BIT(2) /*!< transaction error interrupt flag */
|
||||||
|
#define TLI_INT_FLAG_LCR BIT(3) /*!< layer configuration reloaded interrupt flag */
|
||||||
|
|
||||||
|
/* layer reload configure */
|
||||||
|
#define TLI_FRAME_BLANK_RELOAD_EN ((uint8_t)0x00U) /*!< the layer configuration will be reloaded at frame blank */
|
||||||
|
#define TLI_REQUEST_RELOAD_EN ((uint8_t)0x01U) /*!< the layer configuration will be reloaded after this bit sets */
|
||||||
|
|
||||||
|
/* dither function */
|
||||||
|
#define TLI_DITHER_DISABLE ((uint8_t)0x00U) /*!< dither function disable */
|
||||||
|
#define TLI_DITHER_ENABLE ((uint8_t)0x01U) /*!< dither function enable */
|
||||||
|
|
||||||
|
/* horizontal pulse polarity selection */
|
||||||
|
#define TLI_HSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< horizontal synchronous pulse active low */
|
||||||
|
#define TLI_HSYN_ACTLIVE_HIGHT TLI_CTL_HPPS /*!< horizontal synchronous pulse active high */
|
||||||
|
#define TLI_HSYN_ACTLIVE_HIGH TLI_HSYN_ACTLIVE_HIGHT /*!< horizontal synchronous pulse active high */
|
||||||
|
|
||||||
|
/* vertical pulse polarity selection */
|
||||||
|
#define TLI_VSYN_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< vertical synchronous pulse active low */
|
||||||
|
#define TLI_VSYN_ACTLIVE_HIGHT TLI_CTL_VPPS /*!< vertical synchronous pulse active high */
|
||||||
|
#define TLI_VSYN_ACTLIVE_HIGH TLI_VSYN_ACTLIVE_HIGHT /*!< vertical synchronous pulse active high */
|
||||||
|
|
||||||
|
/* pixel clock polarity selection */
|
||||||
|
#define TLI_PIXEL_CLOCK_TLI ((uint32_t)0x00000000U) /*!< pixel clock is TLI clock */
|
||||||
|
#define TLI_PIXEL_CLOCK_INVERTEDTLI TLI_CTL_CLKPS /*!< pixel clock is inverted TLI clock */
|
||||||
|
|
||||||
|
/* data enable polarity selection */
|
||||||
|
#define TLI_DE_ACTLIVE_LOW ((uint32_t)0x00000000U) /*!< data enable active low */
|
||||||
|
#define TLI_DE_ACTLIVE_HIGHT TLI_CTL_DEPS /*!< data enable active high */
|
||||||
|
#define TLI_DE_ACTLIVE_HIGH TLI_DE_ACTLIVE_HIGHT /*!< data enable active high */
|
||||||
|
|
||||||
|
/* alpha calculation factor 1 of blending method */
|
||||||
|
#define LxBLEND_ACF1(regval) (BITS(8,10) & ((uint32_t)(regval)<<8))
|
||||||
|
#define LAYER_ACF1_SA LxBLEND_ACF1(4) /*!< normalization specified alpha */
|
||||||
|
#define LAYER_ACF1_PASA LxBLEND_ACF1(6) /*!< normalization pixel alpha * normalization specified alpha */
|
||||||
|
|
||||||
|
/* alpha calculation factor 2 of blending method */
|
||||||
|
#define LxBLEND_ACF2(regval) (BITS(0,2) & ((uint32_t)(regval)))
|
||||||
|
#define LAYER_ACF2_SA LxBLEND_ACF2(5) /*!< normalization specified alpha */
|
||||||
|
#define LAYER_ACF2_PASA LxBLEND_ACF2(7) /*!< normalization pixel alpha * normalization specified alpha */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions, TLI enable or disable, TLI reload mode configuration */
|
||||||
|
/* deinitialize TLI registers */
|
||||||
|
void tli_deinit(void);
|
||||||
|
/* initialize the parameters of TLI parameter structure with the default values, it is suggested
|
||||||
|
that call this function after a tli_parameter_struct structure is defined */
|
||||||
|
void tli_struct_para_init(tli_parameter_struct *tli_struct);
|
||||||
|
/* initialize TLI */
|
||||||
|
void tli_init(tli_parameter_struct *tli_struct);
|
||||||
|
/* configure TLI dither function */
|
||||||
|
void tli_dither_config(uint8_t dither_stat);
|
||||||
|
/* enable TLI */
|
||||||
|
void tli_enable(void);
|
||||||
|
/* disable TLI */
|
||||||
|
void tli_disable(void);
|
||||||
|
/* configurate TLI reload mode */
|
||||||
|
void tli_reload_config(uint8_t reload_mod);
|
||||||
|
|
||||||
|
/* TLI layer configuration functions */
|
||||||
|
/* initialize the parameters of TLI layer structure with the default values, it is suggested
|
||||||
|
that call this function after a tli_layer_parameter_struct structure is defined */
|
||||||
|
void tli_layer_struct_para_init(tli_layer_parameter_struct *layer_struct);
|
||||||
|
/* initialize TLI layer */
|
||||||
|
void tli_layer_init(uint32_t layerx, tli_layer_parameter_struct *layer_struct);
|
||||||
|
/* reconfigure window position */
|
||||||
|
void tli_layer_window_offset_modify(uint32_t layerx, uint16_t offset_x, uint16_t offset_y);
|
||||||
|
/* initialize the parameters of TLI layer LUT structure with the default values, it is suggested
|
||||||
|
that call this function after a tli_layer_lut_parameter_struct structure is defined */
|
||||||
|
void tli_lut_struct_para_init(tli_layer_lut_parameter_struct *lut_struct);
|
||||||
|
/* initialize TLI layer LUT */
|
||||||
|
void tli_lut_init(uint32_t layerx, tli_layer_lut_parameter_struct *lut_struct);
|
||||||
|
/* initialize TLI layer color key */
|
||||||
|
void tli_color_key_init(uint32_t layerx, uint8_t redkey, uint8_t greenkey, uint8_t bluekey);
|
||||||
|
/* enable TLI layer */
|
||||||
|
void tli_layer_enable(uint32_t layerx);
|
||||||
|
/* disable TLI layer */
|
||||||
|
void tli_layer_disable(uint32_t layerx);
|
||||||
|
/* enable TLI layer color keying */
|
||||||
|
void tli_color_key_enable(uint32_t layerx);
|
||||||
|
/* disable TLI layer color keying */
|
||||||
|
void tli_color_key_disable(uint32_t layerx);
|
||||||
|
/* enable TLI layer LUT */
|
||||||
|
void tli_lut_enable(uint32_t layerx);
|
||||||
|
/* disable TLI layer LUT */
|
||||||
|
void tli_lut_disable(uint32_t layerx);
|
||||||
|
|
||||||
|
/* set line mark value */
|
||||||
|
void tli_line_mark_set(uint16_t line_num);
|
||||||
|
/* get current displayed position */
|
||||||
|
uint32_t tli_current_pos_get(void);
|
||||||
|
|
||||||
|
/* flag and interrupt functions */
|
||||||
|
/* enable TLI interrupt */
|
||||||
|
void tli_interrupt_enable(uint32_t int_flag);
|
||||||
|
/* disable TLI interrupt */
|
||||||
|
void tli_interrupt_disable(uint32_t int_flag);
|
||||||
|
/* get TLI interrupt flag */
|
||||||
|
FlagStatus tli_interrupt_flag_get(uint32_t int_flag);
|
||||||
|
/* clear TLI interrupt flag */
|
||||||
|
void tli_interrupt_flag_clear(uint32_t int_flag);
|
||||||
|
/* get TLI flag or state in TLI_INTF register or TLI_STAT register */
|
||||||
|
FlagStatus tli_flag_get(uint32_t flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_TLI_H */
|
||||||
@@ -0,0 +1,100 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_trng.h
|
||||||
|
\brief definitions for the TRNG
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_TRNG_H
|
||||||
|
#define GD32F4XX_TRNG_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* TRNG definitions */
|
||||||
|
#define TRNG TRNG_BASE
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define TRNG_CTL REG32(TRNG + 0x00000000U) /*!< control register */
|
||||||
|
#define TRNG_STAT REG32(TRNG + 0x00000004U) /*!< status register */
|
||||||
|
#define TRNG_DATA REG32(TRNG + 0x00000008U) /*!< data register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* TRNG_CTL */
|
||||||
|
#define TRNG_CTL_TRNGEN BIT(2) /*!< TRNG enable bit */
|
||||||
|
#define TRNG_CTL_TRNGIE BIT(3) /*!< interrupt enable bit */
|
||||||
|
|
||||||
|
/* TRNG_STAT */
|
||||||
|
#define TRNG_STAT_DRDY BIT(0) /*!< random data ready status bit */
|
||||||
|
#define TRNG_STAT_CECS BIT(1) /*!< clock error current status */
|
||||||
|
#define TRNG_STAT_SECS BIT(2) /*!< seed error current status */
|
||||||
|
#define TRNG_STAT_CEIF BIT(5) /*!< clock error interrupt flag */
|
||||||
|
#define TRNG_STAT_SEIF BIT(6) /*!< seed error interrupt flag */
|
||||||
|
|
||||||
|
/* TRNG_DATA */
|
||||||
|
#define TRNG_DATA_TRNGDATA BITS(0,31) /*!< 32-Bit Random data */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* TRNG status flag */
|
||||||
|
typedef enum {
|
||||||
|
TRNG_FLAG_DRDY = TRNG_STAT_DRDY, /*!< random Data ready status */
|
||||||
|
TRNG_FLAG_CECS = TRNG_STAT_CECS, /*!< clock error current status */
|
||||||
|
TRNG_FLAG_SECS = TRNG_STAT_SECS /*!< seed error current status */
|
||||||
|
} trng_flag_enum;
|
||||||
|
|
||||||
|
/* TRNG inerrupt flag */
|
||||||
|
typedef enum {
|
||||||
|
TRNG_INT_FLAG_CEIF = TRNG_STAT_CEIF, /*!< clock error interrupt flag */
|
||||||
|
TRNG_INT_FLAG_SEIF = TRNG_STAT_SEIF /*!< seed error interrupt flag */
|
||||||
|
} trng_int_flag_enum;
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* reset TRNG */
|
||||||
|
void trng_deinit(void);
|
||||||
|
/* enable TRNG */
|
||||||
|
void trng_enable(void);
|
||||||
|
/* disable TRNG */
|
||||||
|
void trng_disable(void);
|
||||||
|
/* get the true random data */
|
||||||
|
uint32_t trng_get_true_random_data(void);
|
||||||
|
|
||||||
|
/* interrupt & flag functions */
|
||||||
|
/* enable TRNG interrupt */
|
||||||
|
void trng_interrupt_enable(void);
|
||||||
|
/* disable TRNG interrupt */
|
||||||
|
void trng_interrupt_disable(void);
|
||||||
|
/* get TRNG flag status */
|
||||||
|
FlagStatus trng_flag_get(trng_flag_enum flag);
|
||||||
|
/* get TRNG interrupt flag status */
|
||||||
|
FlagStatus trng_interrupt_flag_get(trng_int_flag_enum int_flag);
|
||||||
|
/* clear TRNG interrupt flag status */
|
||||||
|
void trng_interrupt_flag_clear(trng_int_flag_enum int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_TRNG_H */
|
||||||
@@ -0,0 +1,489 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_usart.h
|
||||||
|
\brief definitions for the USART
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_USART_H
|
||||||
|
#define GD32F4XX_USART_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* USARTx(x=0,1,2,5)/UARTx(x=3,4,6,7) definitions */
|
||||||
|
#define USART1 USART_BASE /*!< USART1 base address */
|
||||||
|
#define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */
|
||||||
|
#define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */
|
||||||
|
#define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */
|
||||||
|
#define UART6 (USART_BASE+0x00003400U) /*!< UART6 base address */
|
||||||
|
#define UART7 (USART_BASE+0x00003800U) /*!< UART7 base address */
|
||||||
|
#define USART0 (USART_BASE+0x0000CC00U) /*!< USART0 base address */
|
||||||
|
#define USART5 (USART_BASE+0x0000D000U) /*!< USART5 base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */
|
||||||
|
#define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */
|
||||||
|
#define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */
|
||||||
|
#define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */
|
||||||
|
#define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */
|
||||||
|
#define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */
|
||||||
|
#define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */
|
||||||
|
#define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */
|
||||||
|
#define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */
|
||||||
|
#define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */
|
||||||
|
#define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* USARTx_STAT0 */
|
||||||
|
#define USART_STAT0_PERR BIT(0) /*!< parity error flag */
|
||||||
|
#define USART_STAT0_FERR BIT(1) /*!< frame error flag */
|
||||||
|
#define USART_STAT0_NERR BIT(2) /*!< noise error flag */
|
||||||
|
#define USART_STAT0_ORERR BIT(3) /*!< overrun error */
|
||||||
|
#define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */
|
||||||
|
#define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */
|
||||||
|
#define USART_STAT0_TC BIT(6) /*!< transmission complete */
|
||||||
|
#define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */
|
||||||
|
#define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */
|
||||||
|
#define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */
|
||||||
|
|
||||||
|
/* USARTx_DATA */
|
||||||
|
#define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */
|
||||||
|
|
||||||
|
/* USARTx_BAUD */
|
||||||
|
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */
|
||||||
|
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */
|
||||||
|
|
||||||
|
/* USARTx_CTL0 */
|
||||||
|
#define USART_CTL0_SBKCMD BIT(0) /*!< send break command */
|
||||||
|
#define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */
|
||||||
|
#define USART_CTL0_REN BIT(2) /*!< enable receiver */
|
||||||
|
#define USART_CTL0_TEN BIT(3) /*!< enable transmitter */
|
||||||
|
#define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */
|
||||||
|
#define USART_CTL0_RBNEIE BIT(5) /*!< enable read data buffer not empty interrupt and overrun error interrupt */
|
||||||
|
#define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */
|
||||||
|
#define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter buffer empty interrupt */
|
||||||
|
#define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */
|
||||||
|
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
||||||
|
#define USART_CTL0_PCEN BIT(10) /*!< enable parity check function */
|
||||||
|
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
||||||
|
#define USART_CTL0_WL BIT(12) /*!< word length */
|
||||||
|
#define USART_CTL0_UEN BIT(13) /*!< enable USART */
|
||||||
|
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
|
||||||
|
|
||||||
|
/* USARTx_CTL1 */
|
||||||
|
#define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */
|
||||||
|
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
||||||
|
#define USART_CTL1_LBDIE BIT(6) /*!< enable LIN break detected interrupt */
|
||||||
|
#define USART_CTL1_CLEN BIT(8) /*!< CK length */
|
||||||
|
#define USART_CTL1_CPH BIT(9) /*!< CK phase */
|
||||||
|
#define USART_CTL1_CPL BIT(10) /*!< CK polarity */
|
||||||
|
#define USART_CTL1_CKEN BIT(11) /*!< enable CK pin */
|
||||||
|
#define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */
|
||||||
|
#define USART_CTL1_LMEN BIT(14) /*!< enable LIN mode */
|
||||||
|
|
||||||
|
/* USARTx_CTL2 */
|
||||||
|
#define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt */
|
||||||
|
#define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */
|
||||||
|
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
||||||
|
#define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */
|
||||||
|
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
||||||
|
#define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */
|
||||||
|
#define USART_CTL2_DENR BIT(6) /*!< enable DMA request for reception */
|
||||||
|
#define USART_CTL2_DENT BIT(7) /*!< enable DMA request for transmission */
|
||||||
|
#define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */
|
||||||
|
#define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */
|
||||||
|
#define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */
|
||||||
|
#define USART_CTL2_OSB BIT(11) /*!< one sample bit method */
|
||||||
|
|
||||||
|
/* USARTx_GP */
|
||||||
|
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
|
||||||
|
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
||||||
|
|
||||||
|
/* USARTx_CTL3 */
|
||||||
|
#define USART_CTL3_RTEN BIT(0) /*!< enable receiver timeout */
|
||||||
|
#define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */
|
||||||
|
#define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */
|
||||||
|
#define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */
|
||||||
|
#define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */
|
||||||
|
#define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */
|
||||||
|
#define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */
|
||||||
|
#define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */
|
||||||
|
|
||||||
|
/* USARTx_RT */
|
||||||
|
#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
|
||||||
|
#define USART_RT_BL BITS(24,31) /*!< block length */
|
||||||
|
|
||||||
|
/* USARTx_STAT1 */
|
||||||
|
#define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */
|
||||||
|
#define USART_STAT1_EBF BIT(12) /*!< end of block flag */
|
||||||
|
#define USART_STAT1_BSY BIT(16) /*!< busy flag */
|
||||||
|
|
||||||
|
/* USARTx_CHC */
|
||||||
|
#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */
|
||||||
|
#define USART_CHC_PCM BIT(1) /*!< parity check coherence mode */
|
||||||
|
#define USART_CHC_BCM BIT(2) /*!< break frame coherence mode */
|
||||||
|
#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
/* define the USART bit position and its register index offset */
|
||||||
|
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||||
|
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)))
|
||||||
|
#define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||||
|
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||||
|
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||||
|
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
|
||||||
|
#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16)
|
||||||
|
|
||||||
|
/* register offset */
|
||||||
|
#define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */
|
||||||
|
#define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */
|
||||||
|
#define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */
|
||||||
|
#define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */
|
||||||
|
#define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */
|
||||||
|
#define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */
|
||||||
|
#define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */
|
||||||
|
|
||||||
|
/* USART flags */
|
||||||
|
typedef enum {
|
||||||
|
/* flags in STAT0 register */
|
||||||
|
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */
|
||||||
|
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
||||||
|
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */
|
||||||
|
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */
|
||||||
|
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */
|
||||||
|
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */
|
||||||
|
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */
|
||||||
|
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */
|
||||||
|
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */
|
||||||
|
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */
|
||||||
|
/* flags in STAT1 register */
|
||||||
|
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */
|
||||||
|
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */
|
||||||
|
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */
|
||||||
|
/* flags in CHC register */
|
||||||
|
USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */
|
||||||
|
} usart_flag_enum;
|
||||||
|
|
||||||
|
/* USART interrupt flags */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt flags in CTL0 register */
|
||||||
|
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
||||||
|
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
||||||
|
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
|
||||||
|
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
|
||||||
|
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
|
||||||
|
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
|
||||||
|
/* interrupt flags in CTL1 register */
|
||||||
|
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
|
||||||
|
/* interrupt flags in CTL2 register */
|
||||||
|
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
|
||||||
|
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
|
||||||
|
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
|
||||||
|
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
|
||||||
|
/* interrupt flags in CTL3 register */
|
||||||
|
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */
|
||||||
|
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */
|
||||||
|
} usart_interrupt_flag_enum;
|
||||||
|
|
||||||
|
/* USART interrupt flags */
|
||||||
|
typedef enum {
|
||||||
|
/* interrupt in CTL0 register */
|
||||||
|
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
||||||
|
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
||||||
|
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
|
||||||
|
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
|
||||||
|
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
|
||||||
|
/* interrupt in CTL1 register */
|
||||||
|
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
|
||||||
|
/* interrupt in CTL2 register */
|
||||||
|
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
|
||||||
|
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
|
||||||
|
/* interrupt in CTL3 register */
|
||||||
|
USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< interrupt enable bit of end of block event */
|
||||||
|
USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< interrupt enable bit of receive timeout event */
|
||||||
|
} usart_interrupt_enum;
|
||||||
|
|
||||||
|
/* configure USART invert */
|
||||||
|
typedef enum {
|
||||||
|
/* data bit level inversion */
|
||||||
|
USART_DINV_ENABLE, /*!< data bit level inversion */
|
||||||
|
USART_DINV_DISABLE, /*!< data bit level not inversion */
|
||||||
|
/* TX pin level inversion */
|
||||||
|
USART_TXPIN_ENABLE, /*!< TX pin level inversion */
|
||||||
|
USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
|
||||||
|
/* RX pin level inversion */
|
||||||
|
USART_RXPIN_ENABLE, /*!< RX pin level inversion */
|
||||||
|
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
|
||||||
|
} usart_invert_enum;
|
||||||
|
|
||||||
|
/* configure USART receiver */
|
||||||
|
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||||
|
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
||||||
|
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
||||||
|
|
||||||
|
/* configure USART transmitter */
|
||||||
|
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
||||||
|
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
||||||
|
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
||||||
|
|
||||||
|
/* USART parity bits definitions */
|
||||||
|
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||||
|
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
|
||||||
|
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
|
||||||
|
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
|
||||||
|
|
||||||
|
/* USART wakeup method in mute mode */
|
||||||
|
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||||
|
#define USART_WM_IDLE CTL0_WM(0) /*!< idle Line */
|
||||||
|
#define USART_WM_ADDR CTL0_WM(1) /*!< address mask */
|
||||||
|
|
||||||
|
/* USART word length definitions */
|
||||||
|
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
|
||||||
|
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
|
||||||
|
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
|
||||||
|
|
||||||
|
/* USART oversampling mode definitions */
|
||||||
|
#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
|
||||||
|
#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< 16 bits */
|
||||||
|
#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< 8 bits */
|
||||||
|
|
||||||
|
/* USART stop bits definitions */
|
||||||
|
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||||
|
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
|
||||||
|
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
|
||||||
|
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
|
||||||
|
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
|
||||||
|
|
||||||
|
/* USART LIN break frame length */
|
||||||
|
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
|
||||||
|
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */
|
||||||
|
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */
|
||||||
|
|
||||||
|
/* USART CK length */
|
||||||
|
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||||
|
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */
|
||||||
|
#define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */
|
||||||
|
|
||||||
|
/* USART clock phase */
|
||||||
|
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||||
|
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
|
||||||
|
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
|
||||||
|
|
||||||
|
/* USART clock polarity */
|
||||||
|
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
|
||||||
|
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
||||||
|
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
||||||
|
|
||||||
|
/* configure USART DMA request for receive */
|
||||||
|
#define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
||||||
|
#define USART_RECEIVE_DMA_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */
|
||||||
|
#define USART_RECEIVE_DMA_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */
|
||||||
|
|
||||||
|
/* configure USART DMA request for transmission */
|
||||||
|
#define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||||
|
#define USART_TRANSMIT_DMA_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */
|
||||||
|
#define USART_TRANSMIT_DMA_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */
|
||||||
|
|
||||||
|
/* configure USART RTS */
|
||||||
|
#define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||||
|
#define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< enable RTS */
|
||||||
|
#define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< disable RTS */
|
||||||
|
|
||||||
|
/* configure USART CTS */
|
||||||
|
#define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||||
|
#define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< enable CTS */
|
||||||
|
#define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< disable CTS */
|
||||||
|
|
||||||
|
/* configure USART one sample bit method */
|
||||||
|
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||||
|
#define USART_OSB_1bit CTL2_OSB(1) /*!< 1 bit */
|
||||||
|
#define USART_OSB_3bit CTL2_OSB(0) /*!< 3 bits */
|
||||||
|
|
||||||
|
/* enable USART IrDA low-power */
|
||||||
|
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||||
|
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
||||||
|
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
||||||
|
|
||||||
|
/* USART data is transmitted/received with the LSB/MSB first */
|
||||||
|
#define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||||
|
#define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */
|
||||||
|
#define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */
|
||||||
|
|
||||||
|
/* break frame coherence mode */
|
||||||
|
#define CHC_BCM(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||||
|
#define USART_BCM_NONE CHC_BCM(0) /*!< no parity error is detected */
|
||||||
|
#define USART_BCM_EN CHC_BCM(1) /*!< parity error is detected */
|
||||||
|
|
||||||
|
/* USART parity check coherence mode */
|
||||||
|
#define CHC_PCM(regval) (BIT(1) & ((uint32_t)(regval) << 1))
|
||||||
|
#define USART_PCM_NONE CHC_PCM(0) /*!< not check parity */
|
||||||
|
#define USART_PCM_EN CHC_PCM(1) /*!< check the parity */
|
||||||
|
|
||||||
|
/* USART hardware flow control coherence mode */
|
||||||
|
#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0))
|
||||||
|
#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */
|
||||||
|
#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* initialization functions */
|
||||||
|
/* reset USART */
|
||||||
|
void usart_deinit(uint32_t usart_periph);
|
||||||
|
/* configure usart baud rate value */
|
||||||
|
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
|
||||||
|
/* configure usart parity function */
|
||||||
|
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
|
||||||
|
/* configure usart word length */
|
||||||
|
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
|
||||||
|
/* configure usart stop bit length */
|
||||||
|
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
|
||||||
|
/* enable usart */
|
||||||
|
void usart_enable(uint32_t usart_periph);
|
||||||
|
/* disable usart */
|
||||||
|
void usart_disable(uint32_t usart_periph);
|
||||||
|
/* configure USART transmitter */
|
||||||
|
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
|
||||||
|
/* configure USART receiver */
|
||||||
|
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
|
||||||
|
|
||||||
|
/* USART normal mode communication */
|
||||||
|
/* data is transmitted/received with the LSB/MSB first */
|
||||||
|
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
|
||||||
|
/* configure USART inverted */
|
||||||
|
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
|
||||||
|
/* configure the USART oversample mode */
|
||||||
|
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
|
||||||
|
/* configure sample bit method */
|
||||||
|
void usart_sample_bit_config(uint32_t usart_periph, uint32_t obsm);
|
||||||
|
/* enable receiver timeout */
|
||||||
|
void usart_receiver_timeout_enable(uint32_t usart_periph);
|
||||||
|
/* disable receiver timeout */
|
||||||
|
void usart_receiver_timeout_disable(uint32_t usart_periph);
|
||||||
|
/* configure receiver timeout threshold */
|
||||||
|
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
|
||||||
|
/* USART transmit data function */
|
||||||
|
void usart_data_transmit(uint32_t usart_periph, uint16_t data);
|
||||||
|
/* USART receive data function */
|
||||||
|
uint16_t usart_data_receive(uint32_t usart_periph);
|
||||||
|
|
||||||
|
/* multi-processor communication */
|
||||||
|
/* configure address of the USART */
|
||||||
|
void usart_address_config(uint32_t usart_periph, uint8_t addr);
|
||||||
|
/* enable mute mode */
|
||||||
|
void usart_mute_mode_enable(uint32_t usart_periph);
|
||||||
|
/* disable mute mode */
|
||||||
|
void usart_mute_mode_disable(uint32_t usart_periph);
|
||||||
|
/* configure wakeup method in mute mode */
|
||||||
|
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmehtod);
|
||||||
|
|
||||||
|
/* LIN mode communication */
|
||||||
|
/* enable LIN mode */
|
||||||
|
void usart_lin_mode_enable(uint32_t usart_periph);
|
||||||
|
/* disable LIN mode */
|
||||||
|
void usart_lin_mode_disable(uint32_t usart_periph);
|
||||||
|
/* LIN break detection length */
|
||||||
|
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
|
||||||
|
/* send break frame */
|
||||||
|
void usart_send_break(uint32_t usart_periph);
|
||||||
|
|
||||||
|
/* half-duplex communication */
|
||||||
|
/* enable half-duplex mode */
|
||||||
|
void usart_halfduplex_enable(uint32_t usart_periph);
|
||||||
|
/* disable half-duplex mode */
|
||||||
|
void usart_halfduplex_disable(uint32_t usart_periph);
|
||||||
|
|
||||||
|
/* synchronous communication */
|
||||||
|
/* enable CK pin in synchronous mode */
|
||||||
|
void usart_synchronous_clock_enable(uint32_t usart_periph);
|
||||||
|
/* disable CK pin in synchronous mode */
|
||||||
|
void usart_synchronous_clock_disable(uint32_t usart_periph);
|
||||||
|
/* configure usart synchronous mode parameters */
|
||||||
|
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
|
||||||
|
|
||||||
|
/* smartcard communication */
|
||||||
|
/* configure guard time value in smartcard mode */
|
||||||
|
void usart_guard_time_config(uint32_t usart_periph, uint8_t guat);
|
||||||
|
/* enable smartcard mode */
|
||||||
|
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
||||||
|
/* disable smartcard mode */
|
||||||
|
void usart_smartcard_mode_disable(uint32_t usart_periph);
|
||||||
|
/* enable NACK in smartcard mode */
|
||||||
|
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
|
||||||
|
/* disable NACK in smartcard mode */
|
||||||
|
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
||||||
|
/* configure smartcard auto-retry number */
|
||||||
|
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint8_t scrtnum);
|
||||||
|
/* configure block length */
|
||||||
|
void usart_block_length_config(uint32_t usart_periph, uint8_t bl);
|
||||||
|
|
||||||
|
/* IrDA communication */
|
||||||
|
/* enable IrDA mode */
|
||||||
|
void usart_irda_mode_enable(uint32_t usart_periph);
|
||||||
|
/* disable IrDA mode */
|
||||||
|
void usart_irda_mode_disable(uint32_t usart_periph);
|
||||||
|
/* configure the peripheral clock prescaler */
|
||||||
|
void usart_prescaler_config(uint32_t usart_periph, uint8_t psc);
|
||||||
|
/* configure IrDA low-power */
|
||||||
|
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
|
||||||
|
|
||||||
|
/* hardware flow communication */
|
||||||
|
/* configure hardware flow control RTS */
|
||||||
|
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
|
||||||
|
/* configure hardware flow control CTS */
|
||||||
|
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
|
||||||
|
|
||||||
|
/* coherence control */
|
||||||
|
/* configure break frame coherence mode */
|
||||||
|
void usart_break_frame_coherence_config(uint32_t usart_periph, uint32_t bcm);
|
||||||
|
/* configure parity check coherence mode */
|
||||||
|
void usart_parity_check_coherence_config(uint32_t usart_periph, uint32_t pcm);
|
||||||
|
/* configure hardware flow control coherence mode */
|
||||||
|
void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
|
||||||
|
|
||||||
|
/* DMA communication */
|
||||||
|
/* configure USART DMA for reception */
|
||||||
|
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||||
|
/* configure USART DMA for transmission */
|
||||||
|
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||||
|
|
||||||
|
/* flag & interrupt functions */
|
||||||
|
/* get flag in STAT0/STAT1 register */
|
||||||
|
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
|
||||||
|
/* clear flag in STAT0/STAT1 register */
|
||||||
|
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
|
||||||
|
/* enable USART interrupt */
|
||||||
|
void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
|
||||||
|
/* disable USART interrupt */
|
||||||
|
void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
|
||||||
|
/* get USART interrupt and flag status */
|
||||||
|
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
|
||||||
|
/* clear interrupt flag in STAT0/STAT1 register */
|
||||||
|
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_USART_H */
|
||||||
@@ -0,0 +1,91 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_wwdgt.h
|
||||||
|
\brief definitions for the WWDGT
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef GD32F4XX_WWDGT_H
|
||||||
|
#define GD32F4XX_WWDGT_H
|
||||||
|
|
||||||
|
#include "gd32f4xx.h"
|
||||||
|
|
||||||
|
/* WWDGT definitions */
|
||||||
|
#define WWDGT WWDGT_BASE /*!< WWDGT base address */
|
||||||
|
|
||||||
|
/* registers definitions */
|
||||||
|
#define WWDGT_CTL REG32((WWDGT) + 0x00U) /*!< WWDGT control register */
|
||||||
|
#define WWDGT_CFG REG32((WWDGT) + 0x04U) /*!< WWDGT configuration register */
|
||||||
|
#define WWDGT_STAT REG32((WWDGT) + 0x08U) /*!< WWDGT status register */
|
||||||
|
|
||||||
|
/* bits definitions */
|
||||||
|
/* WWDGT_CTL */
|
||||||
|
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||||
|
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||||
|
|
||||||
|
/* WWDGT_CFG */
|
||||||
|
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||||
|
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||||
|
#define WWDGT_CFG_EWIE BIT(9) /*!< early wakeup interrupt enable */
|
||||||
|
|
||||||
|
/* WWDGT_STAT */
|
||||||
|
#define WWDGT_STAT_EWIF BIT(0) /*!< early wakeup interrupt flag */
|
||||||
|
|
||||||
|
/* constants definitions */
|
||||||
|
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||||
|
#define WWDGT_CFG_PSC_DIV1 CFG_PSC(0) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||||
|
#define WWDGT_CFG_PSC_DIV2 CFG_PSC(1) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||||
|
#define WWDGT_CFG_PSC_DIV4 CFG_PSC(2) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||||
|
#define WWDGT_CFG_PSC_DIV8 CFG_PSC(3) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||||
|
|
||||||
|
/* write value to WWDGT_CTL_CNT bit field */
|
||||||
|
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||||
|
/* write value to WWDGT_CFG_WIN bit field */
|
||||||
|
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||||
|
|
||||||
|
/* function declarations */
|
||||||
|
/* reset the window watchdog timer configuration */
|
||||||
|
void wwdgt_deinit(void);
|
||||||
|
/* start the window watchdog timer counter */
|
||||||
|
void wwdgt_enable(void);
|
||||||
|
|
||||||
|
/* configure the window watchdog timer counter value */
|
||||||
|
void wwdgt_counter_update(uint16_t counter_value);
|
||||||
|
/* configure counter value, window value, and prescaler divider value */
|
||||||
|
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||||
|
|
||||||
|
/* check early wakeup interrupt state of WWDGT */
|
||||||
|
FlagStatus wwdgt_flag_get(void);
|
||||||
|
/* clear early wakeup interrupt state of WWDGT */
|
||||||
|
void wwdgt_flag_clear(void);
|
||||||
|
/* enable early wakeup interrupt of WWDGT */
|
||||||
|
void wwdgt_interrupt_enable(void);
|
||||||
|
|
||||||
|
#endif /* GD32F4XX_WWDGT_H */
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,127 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_crc.c
|
||||||
|
\brief CRC driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_crc.h"
|
||||||
|
|
||||||
|
#define CRC_DATA_RESET_VALUE ((uint32_t)0xFFFFFFFFU)
|
||||||
|
#define CRC_FDATA_RESET_VALUE ((uint32_t)0x00000000U)
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deinit CRC calculation unit
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void crc_deinit(void)
|
||||||
|
{
|
||||||
|
CRC_DATA = CRC_DATA_RESET_VALUE;
|
||||||
|
CRC_FDATA = CRC_FDATA_RESET_VALUE;
|
||||||
|
CRC_CTL = (uint32_t)CRC_CTL_RST;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief reset data register(CRC_DATA) to the value of 0xFFFFFFFF
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void crc_data_register_reset(void)
|
||||||
|
{
|
||||||
|
CRC_CTL |= (uint32_t)CRC_CTL_RST;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read the value of the data register
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval 32-bit value of the data register
|
||||||
|
*/
|
||||||
|
uint32_t crc_data_register_read(void)
|
||||||
|
{
|
||||||
|
uint32_t data;
|
||||||
|
data = CRC_DATA;
|
||||||
|
return (data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read the value of the free data register
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval 8-bit value of the free data register
|
||||||
|
*/
|
||||||
|
uint8_t crc_free_data_register_read(void)
|
||||||
|
{
|
||||||
|
uint8_t fdata;
|
||||||
|
fdata = (uint8_t)CRC_FDATA;
|
||||||
|
return (fdata);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief write data to the free data register
|
||||||
|
\param[in] free_data: specified 8-bit data
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void crc_free_data_register_write(uint8_t free_data)
|
||||||
|
{
|
||||||
|
CRC_FDATA = (uint32_t)free_data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief calculate the CRC value of a 32-bit data
|
||||||
|
\param[in] sdata: specified 32-bit data
|
||||||
|
\param[out] none
|
||||||
|
\retval 32-bit value calculated by CRC
|
||||||
|
*/
|
||||||
|
uint32_t crc_single_data_calculate(uint32_t sdata)
|
||||||
|
{
|
||||||
|
CRC_DATA = sdata;
|
||||||
|
return (CRC_DATA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief calculate the CRC value of an array of 32-bit values
|
||||||
|
\param[in] array: pointer to an array of 32-bit values
|
||||||
|
\param[in] size: size of the array
|
||||||
|
\param[out] none
|
||||||
|
\retval 32-bit value calculated by CRC
|
||||||
|
*/
|
||||||
|
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size)
|
||||||
|
{
|
||||||
|
uint32_t index;
|
||||||
|
for(index = 0U; index < size; index++) {
|
||||||
|
CRC_DATA = array[index];
|
||||||
|
}
|
||||||
|
return (CRC_DATA);
|
||||||
|
}
|
||||||
@@ -0,0 +1,394 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_ctc.c
|
||||||
|
\brief CTC driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_ctc.h"
|
||||||
|
|
||||||
|
#define CTC_FLAG_MASK ((uint32_t)0x00000700U)
|
||||||
|
|
||||||
|
/* CTC register bit offset */
|
||||||
|
#define CTC_TRIMVALUE_OFFSET ((uint32_t)8U)
|
||||||
|
#define CTC_TRIM_VALUE_OFFSET ((uint32_t)8U)
|
||||||
|
#define CTC_REFCAP_OFFSET ((uint32_t)16U)
|
||||||
|
#define CTC_LIMIT_VALUE_OFFSET ((uint32_t)16U)
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief reset CTC clock trim controller
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_deinit(void)
|
||||||
|
{
|
||||||
|
/* reset CTC */
|
||||||
|
rcu_periph_reset_enable(RCU_CTCRST);
|
||||||
|
rcu_periph_reset_disable(RCU_CTCRST);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable CTC trim counter
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_counter_enable(void)
|
||||||
|
{
|
||||||
|
CTC_CTL0 |= (uint32_t)CTC_CTL0_CNTEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable CTC trim counter
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_counter_disable(void)
|
||||||
|
{
|
||||||
|
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_CNTEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the IRC48M trim value
|
||||||
|
\param[in] ctc_trim_value: 8-bit IRC48M trim value
|
||||||
|
\arg 0x00 - 0x3F
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_irc48m_trim_value_config(uint8_t trim_value)
|
||||||
|
{
|
||||||
|
/* clear TRIMVALUE bits */
|
||||||
|
CTC_CTL0 &= (~(uint32_t)CTC_CTL0_TRIMVALUE);
|
||||||
|
/* set TRIMVALUE bits */
|
||||||
|
CTC_CTL0 |= ((uint32_t)trim_value << CTC_TRIM_VALUE_OFFSET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief generate software reference source sync pulse
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_software_refsource_pulse_generate(void)
|
||||||
|
{
|
||||||
|
CTC_CTL0 |= (uint32_t)CTC_CTL0_SWREFPUL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure hardware automatically trim mode
|
||||||
|
\param[in] hardmode:
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_HARDWARE_TRIM_MODE_ENABLE: hardware automatically trim mode enable
|
||||||
|
\arg CTC_HARDWARE_TRIM_MODE_DISABLE: hardware automatically trim mode disable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_hardware_trim_mode_config(uint32_t hardmode)
|
||||||
|
{
|
||||||
|
CTC_CTL0 &= (uint32_t)(~CTC_CTL0_AUTOTRIM);
|
||||||
|
CTC_CTL0 |= (uint32_t)hardmode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure reference signal source polarity
|
||||||
|
\param[in] polarity:
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_REFSOURCE_POLARITY_FALLING: reference signal source polarity is falling edge
|
||||||
|
\arg CTC_REFSOURCE_POLARITY_RISING: reference signal source polarity is rising edge
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_refsource_polarity_config(uint32_t polarity)
|
||||||
|
{
|
||||||
|
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPOL);
|
||||||
|
CTC_CTL1 |= (uint32_t)polarity;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief select reference signal source
|
||||||
|
\param[in] refs:
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_REFSOURCE_GPIO: GPIO is selected
|
||||||
|
\arg CTC_REFSOURCE_LXTAL: LXTAL is selected
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_refsource_signal_select(uint32_t refs)
|
||||||
|
{
|
||||||
|
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFSEL);
|
||||||
|
CTC_CTL1 |= (uint32_t)refs;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure reference signal source prescaler
|
||||||
|
\param[in] prescaler:
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_REFSOURCE_PSC_OFF: reference signal not divided
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV2: reference signal divided by 2
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV4: reference signal divided by 4
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV8: reference signal divided by 8
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV16: reference signal divided by 16
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV32: reference signal divided by 32
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV64: reference signal divided by 64
|
||||||
|
\arg CTC_REFSOURCE_PSC_DIV128: reference signal divided by 128
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_refsource_prescaler_config(uint32_t prescaler)
|
||||||
|
{
|
||||||
|
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_REFPSC);
|
||||||
|
CTC_CTL1 |= (uint32_t)prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure clock trim base limit value
|
||||||
|
\param[in] limit_value: 8-bit clock trim base limit value
|
||||||
|
\arg 0x00 - 0xFF
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_clock_limit_value_config(uint8_t limit_value)
|
||||||
|
{
|
||||||
|
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_CKLIM);
|
||||||
|
CTC_CTL1 |= (uint32_t)((uint32_t)limit_value << CTC_LIMIT_VALUE_OFFSET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure CTC counter reload value
|
||||||
|
\param[in] reload_value: 16-bit CTC counter reload value
|
||||||
|
\arg 0x0000 - 0xFFFF
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_counter_reload_value_config(uint16_t reload_value)
|
||||||
|
{
|
||||||
|
CTC_CTL1 &= (uint32_t)(~CTC_CTL1_RLVALUE);
|
||||||
|
CTC_CTL1 |= (uint32_t)reload_value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read CTC counter capture value when reference sync pulse occurred
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval the 16-bit CTC counter capture value
|
||||||
|
*/
|
||||||
|
uint16_t ctc_counter_capture_value_read(void)
|
||||||
|
{
|
||||||
|
uint16_t capture_value = 0U;
|
||||||
|
capture_value = (uint16_t)((CTC_STAT & CTC_STAT_REFCAP) >> CTC_REFCAP_OFFSET);
|
||||||
|
return (capture_value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read CTC trim counter direction when reference sync pulse occurred
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
\arg SET: CTC trim counter direction is down-counting
|
||||||
|
\arg RESET: CTC trim counter direction is up-counting
|
||||||
|
*/
|
||||||
|
FlagStatus ctc_counter_direction_read(void)
|
||||||
|
{
|
||||||
|
FlagStatus status;
|
||||||
|
if(RESET != (CTC_STAT & CTC_STAT_REFDIR)) {
|
||||||
|
status = SET;
|
||||||
|
} else {
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read CTC counter reload value
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval the 16-bit CTC counter reload value
|
||||||
|
*/
|
||||||
|
uint16_t ctc_counter_reload_value_read(void)
|
||||||
|
{
|
||||||
|
uint16_t reload_value = 0U;
|
||||||
|
reload_value = (uint16_t)(CTC_CTL1 & CTC_CTL1_RLVALUE);
|
||||||
|
return (reload_value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read the IRC48M trim value
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval the 8-bit IRC48M trim value
|
||||||
|
*/
|
||||||
|
uint8_t ctc_irc48m_trim_value_read(void)
|
||||||
|
{
|
||||||
|
uint8_t trim_value = 0U;
|
||||||
|
trim_value = (uint8_t)((CTC_CTL0 & CTC_CTL0_TRIMVALUE) >> CTC_TRIMVALUE_OFFSET);
|
||||||
|
return (trim_value);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the CTC interrupt
|
||||||
|
\param[in] interrupt: CTC interrupt enable
|
||||||
|
one or more parameters can be selected which are shown as below:
|
||||||
|
\arg CTC_INT_CKOK: clock trim OK interrupt enable
|
||||||
|
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
|
||||||
|
\arg CTC_INT_ERR: error interrupt enable
|
||||||
|
\arg CTC_INT_EREF: expect reference interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_interrupt_enable(uint32_t interrupt)
|
||||||
|
{
|
||||||
|
CTC_CTL0 |= (uint32_t)interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the CTC interrupt
|
||||||
|
\param[in] interrupt: CTC interrupt enable source
|
||||||
|
one or more parameters can be selected which are shown as below:
|
||||||
|
\arg CTC_INT_CKOK: clock trim OK interrupt enable
|
||||||
|
\arg CTC_INT_CKWARN: clock trim warning interrupt enable
|
||||||
|
\arg CTC_INT_ERR: error interrupt enable
|
||||||
|
\arg CTC_INT_EREF: expect reference interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_interrupt_disable(uint32_t interrupt)
|
||||||
|
{
|
||||||
|
CTC_CTL0 &= (uint32_t)(~interrupt);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get CTC interrupt flag
|
||||||
|
\param[in] int_flag: the CTC interrupt flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
|
||||||
|
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
|
||||||
|
\arg CTC_INT_FLAG_ERR: error interrupt
|
||||||
|
\arg CTC_INT_FLAG_EREF: expect reference interrupt
|
||||||
|
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
|
||||||
|
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
|
||||||
|
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag)
|
||||||
|
{
|
||||||
|
FlagStatus status;
|
||||||
|
uint32_t interrupt_flag = 0U;
|
||||||
|
uint32_t intenable = 0U;
|
||||||
|
/* check whether the interrupt is enabled */
|
||||||
|
if(RESET != (int_flag & CTC_FLAG_MASK)) {
|
||||||
|
intenable = CTC_CTL0 & CTC_CTL0_ERRIE;
|
||||||
|
} else {
|
||||||
|
intenable = CTC_CTL0 & int_flag;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* get interrupt flag status */
|
||||||
|
interrupt_flag = CTC_STAT & int_flag;
|
||||||
|
|
||||||
|
if(interrupt_flag && intenable) {
|
||||||
|
status = SET;
|
||||||
|
} else {
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear CTC interrupt flag
|
||||||
|
\param[in] int_flag: the CTC interrupt flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_INT_FLAG_CKOK: clock trim OK interrupt
|
||||||
|
\arg CTC_INT_FLAG_CKWARN: clock trim warning interrupt
|
||||||
|
\arg CTC_INT_FLAG_ERR: error interrupt
|
||||||
|
\arg CTC_INT_FLAG_EREF: expect reference interrupt
|
||||||
|
\arg CTC_INT_FLAG_CKERR: clock trim error bit interrupt
|
||||||
|
\arg CTC_INT_FLAG_REFMISS: reference sync pulse miss interrupt
|
||||||
|
\arg CTC_INT_FLAG_TRIMERR: trim value error interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_interrupt_flag_clear(uint32_t int_flag)
|
||||||
|
{
|
||||||
|
if(RESET != (int_flag & CTC_FLAG_MASK)) {
|
||||||
|
CTC_INTC |= CTC_INTC_ERRIC;
|
||||||
|
} else {
|
||||||
|
CTC_INTC |= int_flag;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get CTC flag
|
||||||
|
\param[in] flag: the CTC flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_FLAG_CKOK: clock trim OK flag
|
||||||
|
\arg CTC_FLAG_CKWARN: clock trim warning flag
|
||||||
|
\arg CTC_FLAG_ERR: error flag
|
||||||
|
\arg CTC_FLAG_EREF: expect reference flag
|
||||||
|
\arg CTC_FLAG_CKERR: clock trim error bit
|
||||||
|
\arg CTC_FLAG_REFMISS: reference sync pulse miss
|
||||||
|
\arg CTC_FLAG_TRIMERR: trim value error bit
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus ctc_flag_get(uint32_t flag)
|
||||||
|
{
|
||||||
|
FlagStatus status;
|
||||||
|
if(RESET != (CTC_STAT & flag)) {
|
||||||
|
status = SET;
|
||||||
|
} else {
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear CTC flag
|
||||||
|
\param[in] flag: the CTC flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg CTC_FLAG_CKOK: clock trim OK flag
|
||||||
|
\arg CTC_FLAG_CKWARN: clock trim warning flag
|
||||||
|
\arg CTC_FLAG_ERR: error flag
|
||||||
|
\arg CTC_FLAG_EREF: expect reference flag
|
||||||
|
\arg CTC_FLAG_CKERR: clock trim error bit
|
||||||
|
\arg CTC_FLAG_REFMISS: reference sync pulse miss
|
||||||
|
\arg CTC_FLAG_TRIMERR: trim value error bit
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void ctc_flag_clear(uint32_t flag)
|
||||||
|
{
|
||||||
|
if(RESET != (flag & CTC_FLAG_MASK)) {
|
||||||
|
CTC_INTC |= CTC_INTC_ERRIC;
|
||||||
|
} else {
|
||||||
|
CTC_INTC |= flag;
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,682 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dac.c
|
||||||
|
\brief DAC driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_dac.h"
|
||||||
|
|
||||||
|
/* DAC register bit offset */
|
||||||
|
#define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
|
||||||
|
#define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
|
||||||
|
#define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
|
||||||
|
|
||||||
|
#define DAC_STAT_FLAG_MASK0 (DAC_FLAG_DDUDR0 | DAC_FLAG_DDUDR1)
|
||||||
|
#define DAC_INT_EN_MASK0 (DAC_INT_DDUDR0 | DAC_INT_DDUDR1)
|
||||||
|
#define DAC_INT_FLAG_MASK0 (DAC_INT_FLAG_DDUDR0 | DAC_INT_FLAG_DDUDR1)
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deinitialize DAC
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_deinit(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
switch(dac_periph){
|
||||||
|
case DAC0:
|
||||||
|
/* reset DAC0 */
|
||||||
|
rcu_periph_reset_enable(RCU_DACRST);
|
||||||
|
rcu_periph_reset_disable(RCU_DACRST);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_enable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN0;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DEN1;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_disable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN0);
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DEN1);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC DMA function
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_dma_enable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN0;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DDMAEN1;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC DMA function
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_dma_disable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN0);
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DDMAEN1);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC output buffer
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_output_buffer_enable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF0);
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DBOFF1);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC output buffer
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_output_buffer_disable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF0;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DBOFF1;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get DAC output value
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval DAC output data: 0~4095
|
||||||
|
*/
|
||||||
|
uint16_t dac_output_value_get(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
uint16_t data = 0U;
|
||||||
|
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
/* store the DACx_OUT0 output value */
|
||||||
|
data = (uint16_t)DAC_OUT0_DO(dac_periph);
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* store the DACx_OUT1 output value */
|
||||||
|
data = (uint16_t)DAC_OUT1_DO(dac_periph);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
|
||||||
|
return data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set DAC data holding register value
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[in] dac_align: DAC data alignment mode
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_ALIGN_12B_R: 12-bit right-aligned data
|
||||||
|
\arg DAC_ALIGN_12B_L: 12-bit left-aligned data
|
||||||
|
\arg DAC_ALIGN_8B_R: 8-bit right-aligned data
|
||||||
|
\param[in] data: data to be loaded(0~4095)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_data_set(uint32_t dac_periph, uint8_t dac_out, uint32_t dac_align, uint16_t data)
|
||||||
|
{
|
||||||
|
/* DAC_OUT0 data alignment */
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
switch(dac_align){
|
||||||
|
/* 12-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
DAC_OUT0_R12DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
/* 12-bit left-aligned data */
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
DAC_OUT0_L12DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
/* 8-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
DAC_OUT0_R8DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* DAC_OUT1 data alignment */
|
||||||
|
switch(dac_align){
|
||||||
|
/* 12-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
DAC_OUT1_R12DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
/* 12-bit left-aligned data */
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
DAC_OUT1_L12DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
/* 8-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
DAC_OUT1_R8DH(dac_periph) = data;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC trigger
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN0;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)DAC_CTL0_DTEN1;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC trigger
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_trigger_disable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN0);
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTEN1);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure DAC trigger source
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[in] triggersource: external trigger of DAC
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
|
||||||
|
\arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
|
||||||
|
\arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
|
||||||
|
\arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
|
||||||
|
\arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
|
||||||
|
\arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO
|
||||||
|
\arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
|
||||||
|
\arg DAC_TRIGGER_SOFTWARE: software trigger
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_trigger_source_config(uint32_t dac_periph, uint8_t dac_out, uint32_t triggersource)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
/* configure DACx_OUT0 trigger source */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL0);
|
||||||
|
DAC_CTL0(dac_periph) |= triggersource;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* configure DACx_OUT1 trigger source */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DTSEL1);
|
||||||
|
DAC_CTL0(dac_periph) |= (triggersource << OUT1_REG_OFFSET);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC software trigger
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_software_trigger_enable(uint32_t dac_periph, uint8_t dac_out)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR0;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
DAC_SWT(dac_periph) |= (uint32_t)DAC_SWT_SWTR1;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure DAC wave mode
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[in] wave_mode: DAC wave mode
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_WAVE_DISABLE: wave mode disable
|
||||||
|
\arg DAC_WAVE_MODE_LFSR: LFSR noise mode
|
||||||
|
\arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_wave_mode_config(uint32_t dac_periph, uint8_t dac_out, uint32_t wave_mode)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
/* configure DACx_OUT0 wave mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM0);
|
||||||
|
DAC_CTL0(dac_periph) |= wave_mode;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* configure DACx_OUT1 wave mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWM1);
|
||||||
|
DAC_CTL0(dac_periph) |= (wave_mode << OUT1_REG_OFFSET);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure DAC LFSR noise mode
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[in] unmask_bits: LFSR noise unmask bits
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_LFSR_BIT0: unmask the LFSR bit0
|
||||||
|
\arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
|
||||||
|
\arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
|
||||||
|
\arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
|
||||||
|
\arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
|
||||||
|
\arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
|
||||||
|
\arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
|
||||||
|
\arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
|
||||||
|
\arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
|
||||||
|
\arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
|
||||||
|
\arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
|
||||||
|
\arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_lfsr_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t unmask_bits)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
/* configure DACx_OUT0 LFSR noise mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
|
||||||
|
DAC_CTL0(dac_periph) |= unmask_bits;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* configure DACx_OUT1 LFSR noise mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
|
||||||
|
DAC_CTL0(dac_periph) |= (unmask_bits << OUT1_REG_OFFSET);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure DAC triangle noise mode
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_out: DAC_OUTx(x=0,1)
|
||||||
|
\param[in] amplitude: the amplitude of the triangle
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
|
||||||
|
\arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_triangle_noise_config(uint32_t dac_periph, uint8_t dac_out, uint32_t amplitude)
|
||||||
|
{
|
||||||
|
if(DAC_OUT0 == dac_out){
|
||||||
|
/* configure DACx_OUT0 triangle noise mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW0);
|
||||||
|
DAC_CTL0(dac_periph) |= amplitude;
|
||||||
|
}else if(DAC_OUT1 == dac_out){
|
||||||
|
/* configure DACx_OUT1 triangle noise mode */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~DAC_CTL0_DWBW1);
|
||||||
|
DAC_CTL0(dac_periph) |= (amplitude << OUT1_REG_OFFSET);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC concurrent mode
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_enable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
|
ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC concurrent mode
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_disable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
|
ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~ctl);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC concurrent software trigger
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_software_trigger_enable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
uint32_t swt = 0U;
|
||||||
|
|
||||||
|
swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
|
||||||
|
DAC_SWT(dac_periph) |= (uint32_t)swt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC concurrent buffer function
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_output_buffer_enable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
|
ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~ctl);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC concurrent buffer function
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_output_buffer_disable(uint32_t dac_periph)
|
||||||
|
{
|
||||||
|
uint32_t ctl = 0U;
|
||||||
|
|
||||||
|
ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set DAC concurrent mode data holding register value
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] dac_align: DAC data alignment mode
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_ALIGN_12B_R: 12-bit right-aligned data
|
||||||
|
\arg DAC_ALIGN_12B_L: 12-bit left-aligned data
|
||||||
|
\arg DAC_ALIGN_8B_R: 8-bit right-aligned data
|
||||||
|
\param[in] data0: data to be loaded(0~4095)
|
||||||
|
\param[in] data1: data to be loaded(0~4095)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_concurrent_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data0, uint16_t data1)
|
||||||
|
{
|
||||||
|
uint32_t data = 0U;
|
||||||
|
|
||||||
|
switch(dac_align){
|
||||||
|
/* 12-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_12B_R:
|
||||||
|
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
|
||||||
|
DACC_R12DH(dac_periph) = (uint32_t)data;
|
||||||
|
break;
|
||||||
|
/* 12-bit left-aligned data */
|
||||||
|
case DAC_ALIGN_12B_L:
|
||||||
|
data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
|
||||||
|
DACC_L12DH(dac_periph) = (uint32_t)data;
|
||||||
|
break;
|
||||||
|
/* 8-bit right-aligned data */
|
||||||
|
case DAC_ALIGN_8B_R:
|
||||||
|
data = (uint32_t)(((uint32_t)data1 << DH_8BIT_OFFSET) | data0);
|
||||||
|
DACC_R8DH(dac_periph) = (uint32_t)data;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get the DAC flag
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] flag: the DAC status flags, only one parameter can be selected which is shown
|
||||||
|
as below:
|
||||||
|
\arg DAC_FLAG_DDUDR0: DACx_OUT0 DMA underrun flag
|
||||||
|
\arg DAC_FLAG_DDUDR1: DACx_OUT1 DMA underrun flag
|
||||||
|
\param[out] none
|
||||||
|
\retval the state of DAC bit(SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus dac_flag_get(uint32_t dac_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
FlagStatus status = RESET;
|
||||||
|
|
||||||
|
if(flag & DAC_STAT_FLAG_MASK0){
|
||||||
|
/* check DAC_STAT0 flag */
|
||||||
|
if(RESET != (DAC_STAT0(dac_periph) & flag)){
|
||||||
|
status = SET;
|
||||||
|
}else{
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear the DAC flag
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] flag: DAC flag
|
||||||
|
one or more parameter can be selected which are shown as below:
|
||||||
|
\arg DAC_FLAG_DDUDR0: DACx_OUT0 DMA underrun flag
|
||||||
|
\arg DAC_FLAG_DDUDR1: DACx_OUT1 DMA underrun flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_flag_clear(uint32_t dac_periph, uint32_t flag)
|
||||||
|
{
|
||||||
|
if(flag & DAC_STAT_FLAG_MASK0){
|
||||||
|
/* check DAC_STAT0 flag */
|
||||||
|
DAC_STAT0(dac_periph) = (uint32_t)(flag & DAC_STAT_FLAG_MASK0);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DAC interrupt(DAC DMA underrun interrupt)
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] interrupt: the DAC interrupt
|
||||||
|
one or more parameter can be selected which are shown as below:
|
||||||
|
\arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt
|
||||||
|
\arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_interrupt_enable(uint32_t dac_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
if(interrupt & DAC_INT_EN_MASK0){
|
||||||
|
/* enable underrun interrupt */
|
||||||
|
DAC_CTL0(dac_periph) |= (uint32_t)(interrupt & DAC_INT_EN_MASK0);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DAC interrupt(DAC DMA underrun interrupt)
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] interrupt: the DAC interrupt
|
||||||
|
one and more parameter can be selected which are shown as below:
|
||||||
|
\arg DAC_INT_DDUDR0: DACx_OUT0 DMA underrun interrupt
|
||||||
|
\arg DAC_INT_DDUDR1: DACx_OUT1 DMA underrun interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_interrupt_disable(uint32_t dac_periph, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
if(interrupt & DAC_INT_EN_MASK0){
|
||||||
|
/* disable underrun interrupt */
|
||||||
|
DAC_CTL0(dac_periph) &= (uint32_t)(~(interrupt & DAC_INT_EN_MASK0));
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get the DAC interrupt flag(DAC DMA underrun interrupt flag)
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] int_flag: DAC interrupt flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DAC_INT_FLAG_DDUDR0: DACx_OUT0 DMA underrun interrupt flag
|
||||||
|
\arg DAC_INT_FLAG_DDUDR1: DACx_OUT1 DMA underrun interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval the state of DAC interrupt flag(SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus dac_interrupt_flag_get(uint32_t dac_periph, uint32_t int_flag)
|
||||||
|
{
|
||||||
|
uint32_t reg1 = 0U, reg2 = 0U;
|
||||||
|
FlagStatus status = RESET;
|
||||||
|
|
||||||
|
if(int_flag & DAC_INT_FLAG_MASK0){
|
||||||
|
/* check underrun interrupt int_flag */
|
||||||
|
reg1 = DAC_STAT0(dac_periph) & int_flag;
|
||||||
|
reg2 = DAC_CTL0(dac_periph) & int_flag;
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
|
||||||
|
/*get DAC interrupt flag status */
|
||||||
|
if((RESET != reg1) && (RESET != reg2)){
|
||||||
|
status = SET;
|
||||||
|
}else{
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear the DAC interrupt flag(DAC DMA underrun interrupt flag)
|
||||||
|
\param[in] dac_periph: DACx(x=0)
|
||||||
|
\param[in] int_flag: DAC interrupt flag
|
||||||
|
one or more parameter can be selected which are shown as below:
|
||||||
|
\arg DAC_INT_FLAG_DDUDR0: DACx_OUT0 DMA underrun interrupt flag
|
||||||
|
\arg DAC_INT_FLAG_DDUDR1: DACx_OUT1 DMA underrun interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dac_interrupt_flag_clear(uint32_t dac_periph, uint32_t int_flag)
|
||||||
|
{
|
||||||
|
/* clear underrun interrupt int_flag */
|
||||||
|
if(int_flag & DAC_INT_FLAG_MASK0){
|
||||||
|
DAC_STAT0(dac_periph) = (uint32_t)(int_flag & DAC_INT_FLAG_MASK0);
|
||||||
|
}else{
|
||||||
|
/* illegal parameters */
|
||||||
|
}
|
||||||
|
}
|
||||||
@@ -0,0 +1,180 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dbg.c
|
||||||
|
\brief DBG driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_dbg.h"
|
||||||
|
|
||||||
|
#define DBG_RESET_VAL 0x00000000U
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deinitialize the DBG
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_deinit(void)
|
||||||
|
{
|
||||||
|
DBG_CTL0 = DBG_RESET_VAL;
|
||||||
|
DBG_CTL1 = DBG_RESET_VAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read DBG_ID code register
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval DBG_ID code
|
||||||
|
*/
|
||||||
|
uint32_t dbg_id_get(void)
|
||||||
|
{
|
||||||
|
return DBG_ID;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable low power behavior when the mcu is in debug mode
|
||||||
|
\param[in] dbg_low_power:
|
||||||
|
this parameter can be any combination of the following values:
|
||||||
|
\arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
|
||||||
|
\arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
|
||||||
|
\arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_low_power_enable(uint32_t dbg_low_power)
|
||||||
|
{
|
||||||
|
DBG_CTL0 |= dbg_low_power;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable low power behavior when the mcu is in debug mode
|
||||||
|
\param[in] dbg_low_power:
|
||||||
|
this parameter can be any combination of the following values:
|
||||||
|
\arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
|
||||||
|
\arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
|
||||||
|
\arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_low_power_disable(uint32_t dbg_low_power)
|
||||||
|
{
|
||||||
|
DBG_CTL0 &= ~dbg_low_power;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable peripheral behavior when the mcu is in debug mode
|
||||||
|
\param[in] dbg_periph: dbg_periph_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted
|
||||||
|
\arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted
|
||||||
|
\arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted
|
||||||
|
\arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted
|
||||||
|
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||||
|
\arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted
|
||||||
|
\arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted
|
||||||
|
\arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted
|
||||||
|
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||||
|
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||||
|
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||||
|
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||||
|
\arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted
|
||||||
|
\arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted
|
||||||
|
\arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted
|
||||||
|
\arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted
|
||||||
|
\arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted
|
||||||
|
\arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted
|
||||||
|
\arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted
|
||||||
|
\arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
|
||||||
|
\arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
|
||||||
|
\arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_periph_enable(dbg_periph_enum dbg_periph)
|
||||||
|
{
|
||||||
|
DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable peripheral behavior when the mcu is in debug mode
|
||||||
|
\param[in] dbg_periph: dbg_periph_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted
|
||||||
|
\arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted
|
||||||
|
\arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted
|
||||||
|
\arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted
|
||||||
|
\arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
|
||||||
|
\arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted
|
||||||
|
\arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted
|
||||||
|
\arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted
|
||||||
|
\arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
|
||||||
|
\arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
|
||||||
|
\arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
|
||||||
|
\arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
|
||||||
|
\arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted
|
||||||
|
\arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted
|
||||||
|
\arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted
|
||||||
|
\arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted
|
||||||
|
\arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted
|
||||||
|
\arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted
|
||||||
|
\arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted
|
||||||
|
\arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
|
||||||
|
\arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
|
||||||
|
\arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_periph_disable(dbg_periph_enum dbg_periph)
|
||||||
|
{
|
||||||
|
DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable trace pin assignment
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_trace_pin_enable(void)
|
||||||
|
{
|
||||||
|
DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable trace pin assignment
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dbg_trace_pin_disable(void)
|
||||||
|
{
|
||||||
|
DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
|
||||||
|
}
|
||||||
|
|
||||||
@@ -0,0 +1,351 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dci.c
|
||||||
|
\brief DCI driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_dci.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DCI deinit
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_deinit(void)
|
||||||
|
{
|
||||||
|
rcu_periph_reset_enable(RCU_DCIRST);
|
||||||
|
rcu_periph_reset_disable(RCU_DCIRST);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize DCI registers
|
||||||
|
\param[in] dci_struct: DCI parameter initialization structure
|
||||||
|
members of the structure and the member values are shown as below:
|
||||||
|
capture_mode : DCI_CAPTURE_MODE_CONTINUOUS, DCI_CAPTURE_MODE_SNAPSHOT
|
||||||
|
colck_polarity : DCI_CK_POLARITY_FALLING, DCI_CK_POLARITY_RISING
|
||||||
|
hsync_polarity : DCI_HSYNC_POLARITY_LOW, DCI_HSYNC_POLARITY_HIGH
|
||||||
|
vsync_polarity : DCI_VSYNC_POLARITY_LOW, DCI_VSYNC_POLARITY_HIGH
|
||||||
|
frame_rate : DCI_FRAME_RATE_ALL, DCI_FRAME_RATE_1_2, DCI_FRAME_RATE_1_4
|
||||||
|
interface_format: DCI_INTERFACE_FORMAT_8BITS, DCI_INTERFACE_FORMAT_10BITS,
|
||||||
|
DCI_INTERFACE_FORMAT_12BITS, DCI_INTERFACE_FORMAT_14BITS
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_init(dci_parameter_struct *dci_struct)
|
||||||
|
{
|
||||||
|
uint32_t reg = 0U;
|
||||||
|
/* disable capture function and DCI */
|
||||||
|
DCI_CTL &= ~(DCI_CTL_CAP | DCI_CTL_DCIEN);
|
||||||
|
/* configure DCI parameter */
|
||||||
|
reg |= dci_struct->capture_mode;
|
||||||
|
reg |= dci_struct->clock_polarity;
|
||||||
|
reg |= dci_struct->hsync_polarity;
|
||||||
|
reg |= dci_struct->vsync_polarity;
|
||||||
|
reg |= dci_struct->frame_rate;
|
||||||
|
reg |= dci_struct->interface_format;
|
||||||
|
|
||||||
|
DCI_CTL = reg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DCI function
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_enable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL |= DCI_CTL_DCIEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DCI function
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_disable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL &= ~DCI_CTL_DCIEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DCI capture
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_capture_enable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL |= DCI_CTL_CAP;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DCI capture
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_capture_disable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL &= ~DCI_CTL_CAP;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DCI jpeg mode
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_jpeg_enable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL |= DCI_CTL_JM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DCI jpeg mode
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_jpeg_disable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL &= ~DCI_CTL_JM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable cropping window function
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_crop_window_enable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL |= DCI_CTL_WDEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable cropping window function
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_crop_window_disable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL &= ~DCI_CTL_WDEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure DCI cropping window
|
||||||
|
\param[in] start_x: window horizontal start position
|
||||||
|
\param[in] start_y: window vertical start position
|
||||||
|
\param[in] size_width: window horizontal size
|
||||||
|
\param[in] size_height: window vertical size
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_crop_window_config(uint16_t start_x, uint16_t start_y, uint16_t size_width, uint16_t size_height)
|
||||||
|
{
|
||||||
|
DCI_CWSPOS = ((uint32_t)start_x | ((uint32_t)start_y << 16));
|
||||||
|
DCI_CWSZ = ((uint32_t)size_width | ((uint32_t)size_height << 16));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable embedded synchronous mode
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_embedded_sync_enable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL |= DCI_CTL_ESM;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disble embedded synchronous mode
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_embedded_sync_disable(void)
|
||||||
|
{
|
||||||
|
DCI_CTL &= ~DCI_CTL_ESM;
|
||||||
|
}
|
||||||
|
/*!
|
||||||
|
\brief config synchronous codes in embedded synchronous mode
|
||||||
|
\param[in] frame_start: frame start code in embedded synchronous mode
|
||||||
|
\param[in] line_start: line start code in embedded synchronous mode
|
||||||
|
\param[in] line_end: line end code in embedded synchronous mode
|
||||||
|
\param[in] frame_end: frame end code in embedded synchronous mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_sync_codes_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end)
|
||||||
|
{
|
||||||
|
DCI_SC = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief config synchronous codes unmask in embedded synchronous mode
|
||||||
|
\param[in] frame_start: frame start code unmask bits in embedded synchronous mode
|
||||||
|
\param[in] line_start: line start code unmask bits in embedded synchronous mode
|
||||||
|
\param[in] line_end: line end code unmask bits in embedded synchronous mode
|
||||||
|
\param[in] frame_end: frame end code unmask bits in embedded synchronous mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_sync_codes_unmask_config(uint8_t frame_start, uint8_t line_start, uint8_t line_end, uint8_t frame_end)
|
||||||
|
{
|
||||||
|
DCI_SCUMSK = ((uint32_t)frame_start | ((uint32_t)line_start << 8) | ((uint32_t)line_end << 16) | ((uint32_t)frame_end << 24));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief read DCI data register
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval data
|
||||||
|
*/
|
||||||
|
uint32_t dci_data_read(void)
|
||||||
|
{
|
||||||
|
return DCI_DATA;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get specified flag
|
||||||
|
\param[in] flag:
|
||||||
|
\arg DCI_FLAG_HS: HS line status
|
||||||
|
\arg DCI_FLAG_VS: VS line status
|
||||||
|
\arg DCI_FLAG_FV:FIFO valid
|
||||||
|
\arg DCI_FLAG_EF: end of frame flag
|
||||||
|
\arg DCI_FLAG_OVR: FIFO overrun flag
|
||||||
|
\arg DCI_FLAG_ESE: embedded synchronous error flag
|
||||||
|
\arg DCI_FLAG_VSYNC: vsync flag
|
||||||
|
\arg DCI_FLAG_EL: end of line flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus dci_flag_get(uint32_t flag)
|
||||||
|
{
|
||||||
|
uint32_t stat = 0U;
|
||||||
|
|
||||||
|
FlagStatus ret = RESET;
|
||||||
|
|
||||||
|
if(flag >> 31) {
|
||||||
|
/* get flag status from DCI_STAT1 register */
|
||||||
|
stat = DCI_STAT1;
|
||||||
|
} else {
|
||||||
|
/* get flag status from DCI_STAT0 register */
|
||||||
|
stat = DCI_STAT0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(flag & stat) {
|
||||||
|
ret = SET;
|
||||||
|
} else {
|
||||||
|
ret = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable specified DCI interrupt
|
||||||
|
\param[in] interrupt:
|
||||||
|
\arg DCI_INT_EF: end of frame interrupt
|
||||||
|
\arg DCI_INT_OVR: FIFO overrun interrupt
|
||||||
|
\arg DCI_INT_ESE: embedded synchronous error interrupt
|
||||||
|
\arg DCI_INT_VSYNC: vsync interrupt
|
||||||
|
\arg DCI_INT_EL: end of line interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_interrupt_enable(uint32_t interrupt)
|
||||||
|
{
|
||||||
|
DCI_INTEN |= interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable specified DCI interrupt
|
||||||
|
\param[in] interrupt:
|
||||||
|
\arg DCI_INT_EF: end of frame interrupt
|
||||||
|
\arg DCI_INT_OVR: FIFO overrun interrupt
|
||||||
|
\arg DCI_INT_ESE: embedded synchronous error interrupt
|
||||||
|
\arg DCI_INT_VSYNC: vsync interrupt
|
||||||
|
\arg DCI_INT_EL: end of line interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_interrupt_disable(uint32_t interrupt)
|
||||||
|
{
|
||||||
|
DCI_INTEN &= ~interrupt;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear specified interrupt flag
|
||||||
|
\param[in] int_flag:
|
||||||
|
\arg DCI_INT_EF: end of frame interrupt
|
||||||
|
\arg DCI_INT_OVR: FIFO overrun interrupt
|
||||||
|
\arg DCI_INT_ESE: embedded synchronous error interrupt
|
||||||
|
\arg DCI_INT_VSYNC: vsync interrupt
|
||||||
|
\arg DCI_INT_EL: end of line interrupt
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dci_interrupt_flag_clear(uint32_t int_flag)
|
||||||
|
{
|
||||||
|
DCI_INTC |= int_flag;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get specified interrupt flag
|
||||||
|
\param[in] int_flag:
|
||||||
|
\arg DCI_INT_FLAG_EF: end of frame interrupt flag
|
||||||
|
\arg DCI_INT_FLAG_OVR: FIFO overrun interrupt flag
|
||||||
|
\arg DCI_INT_FLAG_ESE: embedded synchronous error interrupt flag
|
||||||
|
\arg DCI_INT_FLAG_VSYNC: vsync interrupt flag
|
||||||
|
\arg DCI_INT_FLAG_EL: end of line interrupt flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus dci_interrupt_flag_get(uint32_t int_flag)
|
||||||
|
{
|
||||||
|
FlagStatus ret = RESET;
|
||||||
|
|
||||||
|
if(RESET == (DCI_INTF & int_flag)) {
|
||||||
|
ret = RESET;
|
||||||
|
} else {
|
||||||
|
ret = SET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
@@ -0,0 +1,907 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_dma.c
|
||||||
|
\brief DMA driver
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_dma.h"
|
||||||
|
|
||||||
|
/* DMA register bit offset */
|
||||||
|
#define CHXCTL_PERIEN_OFFSET ((uint32_t)25U)
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deinitialize DMA a channel registers
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel is deinitialized
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
/* disable DMA a channel */
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
|
||||||
|
/* reset DMA channel registers */
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
|
||||||
|
DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
|
||||||
|
DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
|
||||||
|
DMA_CHM0ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
|
||||||
|
DMA_CHM1ADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) = DMA_CHFCTL_RESET_VALUE;
|
||||||
|
if(channelx < DMA_CH4) {
|
||||||
|
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
|
||||||
|
} else {
|
||||||
|
channelx -= (dma_channel_enum)4;
|
||||||
|
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize the DMA single data mode parameters struct with the default values
|
||||||
|
\param[in] init_struct: the initialization data needed to initialize DMA channel
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_single_data_para_struct_init(dma_single_data_parameter_struct *init_struct)
|
||||||
|
{
|
||||||
|
/* set the DMA struct with the default values */
|
||||||
|
init_struct->periph_addr = 0U;
|
||||||
|
init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||||
|
init_struct->memory0_addr = 0U;
|
||||||
|
init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
|
||||||
|
init_struct->periph_memory_width = 0U;
|
||||||
|
init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE;
|
||||||
|
init_struct->direction = DMA_PERIPH_TO_MEMORY;
|
||||||
|
init_struct->number = 0U;
|
||||||
|
init_struct->priority = DMA_PRIORITY_LOW;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize the DMA multi data mode parameters struct with the default values
|
||||||
|
\param[in] init_struct: the initialization data needed to initialize DMA channel
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_multi_data_para_struct_init(dma_multi_data_parameter_struct *init_struct)
|
||||||
|
{
|
||||||
|
/* set the DMA struct with the default values */
|
||||||
|
init_struct->periph_addr = 0U;
|
||||||
|
init_struct->periph_width = 0U;
|
||||||
|
init_struct->periph_inc = DMA_PERIPH_INCREASE_DISABLE;
|
||||||
|
init_struct->memory0_addr = 0U;
|
||||||
|
init_struct->memory_width = 0U;
|
||||||
|
init_struct->memory_inc = DMA_MEMORY_INCREASE_DISABLE;
|
||||||
|
init_struct->memory_burst_width = 0U;
|
||||||
|
init_struct->periph_burst_width = 0U;
|
||||||
|
init_struct->circular_mode = DMA_CIRCULAR_MODE_DISABLE;
|
||||||
|
init_struct->direction = DMA_PERIPH_TO_MEMORY;
|
||||||
|
init_struct->number = 0U;
|
||||||
|
init_struct->priority = DMA_PRIORITY_LOW;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize DMA single data mode
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel is initialized
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] init_struct: the data needed to initialize DMA single data mode
|
||||||
|
periph_addr: peripheral base address
|
||||||
|
periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX
|
||||||
|
memory0_addr: memory base address
|
||||||
|
memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
|
||||||
|
periph_memory_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT
|
||||||
|
circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE
|
||||||
|
direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY
|
||||||
|
number: the number of remaining data to be transferred by the DMA
|
||||||
|
priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_single_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_single_data_parameter_struct *init_struct)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
|
||||||
|
/* select single data mode */
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) &= ~DMA_CHXFCTL_MDMEN;
|
||||||
|
|
||||||
|
/* configure peripheral base address */
|
||||||
|
DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
|
||||||
|
|
||||||
|
/* configure memory base address */
|
||||||
|
DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr;
|
||||||
|
|
||||||
|
/* configure the number of remaining data to be transferred */
|
||||||
|
DMA_CHCNT(dma_periph, channelx) = init_struct->number;
|
||||||
|
|
||||||
|
/* configure peripheral and memory transfer width,channel priotity,transfer mode */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM);
|
||||||
|
ctl |= (init_struct->periph_memory_width | (init_struct->periph_memory_width << 2) | init_struct->priority | init_struct->direction);
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
|
||||||
|
/* configure peripheral increasing mode */
|
||||||
|
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
|
||||||
|
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* configure memory increasing mode */
|
||||||
|
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* configure DMA circular mode */
|
||||||
|
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize DMA multi data mode
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel is initialized
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] dma_multi_data_parameter_struct: the data needed to initialize DMA multi data mode
|
||||||
|
periph_addr: peripheral base address
|
||||||
|
periph_width: DMA_PERIPH_WIDTH_8BIT,DMA_PERIPH_WIDTH_16BIT,DMA_PERIPH_WIDTH_32BIT
|
||||||
|
periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE,DMA_PERIPH_INCREASE_FIX
|
||||||
|
memory0_addr: memory0 base address
|
||||||
|
memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
|
||||||
|
memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
|
||||||
|
memory_burst_width: DMA_MEMORY_BURST_SINGLE,DMA_MEMORY_BURST_4_BEAT,DMA_MEMORY_BURST_8_BEAT,DMA_MEMORY_BURST_16_BEAT
|
||||||
|
periph_burst_width: DMA_PERIPH_BURST_SINGLE,DMA_PERIPH_BURST_4_BEAT,DMA_PERIPH_BURST_8_BEAT,DMA_PERIPH_BURST_16_BEAT
|
||||||
|
critical_value: DMA_FIFO_1_WORD,DMA_FIFO_2_WORD,DMA_FIFO_3_WORD,DMA_FIFO_4_WORD
|
||||||
|
circular_mode: DMA_CIRCULAR_MODE_ENABLE,DMA_CIRCULAR_MODE_DISABLE
|
||||||
|
direction: DMA_PERIPH_TO_MEMORY,DMA_MEMORY_TO_PERIPH,DMA_MEMORY_TO_MEMORY
|
||||||
|
number: the number of remaining data to be transferred by the DMA
|
||||||
|
priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_multi_data_mode_init(uint32_t dma_periph, dma_channel_enum channelx, dma_multi_data_parameter_struct *init_struct)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
|
||||||
|
/* select multi data mode and configure FIFO critical value */
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) |= (DMA_CHXFCTL_MDMEN | init_struct->critical_value);
|
||||||
|
|
||||||
|
/* configure peripheral base address */
|
||||||
|
DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
|
||||||
|
|
||||||
|
/* configure memory base address */
|
||||||
|
DMA_CHM0ADDR(dma_periph, channelx) = init_struct->memory0_addr;
|
||||||
|
|
||||||
|
/* configure the number of remaining data to be transferred */
|
||||||
|
DMA_CHCNT(dma_periph, channelx) = init_struct->number;
|
||||||
|
|
||||||
|
/* configure peripheral and memory transfer width,channel priotity,transfer mode,peripheral and memory burst transfer width */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO | DMA_CHXCTL_TM | DMA_CHXCTL_PBURST | DMA_CHXCTL_MBURST);
|
||||||
|
ctl |= (init_struct->periph_width | (init_struct->memory_width) | init_struct->priority | init_struct->direction | init_struct->memory_burst_width |
|
||||||
|
init_struct->periph_burst_width);
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
|
||||||
|
/* configure peripheral increasing mode */
|
||||||
|
if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
|
||||||
|
} else if(DMA_PERIPH_INCREASE_DISABLE == init_struct->periph_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* configure memory increasing mode */
|
||||||
|
if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* configure DMA circular mode */
|
||||||
|
if(DMA_CIRCULAR_MODE_ENABLE == init_struct->circular_mode) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set DMA peripheral base address
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to set peripheral base address
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] address: peripheral base address
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
|
||||||
|
{
|
||||||
|
DMA_CHPADDR(dma_periph, channelx) = address;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set DMA Memory0 base address
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to set Memory base address
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] memory_flag: DMA_MEMORY_x(x=0,1)
|
||||||
|
\param[in] address: Memory base address
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t memory_flag, uint32_t address)
|
||||||
|
{
|
||||||
|
if(memory_flag) {
|
||||||
|
DMA_CHM1ADDR(dma_periph, channelx) = address;
|
||||||
|
} else {
|
||||||
|
DMA_CHM0ADDR(dma_periph, channelx) = address;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief set the number of remaining data to be transferred by the DMA
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to set number
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] number: the number of remaining data to be transferred by the DMA
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
|
||||||
|
{
|
||||||
|
DMA_CHCNT(dma_periph, channelx) = number;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get the number of remaining data to be transferred by the DMA
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to set number
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval uint32_t: the number of remaining data to be transferred by the DMA
|
||||||
|
*/
|
||||||
|
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
return (uint32_t)DMA_CHCNT(dma_periph, channelx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure priority level of DMA channel
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] priority: priority Level of this channel
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_PRIORITY_LOW: low priority
|
||||||
|
\arg DMA_PRIORITY_MEDIUM: medium priority
|
||||||
|
\arg DMA_PRIORITY_HIGH: high priority
|
||||||
|
\arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_PRIO;
|
||||||
|
ctl |= priority;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure transfer burst beats of memory
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] mbeat: transfer burst beats
|
||||||
|
\arg DMA_MEMORY_BURST_SINGLE: memory transfer single burst
|
||||||
|
\arg DMA_MEMORY_BURST_4_BEAT: memory transfer 4-beat burst
|
||||||
|
\arg DMA_MEMORY_BURST_8_BEAT: memory transfer 8-beat burst
|
||||||
|
\arg DMA_MEMORY_BURST_16_BEAT: memory transfer 16-beat burst
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_memory_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mbeat)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_MBURST;
|
||||||
|
ctl |= mbeat;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure transfer burst beats of peripheral
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] pbeat: transfer burst beats
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_PERIPH_BURST_SINGLE: peripheral transfer single burst
|
||||||
|
\arg DMA_PERIPH_BURST_4_BEAT: peripheral transfer 4-beat burst
|
||||||
|
\arg DMA_PERIPH_BURST_8_BEAT: peripheral transfer 8-beat burst
|
||||||
|
\arg DMA_PERIPH_BURST_16_BEAT: peripheral transfer 16-beat burst
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_periph_burst_beats_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pbeat)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_PBURST;
|
||||||
|
ctl |= pbeat;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure transfer data size of memory
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] msize: transfer data size of memory
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_MEMORY_WIDTH_8BIT: transfer data size of memory is 8-bit
|
||||||
|
\arg DMA_MEMORY_WIDTH_16BIT: transfer data size of memory is 16-bit
|
||||||
|
\arg DMA_MEMORY_WIDTH_32BIT: transfer data size of memory is 32-bit
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t msize)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_MWIDTH;
|
||||||
|
ctl |= msize;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure transfer data size of peripheral
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] msize: transfer data size of peripheral
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data size of peripheral is 8-bit
|
||||||
|
\arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data size of peripheral is 16-bit
|
||||||
|
\arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data size of peripheral is 32-bit
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t psize)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_PWIDTH;
|
||||||
|
ctl |= psize;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure memory address generation generation_algorithm
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] generation_algorithm: the address generation algorithm
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_MEMORY_INCREASE_ENABLE: next address of memory is increasing address mode
|
||||||
|
\arg DMA_MEMORY_INCREASE_DISABLE: next address of memory is fixed address mode
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_memory_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
|
||||||
|
{
|
||||||
|
if(DMA_MEMORY_INCREASE_ENABLE == generation_algorithm) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure peripheral address generation_algorithm
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] generation_algorithm: the address generation algorithm
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_PERIPH_INCREASE_ENABLE: next address of peripheral is increasing address mode
|
||||||
|
\arg DMA_PERIPH_INCREASE_DISABLE: next address of peripheral is fixed address mode
|
||||||
|
\arg DMA_PERIPH_INCREASE_FIX: increasing steps of peripheral address is fixed
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_peripheral_address_generation_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t generation_algorithm)
|
||||||
|
{
|
||||||
|
if(DMA_PERIPH_INCREASE_ENABLE == generation_algorithm) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
|
||||||
|
} else if(DMA_PERIPH_INCREASE_DISABLE == generation_algorithm) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PAIF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DMA circulation mode
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DMA circulation mode
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DMA channel
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DMA channel
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the direction of data transfer on the channel
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] direction: specify the direction of data transfer
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_PERIPH_TO_MEMORY: read from peripheral and write to memory
|
||||||
|
\arg DMA_MEMORY_TO_PERIPH: read from memory and write to peripheral
|
||||||
|
\arg DMA_MEMORY_TO_MEMORY: read from memory and write to memory
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint8_t direction)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_TM;
|
||||||
|
ctl |= direction;
|
||||||
|
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA switch buffer mode config
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] memory1_addr: memory1 base address
|
||||||
|
\param[in] memory_select: DMA_MEMORY_0 or DMA_MEMORY_1
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_switch_buffer_mode_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t memory1_addr, uint32_t memory_select)
|
||||||
|
{
|
||||||
|
/* configure memory1 base address */
|
||||||
|
DMA_CHM1ADDR(dma_periph, channelx) = memory1_addr;
|
||||||
|
|
||||||
|
if(DMA_MEMORY_0 == memory_select) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MBS;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MBS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA using memory get
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval the using memory
|
||||||
|
*/
|
||||||
|
uint32_t dma_using_memory_get(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
uint32_t reval = DMA_MEMORY_0;
|
||||||
|
if((DMA_CHCTL(dma_periph, channelx)) & DMA_CHXCTL_MBS) {
|
||||||
|
reval = DMA_MEMORY_1;
|
||||||
|
} else {
|
||||||
|
reval = DMA_MEMORY_0;
|
||||||
|
}
|
||||||
|
return reval;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA channel peripheral select
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] sub_periph: specify DMA channel peripheral
|
||||||
|
\arg DMA_SUBPERIx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_channel_subperipheral_select(uint32_t dma_periph, dma_channel_enum channelx, dma_subperipheral_enum sub_periph)
|
||||||
|
{
|
||||||
|
uint32_t ctl;
|
||||||
|
/* acquire DMA_CHxCTL register */
|
||||||
|
ctl = DMA_CHCTL(dma_periph, channelx);
|
||||||
|
/* assign regiser */
|
||||||
|
ctl &= ~DMA_CHXCTL_PERIEN;
|
||||||
|
ctl |= ((uint32_t)sub_periph << CHXCTL_PERIEN_OFFSET);
|
||||||
|
|
||||||
|
DMA_CHCTL(dma_periph, channelx) = ctl;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA flow controller configure
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] controller: specify DMA flow controler
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_FLOW_CONTROLLER_DMA: DMA is the flow controller
|
||||||
|
\arg DMA_FLOW_CONTROLLER_PERI: peripheral is the flow controller
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_flow_controller_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t controller)
|
||||||
|
{
|
||||||
|
if(DMA_FLOW_CONTROLLER_DMA == controller) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_TFCS;
|
||||||
|
} else {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_TFCS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA switch buffer mode enable
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] newvalue: ENABLE or DISABLE
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_switch_buffer_mode_enable(uint32_t dma_periph, dma_channel_enum channelx, ControlStatus newvalue)
|
||||||
|
{
|
||||||
|
if(ENABLE == newvalue) {
|
||||||
|
/* switch buffer mode enable */
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_SBMEN;
|
||||||
|
} else {
|
||||||
|
/* switch buffer mode disable */
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_SBMEN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief DMA FIFO status get
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[out] none
|
||||||
|
\retval the using memory
|
||||||
|
*/
|
||||||
|
uint32_t dma_fifo_status_get(uint32_t dma_periph, dma_channel_enum channelx)
|
||||||
|
{
|
||||||
|
return (DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FCNT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get DMA flag is set or not
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to get flag
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] flag: specify get which flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_FLAG_FEE: FIFO error and exception flag
|
||||||
|
\arg DMA_FLAG_SDE: single data mode exception flag
|
||||||
|
\arg DMA_FLAG_TAE: transfer access error flag
|
||||||
|
\arg DMA_FLAG_HTF: half transfer finish flag
|
||||||
|
\arg DMA_FLAG_FTF: full transger finish flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||||||
|
{
|
||||||
|
FlagStatus reval = RESET;
|
||||||
|
if(channelx < DMA_CH4) {
|
||||||
|
if(DMA_INTF0(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
|
||||||
|
reval = SET;
|
||||||
|
} else {
|
||||||
|
reval = RESET;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
channelx -= (dma_channel_enum)4;
|
||||||
|
if(DMA_INTF1(dma_periph) & DMA_FLAG_ADD(flag, channelx)) {
|
||||||
|
reval = SET;
|
||||||
|
} else {
|
||||||
|
reval = RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return reval;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear DMA a channel flag
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to get flag
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] flag: specify get which flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_FLAG_FEE: FIFO error and exception flag
|
||||||
|
\arg DMA_FLAG_SDE: single data mode exception flag
|
||||||
|
\arg DMA_FLAG_TAE: transfer access error flag
|
||||||
|
\arg DMA_FLAG_HTF: half transfer finish flag
|
||||||
|
\arg DMA_FLAG_FTF: full transger finish flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
|
||||||
|
{
|
||||||
|
if(channelx < DMA_CH4) {
|
||||||
|
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
|
||||||
|
} else {
|
||||||
|
channelx -= (dma_channel_enum)4;
|
||||||
|
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable DMA interrupt
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] source: specify which interrupt to enbale
|
||||||
|
only one parameters can be selected which are shown as below:
|
||||||
|
\arg DMA_INT_SDE: single data mode exception interrupt enable
|
||||||
|
\arg DMA_INT_TAE: tranfer access error interrupt enable
|
||||||
|
\arg DMA_INT_HTF: half transfer finish interrupt enable
|
||||||
|
\arg DMA_INT_FTF: full transfer finish interrupt enable
|
||||||
|
\arg DMA_INT_FEE: FIFO exception interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||||||
|
{
|
||||||
|
if(DMA_CHXFCTL_FEEIE != source) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) |= source;
|
||||||
|
} else {
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) |= source;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable DMA interrupt
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] source: specify which interrupt to disbale
|
||||||
|
only one parameters can be selected which are shown as below:
|
||||||
|
\arg DMA_INT_SDE: single data mode exception interrupt enable
|
||||||
|
\arg DMA_INT_TAE: tranfer access error interrupt enable
|
||||||
|
\arg DMA_INT_HTF: half transfer finish interrupt enable
|
||||||
|
\arg DMA_INT_FTF: full transfer finish interrupt enable
|
||||||
|
\arg DMA_INT_FEE: FIFO exception interrupt enable
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
|
||||||
|
{
|
||||||
|
if(DMA_CHXFCTL_FEEIE != source) {
|
||||||
|
DMA_CHCTL(dma_periph, channelx) &= ~source;
|
||||||
|
} else {
|
||||||
|
DMA_CHFCTL(dma_periph, channelx) &= ~source;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get DMA interrupt flag is set or not
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to get interrupt flag
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] interrupt: specify get which flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_INT_FLAG_FEE: FIFO error and exception flag
|
||||||
|
\arg DMA_INT_FLAG_SDE: single data mode exception flag
|
||||||
|
\arg DMA_INT_FLAG_TAE: transfer access error flag
|
||||||
|
\arg DMA_INT_FLAG_HTF: half transfer finish flag
|
||||||
|
\arg DMA_INT_FLAG_FTF: full transger finish flag
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
FlagStatus reval = RESET;
|
||||||
|
uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
|
||||||
|
dma_channel_enum channel_flag_offset = channelx;
|
||||||
|
if(channelx < DMA_CH4) {
|
||||||
|
switch(interrupt) {
|
||||||
|
case DMA_INTF_FEEIF:
|
||||||
|
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_SDEIF:
|
||||||
|
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_TAEIF:
|
||||||
|
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_HTFIF:
|
||||||
|
interrupt_flag = DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_FTFIF:
|
||||||
|
interrupt_flag = (DMA_INTF0(dma_periph) & DMA_FLAG_ADD(interrupt, channelx));
|
||||||
|
interrupt_enable = (DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
channel_flag_offset -= (dma_channel_enum)4;
|
||||||
|
switch(interrupt) {
|
||||||
|
case DMA_INTF_FEEIF:
|
||||||
|
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset);
|
||||||
|
interrupt_enable = DMA_CHFCTL(dma_periph, channelx) & DMA_CHXFCTL_FEEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_SDEIF:
|
||||||
|
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_SDEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_TAEIF:
|
||||||
|
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_TAEIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_HTFIF:
|
||||||
|
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
|
||||||
|
break;
|
||||||
|
case DMA_INTF_FTFIF:
|
||||||
|
interrupt_flag = DMA_INTF1(dma_periph) & DMA_FLAG_ADD(interrupt, channel_flag_offset);
|
||||||
|
interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(interrupt_flag && interrupt_enable) {
|
||||||
|
reval = SET;
|
||||||
|
} else {
|
||||||
|
reval = RESET;
|
||||||
|
}
|
||||||
|
return reval;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear DMA a channel interrupt flag
|
||||||
|
\param[in] dma_periph: DMAx(x=0,1)
|
||||||
|
\arg DMAx(x=0,1)
|
||||||
|
\param[in] channelx: specify which DMA channel to clear interrupt flag
|
||||||
|
\arg DMA_CHx(x=0..7)
|
||||||
|
\param[in] interrupt: specify get which flag
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg DMA_INT_FLAG_FEE: FIFO error and exception flag
|
||||||
|
\arg DMA_INT_FLAG_SDE: single data mode exception flag
|
||||||
|
\arg DMA_INT_FLAG_TAE: transfer access error flag
|
||||||
|
\arg DMA_INT_FLAG_HTF: half transfer finish flag
|
||||||
|
\arg DMA_INT_FLAG_FTF: full transger finish flag
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t interrupt)
|
||||||
|
{
|
||||||
|
if(channelx < DMA_CH4) {
|
||||||
|
DMA_INTC0(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
} else {
|
||||||
|
channelx -= (dma_channel_enum)4;
|
||||||
|
DMA_INTC1(dma_periph) |= DMA_FLAG_ADD(interrupt, channelx);
|
||||||
|
}
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,258 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_exti.c
|
||||||
|
\brief EXTI driver
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_exti.h"
|
||||||
|
|
||||||
|
#define EXTI_REG_RESET_VALUE ((uint32_t)0x00000000U)
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief deinitialize the EXTI
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_deinit(void)
|
||||||
|
{
|
||||||
|
/* reset the value of all the EXTI registers */
|
||||||
|
EXTI_INTEN = EXTI_REG_RESET_VALUE;
|
||||||
|
EXTI_EVEN = EXTI_REG_RESET_VALUE;
|
||||||
|
EXTI_RTEN = EXTI_REG_RESET_VALUE;
|
||||||
|
EXTI_FTEN = EXTI_REG_RESET_VALUE;
|
||||||
|
EXTI_SWIEV = EXTI_REG_RESET_VALUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief initialize the EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[in] mode: interrupt or event mode, refer to exti_mode_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_INTERRUPT: interrupt mode
|
||||||
|
\arg EXTI_EVENT: event mode
|
||||||
|
\param[in] trig_type: interrupt trigger type, refer to exti_trig_type_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_TRIG_RISING: rising edge trigger
|
||||||
|
\arg EXTI_TRIG_FALLING: falling trigger
|
||||||
|
\arg EXTI_TRIG_BOTH: rising and falling trigger
|
||||||
|
\arg EXTI_TRIG_NONE: without rising edge or falling edge trigger
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_init(exti_line_enum linex, \
|
||||||
|
exti_mode_enum mode, \
|
||||||
|
exti_trig_type_enum trig_type)
|
||||||
|
{
|
||||||
|
/* reset the EXTI line x */
|
||||||
|
EXTI_INTEN &= ~(uint32_t)linex;
|
||||||
|
EXTI_EVEN &= ~(uint32_t)linex;
|
||||||
|
EXTI_RTEN &= ~(uint32_t)linex;
|
||||||
|
EXTI_FTEN &= ~(uint32_t)linex;
|
||||||
|
|
||||||
|
/* set the EXTI mode and enable the interrupts or events from EXTI line x */
|
||||||
|
switch(mode) {
|
||||||
|
case EXTI_INTERRUPT:
|
||||||
|
EXTI_INTEN |= (uint32_t)linex;
|
||||||
|
break;
|
||||||
|
case EXTI_EVENT:
|
||||||
|
EXTI_EVEN |= (uint32_t)linex;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* set the EXTI trigger type */
|
||||||
|
switch(trig_type) {
|
||||||
|
case EXTI_TRIG_RISING:
|
||||||
|
EXTI_RTEN |= (uint32_t)linex;
|
||||||
|
EXTI_FTEN &= ~(uint32_t)linex;
|
||||||
|
break;
|
||||||
|
case EXTI_TRIG_FALLING:
|
||||||
|
EXTI_RTEN &= ~(uint32_t)linex;
|
||||||
|
EXTI_FTEN |= (uint32_t)linex;
|
||||||
|
break;
|
||||||
|
case EXTI_TRIG_BOTH:
|
||||||
|
EXTI_RTEN |= (uint32_t)linex;
|
||||||
|
EXTI_FTEN |= (uint32_t)linex;
|
||||||
|
break;
|
||||||
|
case EXTI_TRIG_NONE:
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the interrupts from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_interrupt_enable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_INTEN |= (uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the interrupt from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_interrupt_disable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_INTEN &= ~(uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the events from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_event_enable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_EVEN |= (uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the events from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_event_disable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_EVEN &= ~(uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable the software interrupt event from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_software_interrupt_enable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_SWIEV |= (uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable the software interrupt event from EXTI line x
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_software_interrupt_disable(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_SWIEV &= ~(uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get EXTI line x interrupt pending flag
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: status of flag (RESET or SET)
|
||||||
|
*/
|
||||||
|
FlagStatus exti_flag_get(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
FlagStatus status;
|
||||||
|
|
||||||
|
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||||
|
status = SET;
|
||||||
|
} else {
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear EXTI line x interrupt pending flag
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_flag_clear(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_PD = (uint32_t)linex;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get EXTI line x interrupt pending flag
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: status of flag (RESET or SET)
|
||||||
|
*/
|
||||||
|
FlagStatus exti_interrupt_flag_get(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
FlagStatus status;
|
||||||
|
|
||||||
|
if(RESET != (EXTI_PD & (uint32_t)linex)) {
|
||||||
|
status = SET;
|
||||||
|
} else {
|
||||||
|
status = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief clear EXTI line x interrupt pending flag
|
||||||
|
\param[in] linex: EXTI line number, refer to exti_line_enum
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg EXTI_x (x=0..22): EXTI line x
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void exti_interrupt_flag_clear(exti_line_enum linex)
|
||||||
|
{
|
||||||
|
EXTI_PD = (uint32_t)linex;
|
||||||
|
}
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,226 @@
|
|||||||
|
/*!
|
||||||
|
\file gd32f4xx_fwdgt.c
|
||||||
|
\brief FWDGT driver
|
||||||
|
|
||||||
|
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||||
|
|
||||||
|
Redistribution and use in source and binary forms, with or without modification,
|
||||||
|
are permitted provided that the following conditions are met:
|
||||||
|
|
||||||
|
1. Redistributions of source code must retain the above copyright notice, this
|
||||||
|
list of conditions and the following disclaimer.
|
||||||
|
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||||
|
this list of conditions and the following disclaimer in the documentation
|
||||||
|
and/or other materials provided with the distribution.
|
||||||
|
3. Neither the name of the copyright holder nor the names of its contributors
|
||||||
|
may be used to endorse or promote products derived from this software without
|
||||||
|
specific prior written permission.
|
||||||
|
|
||||||
|
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||||
|
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||||
|
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||||
|
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||||
|
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||||
|
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||||
|
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||||
|
OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gd32f4xx_fwdgt.h"
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief enable write access to FWDGT_PSC and FWDGT_RLD
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fwdgt_write_enable(void)
|
||||||
|
{
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief disable write access to FWDGT_PSC and FWDGT_RLD
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fwdgt_write_disable(void)
|
||||||
|
{
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief start the free watchdog timer counter
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fwdgt_enable(void)
|
||||||
|
{
|
||||||
|
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the free watchdog timer counter prescaler value
|
||||||
|
\param[in] prescaler_value: specify prescaler value
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||||
|
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||||
|
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||||
|
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||||
|
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||||
|
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||||
|
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||||
|
\param[out] none
|
||||||
|
\retval ErrStatus: ERROR or SUCCESS
|
||||||
|
*/
|
||||||
|
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value)
|
||||||
|
{
|
||||||
|
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||||
|
uint32_t flag_status;
|
||||||
|
ErrStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* enable write access to FWDGT_PSC */
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
|
||||||
|
/* configure FWDGT_PSC */
|
||||||
|
FWDGT_PSC = (uint32_t)prescaler_value;
|
||||||
|
|
||||||
|
/* wait until the PUD flag to be reset */
|
||||||
|
do {
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||||
|
} while((--timeout > 0U) && (0U != flag_status));
|
||||||
|
|
||||||
|
if(0U != flag_status) {
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure the free watchdog timer counter reload value
|
||||||
|
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||||
|
\param[out] none
|
||||||
|
\retval ErrStatus: ERROR or SUCCESS
|
||||||
|
*/
|
||||||
|
ErrStatus fwdgt_reload_value_config(uint16_t reload_value)
|
||||||
|
{
|
||||||
|
uint32_t timeout = FWDGT_RLD_TIMEOUT;
|
||||||
|
uint32_t flag_status;
|
||||||
|
ErrStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* enable write access to FWDGT_RLD */
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
|
||||||
|
/* configure FWDGT_RLD */
|
||||||
|
FWDGT_RLD = RLD_RLD(reload_value);
|
||||||
|
|
||||||
|
/* wait until the RUD flag to be reset */
|
||||||
|
do {
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||||
|
} while((--timeout > 0U) && (0U != flag_status));
|
||||||
|
|
||||||
|
if(0U != flag_status) {
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief reload the counter of FWDGT
|
||||||
|
\param[in] none
|
||||||
|
\param[out] none
|
||||||
|
\retval none
|
||||||
|
*/
|
||||||
|
void fwdgt_counter_reload(void)
|
||||||
|
{
|
||||||
|
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief configure counter reload value, and prescaler divider value
|
||||||
|
\param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
|
||||||
|
\param[in] prescaler_value: FWDGT prescaler value
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
|
||||||
|
\arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
|
||||||
|
\arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
|
||||||
|
\arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
|
||||||
|
\arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
|
||||||
|
\arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
|
||||||
|
\arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
|
||||||
|
\param[out] none
|
||||||
|
\retval ErrStatus: ERROR or SUCCESS
|
||||||
|
*/
|
||||||
|
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_value)
|
||||||
|
{
|
||||||
|
uint32_t timeout = FWDGT_PSC_TIMEOUT;
|
||||||
|
uint32_t flag_status;
|
||||||
|
ErrStatus status = SUCCESS;
|
||||||
|
|
||||||
|
/* start the free watchdog timer counter */
|
||||||
|
FWDGT_CTL = FWDGT_KEY_ENABLE;
|
||||||
|
|
||||||
|
/* enable write access to FWDGT_PSC,and FWDGT_RLD */
|
||||||
|
FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
|
||||||
|
|
||||||
|
/* configure FWDGT_PSC */
|
||||||
|
FWDGT_PSC = (uint32_t)prescaler_value;
|
||||||
|
|
||||||
|
do {
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
|
||||||
|
} while((--timeout > 0U) && (0U != flag_status));
|
||||||
|
|
||||||
|
if(0U != flag_status) {
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(SUCCESS == status) {
|
||||||
|
/* configure FWDGT_RLD */
|
||||||
|
FWDGT_RLD = RLD_RLD(reload_value);
|
||||||
|
|
||||||
|
/* wait until the RUD flag to be reset */
|
||||||
|
timeout = FWDGT_RLD_TIMEOUT;
|
||||||
|
do {
|
||||||
|
flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
|
||||||
|
} while((--timeout > 0U) && (0U != flag_status));
|
||||||
|
|
||||||
|
if(0U != flag_status) {
|
||||||
|
status = ERROR;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(SUCCESS == status) {
|
||||||
|
/* reload the counter */
|
||||||
|
FWDGT_CTL = FWDGT_KEY_RELOAD;
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\brief get flag state of FWDGT
|
||||||
|
\param[in] flag: flag to get
|
||||||
|
only one parameter can be selected which is shown as below:
|
||||||
|
\arg FWDGT_STAT_PUD: a write operation to FWDGT_PSC register is on going
|
||||||
|
\arg FWDGT_STAT_RUD: a write operation to FWDGT_RLD register is on going
|
||||||
|
\param[out] none
|
||||||
|
\retval FlagStatus: SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus fwdgt_flag_get(uint16_t flag)
|
||||||
|
{
|
||||||
|
FlagStatus flag_status = RESET;
|
||||||
|
if(RESET != (FWDGT_STAT & flag)) {
|
||||||
|
flag_status = SET;
|
||||||
|
}
|
||||||
|
return flag_status;
|
||||||
|
}
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user