diff --git a/GD32E230.svd b/GD32E230.svd
new file mode 100644
index 0000000..c4b95e9
--- /dev/null
+++ b/GD32E230.svd
@@ -0,0 +1,19783 @@
+
+
+ GD32E230
+ 1.0
+ GD32E230 ARM 32-bit Cortex-M23 Microcontroller based device
+
+ CM23
+ r0p0
+ little
+ 1
+ 1
+ 4
+ 0
+
+ 8
+ 32
+
+
+
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ ADC
+ Analog to digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_CMP
+ 12
+
+
+
+ STAT
+ STAT
+ status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STRC
+ Start flag of regular channel group
+ 4
+ 1
+
+
+ STIC
+ Start flag of inserted channel group
+ 3
+ 1
+
+
+ EOIC
+ End of inserted group conversion flag
+ 2
+ 1
+
+
+ EOC
+ End of group conversion flag
+ 1
+ 1
+
+
+ WDE
+ Analog watchdog event flag
+ 0
+ 1
+
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DRES
+ ADC resolution
+ 24
+ 2
+
+
+ RWDEN
+ Regular channel analog watchdog enable
+ 23
+ 1
+
+
+ IWDEN
+ Inserted channel analog watchdog enable
+ 22
+ 1
+
+
+ DISNUM
+ Number of conversions in discontinuous
+ mode
+ 13
+ 3
+
+
+ DISIC
+ Discontinuous mode on injected
+ channels
+ 12
+ 1
+
+
+ DISRC
+ Discontinuous mode on regular
+ channels
+ 11
+ 1
+
+
+ ICA
+ Inserted channel group convert
+ automatically
+ 10
+ 1
+
+
+ WDSC
+ When in scan mode, analog watchdog
+ is effective on a single channel
+ 9
+ 1
+
+
+ SM
+ Scan mode
+ 8
+ 1
+
+
+ EOICIE
+ Interrupt enable for EOIC
+ 7
+ 1
+
+
+ WDEIE
+ Interrupt enable for WDE
+ 6
+ 1
+
+
+ EOCIE
+ Interrupt enable for EOC
+ 5
+ 1
+
+
+ WDCHSEL
+ Analog watchdog channel select
+ 0
+ 5
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TSVREN
+ Channel 16 and 17 enable of ADC
+ 23
+ 1
+
+
+ SWRCST
+ Start on regular channel
+ 22
+ 1
+
+
+ SWICST
+ Start on inserted channel
+ 21
+ 1
+
+
+ ETERC
+ External trigger enable for regular
+ channel
+ 20
+ 1
+
+
+ ETSRC
+ External trigger select for regular
+ channel
+ 17
+ 3
+
+
+ ETEIC
+ External trigger enable for
+ inserted channels
+ 15
+ 1
+
+
+ ETSIC
+ External trigger select for inserted
+ channel
+ 12
+ 3
+
+
+ DAL
+ Data alignment
+ 11
+ 1
+
+
+ DMA
+ DMA request enable
+ 8
+ 1
+
+
+ RSTCLB
+ Reset calibration
+ 3
+ 1
+
+
+ CLB
+ ADC calibration
+ 2
+ 1
+
+
+ CTN
+ Continuous mode
+ 1
+ 1
+
+
+ ADCON
+ ADC ON
+ 0
+ 1
+
+
+
+
+ SAMPT0
+ SAMPT0
+ Sampling time register 0
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SPT16
+ Channel 16 sample time
+ selection
+ 18
+ 3
+
+
+ SPT17
+ Channel 17 sample time
+ selection
+ 21
+ 3
+
+
+
+
+ SAMPT1
+ SAMPT1
+ Sampling time register 1
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SPT0
+ Channel 0 sample time
+ selection
+ 0
+ 3
+
+
+ SPT1
+ Channel 1 sample time
+ selection
+ 3
+ 3
+
+
+ SPT2
+ Channel 2 sample time
+ selection
+ 6
+ 3
+
+
+ SPT3
+ Channel 3 sample time
+ selection
+ 9
+ 3
+
+
+ SPT4
+ Channel 4 sample time
+ selection
+ 12
+ 3
+
+
+ SPT5
+ Channel 5 sample time
+ selection
+ 15
+ 3
+
+
+ SPT6
+ Channel 6 sample time
+ selection
+ 18
+ 3
+
+
+ SPT7
+ Channel 7 sample time
+ selection
+ 21
+ 3
+
+
+ SPT8
+ Channel 8 sample time
+ selection
+ 24
+ 3
+
+
+ SPT9
+ Channel 9 sample time
+ selection
+ 27
+ 3
+
+
+
+
+ IOFF0
+ IOFF0
+ Inserted channel data offset register
+ 0
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF1
+ IOFF1
+ Inserted channel data offset register
+ 1
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF2
+ IOFF2
+ Inserted channel data offset register
+ 2
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF3
+ IOFF3
+ Inserted channel data offset register
+ 3
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ WDHT
+ WDHT
+ watchdog higher threshold
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WDHT
+ Analog watchdog high
+ threshold
+ 0
+ 12
+
+
+
+
+ WDLT
+ WDLT
+ watchdog low threshold
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDLT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ RSQ0
+ RSQ0
+ regular sequence register 0
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RL
+ Regular channel sequence
+ length
+ 20
+ 4
+
+
+ RSQ15
+ 15th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ14
+ 14th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ13
+ 13th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ12
+ 12th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ RSQ1
+ RSQ1
+ regular sequence register 1
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RSQ11
+ 11th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ RSQ10
+ 10th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ RSQ9
+ 9th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ8
+ 8th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ7
+ 7th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ6
+ 6th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ RSQ2
+ RSQ2
+ regular sequence register 2
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RSQ5
+ 5th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ RSQ4
+ 4th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ RSQ3
+ 3rd conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ2
+ 2nd conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ1
+ 1st conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ0
+ conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ ISQ
+ ISQ
+ injected sequence register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IL
+ Injected sequence length
+ 20
+ 2
+
+
+ ISQ3
+ 3rd conversion in injected
+ sequence
+ 15
+ 5
+
+
+ ISQ2
+ 2nd conversion in injected
+ sequence
+ 10
+ 5
+
+
+ ISQ1
+ 1st conversion in injected
+ sequence
+ 5
+ 5
+
+
+ ISQ0
+ conversion in injected
+ sequence
+ 0
+ 5
+
+
+
+
+ IDATA0
+ IDATA0
+ injected data register 0
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA1
+ IDATA1
+ injected data register 1
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA2
+ IDATA2
+ injected data register 2
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA3
+ IDATA3
+ injected data register 3
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ RDATA
+ RDATA
+ regular data register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RDATA
+ Regular data
+ 0
+ 16
+
+
+
+
+ OVSAMPCTL
+ OVSAMPCTL
+ ADC oversample control register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TOVS
+ Triggered Oversampling
+ 9
+ 1
+
+
+ OVSS
+ Oversampling shift
+ 5
+ 4
+
+
+ OVSR
+ Oversampling ratio
+ 2
+ 3
+
+
+ OVSEN
+ Oversampler Enable
+ 0
+ 1
+
+
+
+
+
+
+ CMP
+ Comparator
+ Comparator
+ 0x4001001C
+
+ 0x0
+ 0x80
+ registers
+
+
+
+ CS
+ CS
+ control and status register
+ 0x00
+ 0x20
+ 0x00000000
+
+
+ CMPEN
+ Comparator enable
+ 0
+ 1
+ read-write
+
+
+ CMPSW
+ Comparator switch
+ 1
+ 1
+ read-write
+
+
+ CMPM
+ Comparator mode
+ 2
+ 2
+ read-write
+
+
+ CMPMSEL
+ Comparator input selection
+ 4
+ 3
+ read-write
+
+
+ CMPOSEL
+ Comparator output selection
+ 8
+ 3
+ read-write
+
+
+ CMPPL
+ Polarity of comparator output
+ 11
+ 1
+ read-write
+
+
+ CMPHST
+ Comparator hysteresis
+ 12
+ 2
+ read-write
+
+
+ CMPO
+ Comparator 0 output
+ 14
+ 1
+ read-only
+
+
+ CMPLK
+ Comparator 0 lock
+ 15
+ 1
+ read-write
+
+
+
+
+
+
+ CRC
+ cyclic redundancy check calculation unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DATA
+ CRC calculation result bits
+ 0
+ 32
+
+
+
+
+ FDATA
+ FDATA
+ Free data register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FDATA
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RST
+ reset bit
+ 0
+ 1
+
+
+ PS
+ Size of polynomial
+ 3
+ 2
+
+
+ REV_I
+ Reverse input data
+ 5
+ 2
+
+
+ REV_O
+ Reverse output data
+ 7
+ 1
+
+
+
+
+ IDATA
+ IDATA
+ Initialization Data Register
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ IDATA
+ CRC calculation initial value
+ 0
+ 32
+
+
+
+
+ POLY
+ POLY
+ Polynomial register
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ POLY
+ User configurable polynomial value
+ 0
+ 32
+
+
+
+
+
+
+ DBGMCU
+ Debug support
+ DBGMCU
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ID
+ ID
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ ID_CODE
+ DBG ID code register
+ 0
+ 32
+
+
+
+
+ CTL0
+ CTL0
+ Debug Control Register 0
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ SLP_HOLD
+ Sleep mode hold register
+ 0
+ 1
+
+
+ DSLP_HOLD
+ DEEPSLEEP mode hold Mode
+ 1
+ 1
+
+
+ STB_HOLD
+ Standby mode hold Mode
+ 2
+ 1
+
+
+ FWDGT_HOLD
+ FWDGT hold register
+ 8
+ 1
+
+
+ WWDGT_HOLD
+ WWDGT hold register
+ 9
+ 1
+
+
+ TIMER0_HOLD
+ Timer 0 hold register
+ 10
+ 1
+
+
+ TIMER2_HOLD
+ Timer 2 hold register
+ 12
+ 1
+
+
+ I2C0_HOLD
+ I2C0 hold register
+ 15
+ 1
+
+
+ I2C1_HOLD
+ I2C1 hold register
+ 16
+ 1
+
+
+ TIMER5_HOLD
+ Timer 5 hold register
+ 19
+ 1
+
+
+ TIMER13_HOLD
+ Timer 13 hold register
+ 27
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Debug Control Register 1
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTC_HOLD
+ RTC hold register
+ 10
+ 1
+
+
+ TIMER14_HOLD
+ Timer 14 hold register
+ 16
+ 1
+
+
+ TIMER15_HOLD
+ Timer 15 hold register
+ 17
+ 1
+
+
+ TIMER16_HOLD
+ Timer 16 hold register
+ 18
+ 1
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA_Channel0
+ 9
+
+
+ DMA_Channel1_2
+ 10
+
+
+ DMA_Channel3_4
+ 11
+
+
+
+ INTF
+ INTF
+ DMA interrupt flag register
+ (DMA_INTF)
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF0
+ Channel 0 Global interrupt
+ flag
+ 0
+ 1
+
+
+ FTFIF0
+ Channel 0 Full Transfer Finish
+ flag
+ 1
+ 1
+
+
+ HTFIF0
+ Channel 0 Half Transfer Finish
+ flag
+ 2
+ 1
+
+
+ ERRIF0
+ Channel 0 Error flag
+ 3
+ 1
+
+
+ GIF1
+ Channel 1 Global interrupt
+ flag
+ 4
+ 1
+
+
+ FTFIF1
+ Channel 1 Full Transfer Finish
+ flag
+ 5
+ 1
+
+
+ HTFIF1
+ Channel 1 Half Transfer Finish
+ flag
+ 6
+ 1
+
+
+ ERRIF1
+ Channel 1 Error flag
+ 7
+ 1
+
+
+ GIF2
+ Channel 2 Global interrupt
+ flag
+ 8
+ 1
+
+
+ FTFIF2
+ Channel 2 Full Transfer Finish
+ flag
+ 9
+ 1
+
+
+ HTFIF2
+ Channel 2 Half Transfer Finish
+ flag
+ 10
+ 1
+
+
+ ERRIF2
+ Channel 2 Error
+ flag
+ 11
+ 1
+
+
+ GIF3
+ Channel 3 Global interrupt
+ flag
+ 12
+ 1
+
+
+ FTFIF3
+ Channel 3 Full Transfer Finish
+ flag
+ 13
+ 1
+
+
+ HTFIF3
+ Channel 3 Half Transfer Finish
+ flag
+ 14
+ 1
+
+
+ ERRIF3
+ Channel 3 Error
+ flag
+ 15
+ 1
+
+
+ GIF4
+ Channel 4 Global interrupt
+ flag
+ 16
+ 1
+
+
+ FTFIF4
+ Channel 4 Full Transfer Finish
+ flag
+ 17
+ 1
+
+
+ HTFIF4
+ Channel 4 Half Transfer Finish
+ flag
+ 18
+ 1
+
+
+ ERRIF4
+ Channel 4 Error
+ flag
+ 19
+ 1
+
+
+
+
+ INTC
+ INTC
+ DMA interrupt flag clear register
+ (DMA_INTC)
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ GIFC0
+ Channel 0 Global interrupt flag
+ clear
+ 0
+ 1
+
+
+ GIFC1
+ Channel 1 Global interrupt flag
+ clear
+ 4
+ 1
+
+
+ GIFC2
+ Channel 2 Global interrupt flag
+ clear
+ 8
+ 1
+
+
+ GIFC3
+ Channel 3 Global interrupt flag
+ clear
+ 12
+ 1
+
+
+ GIFC4
+ Channel 4 Global interrupt flag
+ clear
+ 16
+ 1
+
+
+ FTFIFC0
+ Channel 0 Full Transfer Finish
+ clear
+ 1
+ 1
+
+
+ FTFIFC1
+ Channel 1 Full Transfer Finish
+ clear
+ 5
+ 1
+
+
+ FTFIFC2
+ Channel 2 Full Transfer Finish
+ clear
+ 9
+ 1
+
+
+ FTFIFC3
+ Channel 3 Full Transfer Finish
+ clear
+ 13
+ 1
+
+
+ FTFIFC4
+ Channel 4 Full Transfer Finish
+ clear
+ 17
+ 1
+
+
+ HTFIFC0
+ Channel 0 Half Transfer
+ clear
+ 2
+ 1
+
+
+ HTFIFC1
+ Channel 1 Half Transfer
+ clear
+ 6
+ 1
+
+
+ HTFIFC2
+ Channel 2 Half Transfer
+ clear
+ 10
+ 1
+
+
+ HTFIFC3
+ Channel 3 Half Transfer
+ clear
+ 14
+ 1
+
+
+ HTFIFC4
+ Channel 4 Half Transfer
+ clear
+ 18
+ 1
+
+
+ ERRIFC0
+ Channel 0 Error
+ clear
+ 3
+ 1
+
+
+ ERRIFC1
+ Channel 1 Error
+ clear
+ 7
+ 1
+
+
+ ERRIFC2
+ Channel 2 Error
+ clear
+ 11
+ 1
+
+
+ ERRIFC3
+ Channel 3 Error
+ clear
+ 15
+ 1
+
+
+ ERRIFC4
+ Channel 4 Error
+ clear
+ 19
+ 1
+
+
+
+
+ CH0CTL
+ CH0CTL
+ DMA channel configuration register
+ (DMA_CH0CTL)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Transfer access error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH0CNT
+ CH0CNT
+ DMA channel 0 counter
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH0PADDR
+ CH0PADDR
+ DMA channel 0 peripheral base address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH0MADDR
+ CH0MADDR
+ DMA channel 0 memory base address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH1CTL
+ CH1CTL
+ DMA channel configuration register
+ (DMA_CH1CTL)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH1CNT
+ CH1CNT
+ DMA channel 1 counter
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+
+ CH1PADDR
+ CH1PADDR
+ DMA channel 1 peripheral base address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH1MADDR
+ CH1MADDR
+ DMA channel 1 memory base address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH2CTL
+ CH2CTL
+ DMA channel configuration register
+ (DMA_CH2CTL)
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH2CNT
+ CH2CNT
+ DMA channel 2 counter
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+
+ CH2PADDR
+ CH2PADDR
+ DMA channel 2 peripheral base address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH2MADDR
+ CH2MADDR
+ DMA channel 2 memory base address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH3CTL
+ CH3CTL
+ DMA channel configuration register
+ (DMA_CH3CTL)
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH3CNT
+ CH3CNT
+ DMA channel 3 counter
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH3PADDR
+ CH3PADDR
+ DMA channel 3 peripheral base address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH3MADDR
+ CH3MADDR
+ DMA channel 3 memory base address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH4CTL
+ CH4CTL
+ DMA channel configuration register
+ (DMA_CH4CTL)
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH4CNT
+ CH4CNT
+ DMA channel 4 counter
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH4PADDR
+ CH4PADDR
+ DMA channel 4 peripheral base address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH4MADDR
+ CH4MADDR
+ DMA channel 4 memory base address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LVD
+ 1
+
+
+ EXTI0_1
+ 5
+
+
+ EXTI2_3
+ 6
+
+
+ EXTI4_15
+ 7
+
+
+
+ INTEN
+ INTEN
+ Interrupt enable register
+ (EXTI_INTEN)
+ 0x0
+ 0x20
+ read-write
+ 0x0F940000
+
+
+ INTEN0
+ Enable Interrupt on line 0
+ 0
+ 1
+
+
+ INTEN1
+ Enable Interrupt on line 1
+ 1
+ 1
+
+
+ INTEN2
+ Enable Interrupt on line 2
+ 2
+ 1
+
+
+ INTEN3
+ Enable Interrupt on line 3
+ 3
+ 1
+
+
+ INTEN4
+ Enable Interrupt on line 4
+ 4
+ 1
+
+
+ INTEN5
+ Enable Interrupt on line 5
+ 5
+ 1
+
+
+ INTEN6
+ Enable Interrupt on line 6
+ 6
+ 1
+
+
+ INTEN7
+ Enable Interrupt on line 7
+ 7
+ 1
+
+
+ INTEN8
+ Enable Interrupt on line 8
+ 8
+ 1
+
+
+ INTEN9
+ Enable Interrupt on line 9
+ 9
+ 1
+
+
+ INTEN10
+ Enable Interrupt on line 10
+ 10
+ 1
+
+
+ INTEN11
+ Enable Interrupt on line 11
+ 11
+ 1
+
+
+ INTEN12
+ Enable Interrupt on line 12
+ 12
+ 1
+
+
+ INTEN13
+ Enable Interrupt on line 13
+ 13
+ 1
+
+
+ INTEN14
+ Enable Interrupt on line 14
+ 14
+ 1
+
+
+ INTEN15
+ Enable Interrupt on line 15
+ 15
+ 1
+
+
+ INTEN16
+ Enable Interrupt on line 16
+ 16
+ 1
+
+
+ INTEN17
+ Enable Interrupt on line 17
+ 17
+ 1
+
+
+ INTEN18
+ Enable Interrupt on line 18
+ 18
+ 1
+
+
+ INTEN19
+ Enable Interrupt on line 19
+ 19
+ 1
+
+
+ INTEN20
+ Enable Interrupt on line 20
+ 20
+ 1
+
+
+ INTEN21
+ Enable Interrupt on line 21
+ 21
+ 1
+
+
+ INTEN22
+ Enable Interrupt on line 22
+ 22
+ 1
+
+
+ INTEN23
+ Enable Interrupt on line 23
+ 23
+ 1
+
+
+ INTEN24
+ Enable Interrupt on line 24
+ 24
+ 1
+
+
+ INTEN25
+ Enable Interrupt on line 25
+ 25
+ 1
+
+
+ INTEN26
+ Enable Interrupt on line 26
+ 26
+ 1
+
+
+ INTEN27
+ Enable Interrupt on line 27
+ 27
+ 1
+
+
+
+
+ EVEN
+ EVEN
+ Event enable register (EXTI_EVEN)
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVEN0
+ Enable Event on line 0
+ 0
+ 1
+
+
+ EVEN1
+ Enable Event on line 1
+ 1
+ 1
+
+
+ EVEN2
+ Enable Event on line 2
+ 2
+ 1
+
+
+ EVEN3
+ Enable Event on line 3
+ 3
+ 1
+
+
+ EVEN4
+ Enable Event on line 4
+ 4
+ 1
+
+
+ EVEN5
+ Enable Event on line 5
+ 5
+ 1
+
+
+ EVEN6
+ Enable Event on line 6
+ 6
+ 1
+
+
+ EVEN7
+ Enable Event on line 7
+ 7
+ 1
+
+
+ EVEN8
+ Enable Event on line 8
+ 8
+ 1
+
+
+ EVEN9
+ Enable Event on line 9
+ 9
+ 1
+
+
+ EVEN10
+ Enable Event on line 10
+ 10
+ 1
+
+
+ EVEN11
+ Enable Event on line 11
+ 11
+ 1
+
+
+ EVEN12
+ Enable Event on line 12
+ 12
+ 1
+
+
+ EVEN13
+ Enable Event on line 13
+ 13
+ 1
+
+
+ EVEN14
+ Enable Event on line 14
+ 14
+ 1
+
+
+ EVEN15
+ Enable Event on line 15
+ 15
+ 1
+
+
+ EVEN16
+ Enable Event on line 16
+ 16
+ 1
+
+
+ EVEN17
+ Enable Event on line 17
+ 17
+ 1
+
+
+ EVEN18
+ Enable Event on line 18
+ 18
+ 1
+
+
+ EVEN19
+ Enable Event on line 19
+ 19
+ 1
+
+
+ EVEN20
+ Enable Event on line 20
+ 20
+ 1
+
+
+ EVEN21
+ Enable Event on line 21
+ 21
+ 1
+
+
+ EVEN22
+ Enable Event on line 22
+ 22
+ 1
+
+
+ EVEN23
+ Enable Event on line 23
+ 23
+ 1
+
+
+ EVEN24
+ Enable Event on line 24
+ 24
+ 1
+
+
+ EVEN25
+ Enable Event on line 25
+ 25
+ 1
+
+
+ EVEN26
+ Enable Event on line 26
+ 26
+ 1
+
+
+ EVEN27
+ Enable Event on line 27
+ 27
+ 1
+
+
+
+
+ RTEN
+ RTEN
+ Rising Edge Trigger Enable register
+ (EXTI_RTEN)
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTEN0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ RTEN1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ RTEN2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ RTEN3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ RTEN4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ RTEN5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ RTEN6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ RTEN7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ RTEN8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ RTEN9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ RTEN10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ RTEN11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ RTEN12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ RTEN13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ RTEN14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ RTEN15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ RTEN16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ RTEN17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ RTEN19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ RTEN21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+
+
+ FTEN
+ FTEN
+ Falling Egde Trigger Enable register
+ (EXTI_FTEN)
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FTEN0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ FTEN1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ FTEN2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ FTEN3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ FTEN4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ FTEN5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ FTEN6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ FTEN7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ FTEN8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ FTEN9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ FTEN10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ FTEN11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ FTEN12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ FTEN13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ FTEN14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ FTEN15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ FTEN16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ FTEN17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ FTEN19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ FTEN21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+
+
+ SWIEV
+ SWIEV
+ Software interrupt event register
+ (EXTI_SWIEV)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIEV0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWIEV1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWIEV2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWIEV3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWIEV4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWIEV5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWIEV6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWIEV7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWIEV8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWIEV9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWIEV10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWIEV11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWIEV12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWIEV13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWIEV14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWIEV15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWIEV16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWIEV17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWIEV19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWIEV21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+
+
+ PD
+ PD
+ Pending register (EXTI_PD)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD0
+ Pending bit 0
+ 0
+ 1
+
+
+ PD1
+ Pending bit 1
+ 1
+ 1
+
+
+ PD2
+ Pending bit 2
+ 2
+ 1
+
+
+ PD3
+ Pending bit 3
+ 3
+ 1
+
+
+ PD4
+ Pending bit 4
+ 4
+ 1
+
+
+ PD5
+ Pending bit 5
+ 5
+ 1
+
+
+ PD6
+ Pending bit 6
+ 6
+ 1
+
+
+ PD7
+ Pending bit 7
+ 7
+ 1
+
+
+ PD8
+ Pending bit 8
+ 8
+ 1
+
+
+ PD9
+ Pending bit 9
+ 9
+ 1
+
+
+ PD10
+ Pending bit 10
+ 10
+ 1
+
+
+ PD11
+ Pending bit 11
+ 11
+ 1
+
+
+ PD12
+ Pending bit 12
+ 12
+ 1
+
+
+ PD13
+ Pending bit 13
+ 13
+ 1
+
+
+ PD14
+ Pending bit 14
+ 14
+ 1
+
+
+ PD15
+ Pending bit 15
+ 15
+ 1
+
+
+ PD16
+ Pending bit 16
+ 16
+ 1
+
+
+ PD17
+ Pending bit 17
+ 17
+ 1
+
+
+ PD19
+ Pending bit 19
+ 19
+ 1
+
+
+ PD21
+ Pending bit 21
+ 21
+ 1
+
+
+
+
+
+
+ FMC
+ FMC
+ FMC
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FMC
+ 3
+
+
+
+ WS
+ WS
+ wait state register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WSCNT
+ wait state counter register
+ 0
+ 3
+
+
+ PFEN
+ Pre-fetch enable
+ 4
+ 1
+
+
+ PGW
+ Program width to flash memory
+ 15
+ 1
+
+
+
+
+ KEY
+ KEY
+ Unlock key register
+ 0x04
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ FMC_CTL unlock register
+ 0
+ 32
+
+
+
+
+ OBKEY
+ OBKEY
+ Option byte unlock key register
+ 0x08
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OBKEY
+ FMC_ CTL option bytes operation unlock register
+ 0
+ 32
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x0C
+ 0x20
+ 0x00000000
+
+
+ ENDF
+ End of operation flag bit
+ 5
+ 1
+ read-write
+
+
+ WPERR
+ Erase/Program protection error flag bit
+ 4
+ 1
+ read-write
+
+
+ PGAERR
+ Program alignment error flag bit
+ 3
+ 1
+ read-write
+
+
+ PGERR
+ Program error flag bit
+ 2
+ 1
+ read-write
+
+
+ BUSY
+ The flash is busy bit
+ 0
+ 1
+ read-only
+
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ OBRLD
+ Option byte reload bit
+ 13
+ 1
+
+
+ ENDIE
+ End of operation interrupt enable bit
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable bit
+ 10
+ 1
+
+
+ OBWEN
+ Option byte erase/program enable bit
+ 9
+ 1
+
+
+ LK
+ FMC_CTL lock bit
+ 7
+ 1
+
+
+ START
+ Send erase command to FMC bit
+ 6
+ 1
+
+
+ OBER
+ Option bytes erase command bit
+ 5
+ 1
+
+
+ OBPG
+ Option bytes program command bit
+ 4
+ 1
+
+
+ MER
+ Main flash mass erase for bank0 command bit
+ 2
+ 1
+
+
+ PER
+ Main flash page erase for bank0 command bit
+ 1
+ 1
+
+
+ PG
+ Main flash program for bank0 command bit
+ 0
+ 1
+
+
+
+
+ ADDR
+ ADDR
+ Address register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADDR
+ Flash erase/program command address bits
+ 0
+ 32
+
+
+
+
+ OBSTAT
+ OBSTAT
+ Option byte control register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OBERR
+ Option bytes read error bit
+ 0
+ 1
+
+
+ PLEVEL
+ Option bytes security protection level
+ 1
+ 2
+
+
+ USER
+ Store USER of option bytes block after system reset
+ 8
+ 8
+
+
+ DATA
+ Store DATA[15:0] of option bytes block after system reset
+ 16
+ 16
+
+
+
+
+ WP
+ WP
+ Erase/Program Protection register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WP
+ Store WP[15:0] of option bytes block after system reset
+ 0
+ 16
+
+
+
+
+ PID
+ PID
+ Product ID register
+ 0x100
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PID
+ Product reserved ID code register
+ 0
+ 32
+
+
+
+
+
+
+ FWDGT
+ free watchdog timer
+ FWDGT
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x00
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CMD
+ Key value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ Prescaler register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PSC
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLD
+ RLD
+ Reload register
+ 0x08
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RLD
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x0C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PUD
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+ RUD
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ WUD
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+
+
+ WND
+ WND
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WND
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x0C000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LKK
+ Port x lock bit y
+
+ 16
+ 1
+
+
+ LK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x48000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LKK
+ Port x lock bit y
+
+ 16
+ 1
+
+
+ LK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOC
+ General-purpose I/Os
+ GPIO
+ 0x48000800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOF
+ General-purpose I/Os
+ GPIO
+ 0x48001400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIOF port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port x Reset bit y
+ 0
+ 1
+
+
+ CR1
+ Port x Reset bit y
+ 1
+ 1
+
+
+ CR2
+ Port x Reset bit y
+ 2
+ 1
+
+
+ CR3
+ Port x Reset bit y
+ 3
+ 1
+
+
+ CR4
+ Port x Reset bit y
+ 4
+ 1
+
+
+ CR5
+ Port x Reset bit y
+ 5
+ 1
+
+
+ CR6
+ Port x Reset bit y
+ 6
+ 1
+
+
+ CR7
+ Port x Reset bit y
+ 7
+ 1
+
+
+ CR8
+ Port x Reset bit y
+ 8
+ 1
+
+
+ CR9
+ Port x Reset bit y
+ 9
+ 1
+
+
+ CR10
+ Port x Reset bit y
+ 10
+ 1
+
+
+ CR11
+ Port x Reset bit y
+ 11
+ 1
+
+
+ CR12
+ Port x Reset bit y
+ 12
+ 1
+
+
+ CR13
+ Port x Reset bit y
+ 13
+ 1
+
+
+ CR14
+ Port x Reset bit y
+ 14
+ 1
+
+
+ CR15
+ Port x Reset bit y
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ I2C0
+ Inter integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C0_EV
+ 23
+
+
+ I2C0_ER
+ 32
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SRESET
+ Software reset
+ 15
+ 1
+
+
+ SALT
+ SMBus alert
+ 13
+ 1
+
+
+ PECTRANS
+ Packet error checking
+ 12
+ 1
+
+
+ POAP
+ Acknowledge/PEC Position (for data
+ reception)
+ 11
+ 1
+
+
+ ACKEN
+ Acknowledge enable
+ 10
+ 1
+
+
+ STOP
+ Stop condition
+ 9
+ 1
+
+
+ START
+ Start generation
+ 8
+ 1
+
+
+ SS
+ SCL Stretching(Slave
+ mode)
+ 7
+ 1
+
+
+ GCEN
+ General call enable
+ 6
+ 1
+
+
+ PECEN
+ PEC enable
+ 5
+ 1
+
+
+ ARPEN
+ ARP enable
+ 4
+ 1
+
+
+ SMBSEL
+ SMBus type
+ 3
+ 1
+
+
+ SMBEN
+ SMBus mode
+ 1
+ 1
+
+
+ I2CEN
+ Peripheral enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMALST
+ Flag indicating DMA last transfer
+ 12
+ 1
+
+
+ DMAON
+ DMA mode switch
+ 11
+ 1
+
+
+ BUFIE
+ Buffer interrupt enable
+ 10
+ 1
+
+
+ EVIE
+ Event interrupt enable
+ 9
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 8
+ 1
+
+
+ I2CCLK
+ Peripheral clock frequency
+ 0
+ 7
+
+
+
+
+ SADDR0
+ SADDR0
+ Own address register 0
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADDFORMAT
+ Addressing mode (slave
+ mode)
+ 15
+ 1
+
+
+ ADDRESS
+ Interface address
+ 0
+ 10
+
+
+
+
+ SADDR1
+ SADDR1
+ Own address register 1
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADDRESS2
+ Interface address
+ 1
+ 7
+
+
+ DUADEN
+ Dual addressing mode
+ enable
+ 0
+ 1
+
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRB
+ Transmission or reception data buffer
+ 0
+ 8
+
+
+
+
+ STAT0
+ STAT0
+ Transfer status register 0
+ 0x14
+ 0x20
+ 0x0000
+
+
+ SMBALT
+ SMBus alert
+ 15
+ 1
+ read-write
+
+
+ SMBTO
+ Timeout signal in SMBus mode
+ 14
+ 1
+ read-write
+
+
+ PECERR
+ PEC error when receiving data
+ 12
+ 1
+ read-write
+
+
+ OUERR
+ Overrun/Underrun occurs in slave mode
+ 11
+ 1
+ read-write
+
+
+ AERR
+ Acknowledge error
+ 10
+ 1
+ read-write
+
+
+ LOSTARB
+ Arbitration lost (master
+ mode)
+ 9
+ 1
+ read-write
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-write
+
+
+ TBE
+ I2C_DATA is Empty during transmitting
+ 7
+ 1
+ read-only
+
+
+ RBNE
+ I2C_DATA is not Empty during receiving
+ 6
+ 1
+ read-only
+
+
+ STPDET
+ Stop detection (slave
+ mode)
+ 4
+ 1
+ read-only
+
+
+ ADD10SEND
+ Header of 10-bit address is sent in master mode
+ 3
+ 1
+ read-only
+
+
+ BTC
+ Byte transmission completed
+ 2
+ 1
+ read-only
+
+
+ ADDSEND
+ Address sent (master mode)/matched
+ (slave mode)
+ 1
+ 1
+ read-only
+
+
+ SBSEND
+ Start bit (Master mode)
+ 0
+ 1
+ read-only
+
+
+
+
+ STAT1
+ STAT1
+ Transfer status register 1
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ PECV
+ Packet error checking
+ register
+ 8
+ 8
+
+
+ DUMODF
+ Dual flag (Slave mode)
+ 7
+ 1
+
+
+ HSTSMB
+ SMBus host header (Slave
+ mode)
+ 6
+ 1
+
+
+ DEFSMB
+ SMBus device default address (Slave
+ mode)
+ 5
+ 1
+
+
+ RXGC
+ General call address (Slave
+ mode)
+ 4
+ 1
+
+
+ TR
+ Transmitter/receiver
+ 2
+ 1
+
+
+ I2CBSY
+ Bus busy
+ 1
+ 1
+
+
+ MASTER
+ Master/slave
+ 0
+ 1
+
+
+
+
+ CKCFG
+ CKCFG
+ Clock configure register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ FAST
+ I2C master mode selection
+ 15
+ 1
+
+
+ DTCY
+ Fast mode duty cycle
+ 14
+ 1
+
+
+ CLKC
+ Clock control register in Fast/Standard
+ mode (Master mode)
+ 0
+ 12
+
+
+
+
+ RT
+ RT
+ Rise time register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ RISETIME
+ Maximum rise time in master mode
+ 0
+ 7
+
+
+
+
+ SAMCS
+ SAMCS
+ SAM control and status register
+ 0x80
+ 0x20
+ read-write
+ 0x0000
+
+
+ RFR
+ Rxframe rise flag
+ 15
+ 1
+
+
+ RFF
+ Rxframe fall flag
+ 14
+ 1
+
+
+ TFR
+ Txframe rise flag
+ 13
+ 1
+
+
+ TFF
+ Txframe fall flag
+ 12
+ 1
+
+
+ RXF
+ level of rx frame signal
+ 9
+ 1
+
+
+ TXF
+ level of tx frame signal
+ 8
+ 1
+
+
+ RFRIE
+ Rx frame rise interrupt enable
+ 7
+ 1
+
+
+ RFFIE
+ Rx frame fall interrupt enable
+ 6
+ 1
+
+
+ TFRIE
+ Tx frame rise interrupt enable
+ 5
+ 1
+
+
+ TFFIE
+ Tx frame fall interrupt enable
+ 4
+ 1
+
+
+ STOEN
+ SAM_V interface timeout detect enable
+ 1
+ 1
+
+
+ SAMEN
+ SAM_V interface enable
+ 0
+ 1
+
+
+
+
+ FMPCFG
+ FMPCFG
+ Fast-mode-plus configure register
+ 0x90
+ 0x20
+ read-write
+ 0x0000
+
+
+ FMPEN
+ Fast-mode-plus enable
+ 0
+ 1
+
+
+
+
+
+
+ I2C1
+ 0x40005800
+
+ I2C1_EV
+ 24
+
+
+ I2C1_ER
+ 34
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0xF00
+ registers
+
+
+ 0x33D
+ 0xC3
+ reserved
+
+
+
+ ISER0
+ ISER0
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER1
+ ISER1
+ Interrupt Set Enable Register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER2
+ ISER2
+ Interrupt Set Enable Register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER3
+ ISER3
+ Interrupt Set Enable Register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER4
+ ISER4
+ Interrupt Set Enable Register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER5
+ ISER5
+ Interrupt Set Enable Register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER6
+ ISER6
+ Interrupt Set Enable Register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER7
+ ISER7
+ Interrupt Set Enable Register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER8
+ ISER8
+ Interrupt Set Enable Register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER9
+ ISER9
+ Interrupt Set Enable Register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER10
+ ISER10
+ Interrupt Set Enable Register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER11
+ ISER11
+ Interrupt Set Enable Register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER12
+ ISER12
+ Interrupt Set Enable Register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER13
+ ISER13
+ Interrupt Set Enable Register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER14
+ ISER14
+ Interrupt Set Enable Register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER15
+ ISER15
+ Interrupt Set Enable Register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER0
+ ICER0
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER1
+ ICER1
+ Interrupt Clear Enable
+ Register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER2
+ ICER2
+ Interrupt Clear Enable
+ Register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER3
+ ICER3
+ Interrupt Clear Enable
+ Register
+ 0x90
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER4
+ ICER4
+ Interrupt Clear Enable
+ Register
+ 0x94
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER5
+ ICER5
+ Interrupt Clear Enable
+ Register
+ 0x98
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER6
+ ICER6
+ Interrupt Clear Enable
+ Register
+ 0x9C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER7
+ ICER7
+ Interrupt Clear Enable
+ Register
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER8
+ ICER8
+ Interrupt Clear Enable
+ Register
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER9
+ ICER9
+ Interrupt Clear Enable
+ Register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER10
+ ICER10
+ Interrupt Clear Enable
+ Register
+ 0xAC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER11
+ ICER11
+ Interrupt Clear Enable
+ Register
+ 0xB0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER12
+ ICER12
+ Interrupt Clear Enable
+ Register
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER13
+ ICER13
+ Interrupt Clear Enable
+ Register
+ 0xB8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER14
+ ICER14
+ Interrupt Clear Enable
+ Register
+ 0xBC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER15
+ ICER15
+ Interrupt Clear Enable
+ Register
+ 0xC0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR0
+ ISPR0
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR1
+ ISPR1
+ Interrupt Set-Pending Register
+ 0x104
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR2
+ ISPR2
+ Interrupt Set-Pending Register
+ 0x108
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR3
+ ISPR3
+ Interrupt Set-Pending Register
+ 0x10C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR4
+ ISPR4
+ Interrupt Set-Pending Register
+ 0x110
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR5
+ ISPR5
+ Interrupt Set-Pending Register
+ 0x114
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR6
+ ISPR6
+ Interrupt Set-Pending Register
+ 0x118
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR7
+ ISPR7
+ Interrupt Set-Pending Register
+ 0x11C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR8
+ ISPR8
+ Interrupt Set-Pending Register
+ 0x120
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR9
+ ISPR9
+ Interrupt Set-Pending Register
+ 0x124
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR10
+ ISPR10
+ Interrupt Set-Pending Register
+ 0x128
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR11
+ ISPR11
+ Interrupt Set-Pending Register
+ 0x12C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR12
+ ISPR12
+ Interrupt Set-Pending Register
+ 0x130
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR13
+ ISPR13
+ Interrupt Set-Pending Register
+ 0x134
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR14
+ ISPR14
+ Interrupt Set-Pending Register
+ 0x138
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR15
+ ISPR15
+ Interrupt Set-Pending Register
+ 0x13C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR0
+ ICPR0
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR1
+ ICPR1
+ Interrupt Clear-Pending
+ Register
+ 0x184
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR2
+ ICPR2
+ Interrupt Clear-Pending
+ Register
+ 0x188
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR3
+ ICPR3
+ Interrupt Clear-Pending
+ Register
+ 0x18C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR4
+ ICPR4
+ Interrupt Clear-Pending
+ Register
+ 0x190
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR5
+ ICPR5
+ Interrupt Clear-Pending
+ Register
+ 0x194
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR6
+ ICPR6
+ Interrupt Clear-Pending
+ Register
+ 0x198
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR7
+ ICPR7
+ Interrupt Clear-Pending
+ Register
+ 0x19C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR8
+ ICPR8
+ Interrupt Clear-Pending
+ Register
+ 0x1A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR9
+ ICPR9
+ Interrupt Clear-Pending
+ Register
+ 0x1A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR10
+ ICPR10
+ Interrupt Clear-Pending
+ Register
+ 0x1A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR11
+ ICPR11
+ Interrupt Clear-Pending
+ Register
+ 0x1AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR12
+ ICPR12
+ Interrupt Clear-Pending
+ Register
+ 0x1B0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR13
+ ICPR13
+ Interrupt Clear-Pending
+ Register
+ 0x1B4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR14
+ ICPR14
+ Interrupt Clear-Pending
+ Register
+ 0x1B8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR15
+ ICPR15
+ Interrupt Clear-Pending
+ Register
+ 0x1BC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IABR0
+ IABR0
+ Interrupt Active bit
+ Register
+ 0x200
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR1
+ IABR1
+ Interrupt Active bit
+ Register
+ 0x204
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR2
+ IABR2
+ Interrupt Active bit
+ Register
+ 0x208
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR3
+ IABR3
+ Interrupt Active bit
+ Register
+ 0x20C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR4
+ IABR4
+ Interrupt Active bit
+ Register
+ 0x210
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR5
+ IABR5
+ Interrupt Active bit
+ Register
+ 0x214
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR6
+ IABR6
+ Interrupt Active bit
+ Register
+ 0x218
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR7
+ IABR7
+ Interrupt Active bit
+ Register
+ 0x21C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR8
+ IABR8
+ Interrupt Active bit
+ Register
+ 0x220
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR9
+ IABR9
+ Interrupt Active bit
+ Register
+ 0x224
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR10
+ IABR10
+ Interrupt Active bit
+ Register
+ 0x228
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR11
+ IABR11
+ Interrupt Active bit
+ Register
+ 0x22C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR12
+ IABR12
+ Interrupt Active bit
+ Register
+ 0x230
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR13
+ IABR13
+ Interrupt Active bit
+ Register
+ 0x234
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR14
+ IABR14
+ Interrupt Active bit
+ Register
+ 0x238
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR15
+ IABR15
+ Interrupt Active bit
+ Register
+ 0x23C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ ITNS0
+ ITNS0
+ Interrupt Active bit
+ Register
+ 0x280
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS1
+ ITNS1
+ Interrupt Active bit
+ Register
+ 0x284
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS2
+ ITNS2
+ Interrupt Active bit
+ Register
+ 0x288
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS3
+ ITNS3
+ Interrupt Active bit
+ Register
+ 0x28C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS4
+ ITNS4
+ Interrupt Active bit
+ Register
+ 0x290
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS5
+ ITNS5
+ Interrupt Active bit
+ Register
+ 0x294
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS6
+ ITNS6
+ Interrupt Active bit
+ Register
+ 0x298
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS7
+ ITNS7
+ Interrupt Active bit
+ Register
+ 0x29C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS8
+ ITNS8
+ Interrupt Active bit
+ Register
+ 0x2A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS9
+ ITNS9
+ Interrupt Active bit
+ Register
+ 0x2A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS10
+ ITNS10
+ Interrupt Active bit
+ Register
+ 0x2A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS11
+ ITNS11
+ Interrupt Active bit
+ Register
+ 0x2AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS12
+ ITNS12
+ Interrupt Active bit
+ Register
+ 0x2B0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS13
+ ITNS13
+ Interrupt Active bit
+ Register
+ 0x2B4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS14
+ ITNS14
+ Interrupt Active bit
+ Register
+ 0x2B8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS15
+ ITNS15
+ Interrupt Active bit
+ Register
+ 0x2BC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_00
+ PRI_00
+ 0
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x301
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_01
+ PRI_01
+ 0
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x302
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_02
+ PRI_02
+ 0
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x303
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_03
+ PRI_03
+ 0
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x304
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_04
+ PRI_04
+ 0
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x305
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_05
+ PRI_05
+ 0
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x306
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_06
+ PRI_06
+ 0
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x307
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_07
+ PRI_07
+ 0
+ 8
+
+
+
+
+ IPR8
+ IPR8
+ Interrupt Priority Register 8
+ 0x308
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_08
+ PRI_08
+ 0
+ 8
+
+
+
+
+ IPR9
+ IPR9
+ Interrupt Priority Register 9
+ 0x309
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_09
+ PRI_09
+ 0
+ 8
+
+
+
+
+ IPR10
+ IPR10
+ Interrupt Priority Register 10
+ 0x30A
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_10
+ PRI_10
+ 0
+ 8
+
+
+
+
+ IPR11
+ IPR11
+ Interrupt Priority Register 11
+ 0x30B
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_11
+ PRI_11
+ 0
+ 8
+
+
+
+
+ IPR12
+ IPR12
+ Interrupt Priority Register 12
+ 0x30C
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_12
+ PRI_12
+ 0
+ 8
+
+
+
+
+ IPR13
+ IPR13
+ Interrupt Priority Register 13
+ 0x30D
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_13
+ PRI_13
+ 0
+ 8
+
+
+
+
+ IPR14
+ IPR14
+ Interrupt Priority Register 14
+ 0x30E
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_14
+ PRI_14
+ 0
+ 8
+
+
+
+
+ IPR15
+ IPR15
+ Interrupt Priority Register 15
+ 0x30F
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_15
+ PRI_15
+ 0
+ 8
+
+
+
+
+ IPR16
+ IPR16
+ Interrupt Priority Register 16
+ 0x310
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_16
+ PRI_16
+ 0
+ 8
+
+
+
+
+ IPR17
+ IPR17
+ Interrupt Priority Register 17
+ 0x311
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_17
+ PRI_17
+ 0
+ 8
+
+
+
+
+ IPR18
+ IPR18
+ Interrupt Priority Register 18
+ 0x312
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_18
+ PRI_18
+ 0
+ 8
+
+
+
+
+ IPR19
+ IPR19
+ Interrupt Priority Register 19
+ 0x313
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_19
+ PRI_19
+ 0
+ 8
+
+
+
+
+ IPR20
+ IPR20
+ Interrupt Priority Register 20
+ 0x314
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_20
+ PRI_20
+ 0
+ 8
+
+
+
+
+ IPR21
+ IPR21
+ Interrupt Priority Register 21
+ 0x315
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_21
+ PRI_21
+ 0
+ 8
+
+
+
+
+ IPR22
+ IPR22
+ Interrupt Priority Register 22
+ 0x316
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_22
+ PRI_22
+ 0
+ 8
+
+
+
+
+ IPR23
+ IPR23
+ Interrupt Priority Register 23
+ 0x317
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_23
+ PRI_23
+ 0
+ 8
+
+
+
+
+ IPR24
+ IPR24
+ Interrupt Priority Register 24
+ 0x318
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_24
+ PRI_24
+ 0
+ 8
+
+
+
+
+ IPR25
+ IPR25
+ Interrupt Priority Register 25
+ 0x319
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_25
+ PRI_25
+ 0
+ 8
+
+
+
+
+ IPR26
+ IPR26
+ Interrupt Priority Register 26
+ 0x31A
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_26
+ PRI_26
+ 0
+ 8
+
+
+
+
+ IPR27
+ IPR27
+ Interrupt Priority Register 27
+ 0x31B
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_27
+ PRI_27
+ 0
+ 8
+
+
+
+
+ IPR28
+ IPR28
+ Interrupt Priority Register 28
+ 0x31C
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_28
+ PRI_28
+ 0
+ 8
+
+
+
+
+ IPR29
+ IPR29
+ Interrupt Priority Register 29
+ 0x31D
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_29
+ PRI_29
+ 0
+ 8
+
+
+
+
+ IPR30
+ IPR30
+ Interrupt Priority Register 30
+ 0x31E
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_30
+ PRI_30
+ 0
+ 8
+
+
+
+
+ IPR31
+ IPR31
+ Interrupt Priority Register 31
+ 0x31F
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_31
+ PRI_31
+ 0
+ 8
+
+
+
+
+
+
+ PMU
+ Power management unit
+ PMU
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00004000
+
+
+ LDOVS
+ LDO output voltage select
+ 14
+ 2
+
+
+ BKPWEN
+ Backup Domain Write Enable
+ 8
+ 1
+
+
+ LVDT
+ Low Voltage Detector Threshold
+ 5
+ 3
+
+
+ LVDEN
+ Low Voltage Detector Enable
+ 4
+ 1
+
+
+ STBRST
+ Standby Flag Reset
+ 3
+ 1
+
+
+ WURST
+ Wakeup Flag Reset
+ 2
+ 1
+
+
+ STBMOD
+ Standby Mode
+ 1
+ 1
+
+
+ LDOLP
+ LDO Low Power Mode
+ 0
+ 1
+
+
+
+
+ CS
+ CS
+ power control/status register
+ 0x04
+ 0x20
+ 0x00000000
+
+
+ WUPEN6
+ WKUP pin6 Enable
+ 14
+ 1
+ read-write
+
+
+ WUPEN5
+ WKUP pin5 Enable
+ 13
+ 1
+ read-write
+
+
+ WUPEN1
+ WKUP pin1 Enable
+ 9
+ 1
+ read-write
+
+
+ WUPEN0
+ WKUP pin0 Enable
+ 8
+ 1
+ read-write
+
+
+ LVDF
+ Low Voltage Detector Status Flag
+ 2
+ 1
+ read-only
+
+
+ STBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+
+
+
+
+ RCU
+ Reset and clock unit
+ RCU
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCU
+ 4
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ PLLSTB
+ PLL Clock Stabilization Flag
+ 25
+ 1
+ read-only
+
+
+ PLLEN
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ CKMEN
+ HXTAL Clock Monitor Enable
+ 19
+ 1
+ read-write
+
+
+ HXTALBPS
+ External crystal oscillator (HXTAL) clock bypass mode enable
+ 18
+ 1
+ read-write
+
+
+ HXTALSTB
+ External crystal oscillator (HXTAL) clock stabilization flag
+ 17
+ 1
+ read-only
+
+
+ HXTALEN
+ External High Speed oscillator Enable
+ 16
+ 1
+ read-write
+
+
+ IRC8MCALIB
+ High Speed Internal Oscillator calibration value register
+ 8
+ 8
+ read-only
+
+
+ IRC8MADJ
+ High Speed Internal Oscillator clock trim adjust value
+ 3
+ 5
+ read-write
+
+
+ IRC8MSTB
+ IRC8M High Speed Internal Oscillator stabilization Flag
+ 1
+ 1
+ read-only
+
+
+ IRC8MEN
+ Internal High Speed oscillator Enable
+ 0
+ 1
+ read-write
+
+
+
+
+ CFG0
+ CFG0
+ Clock configuration register 0
+ (RCU_CFG0)
+ 0x04
+ 0x20
+ 0x00000000
+
+
+ PLLDV
+ The CK_PLL divide by 1 or 2 for CK_OUT
+
+ 31
+ 1
+ read-write
+
+
+ CKOUTDIV
+ The CK_OUT divider which the CK_OUT frequency can be reduced
+ 28
+ 3
+ read-write
+
+
+ PLLMF_MSB
+ Bit 4 of PLLMF register
+ 27
+ 1
+ read-write
+
+
+ CKOUTSEL
+ CK_OUT Clock Source Selection
+ 24
+ 3
+ read-write
+
+
+ PLLMF
+ PLL multiply factor
+ 18
+ 4
+ read-write
+
+
+ PLLPREDV
+ HXTAL divider for PLL source clock selection.
+ 17
+ 1
+ read-write
+
+
+ PLLSEL
+ PLL Clock Source Selection
+ 16
+ 1
+ read-write
+
+
+ ADCPSC
+ ADC clock prescaler selection
+ 14
+ 2
+ read-write
+
+
+ APB2PSC
+ APB2 prescaler selection
+ 11
+ 3
+ read-write
+
+
+ APB1PSC
+ APB1 prescaler selection
+ 8
+ 3
+ read-write
+
+
+ AHBPSC
+ AHB prescaler selection
+ 4
+ 4
+ read-write
+
+
+ SCSS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ SCS
+ System clock switch
+ 0
+ 2
+ read-write
+
+
+
+
+ INT
+ INT
+ Clock interrupt register
+ (RCU_INT)
+ 0x08
+ 0x20
+ 0x00000000
+
+
+ CKMIC
+ HXTAL Clock Stuck Interrupt Clear
+ 23
+ 1
+ write-only
+
+
+ IRC28MSTBIC
+ IRC28M stabilization Interrupt Clear
+ 21
+ 1
+ write-only
+
+
+ PLLSTBIC
+ PLL stabilization Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ HXTALSTBIC
+ HXTAL Stabilization Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ IRC8MSTBIC
+ IRC8M Stabilization Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ LXTALSTBIC
+ LXTAL Stabilization Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ IRC40KSTBIC
+ IRC40K Stabilization Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ IRC28MSTBIE
+ IRC28M Stabilization Interrupt Enable
+ 13
+ 1
+ read-write
+
+
+ PLLSTBIE
+ PLL Stabilization Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ HXTALSTBIE
+ HXTAL Stabilization Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ IRC8MSTBIE
+ IRC8M Stabilization Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ LXTALSTBIE
+ LXTAL Stabilization Interrupt Enable
+ 9
+ 1
+ read-write
+
+
+ IRC40KSTBIE
+ IRC40K Stabilization interrupt enable
+ 8
+ 1
+ read-write
+
+
+ CKMIF
+ HXTAL Clock Stuck Interrupt Flag
+ 7
+ 1
+ read-only
+
+
+ IRC28MSTBIF
+ IRC28M stabilization interrupt flag
+ 5
+ 1
+ read-only
+
+
+ PLLSTBIF
+ PLL stabilization interrupt flag
+ 4
+ 1
+ read-only
+
+
+ HXTALSTBIF
+ HXTAL stabilization interrupt flag
+ 3
+ 1
+ read-only
+
+
+ IRC8MSTBIF
+ IRC8M stabilization interrupt flag
+ 2
+ 1
+ read-only
+
+
+ LXTALSTBIF
+ LXTAL stabilization interrupt flag
+ 1
+ 1
+ read-only
+
+
+ IRC40KSTBIF
+ IRC40K stabilization interrupt flag
+ 0
+ 1
+ read-only
+
+
+
+
+ APB2RST
+ APB2RST
+ APB2 reset register
+ (RCU_APB2RST)
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMER16RST
+ TIMER16 reset
+ 18
+ 1
+
+
+ TIMER15RST
+ TIMER15 reset
+ 17
+ 1
+
+
+ TIMER14RST
+ TIMER14 reset
+ 16
+ 1
+
+
+ USART0RST
+ USART0 Reset
+ 14
+ 1
+
+
+ SPI0RST
+ SPI0 Reset
+ 12
+ 1
+
+
+ TIMER0RST
+ TIMER0 reset
+ 11
+ 1
+
+
+ ADCRST
+ ADC reset
+ 9
+ 1
+
+
+ CFGCMPRST
+ System configuration and comparator reset
+ 0
+ 1
+
+
+
+
+ APB1RST
+ APB1RST
+ APB1 reset register
+ (RCU_APB1RST)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PMURST
+ Power control reset
+ 28
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 22
+ 1
+
+
+ I2C0RST
+ I2C0 reset
+ 21
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 17
+ 1
+
+
+ SPI1RST
+ SPI1 reset
+ 14
+ 1
+
+
+ WWDGTRST
+ Window watchdog timer reset
+ 11
+ 1
+
+
+ TIMER13RST
+ TIMER13 timer reset
+ 8
+ 1
+
+
+ TIMER5RST
+ TIMER5 timer reset
+ 4
+ 1
+
+
+ TIMER2RST
+ TIMER2 timer reset
+ 1
+ 1
+
+
+
+
+ AHBEN
+ AHBEN
+ AHB enable register
+ (RCU_AHBEN)
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ PFEN
+ GPIO port F clock enable
+ 22
+ 1
+
+
+ PCEN
+ GPIO port C clock enable
+ 19
+ 1
+
+
+ PBEN
+ GPIO port B clock enable
+ 18
+ 1
+
+
+ PAEN
+ GPIO port A clock enable
+ 17
+ 1
+
+
+ CRCEN
+ CRC clock enable
+ 6
+ 1
+
+
+ FMCSPEN
+ FMC clock during sleep mode enable
+ 4
+ 1
+
+
+ SRAMSPEN
+ SRAM interface clock during sleep mode enable
+ 2
+ 1
+
+
+ DMAEN
+ DMA clock enable
+ 0
+ 1
+
+
+
+
+ APB2EN
+ APB2EN
+ APB2 enable register
+ (RCU_APB2EN)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBGMCUEN
+ DBGMCU clock enable
+ 22
+ 1
+
+
+ TIMER16EN
+ TIMER16 timer clock enable
+ 18
+ 1
+
+
+ TIMER15EN
+ TIMER15 timer clock enable
+ 17
+ 1
+
+
+ TIMER14EN
+ TIMER14 timer clock enable
+ 16
+ 1
+
+
+ USART0EN
+ USART0 clock enable
+ 14
+ 1
+
+
+ SPI0EN
+ SPI0 clock enable
+ 12
+ 1
+
+
+ TIMER0EN
+ TIMER0 timer clock enable
+ 11
+ 1
+
+
+ ADCEN
+ ADC interface clock enable
+ 9
+ 1
+
+
+ CFGCMPEN
+ System configuration and comparator clock enable
+ 0
+ 1
+
+
+
+
+ APB1EN
+ APB1EN
+ APB1 enable register
+ (RCU_APB1EN)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PMUEN
+ Power interface clock enable
+ 28
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable
+ 22
+ 1
+
+
+ I2C0EN
+ I2C0 clock enable
+ 21
+ 1
+
+
+ USART1EN
+ USART1 clock enable
+ 17
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable
+ 14
+ 1
+
+
+ WWDGTEN
+ Window watchdog timer clock enable
+ 11
+ 1
+
+
+ TIMER13EN
+ TIMER13 timer clock enable
+ 8
+ 1
+
+
+ TIMER5EN
+ TIMER5 timer clock enable
+ 4
+ 1
+
+
+ TIMER2EN
+ TIMER2 timer clock enable
+ 1
+ 1
+
+
+
+
+ BDCTL
+ BDCTL
+ Backup domain control register
+ (RCU_BDCTL)
+ 0x20
+ 0x20
+ 0x00000018
+
+
+ BKPRST
+ Backup domain reset
+ 16
+ 1
+ read-write
+
+
+ RTCEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ RTCSRC
+ RTC clock entry selection
+ 8
+ 2
+ read-write
+
+
+ LXTALDRI
+ LXTAL drive capability
+ 3
+ 2
+ read-write
+
+
+ LXTALBPS
+ LXTAL bypass mode enable
+ 2
+ 1
+ read-write
+
+
+ LXTALSTB
+ External low-speed oscillator stabilization
+ 1
+ 1
+ read-only
+
+
+ LXTALEN
+ LXTAL enable
+ 0
+ 1
+ read-write
+
+
+
+
+ RSTSCK
+ RSTSCK
+ Reset source /clock register
+ (RCU_RSTSCK)
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LPRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+ WWDGTRSTF
+ Window watchdog timer reset flag
+ 30
+ 1
+ read-write
+
+
+ FWDGTRSTF
+ Free Watchdog timer reset flag
+ 29
+ 1
+ read-write
+
+
+ SWRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ PORRSTF
+ Power reset flag
+ 27
+ 1
+ read-write
+
+
+ EPRSTF
+ External PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ OBLRSTF
+ Option byte loader reset flag
+ 25
+ 1
+ read-write
+
+
+ RSTFC
+ Reset flag clear
+ 24
+ 1
+ read-write
+
+
+ V12RSTF
+ V12 domain Power reset flag
+ 23
+ 1
+ read-write
+
+
+ IRC40KSTB
+ IRC40K stabilization
+ 1
+ 1
+ read-only
+
+
+ IRC40KEN
+ IRC40K enable
+ 0
+ 1
+ read-write
+
+
+
+
+ AHBRST
+ AHBRST
+ AHB reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PFRST
+ GPIO port F reset
+ 22
+ 1
+
+
+ PCRST
+ GPIO port C reset
+ 19
+ 1
+
+
+ PBRST
+ GPIO port B reset
+ 18
+ 1
+
+
+ PARST
+ GPIO port A reset
+ 17
+ 1
+
+
+
+
+ CFG1
+ CFG1
+ Configuration register 1
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDV
+ CK_HXTAL or CK_IRC48M divider previous PLL
+ 0
+ 4
+
+
+
+
+ CFG2
+ CFG2
+ Configuration register 2
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADCPSC
+ Bit 2 of ADCPSC
+ 31
+ 1
+
+
+ IRC28MDIV
+ CK_IRC28M divider 2 or not
+ 16
+ 1
+
+
+ ADCSEL
+ CK_ADC clock source selection
+ 8
+ 1
+
+
+ USART0SEL
+ CK_USART0 clock source selection
+ 0
+ 2
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x34
+ 0x20
+ 0x00000080
+
+
+ IRC28MCALIB
+ Internal 28M RC Oscillator calibration value register
+ 8
+ 8
+ read-only
+
+
+ IRC28MADJ
+ Internal 28M RC Oscillator clock trim adjust value
+ 3
+ 5
+ read-write
+
+
+ IRC28MSTB
+ IRC28M Internal 28M RC Oscillator stabilization Flag
+ 1
+ 1
+ read-only
+
+
+ IRC28MEN
+ IRC28M Internal 28M RC oscillator Enable
+ 0
+ 1
+ read-write
+
+
+
+
+ VKEY
+ VKEY
+ Voltage key register
+ 0x100
+ 0x20
+ 0x00000000
+
+
+ KEY
+ The key of RCU_DSV register
+ 0
+ 32
+ write
+
+
+
+
+ DSV
+ DSV
+ Deep-sleep mode voltage register
+ 0x134
+ 0x20
+ 0x00000000
+
+
+ DSLPVS
+ Deep-sleep mode voltage select
+ 0
+ 2
+ read-write
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ 2
+
+
+
+ TIME
+ TIME
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM mark
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD code
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD code
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD code
+ 8
+ 4
+
+
+ SCT
+ Second tens in BCD code
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD code
+ 0
+ 4
+
+
+
+
+ DATE
+ DATE
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YRT
+ Year tens in BCD code
+ 20
+ 4
+
+
+ YRU
+ Year units in BCD code
+ 16
+ 4
+
+
+ DOW
+ Days of the week
+ 13
+ 3
+
+
+ MONT
+ Month tens in BCD code
+ 12
+ 1
+
+
+ MONU
+ Month units in BCD code
+ 8
+ 4
+
+
+ DAYT
+ Date tens in BCD code
+ 4
+ 2
+
+
+ DAYU
+ Date units in BCD code
+ 0
+ 4
+
+
+
+
+ CTL
+ CTL
+ control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ COEN
+ Calibration output enable
+ 23
+ 1
+ read-write
+
+
+ OS
+ Output selection
+ 21
+ 2
+ read-write
+
+
+ OPOL
+ Output polarity
+ 20
+ 1
+ read-write
+
+
+ COS
+ Calibration output
+ selection
+ 19
+ 1
+ read-write
+
+
+ DSM
+ Backup
+ 18
+ 1
+ read-write
+
+
+ S1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+ write-only
+
+
+ A1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+ write-only
+
+
+ TSIE
+ Time-stamp interrupt
+ enable
+ 15
+ 1
+ read-write
+
+
+ ALRM0IE
+ Alarm A interrupt enable
+ 12
+ 1
+ read-write
+
+
+ TSEN
+ timestamp enable
+ 11
+ 1
+ read-write
+
+
+ ALRM0EN
+ Alarm A enable
+ 8
+ 1
+ read-write
+
+
+ CS
+ Hour format
+ 6
+ 1
+ read-write
+
+
+ BPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+ read-write
+
+
+ REFEN
+ RTC_REFIN reference clock detection
+ enable (50 or 60 Hz)
+ 4
+ 1
+ read-write
+
+
+ TSEG
+ Time-stamp event active
+ edge
+ 3
+ 1
+ read-write
+
+
+
+
+ STAT
+ STAT
+ initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ SCPF
+ Recalibration pending Flag
+ 16
+ 1
+ read-only
+
+
+ TP1F
+ RTC_TAMP1 detection flag
+ 14
+ 1
+ read-write
+
+
+ TP0F
+ RTC_TAMP0 detection flag
+ 13
+ 1
+ read-write
+
+
+ TSOVRF
+ Time-stamp overflow flag
+ 12
+ 1
+ read-write
+
+
+ TSF
+ Time-stamp flag
+ 11
+ 1
+ read-write
+
+
+ ALRM0F
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ INITM
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ RSYNF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ YCM
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ SOPF
+ Shift operation pending
+ 3
+ 1
+ read-only
+
+
+ ALRM0WF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ FACTOR_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ FACTOR_S
+ Synchronous prescaler
+ factor
+ 0
+ 15
+
+
+
+
+ ALRM0TD
+ ALRM0TD
+ alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSKD
+ Alarm date mask
+ 31
+ 1
+
+
+ DOWS
+ Week day selection
+ 30
+ 1
+
+
+ DAYT
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DAYU
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ MSKH
+ Alarm hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MSKM
+ Alarm minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ MSKS
+ Alarm seconds mask
+ 7
+ 1
+
+
+ SCT
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ WPK
+ WPK
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ WPK
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SS
+ SS
+ sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSC
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTCTL
+ SHIFTCTL
+ shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ A1S
+ One second add
+ 31
+ 1
+
+
+ SFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TTS
+ TTS
+ timestamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM mark
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD code
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD code
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD code
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD code
+ 8
+ 4
+
+
+ SCT
+ Second tens in BCD code
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD code
+ 0
+ 4
+
+
+
+
+ DTS
+ DTS
+ Date of time stamp register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DOW
+ Week day units
+ 13
+ 3
+
+
+ MONT
+ Month tens in BCD code
+ 12
+ 1
+
+
+ MONU
+ Month units in BCD code
+ 8
+ 4
+
+
+ DAYT
+ Date tens in BCD code
+ 5
+ 2
+
+
+ DAYU
+ Date units in BCD code
+ 0
+ 5
+
+
+
+
+ SSTS
+ SSTS
+ time-stamp sub second register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSC
+ Sub second value
+ 0
+ 16
+
+
+
+
+ HRFC
+ HRFC
+ High resolution frequency compensation register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FREQI
+ Increase RTC frequency by 488.5PPM
+ 15
+ 1
+
+
+ CWND8
+ Frequency compensation window 8 second selected
+ 14
+ 1
+
+
+ CWND16
+ Frequency compensation window 16 second selected
+ 13
+ 1
+
+
+ CMSK
+ Calibration mask number
+ 0
+ 9
+
+
+
+
+ TAMP
+ TAMP
+ tamper and alternate function configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PC15MDE
+ PC15 mode
+ 23
+ 1
+
+
+ PC15VAL
+ PC15 value
+ 22
+ 1
+
+
+ PC14MDE
+ PC14 mode
+ 21
+ 1
+
+
+ PC14VAL
+ PC14 value
+ 20
+ 1
+
+
+ PC13MDE
+ PC13 mode
+ 19
+ 1
+
+
+ PC13VAL
+ RTC_ALARM output type/PC13
+ value
+ 18
+ 1
+
+
+ DISPU
+ RTC_TAMPx pull-up disable
+ 15
+ 1
+
+
+ PRCH
+ RTC_TAMPx precharge
+ duration
+ 13
+ 2
+
+
+ FLT
+ RTC_TAMPx filter count
+ 11
+ 2
+
+
+ FREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TPTS
+ Activate timestamp on tamper detection
+ event
+ 7
+ 1
+
+
+ TP1EG
+ Tamper 1 event trigger edge
+ 4
+ 1
+
+
+ TP1EN
+ Tamper 1 detection enable
+ 3
+ 1
+
+
+ TPIE
+ Tamper detection interrupt enable
+ 2
+ 1
+
+
+ TP0EG
+ Active level for RTC_TAMP1
+ input
+ 1
+ 1
+
+
+ TP0EN
+ Tamper 0 event trigger edge
+ 0
+ 1
+
+
+
+
+ ALRM0SS
+ ALRM0SS
+ alarm 0 sub second register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSKSSC
+ Mask control bit of SSC
+ 24
+ 4
+
+
+ SSC
+ Alarm sub second value
+ 0
+ 15
+
+
+
+
+ BKP0
+ BKP0
+ backup register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP1
+ BKP1
+ backup register
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP2
+ BKP2
+ backup register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP3
+ BKP3
+ backup register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP4
+ BKP4
+ backup register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+
+
+ SPI0
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI0
+ 25
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BDEN
+ Bidirectional enable
+ 15
+ 1
+
+
+ BDOEN
+ Bidirectional Transmit output enable
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation enable
+ 13
+ 1
+
+
+ CRCNT
+ CRC transfer next
+ 12
+ 1
+
+
+ FF16
+ Data frame format
+ 11
+ 1
+
+
+ RO
+ Receive only
+ 10
+ 1
+
+
+ SWNSSEN
+ NSS Software Mode Selection
+ 9
+ 1
+
+
+ SWNSS
+ NSS Pin Selection In NSS Software Mode
+ 8
+ 1
+
+
+ LF
+ LSB First Mode
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ PSC
+ Master Clock Prescaler Selection
+ 3
+ 3
+
+
+ MSTMOD
+ Master Mode Enable
+ 2
+ 1
+
+
+ CKPL
+ Clock Polarity Selection
+ 1
+ 1
+
+
+ CKPH
+ Clock Phase Selection
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TBEIE
+ Transmit Buffer Empty Interrupt Enable
+ 7
+ 1
+
+
+ RBNEIE
+ Receive Buffer Not Empty Interrupt Enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ TMOD
+ SPI TI Mode Enable
+ 4
+ 1
+
+
+ NSSP
+ SPI NSS Pulse Mode Enable
+ 3
+ 1
+
+
+ NSSDRV
+ NSS output enable
+ 2
+ 1
+
+
+ DMATEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ DMAREN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ status register
+ 0x08
+ 0x20
+ 0x0002
+
+
+ FERR
+ Format Error
+ 8
+ 1
+ read-write
+
+
+ TRANS
+ Transmitting On-going Bit
+ 7
+ 1
+ read-only
+
+
+ RXORERR
+ Reception Overrun Error Bit
+ 6
+ 1
+ read-only
+
+
+ CONFERR
+ SPI Configuration error
+ 5
+ 1
+ read-only
+
+
+ CRCERR
+ SPI CRC Error Bit
+ 4
+ 1
+ read-write
+
+
+ TXURERR
+ Transmission underrun error bit
+ 3
+ 1
+ read-only
+
+
+ I2SCH
+ I2S channel side
+ 2
+ 1
+ read-only
+
+
+ TBE
+ Transmit Buffer Empty
+ 1
+ 1
+ read-only
+
+
+ RBNE
+ Receive Buffer Not Empty
+ 0
+ 1
+ read-only
+
+
+
+
+ DATA
+ DATA
+ data register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Data register
+ 0
+ 16
+
+
+
+
+ CPCPOLY
+ CPCPOLY
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ RX RCR register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCTL
+ I2SCTL
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SSEL
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOPMOD
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSMOD
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPL
+ Idle state clock polarity
+ 3
+ 1
+
+
+ DTLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPSC
+ I2SPSC
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ MCKOEN
+ I2S_MCK output enable
+ 9
+ 1
+
+
+ OF
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ DIV
+ Dividing factor for the prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI1
+ Serial Peripheral Interface 1
+ 0x40003800
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ 26
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BDEN
+ Bidirectional enable
+ 15
+ 1
+
+
+ BDOEN
+ Bidirectional Transmit output enable
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation enable
+ 13
+ 1
+
+
+ CRCNT
+ CRC transfer next
+ 12
+ 1
+
+
+ CRCL
+ CRC length
+ 11
+ 1
+
+
+ RO
+ Receive only
+ 10
+ 1
+
+
+ SWNSSEN
+ NSS Software Mode Selection
+ 9
+ 1
+
+
+ SWNSS
+ NSS Pin Selection In NSS Software Mode
+ 8
+ 1
+
+
+ LF
+ LSB First Mode
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ PSC
+ Master Clock Prescaler Selection
+ 3
+ 3
+
+
+ MSTMOD
+ Master Mode Enable
+ 2
+ 1
+
+
+ CKPL
+ Clock Polarity Selection
+ 1
+ 1
+
+
+ CKPH
+ Clock Phase Selection
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXDMA_ODD
+ Odd bytes in TX DMA channel
+ 14
+ 1
+
+
+ RXDMA_ODD
+ Odd bytes in RX DMA channel
+ 13
+ 1
+
+
+ BYTEN
+ Byte access enable
+ 12
+ 1
+
+
+ DZ
+ Date size
+ 8
+ 4
+
+
+ TBEIE
+ Transmit Buffer Empty Interrupt Enable
+ 7
+ 1
+
+
+ RBNEIE
+ Receive Buffer Not Empty Interrupt Enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ TMOD
+ SPI TI Mode Enable
+ 4
+ 1
+
+
+ NSSP
+ SPI NSS Pulse Mode Enable
+ 3
+ 1
+
+
+ NSSDRV
+ NSS output enable
+ 2
+ 1
+
+
+ DMATEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ DMAREN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ status register
+ 0x08
+ 0x20
+ 0x0002
+
+
+ TXLVL
+ Tx FIFO level
+ 11
+ 2
+ read-only
+
+
+ RXLVL
+ Rx FIFO level
+ 9
+ 2
+ read-only
+
+
+ FERR
+ Format Error
+ 8
+ 1
+ read-write
+
+
+ TRANS
+ Transmitting On-going Bit
+ 7
+ 1
+ read-only
+
+
+ RXORERR
+ Reception Overrun Error Bit
+ 6
+ 1
+ read-only
+
+
+ CONFERR
+ SPI Configuration error
+ 5
+ 1
+ read-only
+
+
+ CRCERR
+ SPI CRC Error Bit
+ 4
+ 1
+ read-write
+
+
+ TBE
+ Transmit Buffer Empty
+ 1
+ 1
+ read-only
+
+
+ RBNE
+ Receive Buffer Not Empty
+ 0
+ 1
+ read-only
+
+
+
+
+ DATA
+ DATA
+ data register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Data register
+ 0
+ 16
+
+
+
+
+ CPCPOLY
+ CPCPOLY
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ RX RCR register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCTL
+ I2SCTL
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SSEL
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOPMOD
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSMOD
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPL
+ Idle state clock polarity
+ 3
+ 1
+
+
+ DTLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPSC
+ I2SPSC
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ MCKOEN
+ I2S_MCK output enable
+ 9
+ 1
+
+
+ OF
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ DIV
+ Dividing factor for the prescaler
+ 0
+ 8
+
+
+
+
+ QCTL
+ QCTL
+ SPI quad wird control register
+ 0x80
+ 0x20
+ read-write
+ 0000
+
+
+ IO23_DRV
+ Drive IO2 and IO3 enable
+ 2
+ 1
+
+
+ QRD
+ Quad wire read select
+ 1
+ 1
+
+
+ QMOD
+ Quad wire mode enable
+ 0
+ 1
+
+
+
+
+
+
+
+ SYSCFG
+ System configuration controller
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x0400
+ registers
+
+
+
+ CFG0
+ CFG0
+ System configuration register 0
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PB9_HCCE
+ PB9 pin high current capability enable
+ 19
+ 1
+
+
+ TIMER16_DMA_RMP
+ Timer 16 DMA request remapping enable
+ 12
+ 1
+
+
+ TIMER15_DMA_RMP
+ Timer 15 DMA request remapping enable
+ 11
+ 1
+
+
+ USART0_RX_DMA_RMP
+ USART0_RX DMA request remapping enable
+ 10
+ 1
+
+
+ USART0_TX_DMA_RMP
+ USART0_TX DMA request remapping enable
+ 9
+ 1
+
+
+ ADC_DMA_RMP
+ ADC DMA request remapping enable
+ 8
+ 1
+
+
+ PA11_PA12_RMP
+ PA11 and PA12 remapping bit for small packages
+ 4
+ 1
+
+
+ BOOT_MODE
+ Boot mode
+ 0
+ 2
+ read-only
+
+
+
+
+ EXTISS0
+ EXTISS0
+ EXTI sources selection register
+ 0
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI3_SS
+ EXTI 3 sources selection
+ 12
+ 4
+
+
+ EXTI2_SS
+ EXTI 2 sources selection
+ 8
+ 4
+
+
+ EXTI1_SS
+ EXTI 1 sources selection
+ 4
+ 4
+
+
+ EXTI0_SS
+ EXTI 0 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS1
+ EXTISS1
+ EXTI sources selection register
+ 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI7_SS
+ EXTI 7 sources selection
+ 12
+ 4
+
+
+ EXTI6_SS
+ EXTI 6 sources selection
+ 8
+ 4
+
+
+ EXTI5_SS
+ EXTI 5 sources selection
+ 4
+ 4
+
+
+ EXTI4_SS
+ EXTI 4 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS2
+ EXTISS2
+ EXTI sources selection register
+ 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI11_SS
+ EXTI 11 sources selection
+ 12
+ 4
+
+
+ EXTI10_SS
+ EXTI 10 sources selection
+ 8
+ 4
+
+
+ EXTI9_SS
+ EXTI 9 sources selection
+ 4
+ 4
+
+
+ EXTI8_SS
+ EXTI 8 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS3
+ EXTISS3
+ EXTI sources selection register
+ 3
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI15_SS
+ EXTI 15 sources selection
+ 12
+ 4
+
+
+ EXTI14_SS
+ EXTI 14 sources selection
+ 8
+ 4
+
+
+ EXTI13_SS
+ EXTI 13 sources selection
+ 4
+ 4
+
+
+ EXTI12_SS
+ EXTI 12 sources selection
+ 0
+ 4
+
+
+
+
+ CFG2
+ CFG2
+ System configuration register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SRAM_PCEF
+ SRAM parity check error flag
+ 8
+ 1
+
+
+ LVD_LOCK
+ LVD lock
+ 2
+ 1
+
+
+ SRAM_PARITY_ERROR_LOCK
+ SRAM parity check error lock
+ 1
+ 1
+
+
+ LOCKUP_LOCK
+ Cortex-M4 LOCKUP output lock
+ 0
+ 1
+
+
+
+
+ CPU_IRQ_LAT
+ CPU_IRQ_LAT
+ IRQ Latency register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IRQ_LATENCY
+ specifies the minimum number of cycles between an interrupt
+ 0
+ 8
+
+
+
+
+
+
+ TIMER0
+ Advanced-timers
+ TIMER
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER0_BRK_UP_TRG_COM
+ 13
+
+
+ TIMER0_CC
+ 14
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CAM
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO3
+ Idle state of channel 3 output
+ 14
+ 1
+
+
+ ISO2N
+ Idle state of channel 2 complementary output
+ 13
+ 1
+
+
+ ISO2
+ Idle state of channel 2 output
+ 12
+ 1
+
+
+ ISO1N
+ Idle state of channel 1 complementary output
+ 11
+ 1
+
+
+ ISO1
+ Idle state of channel 1 output
+ 10
+ 1
+
+
+ ISO0N
+ Idle state of channel 0 complementary output
+ 9
+ 1
+
+
+ ISO0
+ Idle state of channel 0 output
+ 8
+ 1
+
+
+ TI0S
+ Channel 0 trigger input selection
+ 7
+ 1
+
+
+ MMC
+ Master mode control
+ 4
+ 3
+
+
+ DMAS
+ DMA request source selection
+ 3
+ 1
+
+
+ CCUC
+ Commutation control shadow register update control
+ 2
+ 1
+
+
+ CCSE
+ Commutation control shadow enable
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SCM1
+ Part of SMC for enable External clock mode1
+ 14
+ 1
+
+
+ ETPSC
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETFC
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ OCRC
+ Trigger selection
+ 3
+ 1
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CMTDEN
+ Reserved
+ 13
+ 1
+
+
+ CH3DEN
+ Capture/Compare 3 DMA request
+ enable
+ 12
+ 1
+
+
+ CH2DEN
+ Capture/Compare 2 DMA request
+ enable
+ 11
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH3IE
+ Capture/Compare 3 interrupt
+ enable
+ 4
+ 1
+
+
+ CH2IE
+ Capture/Compare 2 interrupt
+ enable
+ 3
+ 1
+
+
+ CH1IE
+ Capture/Compare 1 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3OF
+ Channel 3 over capture flag
+ 12
+ 1
+
+
+ CH2OF
+ Channel 2 over capture flag
+ 11
+ 1
+
+
+ CH1OF
+ Channel 1 over capture flag
+ 10
+ 1
+
+
+ CH0OF
+ Channel 0 over capture flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH3IF
+ Capture/Compare 3 interrupt
+ flag
+ 4
+ 1
+
+
+ CH2IF
+ Capture/Compare 2 interrupt
+ flag
+ 3
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ Software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break event generation
+ 7
+ 1
+
+
+ TRGG
+ Trigger event generation
+ 6
+ 1
+
+
+ CMTG
+ Channel commutation event generation
+ 5
+ 1
+
+
+ CH3G
+ Channel 3's capture or compare event generation
+ 4
+ 1
+
+
+ CH2G
+ Channel 2's capture or compare event generation
+ 3
+ 1
+
+
+ CH1G
+ Channel 1's capture or compare event generation
+ 2
+ 1
+
+
+ CH0G
+ Channel 0's capture or compare event generation
+ 1
+ 1
+
+
+ UPG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1COMCEN
+ Channel 1 output compare clear enable
+ 15
+ 1
+
+
+ CH1COMCTL
+ Channel 1 compare output control
+ 12
+ 3
+
+
+ CH1COMSEN
+ Channel 1 output compare shadow enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Channel 1 output compare fast enable
+ 10
+ 1
+
+
+ CH1MS
+ Channel 1 mode selection
+ 8
+ 2
+
+
+ CH0COMCEN
+ Channel 0 output compare clear enable
+ 7
+ 1
+
+
+ CH0COMCTL
+ Channel 0 compare output control
+ 4
+ 3
+
+
+ CH0COMSEN
+ Channel 0 compare output shadow enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Channel 0 output compare fast enable
+ 2
+ 1
+
+
+ CH0MS
+ Channel 0 I/O mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1CAPFLT
+ Channel 1 input capture filter control
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Channel 1 input capture prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Channel 1 mode selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Channel 0 input capture filter control
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Channel 0 input capture prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Channel 0 mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Output
+ CHCTL1_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3COMCEN
+ Channel 3 output compare clear enable
+ 15
+ 1
+
+
+ CH3COMCTL
+ Channel 3 compare output control
+ 12
+ 3
+
+
+ CH3COMSEN
+ Channel 3 output compare shadow enable
+ 11
+ 1
+
+
+ CH3COMFEN
+ Channel 3 output compare fast enable
+ 10
+ 1
+
+
+ CH3MS
+ Channel 3 mode selection
+ 8
+ 2
+
+
+ CH2COMCEN
+ Channel 2 output compare clear enable
+ 7
+ 1
+
+
+ CH2COMCTL
+ Channel 2 compare output control
+ 4
+ 3
+
+
+ CH2COMSEN
+ Channel 2 compare output shadow enable
+ 3
+ 1
+
+
+ CH2COMFEN
+ Channel 2 output compare fast enable
+ 2
+ 1
+
+
+ CH2MS
+ Channel 2 I/O mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Input
+ CHCTL1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CHCTL1_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3CAPFLT
+ Channel 3 input capture filter control
+ 12
+ 4
+
+
+ CH3CAPPSC
+ Channel 3 input capture prescaler
+ 10
+ 2
+
+
+ CH3MS
+ Channel 3 mode selection
+ 8
+ 2
+
+
+ CH2CAPFLT
+ Input capture 2 filter
+ 4
+ 4
+
+
+ CH2CAPPSC
+ Input capture 2 prescaler
+ 2
+ 2
+
+
+ CH2MS
+ Capture/compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CH3EN
+ Capture/Compare 3 output
+ enable
+ 12
+ 1
+
+
+ CH2NP
+ Capture/Compare 2 output
+ Polarity
+ 11
+ 1
+
+
+ CH2NEN
+ Capture/Compare 2 complementary output
+ enable
+ 10
+ 1
+
+
+ CH2P
+ Capture/Compare 2 output
+ Polarity
+ 9
+ 1
+
+
+ CH2EN
+ Capture/Compare 2 output
+ enable
+ 8
+ 1
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1NEN
+ Capture/Compare 1 complementary output
+ enable
+ 6
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Counter auto reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 1
+ 0x38
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CH2CV
+ CH2CV
+ capture/compare register 2
+ 0x3C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH2VAL
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CH3CV
+ CH3CV
+ capture/compare register 3
+ 0x40
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3VAL
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ channel complementary protection register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ Lock configuration
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator setup
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA transfer count
+ 8
+ 5
+
+
+ DMATA
+ DMA transfer access start address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ Configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+
+
+
+
+ TIMER2
+ General-purpose-timers
+ TIMER
+ 0x40000400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER2
+ 16
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CAM
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI0S
+ TI0 selection
+ 7
+ 1
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode control register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMC1
+ External clock enable
+ 14
+ 1
+
+
+ ETPSC
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETFC
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ OCRC
+ OCREF clear source selection
+ 3
+ 1
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CH3DEN
+ Capture/Compare 3 DMA request
+ enable
+ 12
+ 1
+
+
+ CH2DEN
+ Capture/Compare 2 DMA request
+ enable
+ 11
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CH3IE
+ Capture/Compare 3 interrupt
+ enable
+ 4
+ 1
+
+
+ CH2IE
+ Capture/Compare 2 interrupt
+ enable
+ 3
+ 1
+
+
+ CH1IE
+ Capture/Compare 1 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3OF
+ Capture/Compare 3 overcapture
+ flag
+ 12
+ 1
+
+
+ CH2OF
+ Capture/Compare 2 overcapture
+ flag
+ 11
+ 1
+
+
+ CH1OF
+ Capture/compare 1 overcapture
+ flag
+ 10
+ 1
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CH3IF
+ Capture/Compare 3 interrupt
+ flag
+ 4
+ 1
+
+
+ CH2IF
+ Capture/Compare 2 interrupt
+ flag
+ 3
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TRGG
+ Trigger generation
+ 6
+ 1
+
+
+ CH3G
+ Capture/compare 3
+ generation
+ 4
+ 1
+
+
+ CH2G
+ Capture/compare 2
+ generation
+ 3
+ 1
+
+
+ CH1G
+ Capture/compare 1
+ generation
+ 2
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register 0 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1COMCEN
+ Output compare 1 clear
+ enable
+ 15
+ 1
+
+
+ CH1COMCTL
+ Output compare 1 mode
+ 12
+ 3
+
+
+ CH1COMSEN
+ Output compare 1 preload
+ enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Output compare 1 fast
+ enable
+ 10
+ 1
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0COMCEN
+ Output compare 0 clear
+ enable
+ 7
+ 1
+
+
+ CH0COMCTL
+ Output compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CAPFLT
+ Input capture 1 filter
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Input capture 1 prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Capture/compare 1
+ selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Output
+ CHCTL1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3COMCEN
+ Output compare 3 clear
+ enable
+ 15
+ 1
+
+
+ CH3COMCTL
+ Output compare 3 mode
+ 12
+ 3
+
+
+ CH3COMSEN
+ Output compare 3 preload
+ enable
+ 11
+ 1
+
+
+ CH3COMFEN
+ Output compare 3 fast
+ enable
+ 10
+ 1
+
+
+ CH3MS
+ Capture/Compare 3
+ selection
+ 8
+ 2
+
+
+ CH2COMCEN
+ Output compare 2 clear
+ enable
+ 7
+ 1
+
+
+ CH2COMCTL
+ Output compare 2 mode
+ 4
+ 3
+
+
+ CH2COMSEN
+ Output compare 2 preload
+ enable
+ 3
+ 1
+
+
+ CH2COMFEN
+ Output compare 2 fast
+ enable
+ 2
+ 1
+
+
+ CH2MS
+ Capture/Compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Input
+ CHCTL1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CHCTL1_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3CAPFLT
+ Input capture 3 filter
+ 12
+ 4
+
+
+ CH3CAPPSC
+ Input capture 3 prescaler
+ 10
+ 2
+
+
+ CH3MS
+ Capture/Compare 3
+ selection
+ 8
+ 2
+
+
+ CH2CAPFLT
+ Input capture 2 filter
+ 4
+ 4
+
+
+ CH2CAPPSC
+ Input capture 2 prescaler
+ 2
+ 2
+
+
+ CH2MS
+ Capture/Compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3NP
+ Capture/Compare 3 output
+ Polarity
+ 15
+ 1
+
+
+ CH3P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CH3EN
+ Capture/Compare 3 output
+ enable
+ 12
+ 1
+
+
+ CH2NP
+ Capture/Compare 2 output
+ Polarity
+ 11
+ 1
+
+
+ CH2P
+ Capture/Compare 2 output
+ Polarity
+ 9
+ 1
+
+
+ CH2EN
+ Capture/Compare 2 output
+ enable
+ 8
+ 1
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0VAL
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1VAL
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CH2CV
+ CH2CV
+ capture/compare register 2
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2VAL
+ High Capture/Compare value (TIM2
+ only)
+ 0
+ 16
+
+
+
+
+ CH3CV
+ CH3CV
+ capture/compare register 3
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3VAL
+ High Capture/Compare value (TIM2
+ only)
+ 0
+ 16
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA burst length
+ 8
+ 5
+
+
+ DMATA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ Configuration
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER5
+ Basic-timers
+ TIMER
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER5
+ 17
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIMER13
+ General-purpose-timers
+ TIMER
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER13
+ 19
+
+
+
+ CTL0
+ CTL0
+ control register 1
+ 0x00
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+ CH0COMFEN
+ Output compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ IRMP
+ IRMP
+ channel input remap register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ CI0_RMP
+ Timer input 0 remap
+ 0
+ 2
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER14
+ General-purpose-timers
+ TIMER
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER14
+ 20
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO1
+ Output Idle state 1
+ 10
+ 1
+
+
+ ISO0N
+ Output Idle state 0
+ 9
+ 1
+
+
+ ISO0
+ Output Idle state 0
+ 8
+ 1
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUC
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCSE
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CMTDEN
+ Commutation DMA request enable
+ 13
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH1IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1OF
+ Capture/compare 1 overcapture
+ flag
+ 10
+ 1
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break generation
+ 7
+ 1
+
+
+ TRGG
+ Trigger generation
+ 6
+ 1
+
+
+ CMTG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CH1G
+ Capture/compare 1
+ generation
+ 2
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1COMCTL
+ Output Compare 1 mode
+ 12
+ 3
+
+
+ CH1COMSEN
+ Output Compare 1 preload
+ enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Output Compare 1 fast
+ enable
+ 10
+ 1
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output Compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CAPFLT
+ Input capture 1 filter
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Input capture 1 prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 1
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ complementary register protect control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator configure
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA burst length
+ 8
+ 5
+
+
+ DMATA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA transfer buffer register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+
+
+
+
+ TIMER15
+ General-purpose-timers
+ TIMER
+ 0x40014400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER15
+ 21
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO0N
+ Output Idle state 0
+ 9
+ 1
+
+
+ ISO0
+ Output Idle state 0
+ 8
+ 1
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUC
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCSE
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break generation
+ 7
+ 1
+
+
+ CMTG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output Compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ complementary register protect control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator setup
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA transfer count
+ 8
+ 5
+
+
+ DMATA
+ DMA transfer access start address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA transfer buffer register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER16
+ 0x40014800
+
+ TIMER16
+ 22
+
+
+
+ USART0
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART0
+ 27
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEA
+ Driver Enable assertion
+ time
+ 21
+ 5
+
+
+ DED
+ Driver Enable deassertion
+ time
+ 16
+ 5
+
+
+ OVSMOD
+ Oversampling mode
+ 15
+ 1
+
+
+ AMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MEN
+ Mute mode enable
+ 13
+ 1
+
+
+ WL
+ Word length
+ 12
+ 1
+
+
+ WM
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCEN
+ Parity control enable
+ 10
+ 1
+
+
+ PM
+ Parity selection
+ 9
+ 1
+
+
+ PERRIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TBEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RBNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TEN
+ Transmitter enable
+ 3
+ 1
+
+
+ REN
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UEN
+ USART enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADDR
+ Address of the USART node
+ 24
+ 8
+
+
+ RTEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABDM
+ Auto baud rate mode
+ 21
+ 2
+
+
+ ABDEN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBF
+ Most significant bit first
+ 19
+ 1
+
+
+ DINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ STRP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LMEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STB
+ STOP bits
+ 12
+ 2
+
+
+ CKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPL
+ Clock polarity
+ 10
+ 1
+
+
+ CPH
+ Clock phase
+ 9
+ 1
+
+
+ CLEN
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBLEN
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CTL2
+ CTL2
+ Control register 2
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUM
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCRTNUM
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRD
+ Overrun Disable
+ 12
+ 1
+
+
+ OSB
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSEN
+ CTS enable
+ 9
+ 1
+
+
+ RTSEN
+ RTS enable
+ 8
+ 1
+
+
+ DENT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DENR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NKEN
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDEN
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BAUD
+ BAUD
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BRR_INT
+ integer of baud-rate divider
+ 4
+ 12
+
+
+ BRR_FRA
+ integer of baud-rate divider
+ 0
+ 4
+
+
+
+
+ GP
+ GP
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ GUAT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RT
+ RT
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BL
+ Block Length
+ 24
+ 8
+
+
+ RT
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ CMD
+ CMD
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TXFCMD
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFCMD
+ Receive data flush request
+ 3
+ 1
+
+
+ MMCMD
+ Mute mode request
+ 2
+ 1
+
+
+ SBKCMD
+ Send break request
+ 1
+ 1
+
+
+ ABDCMD
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x000000C0
+
+
+ REA
+ Receive enable acknowledge
+ flag
+ 22
+ 1
+
+
+ TEA
+ Transmit enable acknowledge
+ flag
+ 21
+ 1
+
+
+ WUF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RWU
+ Receiver wakeup from Mute
+ mode
+ 19
+ 1
+
+
+ SBF
+ Send break flag
+ 18
+ 1
+
+
+ AMF
+ character match flag
+ 17
+ 1
+
+
+ BSY
+ Busy flag
+ 16
+ 1
+
+
+ ABDF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABDE
+ Auto baud rate error
+ 14
+ 1
+
+
+ EBF
+ End of block flag
+ 12
+ 1
+
+
+ RTF
+ Receiver timeout
+ 11
+ 1
+
+
+ CTS
+ CTS flag
+ 10
+ 1
+
+
+ CTSF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LBDF
+ LIN break detection flag
+ 8
+ 1
+
+
+ TBE
+ Transmit data register
+ empty
+ 7
+ 1
+
+
+ TC
+ Transmission complete
+ 6
+ 1
+
+
+ RBNE
+ Read data register not
+ empty
+ 5
+ 1
+
+
+ IDLEF
+ Idle line detected
+ 4
+ 1
+
+
+ ORERR
+ Overrun error
+ 3
+ 1
+
+
+ NERR
+ Noise detected flag
+ 2
+ 1
+
+
+ FERR
+ Framing error
+ 1
+ 1
+
+
+ PERR
+ Parity error
+ 0
+ 1
+
+
+
+
+ INTC
+ INTC
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x00000000
+
+
+ WUC
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ AMC
+ Character match clear flag
+ 17
+ 1
+
+
+ EBC
+ End of timeout clear flag
+ 12
+ 1
+
+
+ RTC
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSC
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDC
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCC
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLEC
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ OREC
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NEC
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FEC
+ Framing error clear flag
+ 1
+ 1
+
+
+ PEC
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDATA
+ RDATA
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RDATA
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDATA
+ TDATA
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TDATA
+ Transmit data value
+ 0
+ 9
+
+
+
+
+ CHC
+ CHC
+ coherence control register
+ 0xC0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EPERR
+ Early parity error flag
+ 8
+ 1
+
+
+ HCM
+ Hardware flow control coherence mode
+ 0
+ 1
+
+
+
+
+ RFCS
+ RFCS
+ USART receive FIFO control and status register
+ 0xD0
+ 0x20
+ 0x00000400
+
+
+ RFFINT
+ Receive FIFO full interrupt flag
+ 15
+ 1
+ read-write
+
+
+ RFCNT
+ Receive FIFO count number
+ 12
+ 3
+ read-only
+
+
+ RFF
+ Receive FIFO full flag
+ 11
+ 1
+ read-only
+
+
+ RFE
+ Receive FIFO empty flag
+ 10
+ 1
+ read-only
+
+
+ RFFIE
+ Receive FIFO full interrupt enable
+ 9
+ 1
+ read-write
+
+
+ RFEN
+ Receive FIFO enable
+ 8
+ 1
+ read-write
+
+
+ ELNACK
+ Early NKEN when smartcard mode is selected
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ USART1
+ 0x40004400
+
+ USART1
+ 28
+
+
+
+ WWDGT
+ Window watchdog timer
+ WWDGT
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDGT
+ 0
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGTEN
+ Activation bit
+ 7
+ 1
+
+
+ CNT
+ 7-bit counter
+ 0
+ 7
+
+
+
+
+ CFG
+ CFG
+ Configuration register
+ 0x04
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWIE
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ PSC
+ Prescaler
+ 7
+ 2
+
+
+ WIN
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+
+
+
diff --git a/GD32E231.svd b/GD32E231.svd
new file mode 100644
index 0000000..92021af
--- /dev/null
+++ b/GD32E231.svd
@@ -0,0 +1,19664 @@
+
+
+ GD32E231
+ 1.0
+ GD32E231 ARM 32-bit Cortex-M23 Microcontroller based device
+
+ CM23
+ r0p0
+ little
+ 1
+ 1
+ 4
+ 0
+
+ 8
+ 32
+
+
+
+
+ 0x20
+ 0x0
+ 0xFFFFFFFF
+
+
+ ADC
+ Analog to digital converter
+ ADC
+ 0x40012400
+
+ 0x0
+ 0x400
+ registers
+
+
+ ADC_CMP
+ 12
+
+
+
+ STAT
+ STAT
+ status register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ STRC
+ Start flag of regular channel group
+ 4
+ 1
+
+
+ STIC
+ Start flag of inserted channel group
+ 3
+ 1
+
+
+ EOIC
+ End of inserted group conversion flag
+ 2
+ 1
+
+
+ EOC
+ End of group conversion flag
+ 1
+ 1
+
+
+ WDE
+ Analog watchdog event flag
+ 0
+ 1
+
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DRES
+ ADC resolution
+ 24
+ 2
+
+
+ RWDEN
+ Regular channel analog watchdog enable
+ 23
+ 1
+
+
+ IWDEN
+ Inserted channel analog watchdog enable
+ 22
+ 1
+
+
+ DISNUM
+ Number of conversions in discontinuous
+ mode
+ 13
+ 3
+
+
+ DISIC
+ Discontinuous mode on injected
+ channels
+ 12
+ 1
+
+
+ DISRC
+ Discontinuous mode on regular
+ channels
+ 11
+ 1
+
+
+ ICA
+ Inserted channel group convert
+ automatically
+ 10
+ 1
+
+
+ WDSC
+ When in scan mode, analog watchdog
+ is effective on a single channel
+ 9
+ 1
+
+
+ SM
+ Scan mode
+ 8
+ 1
+
+
+ EOICIE
+ Interrupt enable for EOIC
+ 7
+ 1
+
+
+ WDEIE
+ Interrupt enable for WDE
+ 6
+ 1
+
+
+ EOCIE
+ Interrupt enable for EOC
+ 5
+ 1
+
+
+ WDCHSEL
+ Analog watchdog channel select
+ 0
+ 5
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TSVREN
+ Channel 16 and 17 enable of ADC
+ 23
+ 1
+
+
+ SWRCST
+ Start on regular channel
+ 22
+ 1
+
+
+ SWICST
+ Start on inserted channel
+ 21
+ 1
+
+
+ ETERC
+ External trigger enable for regular
+ channel
+ 20
+ 1
+
+
+ ETSRC
+ External trigger select for regular
+ channel
+ 17
+ 3
+
+
+ ETEIC
+ External trigger enable for
+ inserted channels
+ 15
+ 1
+
+
+ ETSIC
+ External trigger select for inserted
+ channel
+ 12
+ 3
+
+
+ DAL
+ Data alignment
+ 11
+ 1
+
+
+ DMA
+ DMA request enable
+ 8
+ 1
+
+
+ RSTCLB
+ Reset calibration
+ 3
+ 1
+
+
+ CLB
+ ADC calibration
+ 2
+ 1
+
+
+ CTN
+ Continuous mode
+ 1
+ 1
+
+
+ ADCON
+ ADC ON
+ 0
+ 1
+
+
+
+
+ SAMPT0
+ SAMPT0
+ Sampling time register 0
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SPT16
+ Channel 16 sample time
+ selection
+ 18
+ 3
+
+
+ SPT17
+ Channel 17 sample time
+ selection
+ 21
+ 3
+
+
+
+
+ SAMPT1
+ SAMPT1
+ Sampling time register 1
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SPT0
+ Channel 0 sample time
+ selection
+ 0
+ 3
+
+
+ SPT1
+ Channel 1 sample time
+ selection
+ 3
+ 3
+
+
+ SPT2
+ Channel 2 sample time
+ selection
+ 6
+ 3
+
+
+ SPT3
+ Channel 3 sample time
+ selection
+ 9
+ 3
+
+
+ SPT4
+ Channel 4 sample time
+ selection
+ 12
+ 3
+
+
+ SPT5
+ Channel 5 sample time
+ selection
+ 15
+ 3
+
+
+ SPT6
+ Channel 6 sample time
+ selection
+ 18
+ 3
+
+
+ SPT7
+ Channel 7 sample time
+ selection
+ 21
+ 3
+
+
+ SPT8
+ Channel 8 sample time
+ selection
+ 24
+ 3
+
+
+ SPT9
+ Channel 9 sample time
+ selection
+ 27
+ 3
+
+
+
+
+ IOFF0
+ IOFF0
+ Inserted channel data offset register
+ 0
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF1
+ IOFF1
+ Inserted channel data offset register
+ 1
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF2
+ IOFF2
+ Inserted channel data offset register
+ 2
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ IOFF3
+ IOFF3
+ Inserted channel data offset register
+ 3
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IOFF
+ Data offset for injected channel
+ x
+ 0
+ 12
+
+
+
+
+ WDHT
+ WDHT
+ watchdog higher threshold
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WDHT
+ Analog watchdog high
+ threshold
+ 0
+ 12
+
+
+
+
+ WDLT
+ WDLT
+ watchdog low threshold
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WDLT
+ Analog watchdog lower
+ threshold
+ 0
+ 12
+
+
+
+
+ RSQ0
+ RSQ0
+ regular sequence register 0
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RL
+ Regular channel sequence
+ length
+ 20
+ 4
+
+
+ RSQ15
+ 15th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ14
+ 14th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ13
+ 13th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ12
+ 12th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ RSQ1
+ RSQ1
+ regular sequence register 1
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RSQ11
+ 11th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ RSQ10
+ 10th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ RSQ9
+ 9th conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ8
+ 8th conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ7
+ 7th conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ6
+ 6th conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ RSQ2
+ RSQ2
+ regular sequence register 2
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RSQ5
+ 5th conversion in regular
+ sequence
+ 25
+ 5
+
+
+ RSQ4
+ 4th conversion in regular
+ sequence
+ 20
+ 5
+
+
+ RSQ3
+ 3rd conversion in regular
+ sequence
+ 15
+ 5
+
+
+ RSQ2
+ 2nd conversion in regular
+ sequence
+ 10
+ 5
+
+
+ RSQ1
+ 1st conversion in regular
+ sequence
+ 5
+ 5
+
+
+ RSQ0
+ conversion in regular
+ sequence
+ 0
+ 5
+
+
+
+
+ ISQ
+ ISQ
+ injected sequence register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IL
+ Injected sequence length
+ 20
+ 2
+
+
+ ISQ3
+ 3rd conversion in injected
+ sequence
+ 15
+ 5
+
+
+ ISQ2
+ 2nd conversion in injected
+ sequence
+ 10
+ 5
+
+
+ ISQ1
+ 1st conversion in injected
+ sequence
+ 5
+ 5
+
+
+ ISQ0
+ conversion in injected
+ sequence
+ 0
+ 5
+
+
+
+
+ IDATA0
+ IDATA0
+ injected data register 0
+ 0x3C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA1
+ IDATA1
+ injected data register 1
+ 0x40
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA2
+ IDATA2
+ injected data register 2
+ 0x44
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ IDATA3
+ IDATA3
+ injected data register 3
+ 0x48
+ 0x20
+ read-only
+ 0x00000000
+
+
+ IDATAn
+ Injected data
+ 0
+ 16
+
+
+
+
+ RDATA
+ RDATA
+ regular data register
+ 0x4C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RDATA
+ Regular data
+ 0
+ 16
+
+
+
+
+ OVSAMPCTL
+ OVSAMPCTL
+ ADC oversample control register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TOVS
+ Triggered Oversampling
+ 9
+ 1
+
+
+ OVSS
+ Oversampling shift
+ 5
+ 4
+
+
+ OVSR
+ Oversampling ratio
+ 2
+ 3
+
+
+ OVSEN
+ Oversampler Enable
+ 0
+ 1
+
+
+
+
+
+
+ CMP
+ Comparator
+ Comparator
+ 0x4001001C
+
+ 0x0
+ 0x80
+ registers
+
+
+
+ CS
+ CS
+ control and status register
+ 0x00
+ 0x20
+ 0x00000000
+
+
+ CMPEN
+ Comparator enable
+ 0
+ 1
+ read-write
+
+
+ CMPSW
+ Comparator switch
+ 1
+ 1
+ read-write
+
+
+ CMPM
+ Comparator mode
+ 2
+ 2
+ read-write
+
+
+ CMPMSEL
+ Comparator input selection
+ 4
+ 3
+ read-write
+
+
+ CMPOSEL
+ Comparator output selection
+ 8
+ 3
+ read-write
+
+
+ CMPPL
+ Polarity of comparator output
+ 11
+ 1
+ read-write
+
+
+ CMPHST
+ Comparator hysteresis
+ 12
+ 2
+ read-write
+
+
+ CMPO
+ Comparator 0 output
+ 14
+ 1
+ read-only
+
+
+ CMPLK
+ Comparator 0 lock
+ 15
+ 1
+ read-write
+
+
+
+
+
+
+ CRC
+ cyclic redundancy check calculation unit
+ CRC
+ 0x40023000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x0
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ DATA
+ CRC calculation result bits
+ 0
+ 32
+
+
+
+
+ FDATA
+ FDATA
+ Free data register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FDATA
+ General-purpose 8-bit data register
+ bits
+ 0
+ 8
+
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RST
+ reset bit
+ 0
+ 1
+
+
+ PS
+ Size of polynomial
+ 3
+ 2
+
+
+ REV_I
+ Reverse input data
+ 5
+ 2
+
+
+ REV_O
+ Reverse output data
+ 7
+ 1
+
+
+
+
+ IDATA
+ IDATA
+ Initialization Data Register
+ 0x10
+ 0x20
+ read-write
+ 0xFFFFFFFF
+
+
+ IDATA
+ CRC calculation initial value
+ 0
+ 32
+
+
+
+
+ POLY
+ POLY
+ Polynomial register
+ 0x14
+ 0x20
+ read-write
+ 0x04C11DB7
+
+
+ POLY
+ User configurable polynomial value
+ 0
+ 32
+
+
+
+
+
+
+ DBGMCU
+ Debug support
+ DBGMCU
+ 0x40015800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ ID
+ ID
+ MCU Device ID Code Register
+ 0x0
+ 0x20
+ read-only
+ 0x0
+
+
+ ID_CODE
+ DBG ID code register
+ 0
+ 32
+
+
+
+
+ CTL0
+ CTL0
+ Debug Control Register 0
+ 0x4
+ 0x20
+ read-write
+ 0x0
+
+
+ SLP_HOLD
+ Sleep mode hold register
+ 0
+ 1
+
+
+ DSLP_HOLD
+ DEEPSLEEP mode hold Mode
+ 1
+ 1
+
+
+ STB_HOLD
+ Standby mode hold Mode
+ 2
+ 1
+
+
+ FWDGT_HOLD
+ FWDGT hold register
+ 8
+ 1
+
+
+ WWDGT_HOLD
+ WWDGT hold register
+ 9
+ 1
+
+
+ TIMER0_HOLD
+ Timer 0 hold register
+ 10
+ 1
+
+
+ TIMER2_HOLD
+ Timer 2 hold register
+ 12
+ 1
+
+
+ I2C0_HOLD
+ I2C0 hold register
+ 15
+ 1
+
+
+ I2C1_HOLD
+ I2C1 hold register
+ 16
+ 1
+
+
+ TIMER5_HOLD
+ Timer 5 hold register
+ 19
+ 1
+
+
+ TIMER13_HOLD
+ Timer 13 hold register
+ 27
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Debug Control Register 1
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTC_HOLD
+ RTC hold register
+ 10
+ 1
+
+
+ TIMER14_HOLD
+ Timer 14 hold register
+ 16
+ 1
+
+
+ TIMER15_HOLD
+ Timer 15 hold register
+ 17
+ 1
+
+
+ TIMER16_HOLD
+ Timer 16 hold register
+ 18
+ 1
+
+
+
+
+
+
+ DMA
+ DMA controller
+ DMA
+ 0x40020000
+
+ 0x0
+ 0x400
+ registers
+
+
+ DMA_Channel0
+ 9
+
+
+ DMA_Channel1_2
+ 10
+
+
+ DMA_Channel3_4
+ 11
+
+
+
+ INTF
+ INTF
+ DMA interrupt flag register
+ (DMA_INTF)
+ 0x0
+ 0x20
+ read-only
+ 0x00000000
+
+
+ GIF0
+ Channel 0 Global interrupt
+ flag
+ 0
+ 1
+
+
+ FTFIF0
+ Channel 0 Full Transfer Finish
+ flag
+ 1
+ 1
+
+
+ HTFIF0
+ Channel 0 Half Transfer Finish
+ flag
+ 2
+ 1
+
+
+ ERRIF0
+ Channel 0 Error flag
+ 3
+ 1
+
+
+ GIF1
+ Channel 1 Global interrupt
+ flag
+ 4
+ 1
+
+
+ FTFIF1
+ Channel 1 Full Transfer Finish
+ flag
+ 5
+ 1
+
+
+ HTFIF1
+ Channel 1 Half Transfer Finish
+ flag
+ 6
+ 1
+
+
+ ERRIF1
+ Channel 1 Error flag
+ 7
+ 1
+
+
+ GIF2
+ Channel 2 Global interrupt
+ flag
+ 8
+ 1
+
+
+ FTFIF2
+ Channel 2 Full Transfer Finish
+ flag
+ 9
+ 1
+
+
+ HTFIF2
+ Channel 2 Half Transfer Finish
+ flag
+ 10
+ 1
+
+
+ ERRIF2
+ Channel 2 Error
+ flag
+ 11
+ 1
+
+
+ GIF3
+ Channel 3 Global interrupt
+ flag
+ 12
+ 1
+
+
+ FTFIF3
+ Channel 3 Full Transfer Finish
+ flag
+ 13
+ 1
+
+
+ HTFIF3
+ Channel 3 Half Transfer Finish
+ flag
+ 14
+ 1
+
+
+ ERRIF3
+ Channel 3 Error
+ flag
+ 15
+ 1
+
+
+ GIF4
+ Channel 4 Global interrupt
+ flag
+ 16
+ 1
+
+
+ FTFIF4
+ Channel 4 Full Transfer Finish
+ flag
+ 17
+ 1
+
+
+ HTFIF4
+ Channel 4 Half Transfer Finish
+ flag
+ 18
+ 1
+
+
+ ERRIF4
+ Channel 4 Error
+ flag
+ 19
+ 1
+
+
+
+
+ INTC
+ INTC
+ DMA interrupt flag clear register
+ (DMA_INTC)
+ 0x4
+ 0x20
+ write-only
+ 0x00000000
+
+
+ GIFC0
+ Channel 0 Global interrupt flag
+ clear
+ 0
+ 1
+
+
+ GIFC1
+ Channel 1 Global interrupt flag
+ clear
+ 4
+ 1
+
+
+ GIFC2
+ Channel 2 Global interrupt flag
+ clear
+ 8
+ 1
+
+
+ GIFC3
+ Channel 3 Global interrupt flag
+ clear
+ 12
+ 1
+
+
+ GIFC4
+ Channel 4 Global interrupt flag
+ clear
+ 16
+ 1
+
+
+ FTFIFC0
+ Channel 0 Full Transfer Finish
+ clear
+ 1
+ 1
+
+
+ FTFIFC1
+ Channel 1 Full Transfer Finish
+ clear
+ 5
+ 1
+
+
+ FTFIFC2
+ Channel 2 Full Transfer Finish
+ clear
+ 9
+ 1
+
+
+ FTFIFC3
+ Channel 3 Full Transfer Finish
+ clear
+ 13
+ 1
+
+
+ FTFIFC4
+ Channel 4 Full Transfer Finish
+ clear
+ 17
+ 1
+
+
+ HTFIFC0
+ Channel 0 Half Transfer
+ clear
+ 2
+ 1
+
+
+ HTFIFC1
+ Channel 1 Half Transfer
+ clear
+ 6
+ 1
+
+
+ HTFIFC2
+ Channel 2 Half Transfer
+ clear
+ 10
+ 1
+
+
+ HTFIFC3
+ Channel 3 Half Transfer
+ clear
+ 14
+ 1
+
+
+ HTFIFC4
+ Channel 4 Half Transfer
+ clear
+ 18
+ 1
+
+
+ ERRIFC0
+ Channel 0 Error
+ clear
+ 3
+ 1
+
+
+ ERRIFC1
+ Channel 1 Error
+ clear
+ 7
+ 1
+
+
+ ERRIFC2
+ Channel 2 Error
+ clear
+ 11
+ 1
+
+
+ ERRIFC3
+ Channel 3 Error
+ clear
+ 15
+ 1
+
+
+ ERRIFC4
+ Channel 4 Error
+ clear
+ 19
+ 1
+
+
+
+
+ CH0CTL
+ CH0CTL
+ DMA channel configuration register
+ (DMA_CH0CTL)
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Transfer access error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH0CNT
+ CH0CNT
+ DMA channel 0 counter
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH0PADDR
+ CH0PADDR
+ DMA channel 0 peripheral base address
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH0MADDR
+ CH0MADDR
+ DMA channel 0 memory base address
+ register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH1CTL
+ CH1CTL
+ DMA channel configuration register
+ (DMA_CH1CTL)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH1CNT
+ CH1CNT
+ DMA channel 1 counter
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+
+ CH1PADDR
+ CH1PADDR
+ DMA channel 1 peripheral base address
+ register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH1MADDR
+ CH1MADDR
+ DMA channel 1 memory base address
+ register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH2CTL
+ CH2CTL
+ DMA channel configuration register
+ (DMA_CH2CTL)
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH2CNT
+ CH2CNT
+ DMA channel 2 counter
+ register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+
+ CH2PADDR
+ CH2PADDR
+ DMA channel 2 peripheral base address
+ register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH2MADDR
+ CH2MADDR
+ DMA channel 2 memory base address
+ register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH3CTL
+ CH3CTL
+ DMA channel configuration register
+ (DMA_CH3CTL)
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH3CNT
+ CH3CNT
+ DMA channel 3 counter
+ register
+ 0x48
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH3PADDR
+ CH3PADDR
+ DMA channel 3 peripheral base address
+ register
+ 0x4C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH3MADDR
+ CH3MADDR
+ DMA channel 3 memory base address
+ register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+ CH4CTL
+ CH4CTL
+ DMA channel configuration register
+ (DMA_CH4CTL)
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CHEN
+ Channel enable
+ 0
+ 1
+
+
+ FTFIE
+ Full Transfer Finish interrupt
+ enable
+ 1
+ 1
+
+
+ HTFIE
+ Half Transfer Finish interrupt
+ enable
+ 2
+ 1
+
+
+ ERRIE
+ Error interrupt
+ enable
+ 3
+ 1
+
+
+ DIR
+ Transfer direction
+ 4
+ 1
+
+
+ CMEN
+ Circular mode enable
+ 5
+ 1
+
+
+ PNAGA
+ Next address generation algorithm of peripheral
+ 6
+ 1
+
+
+ MNAGA
+ Next address generation algorithm of memory
+ 7
+ 1
+
+
+ PWIDTH
+ Transfer data size of peripheral
+ 8
+ 2
+
+
+ MWIDTH
+ Transfer data size of memory
+ 10
+ 2
+
+
+ PRIO
+ Priority Level of this channel
+ 12
+ 2
+
+
+ M2M
+ Memory to memory mode
+ 14
+ 1
+
+
+
+
+ CH4CNT
+ CH4CNT
+ DMA channel 4 counter
+ register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Transfer counter
+ 0
+ 16
+
+
+
+
+ CH4PADDR
+ CH4PADDR
+ DMA channel 4 peripheral base address
+ register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PADDR
+ Peripheral base address
+ 0
+ 32
+
+
+
+
+ CH4MADDR
+ CH4MADDR
+ DMA channel 4 memory base address
+ register
+ 0x64
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MADDR
+ Memory address
+ 0
+ 32
+
+
+
+
+
+
+ EXTI
+ External interrupt/event
+ controller
+ EXTI
+ 0x40010400
+
+ 0x0
+ 0x400
+ registers
+
+
+ LVD
+ 1
+
+
+ EXTI0_1
+ 5
+
+
+ EXTI2_3
+ 6
+
+
+ EXTI4_15
+ 7
+
+
+
+ INTEN
+ INTEN
+ Interrupt enable register
+ (EXTI_INTEN)
+ 0x0
+ 0x20
+ read-write
+ 0x0F940000
+
+
+ INTEN0
+ Enable Interrupt on line 0
+ 0
+ 1
+
+
+ INTEN1
+ Enable Interrupt on line 1
+ 1
+ 1
+
+
+ INTEN2
+ Enable Interrupt on line 2
+ 2
+ 1
+
+
+ INTEN3
+ Enable Interrupt on line 3
+ 3
+ 1
+
+
+ INTEN4
+ Enable Interrupt on line 4
+ 4
+ 1
+
+
+ INTEN5
+ Enable Interrupt on line 5
+ 5
+ 1
+
+
+ INTEN6
+ Enable Interrupt on line 6
+ 6
+ 1
+
+
+ INTEN7
+ Enable Interrupt on line 7
+ 7
+ 1
+
+
+ INTEN8
+ Enable Interrupt on line 8
+ 8
+ 1
+
+
+ INTEN9
+ Enable Interrupt on line 9
+ 9
+ 1
+
+
+ INTEN10
+ Enable Interrupt on line 10
+ 10
+ 1
+
+
+ INTEN11
+ Enable Interrupt on line 11
+ 11
+ 1
+
+
+ INTEN12
+ Enable Interrupt on line 12
+ 12
+ 1
+
+
+ INTEN13
+ Enable Interrupt on line 13
+ 13
+ 1
+
+
+ INTEN14
+ Enable Interrupt on line 14
+ 14
+ 1
+
+
+ INTEN15
+ Enable Interrupt on line 15
+ 15
+ 1
+
+
+ INTEN16
+ Enable Interrupt on line 16
+ 16
+ 1
+
+
+ INTEN17
+ Enable Interrupt on line 17
+ 17
+ 1
+
+
+ INTEN18
+ Enable Interrupt on line 18
+ 18
+ 1
+
+
+ INTEN19
+ Enable Interrupt on line 19
+ 19
+ 1
+
+
+ INTEN20
+ Enable Interrupt on line 20
+ 20
+ 1
+
+
+ INTEN21
+ Enable Interrupt on line 21
+ 21
+ 1
+
+
+ INTEN22
+ Enable Interrupt on line 22
+ 22
+ 1
+
+
+ INTEN23
+ Enable Interrupt on line 23
+ 23
+ 1
+
+
+ INTEN24
+ Enable Interrupt on line 24
+ 24
+ 1
+
+
+ INTEN25
+ Enable Interrupt on line 25
+ 25
+ 1
+
+
+ INTEN26
+ Enable Interrupt on line 26
+ 26
+ 1
+
+
+ INTEN27
+ Enable Interrupt on line 27
+ 27
+ 1
+
+
+
+
+ EVEN
+ EVEN
+ Event enable register (EXTI_EVEN)
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EVEN0
+ Enable Event on line 0
+ 0
+ 1
+
+
+ EVEN1
+ Enable Event on line 1
+ 1
+ 1
+
+
+ EVEN2
+ Enable Event on line 2
+ 2
+ 1
+
+
+ EVEN3
+ Enable Event on line 3
+ 3
+ 1
+
+
+ EVEN4
+ Enable Event on line 4
+ 4
+ 1
+
+
+ EVEN5
+ Enable Event on line 5
+ 5
+ 1
+
+
+ EVEN6
+ Enable Event on line 6
+ 6
+ 1
+
+
+ EVEN7
+ Enable Event on line 7
+ 7
+ 1
+
+
+ EVEN8
+ Enable Event on line 8
+ 8
+ 1
+
+
+ EVEN9
+ Enable Event on line 9
+ 9
+ 1
+
+
+ EVEN10
+ Enable Event on line 10
+ 10
+ 1
+
+
+ EVEN11
+ Enable Event on line 11
+ 11
+ 1
+
+
+ EVEN12
+ Enable Event on line 12
+ 12
+ 1
+
+
+ EVEN13
+ Enable Event on line 13
+ 13
+ 1
+
+
+ EVEN14
+ Enable Event on line 14
+ 14
+ 1
+
+
+ EVEN15
+ Enable Event on line 15
+ 15
+ 1
+
+
+ EVEN16
+ Enable Event on line 16
+ 16
+ 1
+
+
+ EVEN17
+ Enable Event on line 17
+ 17
+ 1
+
+
+ EVEN18
+ Enable Event on line 18
+ 18
+ 1
+
+
+ EVEN19
+ Enable Event on line 19
+ 19
+ 1
+
+
+ EVEN20
+ Enable Event on line 20
+ 20
+ 1
+
+
+ EVEN21
+ Enable Event on line 21
+ 21
+ 1
+
+
+ EVEN22
+ Enable Event on line 22
+ 22
+ 1
+
+
+ EVEN23
+ Enable Event on line 23
+ 23
+ 1
+
+
+ EVEN24
+ Enable Event on line 24
+ 24
+ 1
+
+
+ EVEN25
+ Enable Event on line 25
+ 25
+ 1
+
+
+ EVEN26
+ Enable Event on line 26
+ 26
+ 1
+
+
+ EVEN27
+ Enable Event on line 27
+ 27
+ 1
+
+
+
+
+ RTEN
+ RTEN
+ Rising Edge Trigger Enable register
+ (EXTI_RTEN)
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ RTEN0
+ Rising trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ RTEN1
+ Rising trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ RTEN2
+ Rising trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ RTEN3
+ Rising trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ RTEN4
+ Rising trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ RTEN5
+ Rising trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ RTEN6
+ Rising trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ RTEN7
+ Rising trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ RTEN8
+ Rising trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ RTEN9
+ Rising trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ RTEN10
+ Rising trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ RTEN11
+ Rising trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ RTEN12
+ Rising trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ RTEN13
+ Rising trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ RTEN14
+ Rising trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ RTEN15
+ Rising trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ RTEN16
+ Rising trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ RTEN17
+ Rising trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ RTEN19
+ Rising trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ RTEN21
+ Rising trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+
+
+ FTEN
+ FTEN
+ Falling Egde Trigger Enable register
+ (EXTI_FTEN)
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FTEN0
+ Falling trigger event configuration of
+ line 0
+ 0
+ 1
+
+
+ FTEN1
+ Falling trigger event configuration of
+ line 1
+ 1
+ 1
+
+
+ FTEN2
+ Falling trigger event configuration of
+ line 2
+ 2
+ 1
+
+
+ FTEN3
+ Falling trigger event configuration of
+ line 3
+ 3
+ 1
+
+
+ FTEN4
+ Falling trigger event configuration of
+ line 4
+ 4
+ 1
+
+
+ FTEN5
+ Falling trigger event configuration of
+ line 5
+ 5
+ 1
+
+
+ FTEN6
+ Falling trigger event configuration of
+ line 6
+ 6
+ 1
+
+
+ FTEN7
+ Falling trigger event configuration of
+ line 7
+ 7
+ 1
+
+
+ FTEN8
+ Falling trigger event configuration of
+ line 8
+ 8
+ 1
+
+
+ FTEN9
+ Falling trigger event configuration of
+ line 9
+ 9
+ 1
+
+
+ FTEN10
+ Falling trigger event configuration of
+ line 10
+ 10
+ 1
+
+
+ FTEN11
+ Falling trigger event configuration of
+ line 11
+ 11
+ 1
+
+
+ FTEN12
+ Falling trigger event configuration of
+ line 12
+ 12
+ 1
+
+
+ FTEN13
+ Falling trigger event configuration of
+ line 13
+ 13
+ 1
+
+
+ FTEN14
+ Falling trigger event configuration of
+ line 14
+ 14
+ 1
+
+
+ FTEN15
+ Falling trigger event configuration of
+ line 15
+ 15
+ 1
+
+
+ FTEN16
+ Falling trigger event configuration of
+ line 16
+ 16
+ 1
+
+
+ FTEN17
+ Falling trigger event configuration of
+ line 17
+ 17
+ 1
+
+
+ FTEN19
+ Falling trigger event configuration of
+ line 19
+ 19
+ 1
+
+
+ FTEN21
+ Falling trigger event configuration of
+ line 21
+ 21
+ 1
+
+
+
+
+ SWIEV
+ SWIEV
+ Software interrupt event register
+ (EXTI_SWIEV)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SWIEV0
+ Software Interrupt on line
+ 0
+ 0
+ 1
+
+
+ SWIEV1
+ Software Interrupt on line
+ 1
+ 1
+ 1
+
+
+ SWIEV2
+ Software Interrupt on line
+ 2
+ 2
+ 1
+
+
+ SWIEV3
+ Software Interrupt on line
+ 3
+ 3
+ 1
+
+
+ SWIEV4
+ Software Interrupt on line
+ 4
+ 4
+ 1
+
+
+ SWIEV5
+ Software Interrupt on line
+ 5
+ 5
+ 1
+
+
+ SWIEV6
+ Software Interrupt on line
+ 6
+ 6
+ 1
+
+
+ SWIEV7
+ Software Interrupt on line
+ 7
+ 7
+ 1
+
+
+ SWIEV8
+ Software Interrupt on line
+ 8
+ 8
+ 1
+
+
+ SWIEV9
+ Software Interrupt on line
+ 9
+ 9
+ 1
+
+
+ SWIEV10
+ Software Interrupt on line
+ 10
+ 10
+ 1
+
+
+ SWIEV11
+ Software Interrupt on line
+ 11
+ 11
+ 1
+
+
+ SWIEV12
+ Software Interrupt on line
+ 12
+ 12
+ 1
+
+
+ SWIEV13
+ Software Interrupt on line
+ 13
+ 13
+ 1
+
+
+ SWIEV14
+ Software Interrupt on line
+ 14
+ 14
+ 1
+
+
+ SWIEV15
+ Software Interrupt on line
+ 15
+ 15
+ 1
+
+
+ SWIEV16
+ Software Interrupt on line
+ 16
+ 16
+ 1
+
+
+ SWIEV17
+ Software Interrupt on line
+ 17
+ 17
+ 1
+
+
+ SWIEV19
+ Software Interrupt on line
+ 19
+ 19
+ 1
+
+
+ SWIEV21
+ Software Interrupt on line
+ 21
+ 21
+ 1
+
+
+
+
+ PD
+ PD
+ Pending register (EXTI_PD)
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PD0
+ Pending bit 0
+ 0
+ 1
+
+
+ PD1
+ Pending bit 1
+ 1
+ 1
+
+
+ PD2
+ Pending bit 2
+ 2
+ 1
+
+
+ PD3
+ Pending bit 3
+ 3
+ 1
+
+
+ PD4
+ Pending bit 4
+ 4
+ 1
+
+
+ PD5
+ Pending bit 5
+ 5
+ 1
+
+
+ PD6
+ Pending bit 6
+ 6
+ 1
+
+
+ PD7
+ Pending bit 7
+ 7
+ 1
+
+
+ PD8
+ Pending bit 8
+ 8
+ 1
+
+
+ PD9
+ Pending bit 9
+ 9
+ 1
+
+
+ PD10
+ Pending bit 10
+ 10
+ 1
+
+
+ PD11
+ Pending bit 11
+ 11
+ 1
+
+
+ PD12
+ Pending bit 12
+ 12
+ 1
+
+
+ PD13
+ Pending bit 13
+ 13
+ 1
+
+
+ PD14
+ Pending bit 14
+ 14
+ 1
+
+
+ PD15
+ Pending bit 15
+ 15
+ 1
+
+
+ PD16
+ Pending bit 16
+ 16
+ 1
+
+
+ PD17
+ Pending bit 17
+ 17
+ 1
+
+
+ PD19
+ Pending bit 19
+ 19
+ 1
+
+
+ PD21
+ Pending bit 21
+ 21
+ 1
+
+
+
+
+
+
+ FMC
+ FMC
+ FMC
+ 0x40022000
+
+ 0x0
+ 0x400
+ registers
+
+
+ FMC
+ 3
+
+
+
+ WS
+ WS
+ wait state register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WSCNT
+ wait state counter register
+ 0
+ 3
+
+
+ PFEN
+ Pre-fetch enable
+ 4
+ 1
+
+
+ PGW
+ Program width to flash memory
+ 15
+ 1
+
+
+
+
+ KEY
+ KEY
+ Unlock key register
+ 0x04
+ 0x20
+ write-only
+ 0x00000000
+
+
+ KEY
+ FMC_CTL unlock register
+ 0
+ 32
+
+
+
+
+ OBKEY
+ OBKEY
+ Option byte unlock key register
+ 0x08
+ 0x20
+ write-only
+ 0x00000000
+
+
+ OBKEY
+ FMC_ CTL option bytes operation unlock register
+ 0
+ 32
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x0C
+ 0x20
+ 0x00000000
+
+
+ ENDF
+ End of operation flag bit
+ 5
+ 1
+ read-write
+
+
+ WPERR
+ Erase/Program protection error flag bit
+ 4
+ 1
+ read-write
+
+
+ PGAERR
+ Program alignment error flag bit
+ 3
+ 1
+ read-write
+
+
+ PGERR
+ Program error flag bit
+ 2
+ 1
+ read-write
+
+
+ BUSY
+ The flash is busy bit
+ 0
+ 1
+ read-only
+
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x10
+ 0x20
+ read-write
+ 0x00000080
+
+
+ OBRLD
+ Option byte reload bit
+ 13
+ 1
+
+
+ ENDIE
+ End of operation interrupt enable bit
+ 12
+ 1
+
+
+ ERRIE
+ Error interrupt enable bit
+ 10
+ 1
+
+
+ OBWEN
+ Option byte erase/program enable bit
+ 9
+ 1
+
+
+ LK
+ FMC_CTL lock bit
+ 7
+ 1
+
+
+ START
+ Send erase command to FMC bit
+ 6
+ 1
+
+
+ OBER
+ Option bytes erase command bit
+ 5
+ 1
+
+
+ OBPG
+ Option bytes program command bit
+ 4
+ 1
+
+
+ MER
+ Main flash mass erase for bank0 command bit
+ 2
+ 1
+
+
+ PER
+ Main flash page erase for bank0 command bit
+ 1
+ 1
+
+
+ PG
+ Main flash program for bank0 command bit
+ 0
+ 1
+
+
+
+
+ ADDR
+ ADDR
+ Address register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADDR
+ Flash erase/program command address bits
+ 0
+ 32
+
+
+
+
+ OBSTAT
+ OBSTAT
+ Option byte control register
+ 0x1C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ OBERR
+ Option bytes read error bit
+ 0
+ 1
+
+
+ PLEVEL
+ Option bytes security protection level
+ 1
+ 2
+
+
+ USER
+ Store USER of option bytes block after system reset
+ 8
+ 8
+
+
+ DATA
+ Store DATA[15:0] of option bytes block after system reset
+ 16
+ 16
+
+
+
+
+ WP
+ WP
+ Erase/Program Protection register
+ 0x20
+ 0x20
+ read-only
+ 0x00000000
+
+
+ WP
+ Store WP[15:0] of option bytes block after system reset
+ 0
+ 16
+
+
+
+
+ PID
+ PID
+ Product ID register
+ 0x100
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PID
+ Product reserved ID code register
+ 0
+ 32
+
+
+
+
+
+
+ FWDGT
+ free watchdog timer
+ FWDGT
+ 0x40003000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x00
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CMD
+ Key value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ Prescaler register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PSC
+ Prescaler divider
+ 0
+ 3
+
+
+
+
+ RLD
+ RLD
+ Reload register
+ 0x08
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ RLD
+ Watchdog counter reload
+ value
+ 0
+ 12
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x0C
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PUD
+ Watchdog prescaler value
+ update
+ 0
+ 1
+
+
+ RUD
+ Watchdog counter reload value
+ update
+ 1
+ 1
+
+
+ WUD
+ Watchdog counter window value
+ update
+ 2
+ 1
+
+
+
+
+ WND
+ WND
+ Window register
+ 0x10
+ 0x20
+ read-write
+ 0x00000FFF
+
+
+ WND
+ Watchdog counter window
+ value
+ 0
+ 12
+
+
+
+
+
+
+ GPIOA
+ General-purpose I/Os
+ GPIO
+ 0x48000000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x28000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x0C000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x24000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LKK
+ Port x lock bit y
+
+ 16
+ 1
+
+
+ LK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOB
+ General-purpose I/Os
+ GPIO
+ 0x48000400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ LOCK
+ LOCK
+ GPIO port configuration lock
+ register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ LKK
+ Port x lock bit y
+
+ 16
+ 1
+
+
+ LK15
+ Port x lock bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ LK14
+ Port x lock bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ LK13
+ Port x lock bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ LK12
+ Port x lock bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ LK11
+ Port x lock bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ LK10
+ Port x lock bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ LK9
+ Port x lock bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ LK8
+ Port x lock bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ LK7
+ Port x lock bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ LK6
+ Port x lock bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ LK5
+ Port x lock bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ LK4
+ Port x lock bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ LK3
+ Port x lock bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ LK2
+ Port x lock bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ LK1
+ Port x lock bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ LK0
+ Port x lock bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOC
+ General-purpose I/Os
+ GPIO
+ 0x48000800
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIO port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x reset bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ AFSEL0
+ AFSEL0
+ GPIO alternate function low
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL7
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 28
+ 4
+
+
+ SEL6
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 24
+ 4
+
+
+ SEL5
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 20
+ 4
+
+
+ SEL4
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 16
+ 4
+
+
+ SEL3
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 12
+ 4
+
+
+ SEL2
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 8
+ 4
+
+
+ SEL1
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 4
+ 4
+
+
+ SEL0
+ Alternate function selection for port x
+ bit y (y = 0..7)
+ 0
+ 4
+
+
+
+
+ AFSEL1
+ AFSEL1
+ GPIO alternate function
+ register 1
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SEL15
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 28
+ 4
+
+
+ SEL14
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 24
+ 4
+
+
+ SEL13
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 20
+ 4
+
+
+ SEL12
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 16
+ 4
+
+
+ SEL11
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 12
+ 4
+
+
+ SEL10
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 8
+ 4
+
+
+ SEL9
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 4
+ 4
+
+
+ SEL8
+ Alternate function selection for port x
+ bit y (y = 8..15)
+ 0
+ 4
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port cleat bit
+ 0
+ 1
+
+
+ CR1
+ Port cleat bit
+ 1
+ 1
+
+
+ CR2
+ Port cleat bit
+ 2
+ 1
+
+
+ CR3
+ Port cleat bit
+ 3
+ 1
+
+
+ CR4
+ Port cleat bit
+ 4
+ 1
+
+
+ CR5
+ Port cleat bit
+ 5
+ 1
+
+
+ CR6
+ Port cleat bit
+ 6
+ 1
+
+
+ CR7
+ Port cleat bit
+ 7
+ 1
+
+
+ CR8
+ Port cleat bit
+ 8
+ 1
+
+
+ CR9
+ Port cleat bit
+ 9
+ 1
+
+
+ CR10
+ Port cleat bit
+ 10
+ 1
+
+
+ CR11
+ Port cleat bit
+ 11
+ 1
+
+
+ CR12
+ Port cleat bit
+ 12
+ 1
+
+
+ CR13
+ Port cleat bit
+ 13
+ 1
+
+
+ CR14
+ Port cleat bit
+ 14
+ 1
+
+
+ CR15
+ Port cleat bit
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ GPIOF
+ General-purpose I/Os
+ GPIO
+ 0x48001400
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ GPIOF port control register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CTL15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ CTL14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ CTL13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ CTL12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ CTL11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ CTL10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ CTL9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ CTL8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ CTL7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ CTL6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ CTL5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ CTL4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ CTL3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ CTL2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ CTL1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ CTL0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ OMODE
+ OMODE
+ GPIO port output type register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OM15
+ Port x configuration bit
+ 15
+ 15
+ 1
+
+
+ OM14
+ Port x configuration bit
+ 14
+ 14
+ 1
+
+
+ OM13
+ Port x configuration bit
+ 13
+ 13
+ 1
+
+
+ OM12
+ Port x configuration bit
+ 12
+ 12
+ 1
+
+
+ OM11
+ Port x configuration bit
+ 11
+ 11
+ 1
+
+
+ OM10
+ Port x configuration bit
+ 10
+ 10
+ 1
+
+
+ OM9
+ Port x configuration bit 9
+ 9
+ 1
+
+
+ OM8
+ Port x configuration bit 8
+ 8
+ 1
+
+
+ OM7
+ Port x configuration bit 7
+ 7
+ 1
+
+
+ OM6
+ Port x configuration bit 6
+ 6
+ 1
+
+
+ OM5
+ Port x configuration bit 5
+ 5
+ 1
+
+
+ OM4
+ Port x configuration bit 4
+ 4
+ 1
+
+
+ OM3
+ Port x configuration bit 3
+ 3
+ 1
+
+
+ OM2
+ Port x configuration bit 2
+ 2
+ 1
+
+
+ OM1
+ Port x configuration bit 1
+ 1
+ 1
+
+
+ OM0
+ Port x configuration bit 0
+ 0
+ 1
+
+
+
+
+ OSPD
+ OSPD
+ GPIO port output speed
+ register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OSPD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ OSPD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ OSPD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ OSPD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ OSPD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ OSPD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ OSPD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ OSPD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ OSPD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ OSPD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ OSPD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ OSPD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ OSPD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ OSPD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ OSPD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ OSPD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ PUD
+ PUD
+ GPIO port pull-up/pull-down
+ register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PUD15
+ Port x configuration bits (y =
+ 0..15)
+ 30
+ 2
+
+
+ PUD14
+ Port x configuration bits (y =
+ 0..15)
+ 28
+ 2
+
+
+ PUD13
+ Port x configuration bits (y =
+ 0..15)
+ 26
+ 2
+
+
+ PUD12
+ Port x configuration bits (y =
+ 0..15)
+ 24
+ 2
+
+
+ PUD11
+ Port x configuration bits (y =
+ 0..15)
+ 22
+ 2
+
+
+ PUD10
+ Port x configuration bits (y =
+ 0..15)
+ 20
+ 2
+
+
+ PUD9
+ Port x configuration bits (y =
+ 0..15)
+ 18
+ 2
+
+
+ PUD8
+ Port x configuration bits (y =
+ 0..15)
+ 16
+ 2
+
+
+ PUD7
+ Port x configuration bits (y =
+ 0..15)
+ 14
+ 2
+
+
+ PUD6
+ Port x configuration bits (y =
+ 0..15)
+ 12
+ 2
+
+
+ PUD5
+ Port x configuration bits (y =
+ 0..15)
+ 10
+ 2
+
+
+ PUD4
+ Port x configuration bits (y =
+ 0..15)
+ 8
+ 2
+
+
+ PUD3
+ Port x configuration bits (y =
+ 0..15)
+ 6
+ 2
+
+
+ PUD2
+ Port x configuration bits (y =
+ 0..15)
+ 4
+ 2
+
+
+ PUD1
+ Port x configuration bits (y =
+ 0..15)
+ 2
+ 2
+
+
+ PUD0
+ Port x configuration bits (y =
+ 0..15)
+ 0
+ 2
+
+
+
+
+ ISTAT
+ ISTAT
+ GPIO port input data register
+ 0x10
+ 0x20
+ read-only
+ 0x00000000
+
+
+ ISTAT15
+ Port input data (y =
+ 0..15)
+ 15
+ 1
+
+
+ ISTAT14
+ Port input data (y =
+ 0..15)
+ 14
+ 1
+
+
+ ISTAT13
+ Port input data (y =
+ 0..15)
+ 13
+ 1
+
+
+ ISTAT12
+ Port input data (y =
+ 0..15)
+ 12
+ 1
+
+
+ ISTAT11
+ Port input data (y =
+ 0..15)
+ 11
+ 1
+
+
+ ISTAT10
+ Port input data (y =
+ 0..15)
+ 10
+ 1
+
+
+ ISTAT9
+ Port input data (y =
+ 0..15)
+ 9
+ 1
+
+
+ ISTAT8
+ Port input data (y =
+ 0..15)
+ 8
+ 1
+
+
+ ISTAT7
+ Port input data (y =
+ 0..15)
+ 7
+ 1
+
+
+ ISTAT6
+ Port input data (y =
+ 0..15)
+ 6
+ 1
+
+
+ ISTAT5
+ Port input data (y =
+ 0..15)
+ 5
+ 1
+
+
+ ISTAT4
+ Port input data (y =
+ 0..15)
+ 4
+ 1
+
+
+ ISTAT3
+ Port input data (y =
+ 0..15)
+ 3
+ 1
+
+
+ ISTAT2
+ Port input data (y =
+ 0..15)
+ 2
+ 1
+
+
+ ISTAT1
+ Port input data (y =
+ 0..15)
+ 1
+ 1
+
+
+ ISTAT0
+ Port input data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ OCTL
+ OCTL
+ GPIO port output data register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ OCTL15
+ Port output data (y =
+ 0..15)
+ 15
+ 1
+
+
+ OCTL14
+ Port output data (y =
+ 0..15)
+ 14
+ 1
+
+
+ OCTL13
+ Port output data (y =
+ 0..15)
+ 13
+ 1
+
+
+ OCTL12
+ Port output data (y =
+ 0..15)
+ 12
+ 1
+
+
+ OCTL11
+ Port output data (y =
+ 0..15)
+ 11
+ 1
+
+
+ OCTL10
+ Port output data (y =
+ 0..15)
+ 10
+ 1
+
+
+ OCTL9
+ Port output data (y =
+ 0..15)
+ 9
+ 1
+
+
+ OCTL8
+ Port output data (y =
+ 0..15)
+ 8
+ 1
+
+
+ OCTL7
+ Port output data (y =
+ 0..15)
+ 7
+ 1
+
+
+ OCTL6
+ Port output data (y =
+ 0..15)
+ 6
+ 1
+
+
+ OCTL5
+ Port output data (y =
+ 0..15)
+ 5
+ 1
+
+
+ OCTL4
+ Port output data (y =
+ 0..15)
+ 4
+ 1
+
+
+ OCTL3
+ Port output data (y =
+ 0..15)
+ 3
+ 1
+
+
+ OCTL2
+ Port output data (y =
+ 0..15)
+ 2
+ 1
+
+
+ OCTL1
+ Port output data (y =
+ 0..15)
+ 1
+ 1
+
+
+ OCTL0
+ Port output data (y =
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BOP
+ BOP
+ GPIO port bit set/reset
+ register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR15
+ Port x reset bit y (y =
+ 0..15)
+ 31
+ 1
+
+
+ CR14
+ Port x reset bit y (y =
+ 0..15)
+ 30
+ 1
+
+
+ CR13
+ Port x reset bit y (y =
+ 0..15)
+ 29
+ 1
+
+
+ CR12
+ Port x reset bit y (y =
+ 0..15)
+ 28
+ 1
+
+
+ CR11
+ Port x reset bit y (y =
+ 0..15)
+ 27
+ 1
+
+
+ CR10
+ Port x reset bit y (y =
+ 0..15)
+ 26
+ 1
+
+
+ CR9
+ Port x reset bit y (y =
+ 0..15)
+ 25
+ 1
+
+
+ CR8
+ Port x reset bit y (y =
+ 0..15)
+ 24
+ 1
+
+
+ CR7
+ Port x reset bit y (y =
+ 0..15)
+ 23
+ 1
+
+
+ CR6
+ Port x reset bit y (y =
+ 0..15)
+ 22
+ 1
+
+
+ CR5
+ Port x reset bit y (y =
+ 0..15)
+ 21
+ 1
+
+
+ CR4
+ Port x reset bit y (y =
+ 0..15)
+ 20
+ 1
+
+
+ CR3
+ Port x reset bit y (y =
+ 0..15)
+ 19
+ 1
+
+
+ CR2
+ Port x reset bit y (y =
+ 0..15)
+ 18
+ 1
+
+
+ CR1
+ Port x reset bit y (y =
+ 0..15)
+ 17
+ 1
+
+
+ CR0
+ Port x set bit y (y=
+ 0..15)
+ 16
+ 1
+
+
+ BOP15
+ Port x set bit y (y=
+ 0..15)
+ 15
+ 1
+
+
+ BOP14
+ Port x set bit y (y=
+ 0..15)
+ 14
+ 1
+
+
+ BOP13
+ Port x set bit y (y=
+ 0..15)
+ 13
+ 1
+
+
+ BOP12
+ Port x set bit y (y=
+ 0..15)
+ 12
+ 1
+
+
+ BOP11
+ Port x set bit y (y=
+ 0..15)
+ 11
+ 1
+
+
+ BOP10
+ Port x set bit y (y=
+ 0..15)
+ 10
+ 1
+
+
+ BOP9
+ Port x set bit y (y=
+ 0..15)
+ 9
+ 1
+
+
+ BOP8
+ Port x set bit y (y=
+ 0..15)
+ 8
+ 1
+
+
+ BOP7
+ Port x set bit y (y=
+ 0..15)
+ 7
+ 1
+
+
+ BOP6
+ Port x set bit y (y=
+ 0..15)
+ 6
+ 1
+
+
+ BOP5
+ Port x set bit y (y=
+ 0..15)
+ 5
+ 1
+
+
+ BOP4
+ Port x set bit y (y=
+ 0..15)
+ 4
+ 1
+
+
+ BOP3
+ Port x set bit y (y=
+ 0..15)
+ 3
+ 1
+
+
+ BOP2
+ Port x set bit y (y=
+ 0..15)
+ 2
+ 1
+
+
+ BOP1
+ Port x set bit y (y=
+ 0..15)
+ 1
+ 1
+
+
+ BOP0
+ Port x set bit y (y=
+ 0..15)
+ 0
+ 1
+
+
+
+
+ BC
+ BC
+ Port bit reset register
+ 0x28
+ 0x20
+ write-only
+ 0x00000000
+
+
+ CR0
+ Port x Reset bit y
+ 0
+ 1
+
+
+ CR1
+ Port x Reset bit y
+ 1
+ 1
+
+
+ CR2
+ Port x Reset bit y
+ 2
+ 1
+
+
+ CR3
+ Port x Reset bit y
+ 3
+ 1
+
+
+ CR4
+ Port x Reset bit y
+ 4
+ 1
+
+
+ CR5
+ Port x Reset bit y
+ 5
+ 1
+
+
+ CR6
+ Port x Reset bit y
+ 6
+ 1
+
+
+ CR7
+ Port x Reset bit y
+ 7
+ 1
+
+
+ CR8
+ Port x Reset bit y
+ 8
+ 1
+
+
+ CR9
+ Port x Reset bit y
+ 9
+ 1
+
+
+ CR10
+ Port x Reset bit y
+ 10
+ 1
+
+
+ CR11
+ Port x Reset bit y
+ 11
+ 1
+
+
+ CR12
+ Port x Reset bit y
+ 12
+ 1
+
+
+ CR13
+ Port x Reset bit y
+ 13
+ 1
+
+
+ CR14
+ Port x Reset bit y
+ 14
+ 1
+
+
+ CR15
+ Port x Reset bit y
+ 15
+ 1
+
+
+
+
+ TG
+ TG
+ Port bit toggle register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TG0
+ Port toggle bit
+ 0
+ 1
+
+
+ TG1
+ Port toggle bit
+ 1
+ 1
+
+
+ TG2
+ Port toggle bit
+ 2
+ 1
+
+
+ TG3
+ Port toggle bit
+ 3
+ 1
+
+
+ TG4
+ Port toggle bit
+ 4
+ 1
+
+
+ TG5
+ Port toggle bit
+ 5
+ 1
+
+
+ TG6
+ Port toggle bit
+ 6
+ 1
+
+
+ TG7
+ Port toggle bit
+ 7
+ 1
+
+
+ TG8
+ Port toggle bit
+ 8
+ 1
+
+
+ TG9
+ Port toggle bit
+ 9
+ 1
+
+
+ TG10
+ Port toggle bit
+ 10
+ 1
+
+
+ TG11
+ Port toggle bit
+ 11
+ 1
+
+
+ TG12
+ Port toggle bit
+ 12
+ 1
+
+
+ TG13
+ Port toggle bit
+ 13
+ 1
+
+
+ TG14
+ Port toggle bit
+ 14
+ 1
+
+
+ TG15
+ Port toggle bit
+ 15
+ 1
+
+
+
+
+
+
+ I2C0
+ Inter integrated circuit
+ I2C
+ 0x40005400
+
+ 0x0
+ 0x400
+ registers
+
+
+ I2C0_EV
+ 23
+
+
+ I2C0_ER
+ 32
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ SRESET
+ Software reset
+ 15
+ 1
+
+
+ SALT
+ SMBus alert
+ 13
+ 1
+
+
+ PECTRANS
+ Packet error checking
+ 12
+ 1
+
+
+ POAP
+ Acknowledge/PEC Position (for data
+ reception)
+ 11
+ 1
+
+
+ ACKEN
+ Acknowledge enable
+ 10
+ 1
+
+
+ STOP
+ Stop condition
+ 9
+ 1
+
+
+ START
+ Start generation
+ 8
+ 1
+
+
+ SS
+ SCL Stretching(Slave
+ mode)
+ 7
+ 1
+
+
+ GCEN
+ General call enable
+ 6
+ 1
+
+
+ PECEN
+ PEC enable
+ 5
+ 1
+
+
+ ARPEN
+ ARP enable
+ 4
+ 1
+
+
+ SMBSEL
+ SMBus type
+ 3
+ 1
+
+
+ SMBEN
+ SMBus mode
+ 1
+ 1
+
+
+ I2CEN
+ Peripheral enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMALST
+ Flag indicating DMA last transfer
+ 12
+ 1
+
+
+ DMAON
+ DMA mode switch
+ 11
+ 1
+
+
+ BUFIE
+ Buffer interrupt enable
+ 10
+ 1
+
+
+ EVIE
+ Event interrupt enable
+ 9
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 8
+ 1
+
+
+ I2CCLK
+ Peripheral clock frequency
+ 0
+ 7
+
+
+
+
+ SADDR0
+ SADDR0
+ Own address register 0
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADDFORMAT
+ Addressing mode (slave
+ mode)
+ 15
+ 1
+
+
+ ADDRESS
+ Interface address
+ 0
+ 10
+
+
+
+
+ SADDR1
+ SADDR1
+ Own address register 1
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ ADDRESS2
+ Interface address
+ 1
+ 7
+
+
+ DUADEN
+ Dual addressing mode
+ enable
+ 0
+ 1
+
+
+
+
+ DATA
+ DATA
+ Data register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRB
+ Transmission or reception data buffer
+ 0
+ 8
+
+
+
+
+ STAT0
+ STAT0
+ Transfer status register 0
+ 0x14
+ 0x20
+ 0x0000
+
+
+ SMBALT
+ SMBus alert
+ 15
+ 1
+ read-write
+
+
+ SMBTO
+ Timeout signal in SMBus mode
+ 14
+ 1
+ read-write
+
+
+ PECERR
+ PEC error when receiving data
+ 12
+ 1
+ read-write
+
+
+ OUERR
+ Overrun/Underrun occurs in slave mode
+ 11
+ 1
+ read-write
+
+
+ AERR
+ Acknowledge error
+ 10
+ 1
+ read-write
+
+
+ LOSTARB
+ Arbitration lost (master
+ mode)
+ 9
+ 1
+ read-write
+
+
+ BERR
+ Bus error
+ 8
+ 1
+ read-write
+
+
+ TBE
+ I2C_DATA is Empty during transmitting
+ 7
+ 1
+ read-only
+
+
+ RBNE
+ I2C_DATA is not Empty during receiving
+ 6
+ 1
+ read-only
+
+
+ STPDET
+ Stop detection (slave
+ mode)
+ 4
+ 1
+ read-only
+
+
+ ADD10SEND
+ Header of 10-bit address is sent in master mode
+ 3
+ 1
+ read-only
+
+
+ BTC
+ Byte transmission completed
+ 2
+ 1
+ read-only
+
+
+ ADDSEND
+ Address sent (master mode)/matched
+ (slave mode)
+ 1
+ 1
+ read-only
+
+
+ SBSEND
+ Start bit (Master mode)
+ 0
+ 1
+ read-only
+
+
+
+
+ STAT1
+ STAT1
+ Transfer status register 1
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ PECV
+ Packet error checking
+ register
+ 8
+ 8
+
+
+ DUMODF
+ Dual flag (Slave mode)
+ 7
+ 1
+
+
+ HSTSMB
+ SMBus host header (Slave
+ mode)
+ 6
+ 1
+
+
+ DEFSMB
+ SMBus device default address (Slave
+ mode)
+ 5
+ 1
+
+
+ RXGC
+ General call address (Slave
+ mode)
+ 4
+ 1
+
+
+ TR
+ Transmitter/receiver
+ 2
+ 1
+
+
+ I2CBSY
+ Bus busy
+ 1
+ 1
+
+
+ MASTER
+ Master/slave
+ 0
+ 1
+
+
+
+
+ CKCFG
+ CKCFG
+ Clock configure register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ FAST
+ I2C master mode selection
+ 15
+ 1
+
+
+ DTCY
+ Fast mode duty cycle
+ 14
+ 1
+
+
+ CLKC
+ Clock control register in Fast/Standard
+ mode (Master mode)
+ 0
+ 12
+
+
+
+
+ RT
+ RT
+ Rise time register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ RISETIME
+ Maximum rise time in master mode
+ 0
+ 7
+
+
+
+
+ SAMCS
+ SAMCS
+ SAM control and status register
+ 0x80
+ 0x20
+ read-write
+ 0x0000
+
+
+ RFR
+ Rxframe rise flag
+ 15
+ 1
+
+
+ RFF
+ Rxframe fall flag
+ 14
+ 1
+
+
+ TFR
+ Txframe rise flag
+ 13
+ 1
+
+
+ TFF
+ Txframe fall flag
+ 12
+ 1
+
+
+ RXF
+ level of rx frame signal
+ 9
+ 1
+
+
+ TXF
+ level of tx frame signal
+ 8
+ 1
+
+
+ RFRIE
+ Rx frame rise interrupt enable
+ 7
+ 1
+
+
+ RFFIE
+ Rx frame fall interrupt enable
+ 6
+ 1
+
+
+ TFRIE
+ Tx frame rise interrupt enable
+ 5
+ 1
+
+
+ TFFIE
+ Tx frame fall interrupt enable
+ 4
+ 1
+
+
+ STOEN
+ SAM_V interface timeout detect enable
+ 1
+ 1
+
+
+ SAMEN
+ SAM_V interface enable
+ 0
+ 1
+
+
+
+
+ FMPCFG
+ FMPCFG
+ Fast-mode-plus configure register
+ 0x90
+ 0x20
+ read-write
+ 0x0000
+
+
+ FMPEN
+ Fast-mode-plus enable
+ 0
+ 1
+
+
+
+
+
+
+ I2C1
+ 0x40005800
+
+ I2C1_EV
+ 24
+
+
+ I2C1_ER
+ 34
+
+
+
+ NVIC
+ Nested Vectored Interrupt
+ Controller
+ NVIC
+ 0xE000E100
+
+ 0x0
+ 0xF00
+ registers
+
+
+ 0x33D
+ 0xC3
+ reserved
+
+
+
+ ISER0
+ ISER0
+ Interrupt Set Enable Register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER1
+ ISER1
+ Interrupt Set Enable Register
+ 0x04
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER2
+ ISER2
+ Interrupt Set Enable Register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER3
+ ISER3
+ Interrupt Set Enable Register
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER4
+ ISER4
+ Interrupt Set Enable Register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER5
+ ISER5
+ Interrupt Set Enable Register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER6
+ ISER6
+ Interrupt Set Enable Register
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER7
+ ISER7
+ Interrupt Set Enable Register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER8
+ ISER8
+ Interrupt Set Enable Register
+ 0x20
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER9
+ ISER9
+ Interrupt Set Enable Register
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER10
+ ISER10
+ Interrupt Set Enable Register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER11
+ ISER11
+ Interrupt Set Enable Register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER12
+ ISER12
+ Interrupt Set Enable Register
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER13
+ ISER13
+ Interrupt Set Enable Register
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER14
+ ISER14
+ Interrupt Set Enable Register
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ISER15
+ ISER15
+ Interrupt Set Enable Register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETENA
+ SETENA
+ 0
+ 32
+
+
+
+
+ ICER0
+ ICER0
+ Interrupt Clear Enable
+ Register
+ 0x80
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER1
+ ICER1
+ Interrupt Clear Enable
+ Register
+ 0x84
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER2
+ ICER2
+ Interrupt Clear Enable
+ Register
+ 0x8C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER3
+ ICER3
+ Interrupt Clear Enable
+ Register
+ 0x90
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER4
+ ICER4
+ Interrupt Clear Enable
+ Register
+ 0x94
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER5
+ ICER5
+ Interrupt Clear Enable
+ Register
+ 0x98
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER6
+ ICER6
+ Interrupt Clear Enable
+ Register
+ 0x9C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER7
+ ICER7
+ Interrupt Clear Enable
+ Register
+ 0xA0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER8
+ ICER8
+ Interrupt Clear Enable
+ Register
+ 0xA4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER9
+ ICER9
+ Interrupt Clear Enable
+ Register
+ 0xA8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER10
+ ICER10
+ Interrupt Clear Enable
+ Register
+ 0xAC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER11
+ ICER11
+ Interrupt Clear Enable
+ Register
+ 0xB0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER12
+ ICER12
+ Interrupt Clear Enable
+ Register
+ 0xB4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER13
+ ICER13
+ Interrupt Clear Enable
+ Register
+ 0xB8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER14
+ ICER14
+ Interrupt Clear Enable
+ Register
+ 0xBC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ICER15
+ ICER15
+ Interrupt Clear Enable
+ Register
+ 0xC0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRENA
+ CLRENA
+ 0
+ 32
+
+
+
+
+ ISPR0
+ ISPR0
+ Interrupt Set-Pending Register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR1
+ ISPR1
+ Interrupt Set-Pending Register
+ 0x104
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR2
+ ISPR2
+ Interrupt Set-Pending Register
+ 0x108
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR3
+ ISPR3
+ Interrupt Set-Pending Register
+ 0x10C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR4
+ ISPR4
+ Interrupt Set-Pending Register
+ 0x110
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR5
+ ISPR5
+ Interrupt Set-Pending Register
+ 0x114
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR6
+ ISPR6
+ Interrupt Set-Pending Register
+ 0x118
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR7
+ ISPR7
+ Interrupt Set-Pending Register
+ 0x11C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR8
+ ISPR8
+ Interrupt Set-Pending Register
+ 0x120
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR9
+ ISPR9
+ Interrupt Set-Pending Register
+ 0x124
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR10
+ ISPR10
+ Interrupt Set-Pending Register
+ 0x128
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR11
+ ISPR11
+ Interrupt Set-Pending Register
+ 0x12C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR12
+ ISPR12
+ Interrupt Set-Pending Register
+ 0x130
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR13
+ ISPR13
+ Interrupt Set-Pending Register
+ 0x134
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR14
+ ISPR14
+ Interrupt Set-Pending Register
+ 0x138
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ISPR15
+ ISPR15
+ Interrupt Set-Pending Register
+ 0x13C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SETPEND
+ SETPEND
+ 0
+ 32
+
+
+
+
+ ICPR0
+ ICPR0
+ Interrupt Clear-Pending
+ Register
+ 0x180
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR1
+ ICPR1
+ Interrupt Clear-Pending
+ Register
+ 0x184
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR2
+ ICPR2
+ Interrupt Clear-Pending
+ Register
+ 0x188
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR3
+ ICPR3
+ Interrupt Clear-Pending
+ Register
+ 0x18C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR4
+ ICPR4
+ Interrupt Clear-Pending
+ Register
+ 0x190
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR5
+ ICPR5
+ Interrupt Clear-Pending
+ Register
+ 0x194
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR6
+ ICPR6
+ Interrupt Clear-Pending
+ Register
+ 0x198
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR7
+ ICPR7
+ Interrupt Clear-Pending
+ Register
+ 0x19C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR8
+ ICPR8
+ Interrupt Clear-Pending
+ Register
+ 0x1A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR9
+ ICPR9
+ Interrupt Clear-Pending
+ Register
+ 0x1A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR10
+ ICPR10
+ Interrupt Clear-Pending
+ Register
+ 0x1A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR11
+ ICPR11
+ Interrupt Clear-Pending
+ Register
+ 0x1AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR12
+ ICPR12
+ Interrupt Clear-Pending
+ Register
+ 0x1B0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR13
+ ICPR13
+ Interrupt Clear-Pending
+ Register
+ 0x1B4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR14
+ ICPR14
+ Interrupt Clear-Pending
+ Register
+ 0x1B8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ ICPR15
+ ICPR15
+ Interrupt Clear-Pending
+ Register
+ 0x1BC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CLRPEND
+ CLRPEND
+ 0
+ 32
+
+
+
+
+ IABR0
+ IABR0
+ Interrupt Active bit
+ Register
+ 0x200
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR1
+ IABR1
+ Interrupt Active bit
+ Register
+ 0x204
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR2
+ IABR2
+ Interrupt Active bit
+ Register
+ 0x208
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR3
+ IABR3
+ Interrupt Active bit
+ Register
+ 0x20C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR4
+ IABR4
+ Interrupt Active bit
+ Register
+ 0x210
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR5
+ IABR5
+ Interrupt Active bit
+ Register
+ 0x214
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR6
+ IABR6
+ Interrupt Active bit
+ Register
+ 0x218
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR7
+ IABR7
+ Interrupt Active bit
+ Register
+ 0x21C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR8
+ IABR8
+ Interrupt Active bit
+ Register
+ 0x220
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR9
+ IABR9
+ Interrupt Active bit
+ Register
+ 0x224
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR10
+ IABR10
+ Interrupt Active bit
+ Register
+ 0x228
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR11
+ IABR11
+ Interrupt Active bit
+ Register
+ 0x22C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR12
+ IABR12
+ Interrupt Active bit
+ Register
+ 0x230
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR13
+ IABR13
+ Interrupt Active bit
+ Register
+ 0x234
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR14
+ IABR14
+ Interrupt Active bit
+ Register
+ 0x238
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ IABR15
+ IABR15
+ Interrupt Active bit
+ Register
+ 0x23C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IABR
+ IABR
+ 0
+ 32
+
+
+
+
+ ITNS0
+ ITNS0
+ Interrupt Active bit
+ Register
+ 0x280
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS1
+ ITNS1
+ Interrupt Active bit
+ Register
+ 0x284
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS2
+ ITNS2
+ Interrupt Active bit
+ Register
+ 0x288
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS3
+ ITNS3
+ Interrupt Active bit
+ Register
+ 0x28C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS4
+ ITNS4
+ Interrupt Active bit
+ Register
+ 0x290
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS5
+ ITNS5
+ Interrupt Active bit
+ Register
+ 0x294
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS6
+ ITNS6
+ Interrupt Active bit
+ Register
+ 0x298
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS7
+ ITNS7
+ Interrupt Active bit
+ Register
+ 0x29C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS8
+ ITNS8
+ Interrupt Active bit
+ Register
+ 0x2A0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS9
+ ITNS9
+ Interrupt Active bit
+ Register
+ 0x2A4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS10
+ ITNS10
+ Interrupt Active bit
+ Register
+ 0x2A8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS11
+ ITNS11
+ Interrupt Active bit
+ Register
+ 0x2AC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS12
+ ITNS12
+ Interrupt Active bit
+ Register
+ 0x2B0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS13
+ ITNS13
+ Interrupt Active bit
+ Register
+ 0x2B4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS14
+ ITNS14
+ Interrupt Active bit
+ Register
+ 0x2B8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ ITNS15
+ ITNS15
+ Interrupt Active bit
+ Register
+ 0x2BC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ITNS
+ ITNS
+ 0
+ 32
+
+
+
+
+ IPR0
+ IPR0
+ Interrupt Priority Register 0
+ 0x300
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_00
+ PRI_00
+ 0
+ 8
+
+
+
+
+ IPR1
+ IPR1
+ Interrupt Priority Register 1
+ 0x301
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_01
+ PRI_01
+ 0
+ 8
+
+
+
+
+ IPR2
+ IPR2
+ Interrupt Priority Register 2
+ 0x302
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_02
+ PRI_02
+ 0
+ 8
+
+
+
+
+ IPR3
+ IPR3
+ Interrupt Priority Register 3
+ 0x303
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_03
+ PRI_03
+ 0
+ 8
+
+
+
+
+ IPR4
+ IPR4
+ Interrupt Priority Register 4
+ 0x304
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_04
+ PRI_04
+ 0
+ 8
+
+
+
+
+ IPR5
+ IPR5
+ Interrupt Priority Register 5
+ 0x305
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_05
+ PRI_05
+ 0
+ 8
+
+
+
+
+ IPR6
+ IPR6
+ Interrupt Priority Register 6
+ 0x306
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_06
+ PRI_06
+ 0
+ 8
+
+
+
+
+ IPR7
+ IPR7
+ Interrupt Priority Register 7
+ 0x307
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_07
+ PRI_07
+ 0
+ 8
+
+
+
+
+ IPR8
+ IPR8
+ Interrupt Priority Register 8
+ 0x308
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_08
+ PRI_08
+ 0
+ 8
+
+
+
+
+ IPR9
+ IPR9
+ Interrupt Priority Register 9
+ 0x309
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_09
+ PRI_09
+ 0
+ 8
+
+
+
+
+ IPR10
+ IPR10
+ Interrupt Priority Register 10
+ 0x30A
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_10
+ PRI_10
+ 0
+ 8
+
+
+
+
+ IPR11
+ IPR11
+ Interrupt Priority Register 11
+ 0x30B
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_11
+ PRI_11
+ 0
+ 8
+
+
+
+
+ IPR12
+ IPR12
+ Interrupt Priority Register 12
+ 0x30C
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_12
+ PRI_12
+ 0
+ 8
+
+
+
+
+ IPR13
+ IPR13
+ Interrupt Priority Register 13
+ 0x30D
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_13
+ PRI_13
+ 0
+ 8
+
+
+
+
+ IPR14
+ IPR14
+ Interrupt Priority Register 14
+ 0x30E
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_14
+ PRI_14
+ 0
+ 8
+
+
+
+
+ IPR15
+ IPR15
+ Interrupt Priority Register 15
+ 0x30F
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_15
+ PRI_15
+ 0
+ 8
+
+
+
+
+ IPR16
+ IPR16
+ Interrupt Priority Register 16
+ 0x310
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_16
+ PRI_16
+ 0
+ 8
+
+
+
+
+ IPR17
+ IPR17
+ Interrupt Priority Register 17
+ 0x311
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_17
+ PRI_17
+ 0
+ 8
+
+
+
+
+ IPR18
+ IPR18
+ Interrupt Priority Register 18
+ 0x312
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_18
+ PRI_18
+ 0
+ 8
+
+
+
+
+ IPR19
+ IPR19
+ Interrupt Priority Register 19
+ 0x313
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_19
+ PRI_19
+ 0
+ 8
+
+
+
+
+ IPR20
+ IPR20
+ Interrupt Priority Register 20
+ 0x314
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_20
+ PRI_20
+ 0
+ 8
+
+
+
+
+ IPR21
+ IPR21
+ Interrupt Priority Register 21
+ 0x315
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_21
+ PRI_21
+ 0
+ 8
+
+
+
+
+ IPR22
+ IPR22
+ Interrupt Priority Register 22
+ 0x316
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_22
+ PRI_22
+ 0
+ 8
+
+
+
+
+ IPR23
+ IPR23
+ Interrupt Priority Register 23
+ 0x317
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_23
+ PRI_23
+ 0
+ 8
+
+
+
+
+ IPR24
+ IPR24
+ Interrupt Priority Register 24
+ 0x318
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_24
+ PRI_24
+ 0
+ 8
+
+
+
+
+ IPR25
+ IPR25
+ Interrupt Priority Register 25
+ 0x319
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_25
+ PRI_25
+ 0
+ 8
+
+
+
+
+ IPR26
+ IPR26
+ Interrupt Priority Register 26
+ 0x31A
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_26
+ PRI_26
+ 0
+ 8
+
+
+
+
+ IPR27
+ IPR27
+ Interrupt Priority Register 27
+ 0x31B
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_27
+ PRI_27
+ 0
+ 8
+
+
+
+
+ IPR28
+ IPR28
+ Interrupt Priority Register 28
+ 0x31C
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_28
+ PRI_28
+ 0
+ 8
+
+
+
+
+ IPR29
+ IPR29
+ Interrupt Priority Register 29
+ 0x31D
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_29
+ PRI_29
+ 0
+ 8
+
+
+
+
+ IPR30
+ IPR30
+ Interrupt Priority Register 30
+ 0x31E
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_30
+ PRI_30
+ 0
+ 8
+
+
+
+
+ IPR31
+ IPR31
+ Interrupt Priority Register 31
+ 0x31F
+ 0x08
+ read-write
+ 0x00
+
+
+ PRI_31
+ PRI_31
+ 0
+ 8
+
+
+
+
+
+
+ PMU
+ Power management unit
+ PMU
+ 0x40007000
+
+ 0x0
+ 0x400
+ registers
+
+
+
+ CTL
+ CTL
+ power control register
+ 0x0
+ 0x20
+ read-write
+ 0x00004000
+
+
+ LDOVS
+ LDO output voltage select
+ 14
+ 2
+
+
+ BKPWEN
+ Backup Domain Write Enable
+ 8
+ 1
+
+
+ LVDT
+ Low Voltage Detector Threshold
+ 5
+ 3
+
+
+ LVDEN
+ Low Voltage Detector Enable
+ 4
+ 1
+
+
+ STBRST
+ Standby Flag Reset
+ 3
+ 1
+
+
+ WURST
+ Wakeup Flag Reset
+ 2
+ 1
+
+
+ STBMOD
+ Standby Mode
+ 1
+ 1
+
+
+ LDOLP
+ LDO Low Power Mode
+ 0
+ 1
+
+
+
+
+ CS
+ CS
+ power control/status register
+ 0x04
+ 0x20
+ 0x00000000
+
+
+ WUPEN6
+ WKUP pin6 Enable
+ 14
+ 1
+ read-write
+
+
+ WUPEN5
+ WKUP pin5 Enable
+ 13
+ 1
+ read-write
+
+
+ WUPEN0
+ WKUP pin0 Enable
+ 8
+ 1
+ read-write
+
+
+ LVDF
+ Low Voltage Detector Status Flag
+ 2
+ 1
+ read-only
+
+
+ STBF
+ Standby flag
+ 1
+ 1
+ read-only
+
+
+ WUF
+ Wakeup flag
+ 0
+ 1
+ read-only
+
+
+
+
+
+
+ RCU
+ Reset and clock unit
+ RCU
+ 0x40021000
+
+ 0x0
+ 0x400
+ registers
+
+
+ RCU
+ 4
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ 0x00000083
+
+
+ PLLSTB
+ PLL Clock Stabilization Flag
+ 25
+ 1
+ read-only
+
+
+ PLLEN
+ PLL enable
+ 24
+ 1
+ read-write
+
+
+ CKMEN
+ HXTAL Clock Monitor Enable
+ 19
+ 1
+ read-write
+
+
+ HXTALBPS
+ External crystal oscillator (HXTAL) clock bypass mode enable
+ 18
+ 1
+ read-write
+
+
+ HXTALSTB
+ External crystal oscillator (HXTAL) clock stabilization flag
+ 17
+ 1
+ read-only
+
+
+ HXTALEN
+ External High Speed oscillator Enable
+ 16
+ 1
+ read-write
+
+
+ IRC8MCALIB
+ High Speed Internal Oscillator calibration value register
+ 8
+ 8
+ read-only
+
+
+ IRC8MADJ
+ High Speed Internal Oscillator clock trim adjust value
+ 3
+ 5
+ read-write
+
+
+ IRC8MSTB
+ IRC8M High Speed Internal Oscillator stabilization Flag
+ 1
+ 1
+ read-only
+
+
+ IRC8MEN
+ Internal High Speed oscillator Enable
+ 0
+ 1
+ read-write
+
+
+
+
+ CFG0
+ CFG0
+ Clock configuration register 0
+ (RCU_CFG0)
+ 0x04
+ 0x20
+ 0x00000000
+
+
+ PLLDV
+ The CK_PLL divide by 1 or 2 for CK_OUT
+
+ 31
+ 1
+ read-write
+
+
+ CKOUTDIV
+ The CK_OUT divider which the CK_OUT frequency can be reduced
+ 28
+ 3
+ read-write
+
+
+ PLLMF_MSB
+ Bit 4 of PLLMF register
+ 27
+ 1
+ read-write
+
+
+ CKOUTSEL
+ CK_OUT Clock Source Selection
+ 24
+ 3
+ read-write
+
+
+ PLLMF
+ PLL multiply factor
+ 18
+ 4
+ read-write
+
+
+ PLLPREDV
+ HXTAL divider for PLL source clock selection.
+ 17
+ 1
+ read-write
+
+
+ PLLSEL
+ PLL Clock Source Selection
+ 16
+ 1
+ read-write
+
+
+ ADCPSC
+ ADC clock prescaler selection
+ 14
+ 2
+ read-write
+
+
+ APB2PSC
+ APB2 prescaler selection
+ 11
+ 3
+ read-write
+
+
+ APB1PSC
+ APB1 prescaler selection
+ 8
+ 3
+ read-write
+
+
+ AHBPSC
+ AHB prescaler selection
+ 4
+ 4
+ read-write
+
+
+ SCSS
+ System clock switch status
+ 2
+ 2
+ read-only
+
+
+ SCS
+ System clock switch
+ 0
+ 2
+ read-write
+
+
+
+
+ INT
+ INT
+ Clock interrupt register
+ (RCU_INT)
+ 0x08
+ 0x20
+ 0x00000000
+
+
+ CKMIC
+ HXTAL Clock Stuck Interrupt Clear
+ 23
+ 1
+ write-only
+
+
+ IRC28MSTBIC
+ IRC28M stabilization Interrupt Clear
+ 21
+ 1
+ write-only
+
+
+ PLLSTBIC
+ PLL stabilization Interrupt Clear
+ 20
+ 1
+ write-only
+
+
+ HXTALSTBIC
+ HXTAL Stabilization Interrupt Clear
+ 19
+ 1
+ write-only
+
+
+ IRC8MSTBIC
+ IRC8M Stabilization Interrupt Clear
+ 18
+ 1
+ write-only
+
+
+ LXTALSTBIC
+ LXTAL Stabilization Interrupt Clear
+ 17
+ 1
+ write-only
+
+
+ IRC40KSTBIC
+ IRC40K Stabilization Interrupt Clear
+ 16
+ 1
+ write-only
+
+
+ IRC28MSTBIE
+ IRC28M Stabilization Interrupt Enable
+ 13
+ 1
+ read-write
+
+
+ PLLSTBIE
+ PLL Stabilization Interrupt Enable
+ 12
+ 1
+ read-write
+
+
+ HXTALSTBIE
+ HXTAL Stabilization Interrupt Enable
+ 11
+ 1
+ read-write
+
+
+ IRC8MSTBIE
+ IRC8M Stabilization Interrupt Enable
+ 10
+ 1
+ read-write
+
+
+ LXTALSTBIE
+ LXTAL Stabilization Interrupt Enable
+ 9
+ 1
+ read-write
+
+
+ IRC40KSTBIE
+ IRC40K Stabilization interrupt enable
+ 8
+ 1
+ read-write
+
+
+ CKMIF
+ HXTAL Clock Stuck Interrupt Flag
+ 7
+ 1
+ read-only
+
+
+ IRC28MSTBIF
+ IRC28M stabilization interrupt flag
+ 5
+ 1
+ read-only
+
+
+ PLLSTBIF
+ PLL stabilization interrupt flag
+ 4
+ 1
+ read-only
+
+
+ HXTALSTBIF
+ HXTAL stabilization interrupt flag
+ 3
+ 1
+ read-only
+
+
+ IRC8MSTBIF
+ IRC8M stabilization interrupt flag
+ 2
+ 1
+ read-only
+
+
+ LXTALSTBIF
+ LXTAL stabilization interrupt flag
+ 1
+ 1
+ read-only
+
+
+ IRC40KSTBIF
+ IRC40K stabilization interrupt flag
+ 0
+ 1
+ read-only
+
+
+
+
+ APB2RST
+ APB2RST
+ APB2 reset register
+ (RCU_APB2RST)
+ 0x0C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMER16RST
+ TIMER16 reset
+ 18
+ 1
+
+
+ TIMER15RST
+ TIMER15 reset
+ 17
+ 1
+
+
+ TIMER14RST
+ TIMER14 reset
+ 16
+ 1
+
+
+ USART0RST
+ USART0 Reset
+ 14
+ 1
+
+
+ SPI0RST
+ SPI0 Reset
+ 12
+ 1
+
+
+ TIMER0RST
+ TIMER0 reset
+ 11
+ 1
+
+
+ ADCRST
+ ADC reset
+ 9
+ 1
+
+
+ CFGCMPRST
+ System configuration and comparator reset
+ 0
+ 1
+
+
+
+
+ APB1RST
+ APB1RST
+ APB1 reset register
+ (RCU_APB1RST)
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PMURST
+ Power control reset
+ 28
+ 1
+
+
+ I2C1RST
+ I2C1 reset
+ 22
+ 1
+
+
+ I2C0RST
+ I2C0 reset
+ 21
+ 1
+
+
+ USART1RST
+ USART1 reset
+ 17
+ 1
+
+
+ SPI1RST
+ SPI1 reset
+ 14
+ 1
+
+
+ WWDGTRST
+ Window watchdog timer reset
+ 11
+ 1
+
+
+ TIMER13RST
+ TIMER13 timer reset
+ 8
+ 1
+
+
+ TIMER5RST
+ TIMER5 timer reset
+ 4
+ 1
+
+
+ TIMER2RST
+ TIMER2 timer reset
+ 1
+ 1
+
+
+
+
+ AHBEN
+ AHBEN
+ AHB enable register
+ (RCU_AHBEN)
+ 0x14
+ 0x20
+ read-write
+ 0x00000014
+
+
+ PFEN
+ GPIO port F clock enable
+ 22
+ 1
+
+
+ PCEN
+ GPIO port C clock enable
+ 19
+ 1
+
+
+ PBEN
+ GPIO port B clock enable
+ 18
+ 1
+
+
+ PAEN
+ GPIO port A clock enable
+ 17
+ 1
+
+
+ CRCEN
+ CRC clock enable
+ 6
+ 1
+
+
+ FMCSPEN
+ FMC clock during sleep mode enable
+ 4
+ 1
+
+
+ SRAMSPEN
+ SRAM interface clock during sleep mode enable
+ 2
+ 1
+
+
+ DMAEN
+ DMA clock enable
+ 0
+ 1
+
+
+
+
+ APB2EN
+ APB2EN
+ APB2 enable register
+ (RCU_APB2EN)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DBGMCUEN
+ DBGMCU clock enable
+ 22
+ 1
+
+
+ TIMER16EN
+ TIMER16 timer clock enable
+ 18
+ 1
+
+
+ TIMER15EN
+ TIMER15 timer clock enable
+ 17
+ 1
+
+
+ TIMER14EN
+ TIMER14 timer clock enable
+ 16
+ 1
+
+
+ USART0EN
+ USART0 clock enable
+ 14
+ 1
+
+
+ SPI0EN
+ SPI0 clock enable
+ 12
+ 1
+
+
+ TIMER0EN
+ TIMER0 timer clock enable
+ 11
+ 1
+
+
+ ADCEN
+ ADC interface clock enable
+ 9
+ 1
+
+
+ CFGCMPEN
+ System configuration and comparator clock enable
+ 0
+ 1
+
+
+
+
+ APB1EN
+ APB1EN
+ APB1 enable register
+ (RCU_APB1EN)
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PMUEN
+ Power interface clock enable
+ 28
+ 1
+
+
+ I2C1EN
+ I2C1 clock enable
+ 22
+ 1
+
+
+ I2C0EN
+ I2C0 clock enable
+ 21
+ 1
+
+
+ USART1EN
+ USART1 clock enable
+ 17
+ 1
+
+
+ SPI1EN
+ SPI1 clock enable
+ 14
+ 1
+
+
+ WWDGTEN
+ Window watchdog timer clock enable
+ 11
+ 1
+
+
+ TIMER13EN
+ TIMER13 timer clock enable
+ 8
+ 1
+
+
+ TIMER5EN
+ TIMER5 timer clock enable
+ 4
+ 1
+
+
+ TIMER2EN
+ TIMER2 timer clock enable
+ 1
+ 1
+
+
+
+
+ BDCTL
+ BDCTL
+ Backup domain control register
+ (RCU_BDCTL)
+ 0x20
+ 0x20
+ 0x00000018
+
+
+ BKPRST
+ Backup domain reset
+ 16
+ 1
+ read-write
+
+
+ RTCEN
+ RTC clock enable
+ 15
+ 1
+ read-write
+
+
+ RTCSRC
+ RTC clock entry selection
+ 8
+ 2
+ read-write
+
+
+ LXTALDRI
+ LXTAL drive capability
+ 3
+ 2
+ read-write
+
+
+ LXTALBPS
+ LXTAL bypass mode enable
+ 2
+ 1
+ read-write
+
+
+ LXTALSTB
+ External low-speed oscillator stabilization
+ 1
+ 1
+ read-only
+
+
+ LXTALEN
+ LXTAL enable
+ 0
+ 1
+ read-write
+
+
+
+
+ RSTSCK
+ RSTSCK
+ Reset source /clock register
+ (RCU_RSTSCK)
+ 0x24
+ 0x20
+ 0x0C000000
+
+
+ LPRSTF
+ Low-power reset flag
+ 31
+ 1
+ read-write
+
+
+ WWDGTRSTF
+ Window watchdog timer reset flag
+ 30
+ 1
+ read-write
+
+
+ FWDGTRSTF
+ Free Watchdog timer reset flag
+ 29
+ 1
+ read-write
+
+
+ SWRSTF
+ Software reset flag
+ 28
+ 1
+ read-write
+
+
+ PORRSTF
+ Power reset flag
+ 27
+ 1
+ read-write
+
+
+ EPRSTF
+ External PIN reset flag
+ 26
+ 1
+ read-write
+
+
+ OBLRSTF
+ Option byte loader reset flag
+ 25
+ 1
+ read-write
+
+
+ RSTFC
+ Reset flag clear
+ 24
+ 1
+ read-write
+
+
+ V12RSTF
+ V12 domain Power reset flag
+ 23
+ 1
+ read-write
+
+
+ IRC40KSTB
+ IRC40K stabilization
+ 1
+ 1
+ read-only
+
+
+ IRC40KEN
+ IRC40K enable
+ 0
+ 1
+ read-write
+
+
+
+
+ AHBRST
+ AHBRST
+ AHB reset register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PFRST
+ GPIO port F reset
+ 22
+ 1
+
+
+ PCRST
+ GPIO port C reset
+ 19
+ 1
+
+
+ PBRST
+ GPIO port B reset
+ 18
+ 1
+
+
+ PARST
+ GPIO port A reset
+ 17
+ 1
+
+
+
+
+ CFG1
+ CFG1
+ Configuration register 1
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PREDV
+ CK_HXTAL or CK_IRC48M divider previous PLL
+ 0
+ 4
+
+
+
+
+ CFG2
+ CFG2
+ Configuration register 2
+ 0x30
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADCPSC
+ Bit 2 of ADCPSC
+ 31
+ 1
+
+
+ IRC28MDIV
+ CK_IRC28M divider 2 or not
+ 16
+ 1
+
+
+ ADCSEL
+ CK_ADC clock source selection
+ 8
+ 1
+
+
+ USART0SEL
+ CK_USART0 clock source selection
+ 0
+ 2
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x34
+ 0x20
+ 0x00000080
+
+
+ IRC28MCALIB
+ Internal 28M RC Oscillator calibration value register
+ 8
+ 8
+ read-only
+
+
+ IRC28MADJ
+ Internal 28M RC Oscillator clock trim adjust value
+ 3
+ 5
+ read-write
+
+
+ IRC28MSTB
+ IRC28M Internal 28M RC Oscillator stabilization Flag
+ 1
+ 1
+ read-only
+
+
+ IRC28MEN
+ IRC28M Internal 28M RC oscillator Enable
+ 0
+ 1
+ read-write
+
+
+
+
+ VKEY
+ VKEY
+ Voltage key register
+ 0x100
+ 0x20
+ 0x00000000
+
+
+ KEY
+ The key of RCU_DSV register
+ 0
+ 32
+ write
+
+
+
+
+ DSV
+ DSV
+ Deep-sleep mode voltage register
+ 0x134
+ 0x20
+ 0x00000000
+
+
+ DSLPVS
+ Deep-sleep mode voltage select
+ 0
+ 2
+ read-write
+
+
+
+
+
+
+ RTC
+ Real-time clock
+ RTC
+ 0x40002800
+
+ 0x0
+ 0x400
+ registers
+
+
+ RTC
+ 2
+
+
+
+ TIME
+ TIME
+ time register
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PM
+ AM/PM mark
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD code
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD format
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD code
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD code
+ 8
+ 4
+
+
+ SCT
+ Second tens in BCD code
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD code
+ 0
+ 4
+
+
+
+
+ DATE
+ DATE
+ date register
+ 0x4
+ 0x20
+ read-write
+ 0x00002101
+
+
+ YRT
+ Year tens in BCD code
+ 20
+ 4
+
+
+ YRU
+ Year units in BCD code
+ 16
+ 4
+
+
+ DOW
+ Days of the week
+ 13
+ 3
+
+
+ MONT
+ Month tens in BCD code
+ 12
+ 1
+
+
+ MONU
+ Month units in BCD code
+ 8
+ 4
+
+
+ DAYT
+ Date tens in BCD code
+ 4
+ 2
+
+
+ DAYU
+ Date units in BCD code
+ 0
+ 4
+
+
+
+
+ CTL
+ CTL
+ control register
+ 0x8
+ 0x20
+ 0x00000000
+
+
+ DSM
+ Backup
+ 18
+ 1
+ read-write
+
+
+ S1H
+ Subtract 1 hour (winter time
+ change)
+ 17
+ 1
+ write-only
+
+
+ A1H
+ Add 1 hour (summer time
+ change)
+ 16
+ 1
+ write-only
+
+
+ ALRM0IE
+ Alarm A interrupt enable
+ 12
+ 1
+ read-write
+
+
+ ALRM0EN
+ Alarm A enable
+ 8
+ 1
+ read-write
+
+
+ CS
+ Hour format
+ 6
+ 1
+ read-write
+
+
+ BPSHAD
+ Bypass the shadow
+ registers
+ 5
+ 1
+ read-write
+
+
+ REFEN
+ RTC_REFIN reference clock detection
+ enable (50 or 60 Hz)
+ 4
+ 1
+ read-write
+
+
+
+
+ STAT
+ STAT
+ initialization and status
+ register
+ 0xC
+ 0x20
+ 0x00000007
+
+
+ SCPF
+ Recalibration pending Flag
+ 16
+ 1
+ read-only
+
+
+ TP1F
+ RTC_TAMP1 detection flag
+ 14
+ 1
+ read-write
+
+
+ ALRM0F
+ Alarm A flag
+ 8
+ 1
+ read-write
+
+
+ INITM
+ Initialization mode
+ 7
+ 1
+ read-write
+
+
+ INITF
+ Initialization flag
+ 6
+ 1
+ read-only
+
+
+ RSYNF
+ Registers synchronization
+ flag
+ 5
+ 1
+ read-write
+
+
+ YCM
+ Initialization status flag
+ 4
+ 1
+ read-only
+
+
+ SOPF
+ Shift operation pending
+ 3
+ 1
+ read-only
+
+
+ ALRM0WF
+ Alarm A write flag
+ 0
+ 1
+ read-only
+
+
+
+
+ PSC
+ PSC
+ prescaler register
+ 0x10
+ 0x20
+ read-write
+ 0x007F00FF
+
+
+ FACTOR_A
+ Asynchronous prescaler
+ factor
+ 16
+ 7
+
+
+ FACTOR_S
+ Synchronous prescaler
+ factor
+ 0
+ 15
+
+
+
+
+ ALRM0TD
+ ALRM0TD
+ alarm A register
+ 0x1C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSKD
+ Alarm date mask
+ 31
+ 1
+
+
+ DOWS
+ Week day selection
+ 30
+ 1
+
+
+ DAYT
+ Date tens in BCD format.
+ 28
+ 2
+
+
+ DAYU
+ Date units or day in BCD
+ format.
+ 24
+ 4
+
+
+ MSKH
+ Alarm hours mask
+ 23
+ 1
+
+
+ PM
+ AM/PM notation
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD format.
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD format.
+ 16
+ 4
+
+
+ MSKM
+ Alarm minutes mask
+ 15
+ 1
+
+
+ MNT
+ Minute tens in BCD format.
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD
+ format.
+ 8
+ 4
+
+
+ MSKS
+ Alarm seconds mask
+ 7
+ 1
+
+
+ SCT
+ Second tens in BCD format.
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD
+ format.
+ 0
+ 4
+
+
+
+
+ WPK
+ WPK
+ write protection register
+ 0x24
+ 0x20
+ write-only
+ 0x00000000
+
+
+ WPK
+ Write protection key
+ 0
+ 8
+
+
+
+
+ SS
+ SS
+ sub second register
+ 0x28
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSC
+ Sub second value
+ 0
+ 16
+
+
+
+
+ SHIFTCTL
+ SHIFTCTL
+ shift control register
+ 0x2C
+ 0x20
+ write-only
+ 0x00000000
+
+
+ A1S
+ One second add
+ 31
+ 1
+
+
+ SFS
+ Subtract a fraction of a
+ second
+ 0
+ 15
+
+
+
+
+ TTS
+ TTS
+ timestamp time register
+ 0x30
+ 0x20
+ read-only
+ 0x00000000
+
+
+ PM
+ AM/PM mark
+ 22
+ 1
+
+
+ HRT
+ Hour tens in BCD code
+ 20
+ 2
+
+
+ HRU
+ Hour units in BCD code
+ 16
+ 4
+
+
+ MNT
+ Minute tens in BCD code
+ 12
+ 3
+
+
+ MNU
+ Minute units in BCD code
+ 8
+ 4
+
+
+ SCT
+ Second tens in BCD code
+ 4
+ 3
+
+
+ SCU
+ Second units in BCD code
+ 0
+ 4
+
+
+
+
+ DTS
+ DTS
+ Date of time stamp register
+ 0x34
+ 0x20
+ read-only
+ 0x00000000
+
+
+ DOW
+ Week day units
+ 13
+ 3
+
+
+ MONT
+ Month tens in BCD code
+ 12
+ 1
+
+
+ MONU
+ Month units in BCD code
+ 8
+ 4
+
+
+ DAYT
+ Date tens in BCD code
+ 5
+ 2
+
+
+ DAYU
+ Date units in BCD code
+ 0
+ 5
+
+
+
+
+ SSTS
+ SSTS
+ time-stamp sub second register
+ 0x38
+ 0x20
+ read-only
+ 0x00000000
+
+
+ SSC
+ Sub second value
+ 0
+ 16
+
+
+
+
+ HRFC
+ HRFC
+ High resolution frequency compensation register
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ FREQI
+ Increase RTC frequency by 488.5PPM
+ 15
+ 1
+
+
+ CWND8
+ Frequency compensation window 8 second selected
+ 14
+ 1
+
+
+ CWND16
+ Frequency compensation window 16 second selected
+ 13
+ 1
+
+
+ CMSK
+ Calibration mask number
+ 0
+ 9
+
+
+
+
+ TAMP
+ TAMP
+ tamper and alternate function configuration
+ register
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ PC15MDE
+ PC15 mode
+ 23
+ 1
+
+
+ PC15VAL
+ PC15 value
+ 22
+ 1
+
+
+ PC14MDE
+ PC14 mode
+ 21
+ 1
+
+
+ PC14VAL
+ PC14 value
+ 20
+ 1
+
+
+ DISPU
+ RTC_TAMPx pull-up disable
+ 15
+ 1
+
+
+ PRCH
+ RTC_TAMPx precharge
+ duration
+ 13
+ 2
+
+
+ FLT
+ RTC_TAMPx filter count
+ 11
+ 2
+
+
+ FREQ
+ Tamper sampling frequency
+ 8
+ 3
+
+
+ TP1EG
+ Tamper 1 event trigger edge
+ 4
+ 1
+
+
+ TP1EN
+ Tamper 1 detection enable
+ 3
+ 1
+
+
+ TPIE
+ Tamper detection interrupt enable
+ 2
+ 1
+
+
+
+
+ ALRM0SS
+ ALRM0SS
+ alarm 0 sub second register
+ 0x44
+ 0x20
+ read-write
+ 0x00000000
+
+
+ MSKSSC
+ Mask control bit of SSC
+ 24
+ 4
+
+
+ SSC
+ Alarm sub second value
+ 0
+ 15
+
+
+
+
+ BKP0
+ BKP0
+ backup register
+ 0x50
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP1
+ BKP1
+ backup register
+ 0x54
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP2
+ BKP2
+ backup register
+ 0x58
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP3
+ BKP3
+ backup register
+ 0x5C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+ BKP4
+ BKP4
+ backup register
+ 0x60
+ 0x20
+ read-write
+ 0x00000000
+
+
+ DATA
+ BKP data
+ 0
+ 32
+
+
+
+
+
+
+ SPI0
+ Serial peripheral interface
+ SPI
+ 0x40013000
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI0
+ 25
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BDEN
+ Bidirectional enable
+ 15
+ 1
+
+
+ BDOEN
+ Bidirectional Transmit output enable
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation enable
+ 13
+ 1
+
+
+ CRCNT
+ CRC transfer next
+ 12
+ 1
+
+
+ FF16
+ Data frame format
+ 11
+ 1
+
+
+ RO
+ Receive only
+ 10
+ 1
+
+
+ SWNSSEN
+ NSS Software Mode Selection
+ 9
+ 1
+
+
+ SWNSS
+ NSS Pin Selection In NSS Software Mode
+ 8
+ 1
+
+
+ LF
+ LSB First Mode
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ PSC
+ Master Clock Prescaler Selection
+ 3
+ 3
+
+
+ MSTMOD
+ Master Mode Enable
+ 2
+ 1
+
+
+ CKPL
+ Clock Polarity Selection
+ 1
+ 1
+
+
+ CKPH
+ Clock Phase Selection
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TBEIE
+ Transmit Buffer Empty Interrupt Enable
+ 7
+ 1
+
+
+ RBNEIE
+ Receive Buffer Not Empty Interrupt Enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ TMOD
+ SPI TI Mode Enable
+ 4
+ 1
+
+
+ NSSP
+ SPI NSS Pulse Mode Enable
+ 3
+ 1
+
+
+ NSSDRV
+ NSS output enable
+ 2
+ 1
+
+
+ DMATEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ DMAREN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ status register
+ 0x08
+ 0x20
+ 0x0002
+
+
+ FERR
+ Format Error
+ 8
+ 1
+ read-write
+
+
+ TRANS
+ Transmitting On-going Bit
+ 7
+ 1
+ read-only
+
+
+ RXORERR
+ Reception Overrun Error Bit
+ 6
+ 1
+ read-only
+
+
+ CONFERR
+ SPI Configuration error
+ 5
+ 1
+ read-only
+
+
+ CRCERR
+ SPI CRC Error Bit
+ 4
+ 1
+ read-write
+
+
+ TXURERR
+ Transmission underrun error bit
+ 3
+ 1
+ read-only
+
+
+ I2SCH
+ I2S channel side
+ 2
+ 1
+ read-only
+
+
+ TBE
+ Transmit Buffer Empty
+ 1
+ 1
+ read-only
+
+
+ RBNE
+ Receive Buffer Not Empty
+ 0
+ 1
+ read-only
+
+
+
+
+ DATA
+ DATA
+ data register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Data register
+ 0
+ 16
+
+
+
+
+ CPCPOLY
+ CPCPOLY
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ RX RCR register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCTL
+ I2SCTL
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SSEL
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOPMOD
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSMOD
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPL
+ Idle state clock polarity
+ 3
+ 1
+
+
+ DTLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPSC
+ I2SPSC
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ MCKOEN
+ I2S_MCK output enable
+ 9
+ 1
+
+
+ OF
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ DIV
+ Dividing factor for the prescaler
+ 0
+ 8
+
+
+
+
+
+
+ SPI1
+ Serial Peripheral Interface 1
+ 0x40003800
+
+ 0x0
+ 0x400
+ registers
+
+
+ SPI1
+ 26
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ BDEN
+ Bidirectional enable
+ 15
+ 1
+
+
+ BDOEN
+ Bidirectional Transmit output enable
+ 14
+ 1
+
+
+ CRCEN
+ Hardware CRC calculation enable
+ 13
+ 1
+
+
+ CRCNT
+ CRC transfer next
+ 12
+ 1
+
+
+ CRCL
+ CRC length
+ 11
+ 1
+
+
+ RO
+ Receive only
+ 10
+ 1
+
+
+ SWNSSEN
+ NSS Software Mode Selection
+ 9
+ 1
+
+
+ SWNSS
+ NSS Pin Selection In NSS Software Mode
+ 8
+ 1
+
+
+ LF
+ LSB First Mode
+ 7
+ 1
+
+
+ SPIEN
+ SPI enable
+ 6
+ 1
+
+
+ PSC
+ Master Clock Prescaler Selection
+ 3
+ 3
+
+
+ MSTMOD
+ Master Mode Enable
+ 2
+ 1
+
+
+ CKPL
+ Clock Polarity Selection
+ 1
+ 1
+
+
+ CKPH
+ Clock Phase Selection
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TXDMA_ODD
+ Odd bytes in TX DMA channel
+ 14
+ 1
+
+
+ RXDMA_ODD
+ Odd bytes in RX DMA channel
+ 13
+ 1
+
+
+ BYTEN
+ Byte access enable
+ 12
+ 1
+
+
+ DZ
+ Date size
+ 8
+ 4
+
+
+ TBEIE
+ Transmit Buffer Empty Interrupt Enable
+ 7
+ 1
+
+
+ RBNEIE
+ Receive Buffer Not Empty Interrupt Enable
+ 6
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 5
+ 1
+
+
+ TMOD
+ SPI TI Mode Enable
+ 4
+ 1
+
+
+ NSSP
+ SPI NSS Pulse Mode Enable
+ 3
+ 1
+
+
+ NSSDRV
+ NSS output enable
+ 2
+ 1
+
+
+ DMATEN
+ Tx buffer DMA enable
+ 1
+ 1
+
+
+ DMAREN
+ Rx buffer DMA enable
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ status register
+ 0x08
+ 0x20
+ 0x0002
+
+
+ TXLVL
+ Tx FIFO level
+ 11
+ 2
+ read-only
+
+
+ RXLVL
+ Rx FIFO level
+ 9
+ 2
+ read-only
+
+
+ FERR
+ Format Error
+ 8
+ 1
+ read-write
+
+
+ TRANS
+ Transmitting On-going Bit
+ 7
+ 1
+ read-only
+
+
+ RXORERR
+ Reception Overrun Error Bit
+ 6
+ 1
+ read-only
+
+
+ CONFERR
+ SPI Configuration error
+ 5
+ 1
+ read-only
+
+
+ CRCERR
+ SPI CRC Error Bit
+ 4
+ 1
+ read-write
+
+
+ TBE
+ Transmit Buffer Empty
+ 1
+ 1
+ read-only
+
+
+ RBNE
+ Receive Buffer Not Empty
+ 0
+ 1
+ read-only
+
+
+
+
+ DATA
+ DATA
+ data register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DATA
+ Data register
+ 0
+ 16
+
+
+
+
+ CPCPOLY
+ CPCPOLY
+ CRC polynomial register
+ 0x10
+ 0x20
+ read-write
+ 0x0007
+
+
+ CRCPOLY
+ CRC polynomial register
+ 0
+ 16
+
+
+
+
+ RCRC
+ RCRC
+ RX CRC register
+ 0x14
+ 0x20
+ read-only
+ 0x0000
+
+
+ RCRC
+ RX RCR register
+ 0
+ 16
+
+
+
+
+ TCRC
+ TCRC
+ TX CRC register
+ 0x18
+ 0x20
+ read-only
+ 0x0000
+
+
+ TCRC
+ Tx CRC register
+ 0
+ 16
+
+
+
+
+ I2SCTL
+ I2SCTL
+ I2S configuration register
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ I2SSEL
+ I2S mode selection
+ 11
+ 1
+
+
+ I2SEN
+ I2S Enable
+ 10
+ 1
+
+
+ I2SOPMOD
+ I2S configuration mode
+ 8
+ 2
+
+
+ PCMSMOD
+ PCM frame synchronization
+ 7
+ 1
+
+
+ I2SSTD
+ I2S standard selection
+ 4
+ 2
+
+
+ CKPL
+ Idle state clock polarity
+ 3
+ 1
+
+
+ DTLEN
+ Data length to be
+ transferred
+ 1
+ 2
+
+
+ CHLEN
+ Channel length (number of bits per audio
+ channel)
+ 0
+ 1
+
+
+
+
+ I2SPSC
+ I2SPSC
+ I2S prescaler register
+ 0x20
+ 0x20
+ read-write
+ 0x0002
+
+
+ MCKOEN
+ I2S_MCK output enable
+ 9
+ 1
+
+
+ OF
+ Odd factor for the
+ prescaler
+ 8
+ 1
+
+
+ DIV
+ Dividing factor for the prescaler
+ 0
+ 8
+
+
+
+
+ QCTL
+ QCTL
+ SPI quad wird control register
+ 0x80
+ 0x20
+ read-write
+ 0000
+
+
+ IO23_DRV
+ Drive IO2 and IO3 enable
+ 2
+ 1
+
+
+ QRD
+ Quad wire read select
+ 1
+ 1
+
+
+ QMOD
+ Quad wire mode enable
+ 0
+ 1
+
+
+
+
+
+
+
+ SYSCFG
+ System configuration controller
+ SYSCFG
+ 0x40010000
+
+ 0x0
+ 0x0400
+ registers
+
+
+
+ CFG0
+ CFG0
+ System configuration register 0
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TIMER16_DMA_RMP
+ Timer 16 DMA request remapping enable
+ 12
+ 1
+
+
+ TIMER15_DMA_RMP
+ Timer 15 DMA request remapping enable
+ 11
+ 1
+
+
+ USART0_RX_DMA_RMP
+ USART0_RX DMA request remapping enable
+ 10
+ 1
+
+
+ USART0_TX_DMA_RMP
+ USART0_TX DMA request remapping enable
+ 9
+ 1
+
+
+ ADC_DMA_RMP
+ ADC DMA request remapping enable
+ 8
+ 1
+
+
+ PA11_PA12_RMP
+ PA11 and PA12 remapping bit for small packages
+ 4
+ 1
+
+
+ BOOT_MODE
+ Boot mode
+ 0
+ 2
+ read-only
+
+
+
+
+ EXTISS0
+ EXTISS0
+ EXTI sources selection register
+ 0
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI3_SS
+ EXTI 3 sources selection
+ 12
+ 4
+
+
+ EXTI2_SS
+ EXTI 2 sources selection
+ 8
+ 4
+
+
+ EXTI1_SS
+ EXTI 1 sources selection
+ 4
+ 4
+
+
+ EXTI0_SS
+ EXTI 0 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS1
+ EXTISS1
+ EXTI sources selection register
+ 1
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI7_SS
+ EXTI 7 sources selection
+ 12
+ 4
+
+
+ EXTI6_SS
+ EXTI 6 sources selection
+ 8
+ 4
+
+
+ EXTI5_SS
+ EXTI 5 sources selection
+ 4
+ 4
+
+
+ EXTI4_SS
+ EXTI 4 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS2
+ EXTISS2
+ EXTI sources selection register
+ 2
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI11_SS
+ EXTI 11 sources selection
+ 12
+ 4
+
+
+ EXTI10_SS
+ EXTI 10 sources selection
+ 8
+ 4
+
+
+ EXTI9_SS
+ EXTI 9 sources selection
+ 4
+ 4
+
+
+ EXTI8_SS
+ EXTI 8 sources selection
+ 0
+ 4
+
+
+
+
+ EXTISS3
+ EXTISS3
+ EXTI sources selection register
+ 3
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EXTI15_SS
+ EXTI 15 sources selection
+ 12
+ 4
+
+
+ EXTI14_SS
+ EXTI 14 sources selection
+ 8
+ 4
+
+
+ EXTI13_SS
+ EXTI 13 sources selection
+ 4
+ 4
+
+
+ EXTI12_SS
+ EXTI 12 sources selection
+ 0
+ 4
+
+
+
+
+ CFG2
+ CFG2
+ System configuration register 2
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ SRAM_PCEF
+ SRAM parity check error flag
+ 8
+ 1
+
+
+ LVD_LOCK
+ LVD lock
+ 2
+ 1
+
+
+ SRAM_PARITY_ERROR_LOCK
+ SRAM parity check error lock
+ 1
+ 1
+
+
+ LOCKUP_LOCK
+ Cortex-M4 LOCKUP output lock
+ 0
+ 1
+
+
+
+
+ CPU_IRQ_LAT
+ CPU_IRQ_LAT
+ IRQ Latency register
+ 0x100
+ 0x20
+ read-write
+ 0x00000000
+
+
+ IRQ_LATENCY
+ specifies the minimum number of cycles between an interrupt
+ 0
+ 8
+
+
+
+
+
+
+ TIMER0
+ Advanced-timers
+ TIMER
+ 0x40012C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER0_BRK_UP_TRG_COM
+ 13
+
+
+ TIMER0_CC
+ 14
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CAM
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO3
+ Idle state of channel 3 output
+ 14
+ 1
+
+
+ ISO2N
+ Idle state of channel 2 complementary output
+ 13
+ 1
+
+
+ ISO2
+ Idle state of channel 2 output
+ 12
+ 1
+
+
+ ISO1N
+ Idle state of channel 1 complementary output
+ 11
+ 1
+
+
+ ISO1
+ Idle state of channel 1 output
+ 10
+ 1
+
+
+ ISO0N
+ Idle state of channel 0 complementary output
+ 9
+ 1
+
+
+ ISO0
+ Idle state of channel 0 output
+ 8
+ 1
+
+
+ TI0S
+ Channel 0 trigger input selection
+ 7
+ 1
+
+
+ MMC
+ Master mode control
+ 4
+ 3
+
+
+ DMAS
+ DMA request source selection
+ 3
+ 1
+
+
+ CCUC
+ Commutation control shadow register update control
+ 2
+ 1
+
+
+ CCSE
+ Commutation control shadow enable
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SCM1
+ Part of SMC for enable External clock mode1
+ 14
+ 1
+
+
+ ETPSC
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETFC
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ OCRC
+ Trigger selection
+ 3
+ 1
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CMTDEN
+ Reserved
+ 13
+ 1
+
+
+ CH3DEN
+ Capture/Compare 3 DMA request
+ enable
+ 12
+ 1
+
+
+ CH2DEN
+ Capture/Compare 2 DMA request
+ enable
+ 11
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH3IE
+ Capture/Compare 3 interrupt
+ enable
+ 4
+ 1
+
+
+ CH2IE
+ Capture/Compare 2 interrupt
+ enable
+ 3
+ 1
+
+
+ CH1IE
+ Capture/Compare 1 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3OF
+ Channel 3 over capture flag
+ 12
+ 1
+
+
+ CH2OF
+ Channel 2 over capture flag
+ 11
+ 1
+
+
+ CH1OF
+ Channel 1 over capture flag
+ 10
+ 1
+
+
+ CH0OF
+ Channel 0 over capture flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH3IF
+ Capture/Compare 3 interrupt
+ flag
+ 4
+ 1
+
+
+ CH2IF
+ Capture/Compare 2 interrupt
+ flag
+ 3
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ Software event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break event generation
+ 7
+ 1
+
+
+ TRGG
+ Trigger event generation
+ 6
+ 1
+
+
+ CMTG
+ Channel commutation event generation
+ 5
+ 1
+
+
+ CH3G
+ Channel 3's capture or compare event generation
+ 4
+ 1
+
+
+ CH2G
+ Channel 2's capture or compare event generation
+ 3
+ 1
+
+
+ CH1G
+ Channel 1's capture or compare event generation
+ 2
+ 1
+
+
+ CH0G
+ Channel 0's capture or compare event generation
+ 1
+ 1
+
+
+ UPG
+ Update event generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1COMCEN
+ Channel 1 output compare clear enable
+ 15
+ 1
+
+
+ CH1COMCTL
+ Channel 1 compare output control
+ 12
+ 3
+
+
+ CH1COMSEN
+ Channel 1 output compare shadow enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Channel 1 output compare fast enable
+ 10
+ 1
+
+
+ CH1MS
+ Channel 1 mode selection
+ 8
+ 2
+
+
+ CH0COMCEN
+ Channel 0 output compare clear enable
+ 7
+ 1
+
+
+ CH0COMCTL
+ Channel 0 compare output control
+ 4
+ 3
+
+
+ CH0COMSEN
+ Channel 0 compare output shadow enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Channel 0 output compare fast enable
+ 2
+ 1
+
+
+ CH0MS
+ Channel 0 I/O mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1CAPFLT
+ Channel 1 input capture filter control
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Channel 1 input capture prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Channel 1 mode selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Channel 0 input capture filter control
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Channel 0 input capture prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Channel 0 mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Output
+ CHCTL1_Output
+ capture/compare mode register (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3COMCEN
+ Channel 3 output compare clear enable
+ 15
+ 1
+
+
+ CH3COMCTL
+ Channel 3 compare output control
+ 12
+ 3
+
+
+ CH3COMSEN
+ Channel 3 output compare shadow enable
+ 11
+ 1
+
+
+ CH3COMFEN
+ Channel 3 output compare fast enable
+ 10
+ 1
+
+
+ CH3MS
+ Channel 3 mode selection
+ 8
+ 2
+
+
+ CH2COMCEN
+ Channel 2 output compare clear enable
+ 7
+ 1
+
+
+ CH2COMCTL
+ Channel 2 compare output control
+ 4
+ 3
+
+
+ CH2COMSEN
+ Channel 2 compare output shadow enable
+ 3
+ 1
+
+
+ CH2COMFEN
+ Channel 2 output compare fast enable
+ 2
+ 1
+
+
+ CH2MS
+ Channel 2 I/O mode selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Input
+ CHCTL1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CHCTL1_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3CAPFLT
+ Channel 3 input capture filter control
+ 12
+ 4
+
+
+ CH3CAPPSC
+ Channel 3 input capture prescaler
+ 10
+ 2
+
+
+ CH3MS
+ Channel 3 mode selection
+ 8
+ 2
+
+
+ CH2CAPFLT
+ Input capture 2 filter
+ 4
+ 4
+
+
+ CH2CAPPSC
+ Input capture 2 prescaler
+ 2
+ 2
+
+
+ CH2MS
+ Capture/compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CH3EN
+ Capture/Compare 3 output
+ enable
+ 12
+ 1
+
+
+ CH2NP
+ Capture/Compare 2 output
+ Polarity
+ 11
+ 1
+
+
+ CH2NEN
+ Capture/Compare 2 complementary output
+ enable
+ 10
+ 1
+
+
+ CH2P
+ Capture/Compare 2 output
+ Polarity
+ 9
+ 1
+
+
+ CH2EN
+ Capture/Compare 2 output
+ enable
+ 8
+ 1
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1NEN
+ Capture/Compare 1 complementary output
+ enable
+ 6
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Counter auto reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 1
+ 0x38
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CH2CV
+ CH2CV
+ capture/compare register 2
+ 0x3C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH2VAL
+ Capture/Compare 2 value
+ 0
+ 16
+
+
+
+
+ CH3CV
+ CH3CV
+ capture/compare register 3
+ 0x40
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3VAL
+ Capture/Compare 3 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ channel complementary protection register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ Lock configuration
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator setup
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA transfer count
+ 8
+ 5
+
+
+ DMATA
+ DMA transfer access start address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ Configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+
+
+
+
+ TIMER2
+ General-purpose-timers
+ TIMER
+ 0x40000400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER2
+ 16
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ CAM
+ Center-aligned mode
+ selection
+ 5
+ 2
+
+
+ DIR
+ Direction
+ 4
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ TI0S
+ TI0 selection
+ 7
+ 1
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode control register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ ETP
+ External trigger polarity
+ 15
+ 1
+
+
+ SMC1
+ External clock enable
+ 14
+ 1
+
+
+ ETPSC
+ External trigger prescaler
+ 12
+ 2
+
+
+ ETFC
+ External trigger filter
+ 8
+ 4
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ OCRC
+ OCREF clear source selection
+ 3
+ 1
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CH3DEN
+ Capture/Compare 3 DMA request
+ enable
+ 12
+ 1
+
+
+ CH2DEN
+ Capture/Compare 2 DMA request
+ enable
+ 11
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 1 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CH3IE
+ Capture/Compare 3 interrupt
+ enable
+ 4
+ 1
+
+
+ CH2IE
+ Capture/Compare 2 interrupt
+ enable
+ 3
+ 1
+
+
+ CH1IE
+ Capture/Compare 1 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3OF
+ Capture/Compare 3 overcapture
+ flag
+ 12
+ 1
+
+
+ CH2OF
+ Capture/Compare 2 overcapture
+ flag
+ 11
+ 1
+
+
+ CH1OF
+ Capture/compare 1 overcapture
+ flag
+ 10
+ 1
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CH3IF
+ Capture/Compare 3 interrupt
+ flag
+ 4
+ 1
+
+
+ CH2IF
+ Capture/Compare 2 interrupt
+ flag
+ 3
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ TRGG
+ Trigger generation
+ 6
+ 1
+
+
+ CH3G
+ Capture/compare 3
+ generation
+ 4
+ 1
+
+
+ CH2G
+ Capture/compare 2
+ generation
+ 3
+ 1
+
+
+ CH1G
+ Capture/compare 1
+ generation
+ 2
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register 0 (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1COMCEN
+ Output compare 1 clear
+ enable
+ 15
+ 1
+
+
+ CH1COMCTL
+ Output compare 1 mode
+ 12
+ 3
+
+
+ CH1COMSEN
+ Output compare 1 preload
+ enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Output compare 1 fast
+ enable
+ 10
+ 1
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0COMCEN
+ Output compare 0 clear
+ enable
+ 7
+ 1
+
+
+ CH0COMCTL
+ Output compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CAPFLT
+ Input capture 1 filter
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Input capture 1 prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Capture/compare 1
+ selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Output
+ CHCTL1_Output
+ capture/compare mode register 1 (output
+ mode)
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3COMCEN
+ Output compare 3 clear
+ enable
+ 15
+ 1
+
+
+ CH3COMCTL
+ Output compare 3 mode
+ 12
+ 3
+
+
+ CH3COMSEN
+ Output compare 3 preload
+ enable
+ 11
+ 1
+
+
+ CH3COMFEN
+ Output compare 3 fast
+ enable
+ 10
+ 1
+
+
+ CH3MS
+ Capture/Compare 3
+ selection
+ 8
+ 2
+
+
+ CH2COMCEN
+ Output compare 2 clear
+ enable
+ 7
+ 1
+
+
+ CH2COMCTL
+ Output compare 2 mode
+ 4
+ 3
+
+
+ CH2COMSEN
+ Output compare 2 preload
+ enable
+ 3
+ 1
+
+
+ CH2COMFEN
+ Output compare 2 fast
+ enable
+ 2
+ 1
+
+
+ CH2MS
+ Capture/Compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL1_Input
+ CHCTL1_Input
+ capture/compare mode register 1 (input
+ mode)
+ CHCTL1_Output
+ 0x1C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3CAPFLT
+ Input capture 3 filter
+ 12
+ 4
+
+
+ CH3CAPPSC
+ Input capture 3 prescaler
+ 10
+ 2
+
+
+ CH3MS
+ Capture/Compare 3
+ selection
+ 8
+ 2
+
+
+ CH2CAPFLT
+ Input capture 2 filter
+ 4
+ 4
+
+
+ CH2CAPPSC
+ Input capture 2 prescaler
+ 2
+ 2
+
+
+ CH2MS
+ Capture/Compare 2
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH3NP
+ Capture/Compare 3 output
+ Polarity
+ 15
+ 1
+
+
+ CH3P
+ Capture/Compare 3 output
+ Polarity
+ 13
+ 1
+
+
+ CH3EN
+ Capture/Compare 3 output
+ enable
+ 12
+ 1
+
+
+ CH2NP
+ Capture/Compare 2 output
+ Polarity
+ 11
+ 1
+
+
+ CH2P
+ Capture/Compare 2 output
+ Polarity
+ 9
+ 1
+
+
+ CH2EN
+ Capture/Compare 2 output
+ enable
+ 8
+ 1
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 1
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0VAL
+ Low Capture/Compare 1
+ value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 2
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1VAL
+ Low Capture/Compare 2
+ value
+ 0
+ 16
+
+
+
+
+ CH2CV
+ CH2CV
+ capture/compare register 2
+ 0x3C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH2VAL
+ High Capture/Compare value (TIM2
+ only)
+ 0
+ 16
+
+
+
+
+ CH3CV
+ CH3CV
+ capture/compare register 3
+ 0x40
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH3VAL
+ High Capture/Compare value (TIM2
+ only)
+ 0
+ 16
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA control register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA burst length
+ 8
+ 5
+
+
+ DMATA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA address for full transfer
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ Configuration
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER5
+ Basic-timers
+ TIMER
+ 0x40001000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER5
+ 17
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ status register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CNT
+ Low counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Low Auto-reload value
+ 0
+ 16
+
+
+
+
+
+
+ TIMER13
+ General-purpose-timers
+ TIMER
+ 0x40002000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER13
+ 19
+
+
+
+ CTL0
+ CTL0
+ control register 1
+ 0x00
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+ CH0COMFEN
+ Output compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 1 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ IRMP
+ IRMP
+ channel input remap register
+ 0x50
+ 0x20
+ read-write
+ 0x0000
+
+
+ CI0_RMP
+ Timer input 0 remap
+ 0
+ 2
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER14
+ General-purpose-timers
+ TIMER
+ 0x40014000
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER14
+ 20
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO1
+ Output Idle state 1
+ 10
+ 1
+
+
+ ISO0N
+ Output Idle state 0
+ 9
+ 1
+
+
+ ISO0
+ Output Idle state 0
+ 8
+ 1
+
+
+ MMC
+ Master mode selection
+ 4
+ 3
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUC
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCSE
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ SMCFG
+ SMCFG
+ slave mode configuration register
+ 0x08
+ 0x20
+ read-write
+ 0x0000
+
+
+ MSM
+ Master/Slave mode
+ 7
+ 1
+
+
+ TRGS
+ Trigger selection
+ 4
+ 3
+
+
+ SMC
+ Slave mode selection
+ 0
+ 3
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ TRGDEN
+ Trigger DMA request enable
+ 14
+ 1
+
+
+ CMTDEN
+ Commutation DMA request enable
+ 13
+ 1
+
+
+ CH1DEN
+ Capture/Compare 1 DMA request
+ enable
+ 10
+ 1
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ TRGIE
+ Trigger interrupt enable
+ 6
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH1IE
+ Capture/Compare 2 interrupt
+ enable
+ 2
+ 1
+
+
+ CH0IE
+ Capture/Compare 1 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1OF
+ Capture/compare 1 overcapture
+ flag
+ 10
+ 1
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ TRGIF
+ Trigger interrupt flag
+ 6
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH1IF
+ Capture/Compare 1 interrupt
+ flag
+ 2
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break generation
+ 7
+ 1
+
+
+ TRGG
+ Trigger generation
+ 6
+ 1
+
+
+ CMTG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CH1G
+ Capture/compare 1
+ generation
+ 2
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1COMCTL
+ Output Compare 1 mode
+ 12
+ 3
+
+
+ CH1COMSEN
+ Output Compare 1 preload
+ enable
+ 11
+ 1
+
+
+ CH1COMFEN
+ Output Compare 1 fast
+ enable
+ 10
+ 1
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output Compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1CAPFLT
+ Input capture 1 filter
+ 12
+ 4
+
+
+ CH1CAPPSC
+ Input capture 1 prescaler
+ 10
+ 2
+
+
+ CH1MS
+ Capture/Compare 1
+ selection
+ 8
+ 2
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH1NP
+ Capture/Compare 1 output
+ Polarity
+ 7
+ 1
+
+
+ CH1P
+ Capture/Compare 1 output
+ Polarity
+ 5
+ 1
+
+
+ CH1EN
+ Capture/Compare 1 output
+ enable
+ 4
+ 1
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CH1CV
+ CH1CV
+ capture/compare register 1
+ 0x38
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH1VAL
+ Capture/Compare 1 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ complementary register protect control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator configure
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA burst length
+ 8
+ 5
+
+
+ DMATA
+ DMA base address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA transfer buffer register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+
+
+
+
+ TIMER15
+ General-purpose-timers
+ TIMER
+ 0x40014400
+
+ 0x0
+ 0x400
+ registers
+
+
+ TIMER15
+ 21
+
+
+
+ CTL0
+ CTL0
+ control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x0000
+
+
+ CKDIV
+ Clock division
+ 8
+ 2
+
+
+ ARSE
+ Auto-reload preload enable
+ 7
+ 1
+
+
+ SPM
+ One-pulse mode
+ 3
+ 1
+
+
+ UPS
+ Update request source
+ 2
+ 1
+
+
+ UPDIS
+ Update disable
+ 1
+ 1
+
+
+ CEN
+ Counter enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ control register 1
+ 0x04
+ 0x20
+ read-write
+ 0x0000
+
+
+ ISO0N
+ Output Idle state 0
+ 9
+ 1
+
+
+ ISO0
+ Output Idle state 0
+ 8
+ 1
+
+
+ DMAS
+ Capture/compare DMA
+ selection
+ 3
+ 1
+
+
+ CCUC
+ Capture/compare control update
+ selection
+ 2
+ 1
+
+
+ CCSE
+ Capture/compare preloaded
+ control
+ 0
+ 1
+
+
+
+
+ DMAINTEN
+ DMAINTEN
+ DMA/Interrupt enable register
+ 0x0C
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0DEN
+ Capture/Compare 0 DMA request
+ enable
+ 9
+ 1
+
+
+ UPDEN
+ Update DMA request enable
+ 8
+ 1
+
+
+ BRKIE
+ Break interrupt enable
+ 7
+ 1
+
+
+ CMTIE
+ COM interrupt enable
+ 5
+ 1
+
+
+ CH0IE
+ Capture/Compare 0 interrupt
+ enable
+ 1
+ 1
+
+
+ UPIE
+ Update interrupt enable
+ 0
+ 1
+
+
+
+
+ INTF
+ INTF
+ interrupt flag register
+ 0x10
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0OF
+ Capture/Compare 0 overcapture
+ flag
+ 9
+ 1
+
+
+ BRKIF
+ Break interrupt flag
+ 7
+ 1
+
+
+ CMTIF
+ COM interrupt flag
+ 5
+ 1
+
+
+ CH0IF
+ Capture/compare 0 interrupt
+ flag
+ 1
+ 1
+
+
+ UPIF
+ Update interrupt flag
+ 0
+ 1
+
+
+
+
+ SWEVG
+ SWEVG
+ event generation register
+ 0x14
+ 0x20
+ write-only
+ 0x0000
+
+
+ BRKG
+ Break generation
+ 7
+ 1
+
+
+ CMTG
+ Capture/Compare control update
+ generation
+ 5
+ 1
+
+
+ CH0G
+ Capture/compare 0
+ generation
+ 1
+ 1
+
+
+ UPG
+ Update generation
+ 0
+ 1
+
+
+
+
+ CHCTL0_Output
+ CHCTL0_Output
+ capture/compare mode register (output
+ mode)
+ 0x18
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CH0COMCTL
+ Output Compare 0 mode
+ 4
+ 3
+
+
+ CH0COMSEN
+ Output Compare 0 preload
+ enable
+ 3
+ 1
+
+
+ CH0COMFEN
+ Output Compare 0 fast
+ enable
+ 2
+ 1
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL0_Input
+ CHCTL0_Input
+ capture/compare mode register 0 (input
+ mode)
+ CHCTL0_Output
+ 0x18
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0CAPFLT
+ Input capture 0 filter
+ 4
+ 4
+
+
+ CH0CAPPSC
+ Input capture 0 prescaler
+ 2
+ 2
+
+
+ CH0MS
+ Capture/Compare 0
+ selection
+ 0
+ 2
+
+
+
+
+ CHCTL2
+ CHCTL2
+ capture/compare enable
+ register
+ 0x20
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0NP
+ Capture/Compare 0 output
+ Polarity
+ 3
+ 1
+
+
+ CH0NEN
+ Capture/Compare 0 complementary output
+ enable
+ 2
+ 1
+
+
+ CH0P
+ Capture/Compare 0 output
+ Polarity
+ 1
+ 1
+
+
+ CH0EN
+ Capture/Compare 0 output
+ enable
+ 0
+ 1
+
+
+
+
+ CNT
+ CNT
+ counter
+ 0x24
+ 0x20
+ read-write
+ 0x0000
+
+
+ CNT
+ counter value
+ 0
+ 16
+
+
+
+
+ PSC
+ PSC
+ prescaler
+ 0x28
+ 0x20
+ read-write
+ 0x0000
+
+
+ PSC
+ Prescaler value
+ 0
+ 16
+
+
+
+
+ CAR
+ CAR
+ auto-reload register
+ 0x2C
+ 0x20
+ read-write
+ 0x00000000
+
+
+ CARL
+ Auto-reload value
+ 0
+ 16
+
+
+
+
+ CREP
+ CREP
+ repetition counter register
+ 0x30
+ 0x20
+ read-write
+ 0x0000
+
+
+ CREP
+ Repetition counter value
+ 0
+ 8
+
+
+
+
+ CH0CV
+ CH0CV
+ capture/compare register 0
+ 0x34
+ 0x20
+ read-write
+ 0x0000
+
+
+ CH0VAL
+ Capture/Compare 0 value
+ 0
+ 16
+
+
+
+
+ CCHP
+ CCHP
+ break and dead-time register
+ 0x44
+ 0x20
+ read-write
+ 0x0000
+
+
+ POEN
+ Main output enable
+ 15
+ 1
+
+
+ OAEN
+ Automatic output enable
+ 14
+ 1
+
+
+ BRKP
+ Break polarity
+ 13
+ 1
+
+
+ BRKEN
+ Break enable
+ 12
+ 1
+
+
+ ROS
+ Off-state selection for Run
+ mode
+ 11
+ 1
+
+
+ IOS
+ Off-state selection for Idle
+ mode
+ 10
+ 1
+
+
+ PROT
+ complementary register protect control
+ 8
+ 2
+
+
+ DTCFG
+ Dead-time generator setup
+ 0
+ 8
+
+
+
+
+ DMACFG
+ DMACFG
+ DMA configuration register
+ 0x48
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATC
+ DMA transfer count
+ 8
+ 5
+
+
+ DMATA
+ DMA transfer access start address
+ 0
+ 5
+
+
+
+
+ DMATB
+ DMATB
+ DMA transfer buffer register
+ 0x4C
+ 0x20
+ read-write
+ 0x0000
+
+
+ DMATB
+ DMA register for burst
+ accesses
+ 0
+ 16
+
+
+
+
+ CFG
+ CFG
+ configuration register
+ 0xFC
+ 0x20
+ read-write
+ 0x0000
+
+
+ OUTSEL
+ The output value selection
+ 0
+ 1
+
+
+ CHVSEL
+ Write CHxVAL register selection
+ 1
+ 1
+
+
+
+
+
+
+ TIMER16
+ 0x40014800
+
+ TIMER16
+ 22
+
+
+
+ USART0
+ Universal synchronous asynchronous receiver
+ transmitter
+ USART
+ 0x40013800
+
+ 0x0
+ 0x400
+ registers
+
+
+ USART0
+ 27
+
+
+
+ CTL0
+ CTL0
+ Control register 0
+ 0x0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EBIE
+ End of Block interrupt
+ enable
+ 27
+ 1
+
+
+ RTIE
+ Receiver timeout interrupt
+ enable
+ 26
+ 1
+
+
+ DEA
+ Driver Enable assertion
+ time
+ 21
+ 5
+
+
+ DED
+ Driver Enable deassertion
+ time
+ 16
+ 5
+
+
+ OVSMOD
+ Oversampling mode
+ 15
+ 1
+
+
+ AMIE
+ Character match interrupt
+ enable
+ 14
+ 1
+
+
+ MEN
+ Mute mode enable
+ 13
+ 1
+
+
+ WL
+ Word length
+ 12
+ 1
+
+
+ WM
+ Receiver wakeup method
+ 11
+ 1
+
+
+ PCEN
+ Parity control enable
+ 10
+ 1
+
+
+ PM
+ Parity selection
+ 9
+ 1
+
+
+ PERRIE
+ PE interrupt enable
+ 8
+ 1
+
+
+ TBEIE
+ interrupt enable
+ 7
+ 1
+
+
+ TCIE
+ Transmission complete interrupt
+ enable
+ 6
+ 1
+
+
+ RBNEIE
+ RXNE interrupt enable
+ 5
+ 1
+
+
+ IDLEIE
+ IDLE interrupt enable
+ 4
+ 1
+
+
+ TEN
+ Transmitter enable
+ 3
+ 1
+
+
+ REN
+ Receiver enable
+ 2
+ 1
+
+
+ UESM
+ USART enable in Stop mode
+ 1
+ 1
+
+
+ UEN
+ USART enable
+ 0
+ 1
+
+
+
+
+ CTL1
+ CTL1
+ Control register 1
+ 0x4
+ 0x20
+ read-write
+ 0x00000000
+
+
+ ADDR
+ Address of the USART node
+ 24
+ 8
+
+
+ RTEN
+ Receiver timeout enable
+ 23
+ 1
+
+
+ ABDM
+ Auto baud rate mode
+ 21
+ 2
+
+
+ ABDEN
+ Auto baud rate enable
+ 20
+ 1
+
+
+ MSBF
+ Most significant bit first
+ 19
+ 1
+
+
+ DINV
+ Binary data inversion
+ 18
+ 1
+
+
+ TINV
+ TX pin active level
+ inversion
+ 17
+ 1
+
+
+ RINV
+ RX pin active level
+ inversion
+ 16
+ 1
+
+
+ STRP
+ Swap TX/RX pins
+ 15
+ 1
+
+
+ LMEN
+ LIN mode enable
+ 14
+ 1
+
+
+ STB
+ STOP bits
+ 12
+ 2
+
+
+ CKEN
+ Clock enable
+ 11
+ 1
+
+
+ CPL
+ Clock polarity
+ 10
+ 1
+
+
+ CPH
+ Clock phase
+ 9
+ 1
+
+
+ CLEN
+ Last bit clock pulse
+ 8
+ 1
+
+
+ LBDIE
+ LIN break detection interrupt
+ enable
+ 6
+ 1
+
+
+ LBLEN
+ LIN break detection length
+ 5
+ 1
+
+
+ ADDM
+ 7-bit Address Detection/4-bit Address
+ Detection
+ 4
+ 1
+
+
+
+
+ CTL2
+ CTL2
+ Control register 2
+ 0x8
+ 0x20
+ read-write
+ 0x00000000
+
+
+ WUIE
+ Wakeup from Stop mode interrupt
+ enable
+ 22
+ 1
+
+
+ WUM
+ Wakeup from Stop mode interrupt flag
+ selection
+ 20
+ 2
+
+
+ SCRTNUM
+ Smartcard auto-retry count
+ 17
+ 3
+
+
+ DEP
+ Driver enable polarity
+ selection
+ 15
+ 1
+
+
+ DEM
+ Driver enable mode
+ 14
+ 1
+
+
+ DDRE
+ DMA Disable on Reception
+ Error
+ 13
+ 1
+
+
+ OVRD
+ Overrun Disable
+ 12
+ 1
+
+
+ OSB
+ One sample bit method
+ enable
+ 11
+ 1
+
+
+ CTSIE
+ CTS interrupt enable
+ 10
+ 1
+
+
+ CTSEN
+ CTS enable
+ 9
+ 1
+
+
+ RTSEN
+ RTS enable
+ 8
+ 1
+
+
+ DENT
+ DMA enable transmitter
+ 7
+ 1
+
+
+ DENR
+ DMA enable receiver
+ 6
+ 1
+
+
+ SCEN
+ Smartcard mode enable
+ 5
+ 1
+
+
+ NKEN
+ Smartcard NACK enable
+ 4
+ 1
+
+
+ HDEN
+ Half-duplex selection
+ 3
+ 1
+
+
+ IRLP
+ IrDA low-power
+ 2
+ 1
+
+
+ IREN
+ IrDA mode enable
+ 1
+ 1
+
+
+ ERRIE
+ Error interrupt enable
+ 0
+ 1
+
+
+
+
+ BAUD
+ BAUD
+ Baud rate register
+ 0xC
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BRR_INT
+ integer of baud-rate divider
+ 4
+ 12
+
+
+ BRR_FRA
+ integer of baud-rate divider
+ 0
+ 4
+
+
+
+
+ GP
+ GP
+ Guard time and prescaler
+ register
+ 0x10
+ 0x20
+ read-write
+ 0x00000000
+
+
+ GUAT
+ Guard time value
+ 8
+ 8
+
+
+ PSC
+ Prescaler value
+ 0
+ 8
+
+
+
+
+ RT
+ RT
+ Receiver timeout register
+ 0x14
+ 0x20
+ read-write
+ 0x00000000
+
+
+ BL
+ Block Length
+ 24
+ 8
+
+
+ RT
+ Receiver timeout value
+ 0
+ 24
+
+
+
+
+ CMD
+ CMD
+ Request register
+ 0x18
+ 0x20
+ write-only
+ 0x00000000
+
+
+ TXFCMD
+ Transmit data flush
+ request
+ 4
+ 1
+
+
+ RXFCMD
+ Receive data flush request
+ 3
+ 1
+
+
+ MMCMD
+ Mute mode request
+ 2
+ 1
+
+
+ SBKCMD
+ Send break request
+ 1
+ 1
+
+
+ ABDCMD
+ Auto baud rate request
+ 0
+ 1
+
+
+
+
+ STAT
+ STAT
+ Interrupt & status
+ register
+ 0x1C
+ 0x20
+ read-only
+ 0x000000C0
+
+
+ REA
+ Receive enable acknowledge
+ flag
+ 22
+ 1
+
+
+ TEA
+ Transmit enable acknowledge
+ flag
+ 21
+ 1
+
+
+ WUF
+ Wakeup from Stop mode flag
+ 20
+ 1
+
+
+ RWU
+ Receiver wakeup from Mute
+ mode
+ 19
+ 1
+
+
+ SBF
+ Send break flag
+ 18
+ 1
+
+
+ AMF
+ character match flag
+ 17
+ 1
+
+
+ BSY
+ Busy flag
+ 16
+ 1
+
+
+ ABDF
+ Auto baud rate flag
+ 15
+ 1
+
+
+ ABDE
+ Auto baud rate error
+ 14
+ 1
+
+
+ EBF
+ End of block flag
+ 12
+ 1
+
+
+ RTF
+ Receiver timeout
+ 11
+ 1
+
+
+ CTS
+ CTS flag
+ 10
+ 1
+
+
+ CTSF
+ CTS interrupt flag
+ 9
+ 1
+
+
+ LBDF
+ LIN break detection flag
+ 8
+ 1
+
+
+ TBE
+ Transmit data register
+ empty
+ 7
+ 1
+
+
+ TC
+ Transmission complete
+ 6
+ 1
+
+
+ RBNE
+ Read data register not
+ empty
+ 5
+ 1
+
+
+ IDLEF
+ Idle line detected
+ 4
+ 1
+
+
+ ORERR
+ Overrun error
+ 3
+ 1
+
+
+ NERR
+ Noise detected flag
+ 2
+ 1
+
+
+ FERR
+ Framing error
+ 1
+ 1
+
+
+ PERR
+ Parity error
+ 0
+ 1
+
+
+
+
+ INTC
+ INTC
+ Interrupt flag clear register
+ 0x20
+ 0x20
+ write-only
+ 0x00000000
+
+
+ WUC
+ Wakeup from Stop mode clear
+ flag
+ 20
+ 1
+
+
+ AMC
+ Character match clear flag
+ 17
+ 1
+
+
+ EBC
+ End of timeout clear flag
+ 12
+ 1
+
+
+ RTC
+ Receiver timeout clear
+ flag
+ 11
+ 1
+
+
+ CTSC
+ CTS clear flag
+ 9
+ 1
+
+
+ LBDC
+ LIN break detection clear
+ flag
+ 8
+ 1
+
+
+ TCC
+ Transmission complete clear
+ flag
+ 6
+ 1
+
+
+ IDLEC
+ Idle line detected clear
+ flag
+ 4
+ 1
+
+
+ OREC
+ Overrun error clear flag
+ 3
+ 1
+
+
+ NEC
+ Noise detected clear flag
+ 2
+ 1
+
+
+ FEC
+ Framing error clear flag
+ 1
+ 1
+
+
+ PEC
+ Parity error clear flag
+ 0
+ 1
+
+
+
+
+ RDATA
+ RDATA
+ Receive data register
+ 0x24
+ 0x20
+ read-only
+ 0x00000000
+
+
+ RDATA
+ Receive data value
+ 0
+ 9
+
+
+
+
+ TDATA
+ TDATA
+ Transmit data register
+ 0x28
+ 0x20
+ read-write
+ 0x00000000
+
+
+ TDATA
+ Transmit data value
+ 0
+ 9
+
+
+
+
+ CHC
+ CHC
+ coherence control register
+ 0xC0
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EPERR
+ Early parity error flag
+ 8
+ 1
+
+
+ HCM
+ Hardware flow control coherence mode
+ 0
+ 1
+
+
+
+
+ RFCS
+ RFCS
+ USART receive FIFO control and status register
+ 0xD0
+ 0x20
+ 0x00000400
+
+
+ RFFINT
+ Receive FIFO full interrupt flag
+ 15
+ 1
+ read-write
+
+
+ RFCNT
+ Receive FIFO count number
+ 12
+ 3
+ read-only
+
+
+ RFF
+ Receive FIFO full flag
+ 11
+ 1
+ read-only
+
+
+ RFE
+ Receive FIFO empty flag
+ 10
+ 1
+ read-only
+
+
+ RFFIE
+ Receive FIFO full interrupt enable
+ 9
+ 1
+ read-write
+
+
+ RFEN
+ Receive FIFO enable
+ 8
+ 1
+ read-write
+
+
+ ELNACK
+ Early NKEN when smartcard mode is selected
+ 0
+ 1
+ read-write
+
+
+
+
+
+
+ USART1
+ 0x40004400
+
+ USART1
+ 28
+
+
+
+ WWDGT
+ Window watchdog timer
+ WWDGT
+ 0x40002C00
+
+ 0x0
+ 0x400
+ registers
+
+
+ WWDGT
+ 0
+
+
+
+ CTL
+ CTL
+ Control register
+ 0x0
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ WDGTEN
+ Activation bit
+ 7
+ 1
+
+
+ CNT
+ 7-bit counter
+ 0
+ 7
+
+
+
+
+ CFG
+ CFG
+ Configuration register
+ 0x04
+ 0x20
+ read-write
+ 0x0000007F
+
+
+ EWIE
+ Early wakeup interrupt
+ 9
+ 1
+
+
+ PSC
+ Prescaler
+ 7
+ 2
+
+
+ WIN
+ 7-bit window value
+ 0
+ 7
+
+
+
+
+ STAT
+ STAT
+ Status register
+ 0x08
+ 0x20
+ read-write
+ 0x00000000
+
+
+ EWIF
+ Early wakeup interrupt
+ flag
+ 0
+ 1
+
+
+
+
+
+
+
+
+