#
# GigaDevice GD32E23x target
#

adapter driver cmsis-dap

# adapter driver jlink

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME gd32e23x
}

# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some GD32E230s)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

# Allow overriding the Flash bank size
if { [info exists FLASH_SIZE] } {
    set _FLASH_SIZE $FLASH_SIZE
} else {
    # autodetect size
    set _FLASH_SIZE 0
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   # this is the SW-DP tap id not the jtag tap id
   set _CPUTAPID 0x0BF11477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME gd32e23x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME

# SWD speed (may be updated to higher value in board config file)
adapter speed 1000

# use the hardware reset line (DAPLink RST pin -> GD32 NRST);
# connect_assert_srst: hold the chip in reset while connecting, so SWD pins
# (shared with LED in firmware) revert to SWD function before any access
adapter srst delay 100
reset_config srst_only srst_nogate connect_assert_srst

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
	mmw 0x40021018 0x00400000 0
	mmw 0x40015804 0x00000307 0
}