generated from hulk/gd32e23x_template_cmake_vscode
819 lines
23 KiB
C
819 lines
23 KiB
C
/*
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* Copyright (c) 2009-2024 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* CMSIS-Core(M) Compiler ARMClang (Arm Compiler 6) Header File
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*/
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#ifndef __CMSIS_ARMCLANG_M_H
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#define __CMSIS_ARMCLANG_M_H
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#pragma clang system_header /* treat file as system include file */
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#ifndef __CMSIS_ARMCLANG_H
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#error "This file must not be included directly"
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#endif
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#if (__ARM_ACLE >= 200)
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#include <arm_acle.h>
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#else
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#error Compiler must support ACLE V2.0
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#endif /* (__ARM_ACLE >= 200) */
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/* ######################### Startup and Lowlevel Init ######################## */
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#ifndef __PROGRAM_START
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#define __PROGRAM_START __main
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#endif
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#ifndef __INITIAL_SP
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#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
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#endif
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#ifndef __STACK_LIMIT
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#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
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#endif
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#ifndef __VECTOR_TABLE
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#define __VECTOR_TABLE __Vectors
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#endif
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#ifndef __VECTOR_TABLE_ATTRIBUTE
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#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
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#endif
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#if (__ARM_FEATURE_CMSE == 3)
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#ifndef __STACK_SEAL
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#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base
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#endif
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#ifndef __TZ_STACK_SEAL_SIZE
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#define __TZ_STACK_SEAL_SIZE 8U
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#endif
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#ifndef __TZ_STACK_SEAL_VALUE
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#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
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#endif
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__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
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*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
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}
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#endif
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#if (__ARM_ARCH_ISA_THUMB >= 2)
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/**
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\brief STRT Unprivileged (8 bit)
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\details Executes a Unprivileged STRT instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
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{
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__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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}
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/**
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\brief STRT Unprivileged (16 bit)
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\details Executes a Unprivileged STRT instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
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{
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__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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}
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/**
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\brief STRT Unprivileged (32 bit)
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\details Executes a Unprivileged STRT instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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*/
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__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
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{
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__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
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}
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#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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/**
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\brief Get Control Register
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\details Returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, control" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Control Register (non-secure)
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\details Returns the content of the non-secure Control Register when in secure mode.
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\return non-secure Control Register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, control_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Control Register
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\details Writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
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{
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__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
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__ISB();
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Control Register (non-secure)
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\details Writes the given value to the non-secure Control Register when in secure state.
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\param [in] control Control Register value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
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{
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__ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
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__ISB();
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}
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#endif
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/**
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\brief Get IPSR Register
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\details Returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
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return (result);
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}
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/**
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\brief Get APSR Register
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\details Returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_APSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, apsr" : "=r" (result) );
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return (result);
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}
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/**
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\brief Get xPSR Register
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\details Returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
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return (result);
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}
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/**
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\brief Get Process Stack Pointer
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\details Returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_PSP(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, psp" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Process Stack Pointer (non-secure)
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\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
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\return PSP Register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Process Stack Pointer
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\details Assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
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{
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__ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Process Stack Pointer (non-secure)
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\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
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{
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__ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
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}
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#endif
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/**
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\brief Get Main Stack Pointer
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\details Returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_MSP(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, msp" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Main Stack Pointer (non-secure)
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\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
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\return MSP Register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Main Stack Pointer
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\details Assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
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{
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__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Main Stack Pointer (non-secure)
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\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
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{
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__ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
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}
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#endif
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Stack Pointer (non-secure)
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\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
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\return SP Register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
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return (result);
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}
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/**
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\brief Set Stack Pointer (non-secure)
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\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
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\param [in] topOfStack Stack Pointer value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
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{
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__ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
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}
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#endif
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/**
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\brief Get Priority Mask
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\details Returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Priority Mask (non-secure)
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\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
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\return Priority Mask value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Priority Mask
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\details Assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
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{
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__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Priority Mask (non-secure)
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\details Assigns the given value to the non-secure Priority Mask Register when in secure state.
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\param [in] priMask Priority Mask
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*/
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__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
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{
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__ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
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}
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#endif
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#if (__ARM_ARCH_ISA_THUMB >= 2)
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/**
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\brief Get Base Priority
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\details Returns the current value of the Base Priority register.
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\return Base Priority register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, basepri" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Base Priority (non-secure)
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\details Returns the current value of the non-secure Base Priority register when in secure state.
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\return Base Priority register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Base Priority
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\details Assigns the given value to the Base Priority register.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
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{
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__ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Base Priority (non-secure)
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\details Assigns the given value to the non-secure Base Priority register when in secure state.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
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{
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__ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
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}
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#endif
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/**
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\brief Set Base Priority with condition
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\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
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or the new value increases the BASEPRI priority level.
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
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{
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__ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
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}
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/**
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\brief Get Fault Mask
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\details Returns the current value of the Fault Mask register.
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\return Fault Mask register value
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*/
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__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
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return (result);
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Get Fault Mask (non-secure)
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\details Returns the current value of the non-secure Fault Mask register when in secure state.
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\return Fault Mask register value
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
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return (result);
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}
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#endif
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/**
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\brief Set Fault Mask
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\details Assigns the given value to the Fault Mask register.
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\param [in] faultMask Fault Mask value to set
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*/
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__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
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{
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__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
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}
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#if (__ARM_FEATURE_CMSE == 3)
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/**
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\brief Set Fault Mask (non-secure)
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\details Assigns the given value to the non-secure Fault Mask register when in secure state.
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\param [in] faultMask Fault Mask value to set
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*/
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__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
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{
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__ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
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}
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#endif
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#endif /* (__ARM_ARCH_ISA_THUMB >= 2) */
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#if (__ARM_ARCH >= 8)
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/**
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\brief Get Process Stack Pointer Limit
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|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
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Stack Pointer Limit register hence zero is returned always in non-secure
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|
mode.
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\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
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\return PSPLIM Register value
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*/
|
|
__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
|
|
{
|
|
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
|
|
(__ARM_FEATURE_CMSE < 3) )
|
|
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
|
|
return (0U);
|
|
#else
|
|
uint32_t result;
|
|
__ASM volatile ("MRS %0, psplim" : "=r" (result) );
|
|
return (result);
|
|
#endif
|
|
}
|
|
|
|
#if (__ARM_FEATURE_CMSE == 3)
|
|
/**
|
|
\brief Get Process Stack Pointer Limit (non-secure)
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence zero is returned always.
|
|
|
|
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
|
|
\return PSPLIM Register value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
|
|
{
|
|
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) )
|
|
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
|
|
return (0U);
|
|
#else
|
|
uint32_t result;
|
|
__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
|
|
return (result);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief Set Process Stack Pointer Limit
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence the write is silently ignored in non-secure
|
|
mode.
|
|
|
|
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
|
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
|
|
{
|
|
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
|
|
(__ARM_FEATURE_CMSE < 3) )
|
|
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
|
|
(void)ProcStackPtrLimit;
|
|
#else
|
|
__ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
|
|
#endif
|
|
}
|
|
|
|
|
|
#if (__ARM_FEATURE_CMSE == 3)
|
|
/**
|
|
\brief Set Process Stack Pointer (non-secure)
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence the write is silently ignored.
|
|
|
|
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
|
|
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
|
|
{
|
|
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) )
|
|
/* without main extensions, the non-secure PSPLIM is RAZ/WI */
|
|
(void)ProcStackPtrLimit;
|
|
#else
|
|
__ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief Get Main Stack Pointer Limit
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence zero is returned always.
|
|
|
|
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
|
|
\return MSPLIM Register value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
|
|
{
|
|
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
|
|
(__ARM_FEATURE_CMSE < 3) )
|
|
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
|
|
return (0U);
|
|
#else
|
|
uint32_t result;
|
|
__ASM volatile ("MRS %0, msplim" : "=r" (result) );
|
|
return (result);
|
|
#endif
|
|
}
|
|
|
|
|
|
#if (__ARM_FEATURE_CMSE == 3)
|
|
/**
|
|
\brief Get Main Stack Pointer Limit (non-secure)
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence zero is returned always.
|
|
|
|
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
|
|
\return MSPLIM Register value
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
|
|
{
|
|
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) )
|
|
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
|
|
return (0U);
|
|
#else
|
|
uint32_t result;
|
|
__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
|
|
return (result);
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
|
|
/**
|
|
\brief Set Main Stack Pointer Limit
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence the write is silently ignored.
|
|
|
|
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
|
|
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
|
|
{
|
|
#if (((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) ) && \
|
|
(__ARM_FEATURE_CMSE < 3) )
|
|
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
|
|
(void)MainStackPtrLimit;
|
|
#else
|
|
__ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
|
|
#endif
|
|
}
|
|
|
|
|
|
#if (__ARM_FEATURE_CMSE == 3)
|
|
/**
|
|
\brief Set Main Stack Pointer Limit (non-secure)
|
|
Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
|
Stack Pointer Limit register hence the write is silently ignored.
|
|
|
|
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
|
|
\param [in] MainStackPtrLimit Main Stack Pointer value to set
|
|
*/
|
|
__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
|
|
{
|
|
#if ((__ARM_ARCH_8M_MAIN__ < 1) && \
|
|
(__ARM_ARCH_8_1M_MAIN__ < 1) )
|
|
/* without main extensions, the non-secure MSPLIM is RAZ/WI */
|
|
(void)MainStackPtrLimit;
|
|
#else
|
|
__ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif /* (__ARM_ARCH >= 8) */
|
|
/** @} end of CMSIS_Core_RegAccFunctions */
|
|
|
|
|
|
/* ################### Compiler specific Intrinsics ########################### */
|
|
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
|
Access to dedicated SIMD instructions
|
|
@{
|
|
*/
|
|
|
|
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
|
#define __SADD8 __sadd8
|
|
#define __QADD8 __qadd8
|
|
#define __SHADD8 __shadd8
|
|
#define __UADD8 __uadd8
|
|
#define __UQADD8 __uqadd8
|
|
#define __UHADD8 __uhadd8
|
|
#define __SSUB8 __ssub8
|
|
#define __QSUB8 __qsub8
|
|
#define __SHSUB8 __shsub8
|
|
#define __USUB8 __usub8
|
|
#define __UQSUB8 __uqsub8
|
|
#define __UHSUB8 __uhsub8
|
|
#define __SADD16 __sadd16
|
|
#define __QADD16 __qadd16
|
|
#define __SHADD16 __shadd16
|
|
#define __UADD16 __uadd16
|
|
#define __UQADD16 __uqadd16
|
|
#define __UHADD16 __uhadd16
|
|
#define __SSUB16 __ssub16
|
|
#define __QSUB16 __qsub16
|
|
#define __SHSUB16 __shsub16
|
|
#define __USUB16 __usub16
|
|
#define __UQSUB16 __uqsub16
|
|
#define __UHSUB16 __uhsub16
|
|
#define __SASX __sasx
|
|
#define __QASX __qasx
|
|
#define __SHASX __shasx
|
|
#define __UASX __uasx
|
|
#define __UQASX __uqasx
|
|
#define __UHASX __uhasx
|
|
#define __SSAX __ssax
|
|
#define __QSAX __qsax
|
|
#define __SHSAX __shsax
|
|
#define __USAX __usax
|
|
#define __UQSAX __uqsax
|
|
#define __UHSAX __uhsax
|
|
#define __USAD8 __usad8
|
|
#define __USADA8 __usada8
|
|
#define __SSAT16 __ssat16
|
|
#define __USAT16 __usat16
|
|
#define __UXTB16 __uxtb16
|
|
#define __UXTAB16 __uxtab16
|
|
#define __SXTB16 __sxtb16
|
|
#define __SXTAB16 __sxtab16
|
|
#define __SMUAD __smuad
|
|
#define __SMUADX __smuadx
|
|
#define __SMLAD __smlad
|
|
#define __SMLADX __smladx
|
|
#define __SMLALD __smlald
|
|
#define __SMLALDX __smlaldx
|
|
#define __SMUSD __smusd
|
|
#define __SMUSDX __smusdx
|
|
#define __SMLSD __smlsd
|
|
#define __SMLSDX __smlsdx
|
|
#define __SMLSLD __smlsld
|
|
#define __SMLSLDX __smlsldx
|
|
#define __SEL __sel
|
|
#define __QADD __qadd
|
|
#define __QSUB __qsub
|
|
|
|
#define __PKHBT(ARG1,ARG2,ARG3) \
|
|
__extension__ \
|
|
({ \
|
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
|
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
|
__RES; \
|
|
})
|
|
|
|
#define __PKHTB(ARG1,ARG2,ARG3) \
|
|
__extension__ \
|
|
({ \
|
|
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
|
if (ARG3 == 0) \
|
|
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
|
else \
|
|
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
|
__RES; \
|
|
})
|
|
|
|
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
|
|
|
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
|
|
|
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
|
{
|
|
int32_t result;
|
|
|
|
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
|
return (result);
|
|
}
|
|
#endif /* (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) */
|
|
/** @} end of group CMSIS_SIMD_intrinsics */
|
|
|
|
|
|
#endif /* __CMSIS_ARMCLANG_M_H */
|