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/*!
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\file gd32f4xx_syscfg.c
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\brief SYSCFG driver
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\version 2026-02-05, V3.3.3, firmware for GD32F4xx
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*/
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/*
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Copyright (c) 2026, GigaDevice Semiconductor Inc.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#include "gd32f4xx_syscfg.h"
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/*!
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\brief reset the SYSCFG registers
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\param[in] none
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\param[out] none
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\retval none
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*/
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void syscfg_deinit(void)
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{
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rcu_periph_reset_enable(RCU_SYSCFGRST);
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rcu_periph_reset_disable(RCU_SYSCFGRST);
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}
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/*!
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\brief configure the boot mode
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\param[in] syscfg_bootmode: selects the memory remapping
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only one parameter can be selected which is shown as below:
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\arg SYSCFG_BOOTMODE_FLASH: main flash memory (0x08000000~0x083BFFFF) is mapped at address 0x00000000
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\arg SYSCFG_BOOTMODE_BOOTLOADER: boot loader (0x1FFF0000 - 0x1FFF77FF) is mapped at address 0x00000000
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\arg SYSCFG_BOOTMODE_EXMC_SRAM: SRAM/NOR 0 and 1 of EXMC (0x60000000~0x67FFFFFF) is mapped at address 0x00000000
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\arg SYSCFG_BOOTMODE_SRAM: SRAM0 of on-chip SRAM (0x20000000~0x2001BFFF) is mapped at address 0x00000000
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\arg SYSCFG_BOOTMODE_EXMC_SDRAM: SDRAM bank0 of EXMC (0xC0000000~0xC7FFFFFF) is mapped at address 0x00000000
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\param[out] none
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\retval none
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*/
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void syscfg_bootmode_config(uint8_t syscfg_bootmode)
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{
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/* reset the SYSCFG_CFG0_BOOT_MODE bit and set according to syscfg_bootmode */
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SYSCFG_CFG0 &= ~SYSCFG_CFG0_BOOT_MODE;
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SYSCFG_CFG0 |= (uint32_t)syscfg_bootmode;
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}
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/*!
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\brief FMC memory mapping swap
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\param[in] syscfg_fmc_swap: selects the interal flash bank swapping
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only one parameter can be selected which is shown as below:
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\arg SYSCFG_FMC_SWP_BANK0: bank 0 is mapped at address 0x08000000 and bank 1 is mapped at address 0x08100000
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\arg SYSCFG_FMC_SWP_BANK1: bank 1 is mapped at address 0x08000000 and bank 0 is mapped at address 0x08100000
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\param[out] none
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\retval none
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*/
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void syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap)
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{
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uint32_t reg;
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reg = SYSCFG_CFG0;
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/* reset the FMC_SWP bit and set according to syscfg_fmc_swap */
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reg &= ~SYSCFG_CFG0_FMC_SWP;
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SYSCFG_CFG0 = (reg | syscfg_fmc_swap);
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}
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/*!
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\brief EXMC memory mapping swap
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\param[in] syscfg_exmc_swap: selects the memories in EXMC swapping
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only one parameter can be selected which is shown as below:
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\arg SYSCFG_EXMC_SWP_ENABLE: SDRAM bank 0 and bank 1 are swapped with NAND bank 1 and PC card
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\arg SYSCFG_EXMC_SWP_DISABLE: no memory mapping swap
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\param[out] none
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\retval none
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*/
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void syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap)
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{
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uint32_t reg;
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reg = SYSCFG_CFG0;
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/* reset the SYSCFG_CFG0_EXMC_SWP bits and set according to syscfg_exmc_swap */
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reg &= ~SYSCFG_CFG0_EXMC_SWP;
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SYSCFG_CFG0 = (reg | syscfg_exmc_swap);
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}
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/*!
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\brief configure the GPIO pin as EXTI Line
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\param[in] exti_port: specify the GPIO port used in EXTI
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only one parameter can be selected which is shown as below:
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\arg EXTI_SOURCE_GPIOx(x = A,B,C,D,E,F,G,H,I): EXTI GPIO port
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\param[in] exti_pin: specify the EXTI line
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only one parameter can be selected which is shown as below:
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\arg EXTI_SOURCE_PINx(x = 0..15): EXTI GPIO pin
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\param[out] none
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\retval none
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*/
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void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
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{
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uint32_t clear_exti_mask = ~((uint32_t)EXTI_SS_MASK << (EXTI_SS_MSTEP(exti_pin)));
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uint32_t config_exti_mask = ((uint32_t)exti_port) << (EXTI_SS_MSTEP(exti_pin));
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switch(exti_pin / EXTI_SS_JSTEP) {
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case EXTISS0:
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/* clear EXTI source line(0..3) */
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SYSCFG_EXTISS0 &= clear_exti_mask;
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/* configure EXTI soure line(0..3) */
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SYSCFG_EXTISS0 |= config_exti_mask;
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break;
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case EXTISS1:
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/* clear EXTI soure line(4..7) */
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SYSCFG_EXTISS1 &= clear_exti_mask;
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/* configure EXTI soure line(4..7) */
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SYSCFG_EXTISS1 |= config_exti_mask;
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break;
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case EXTISS2:
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/* clear EXTI soure line(8..11) */
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SYSCFG_EXTISS2 &= clear_exti_mask;
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/* configure EXTI soure line(8..11) */
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SYSCFG_EXTISS2 |= config_exti_mask;
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break;
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case EXTISS3:
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/* clear EXTI soure line(12..15) */
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SYSCFG_EXTISS3 &= clear_exti_mask;
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/* configure EXTI soure line(12..15) */
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SYSCFG_EXTISS3 |= config_exti_mask;
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break;
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default:
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break;
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}
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}
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/*!
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\brief configure the PHY interface for the ethernet MAC
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\param[in] syscfg_enet_phy_interface: specifies the media interface mode.
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only one parameter can be selected which is shown as below:
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\arg SYSCFG_ENET_PHY_MII: MII mode is selected
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\arg SYSCFG_ENET_PHY_RMII: RMII mode is selected
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\param[out] none
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\retval none
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*/
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void syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface)
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{
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uint32_t reg;
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reg = SYSCFG_CFG1;
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/* reset the ENET_PHY_SEL bit and set according to syscfg_enet_phy_interface */
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reg &= ~SYSCFG_CFG1_ENET_PHY_SEL;
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SYSCFG_CFG1 = (reg | syscfg_enet_phy_interface);
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}
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/*!
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\brief configure the I/O compensation cell
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\param[in] syscfg_compensation: specifies the I/O compensation cell mode
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only one parameter can be selected which is shown as below:
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\arg SYSCFG_COMPENSATION_ENABLE: I/O compensation cell is enabled
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\arg SYSCFG_COMPENSATION_DISABLE: I/O compensation cell is disabled
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\param[out] none
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\retval none
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*/
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void syscfg_compensation_config(uint32_t syscfg_compensation)
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{
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uint32_t reg;
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reg = SYSCFG_CPSCTL;
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/* reset the SYSCFG_CPSCTL_CPS_EN bit and set according to syscfg_compensation */
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reg &= ~SYSCFG_CPSCTL_CPS_EN;
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SYSCFG_CPSCTL = (reg | syscfg_compensation);
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}
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/*!
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\brief checks whether the I/O compensation cell ready flag is set or not
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\param[in] none
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\param[out] none
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\retval FlagStatus: SET or RESET
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*/
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FlagStatus syscfg_flag_get(void)
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{
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FlagStatus reval = RESET;
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if(((uint32_t)RESET) != (SYSCFG_CPSCTL & SYSCFG_CPSCTL_CPS_RDY)) {
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reval = SET;
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} else {
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reval = RESET;
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}
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return reval;
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}
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