generated from hulk/gd32f4xx_template_cmake_vscode
Initial commit
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/*!
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\file gd32f4xx.h
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\brief general definitions for GD32F4xx
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\version 2026-02-05, V3.3.3, firmware for GD32F4xx
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*/
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/* Copyright (c) 2012 ARM LIMITED
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Copyright (c) 2026, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
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#ifndef GD32F4XX_H
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#define GD32F4XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* define GD32F4xx */
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#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
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/* #define GD32F450 */
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/* #define GD32F405 */
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/* #define GD32F407 */
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/* #define GD32F470 */
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/* #define GD32F425 */
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/* #define GD32F427 */
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#endif /* define GD32F4xx */
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#if !defined (GD32F450) && !defined (GD32F405) && !defined (GD32F407) && !defined (GD32F470) && !defined (GD32F425) && !defined (GD32F427)
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#error "Please select the target GD32F4xx device in gd32f4xx.h file"
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#endif /* undefine GD32F4xx tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)25000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
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#if !defined (IRC16M_VALUE)
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#define IRC16M_VALUE ((uint32_t)16000000)
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#endif /* internal 16MHz RC oscillator value */
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/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
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#if !defined (IRC16M_STARTUP_TIMEOUT)
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#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 16MHz RC oscillator startup timeout */
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/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
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#if !defined (IRC32K_VALUE)
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#define IRC32K_VALUE ((uint32_t)32000)
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#endif /* internal 32KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* I2S external clock in selection */
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//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
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/* GD32F4xx firmware library version number V1.0 */
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#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
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#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F4xx_STDPERIPH_VERSION_RC))
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/* configuration of the cortex-M4 processor and core peripherals */
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#define __CM4_REV 0x0001 /*!< core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< GD32F4xx provide MPU */
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#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
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#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* cortex-M4 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
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HardFault_IRQn = -13, /*!< hard-fault interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 cortex-M4 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 cortex-M4 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 cortex-M4 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 cortex-M4 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 cortex-M4 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 cortex-M4 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 cortex-M4 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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TAMPER_STAMP_IRQn = 2, /*!< tamper and timestamp through EXTI line detect */
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RTC_WKUP_IRQn = 3, /*!< RTC wakeup through EXTI line interrupt */
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FMC_IRQn = 4, /*!< FMC interrupt */
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RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 Interrupt */
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DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 Interrupt */
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DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
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DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
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DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
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DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
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DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
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ADC_IRQn = 18, /*!< ADC interrupt */
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CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
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CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupts */
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TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupts */
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TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupts */
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TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
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USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
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TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupts */
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TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupts */
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TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupts */
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TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
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DMA0_Channel7_IRQn = 47, /*!< DMA0 channel7 interrupt */
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#if defined (GD32F450) || defined (GD32F470)
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EXMC_IRQn = 48, /*!< EXMC interrupt */
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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ENET_IRQn = 61, /*!< ENET interrupt */
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ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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UART6_IRQn = 82, /*!< UART6 interrupt */
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UART7_IRQn = 83, /*!< UART7 interrupt */
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SPI3_IRQn = 84, /*!< SPI3 interrupt */
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SPI4_IRQn = 85, /*!< SPI4 interrupt */
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SPI5_IRQn = 86, /*!< SPI5 interrupt */
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TLI_IRQn = 88, /*!< TLI interrupt */
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TLI_ER_IRQn = 89, /*!< TLI error interrupt */
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IPA_IRQn = 90, /*!< IPA interrupt */
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#endif /* GD32F450 and GD32F470 */
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#if defined (GD32F405) || defined (GD32F425)
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 Out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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#endif /* GD32F405 and GD32F425 */
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#if defined (GD32F407) || defined (GD32F427)
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EXMC_IRQn = 48, /*!< EXMC interrupt */
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SDIO_IRQn = 49, /*!< SDIO interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 interrupt */
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SPI2_IRQn = 51, /*!< SPI2 interrupt */
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UART3_IRQn = 52, /*!< UART3 interrupt */
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UART4_IRQn = 53, /*!< UART4 interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 underrun error interrupts */
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TIMER6_IRQn = 55, /*!< TIMER6 interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 channel4 interrupt */
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ENET_IRQn = 61, /*!< ENET interrupt */
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ENET_WKUP_IRQn = 62, /*!< ENET wakeup through EXTI line interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
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USBFS_IRQn = 67, /*!< USBFS interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 channel5 interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 channel6 interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 channel7 interrupt */
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USART5_IRQn = 71, /*!< USART5 interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 event interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 error interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS endpoint 1 out interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS endpoint 1 in interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS wakeup through EXTI line interrupt */
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USBHS_IRQn = 77, /*!< USBHS interrupt */
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DCI_IRQn = 78, /*!< DCI interrupt */
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TRNG_IRQn = 80, /*!< TRNG interrupt */
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FPU_IRQn = 81, /*!< FPU interrupt */
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#endif /* GD32F407 and GD32F427 */
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} IRQn_Type;
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/* includes */
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#include "core_cm4.h"
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#include "system_gd32f4xx.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
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#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
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/* EXMC memory map */
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#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
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#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
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||||
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/* advanced peripheral bus 2 memory map */
|
||||
#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
|
||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
|
||||
#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
|
||||
#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
|
||||
#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
|
||||
#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
|
||||
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
|
||||
#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
|
||||
#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "gd32f4xx_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,65 @@
|
||||
/*!
|
||||
\file system_gd32f4xx.h
|
||||
\brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File for
|
||||
GD32F4xx Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32F4XX_H
|
||||
#define SYSTEM_GD32F4XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
/* firmware version can be aquired by uncommenting the macro */
|
||||
#define __FIRMWARE_VERSION_DEFINE
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
#ifdef __FIRMWARE_VERSION_DEFINE
|
||||
/* get firmware version */
|
||||
extern uint32_t gd32f4xx_firmware_version_get(void);
|
||||
#endif /* __FIRMWARE_VERSION_DEFINE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32F4XX_H */
|
||||
@@ -0,0 +1,423 @@
|
||||
;/*!
|
||||
; \file startup_gd32f405_425.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD 0 ; 64:Reserved
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD 0 ; 77:Reserved
|
||||
DCD 0 ; 78:Reserved
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT DCI_IRQHandler [WEAK]
|
||||
EXPORT TRNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
DMA0_Channel7_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
USBHS_EP1_In_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
DCI_IRQHandler
|
||||
TRNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,429 @@
|
||||
;/*!
|
||||
; \file startup_gd32f407_427.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT DCI_IRQHandler [WEAK]
|
||||
EXPORT TRNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
DMA0_Channel7_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
USBHS_EP1_In_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
DCI_IRQHandler
|
||||
TRNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,454 @@
|
||||
;/*!
|
||||
; \file startup_gd32f450_470.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000400
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; /* reset Vector Mapped to at Address 0 */
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; /* external interrupts handler */
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commutation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commutation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
DCD UART6_IRQHandler ; 98:UART6
|
||||
DCD UART7_IRQHandler ; 99:UART7
|
||||
DCD SPI3_IRQHandler ; 100:SPI3
|
||||
DCD SPI4_IRQHandler ; 101:SPI4
|
||||
DCD SPI5_IRQHandler ; 102:SPI5
|
||||
DCD 0 ; 103:Reserved
|
||||
DCD TLI_IRQHandler ; 104:TLI
|
||||
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||
DCD IPA_IRQHandler ; 106:IPA
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
;/* reset Handler */
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
;/* dummy Exception Handlers */
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler\
|
||||
PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler\
|
||||
PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
; /* external interrupts handler */
|
||||
EXPORT WWDGT_IRQHandler [WEAK]
|
||||
EXPORT LVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_STAMP_IRQHandler [WEAK]
|
||||
EXPORT RTC_WKUP_IRQHandler [WEAK]
|
||||
EXPORT FMC_IRQHandler [WEAK]
|
||||
EXPORT RCU_CTC_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel6_IRQHandler [WEAK]
|
||||
EXPORT ADC_IRQHandler [WEAK]
|
||||
EXPORT CAN0_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN0_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN0_EWMC_IRQHandler [WEAK]
|
||||
EXPORT EXTI5_9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_BRK_TIMER8_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_UP_TIMER9_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_TRG_CMT_TIMER10_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_Channel_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT I2C0_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C0_ER_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ER_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT EXTI10_15_IRQHandler [WEAK]
|
||||
EXPORT RTC_Alarm_IRQHandler [WEAK]
|
||||
EXPORT USBFS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_BRK_TIMER11_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_UP_TIMER12_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_TRG_CMT_TIMER13_IRQHandler [WEAK]
|
||||
EXPORT TIMER7_Channel_IRQHandler [WEAK]
|
||||
EXPORT DMA0_Channel7_IRQHandler [WEAK]
|
||||
EXPORT EXMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIMER4_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT TIMER5_DAC_IRQHandler [WEAK]
|
||||
EXPORT TIMER6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel0_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT ENET_IRQHandler [WEAK]
|
||||
EXPORT ENET_WKUP_IRQHandler [WEAK]
|
||||
EXPORT CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_EWMC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT USART5_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EV_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ER_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_Out_IRQHandler [WEAK]
|
||||
EXPORT USBHS_EP1_In_IRQHandler [WEAK]
|
||||
EXPORT USBHS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT USBHS_IRQHandler [WEAK]
|
||||
EXPORT DCI_IRQHandler [WEAK]
|
||||
EXPORT TRNG_IRQHandler [WEAK]
|
||||
EXPORT FPU_IRQHandler [WEAK]
|
||||
EXPORT UART6_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT SPI5_IRQHandler [WEAK]
|
||||
EXPORT TLI_IRQHandler [WEAK]
|
||||
EXPORT TLI_ER_IRQHandler [WEAK]
|
||||
EXPORT IPA_IRQHandler [WEAK]
|
||||
|
||||
;/* external interrupts handler */
|
||||
WWDGT_IRQHandler
|
||||
LVD_IRQHandler
|
||||
TAMPER_STAMP_IRQHandler
|
||||
RTC_WKUP_IRQHandler
|
||||
FMC_IRQHandler
|
||||
RCU_CTC_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA0_Channel0_IRQHandler
|
||||
DMA0_Channel1_IRQHandler
|
||||
DMA0_Channel2_IRQHandler
|
||||
DMA0_Channel3_IRQHandler
|
||||
DMA0_Channel4_IRQHandler
|
||||
DMA0_Channel5_IRQHandler
|
||||
DMA0_Channel6_IRQHandler
|
||||
ADC_IRQHandler
|
||||
CAN0_TX_IRQHandler
|
||||
CAN0_RX0_IRQHandler
|
||||
CAN0_RX1_IRQHandler
|
||||
CAN0_EWMC_IRQHandler
|
||||
EXTI5_9_IRQHandler
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
TIMER0_Channel_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
I2C0_EV_IRQHandler
|
||||
I2C0_ER_IRQHandler
|
||||
I2C1_EV_IRQHandler
|
||||
I2C1_ER_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
EXTI10_15_IRQHandler
|
||||
RTC_Alarm_IRQHandler
|
||||
USBFS_WKUP_IRQHandler
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
TIMER7_Channel_IRQHandler
|
||||
DMA0_Channel7_IRQHandler
|
||||
EXMC_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIMER4_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
TIMER5_DAC_IRQHandler
|
||||
TIMER6_IRQHandler
|
||||
DMA1_Channel0_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
ENET_IRQHandler
|
||||
ENET_WKUP_IRQHandler
|
||||
CAN1_TX_IRQHandler
|
||||
CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_EWMC_IRQHandler
|
||||
USBFS_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
USART5_IRQHandler
|
||||
I2C2_EV_IRQHandler
|
||||
I2C2_ER_IRQHandler
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
USBHS_EP1_In_IRQHandler
|
||||
USBHS_WKUP_IRQHandler
|
||||
USBHS_IRQHandler
|
||||
DCI_IRQHandler
|
||||
TRNG_IRQHandler
|
||||
FPU_IRQHandler
|
||||
UART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
SPI5_IRQHandler
|
||||
TLI_IRQHandler
|
||||
TLI_ER_IRQHandler
|
||||
IPA_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; user Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap PROC
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f405_407_xE_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f405_407_xG_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f405_407_xK_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 128K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f425_427_xE_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f425_427_xG_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f425_427_xK_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f450xE_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f450xG_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,179 @@
|
||||
/*!
|
||||
\file gd32f450xI_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 448K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f450xK_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f470xE_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f470xG_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f470xI_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 704K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
/*!
|
||||
\file gd32f470xK_flash.ld
|
||||
\brief linker script file
|
||||
|
||||
\version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
/* memory map */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x08000000, LENGTH = 3072K
|
||||
RAM (xrw): ORIGIN = 0x20000000, LENGTH = 192K
|
||||
TCMRAM (xrw): ORIGIN = 0x10000000, LENGTH = 64K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
|
||||
__heap_size = DEFINED(__heap_size) ? __heap_size : 1K;
|
||||
|
||||
/* ISR vectors */
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
__Vectors_End = .;
|
||||
__Vectors_Size = __Vectors_End - __gVectors;
|
||||
} >FLASH
|
||||
|
||||
/* text section, such as program code */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_etext' will be defined at the end of code section */
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
/* ro-data section, such as constant data */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* exception process table */
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
/* exception process table index */
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* ARM attributes */
|
||||
.ARM.attributes :
|
||||
{
|
||||
*(.ARM.attributes)
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(.fini_array*))
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* provide some necessary symbols for initialized data */
|
||||
_sidata = LOADADDR(.data);
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sdata' will be defined at the data section end start */
|
||||
_sdata = .;
|
||||
*(.data)
|
||||
*(.data*)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_edata' will be defined at the data section end */
|
||||
_edata = .;
|
||||
} > RAM AT> FLASH
|
||||
|
||||
/* provide some necessary symbols for uninitialized data */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_sbss' will be defined at the bss section start */
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
/* the symbol '_ebss' will be defined at the bss section end */
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
} > RAM
|
||||
|
||||
/* heap and stack space */
|
||||
.heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = _ebss );
|
||||
PROVIDE ( _end = _ebss );
|
||||
. = . + __heap_size;
|
||||
PROVIDE( _heap_end = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _sp = . );
|
||||
. = ALIGN(8);
|
||||
} > RAM
|
||||
|
||||
/* Note: To use TCMRAM, initialization in the startup file is required. */
|
||||
_sitcmram = LOADADDR(.tcmram);
|
||||
.tcmram :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
.stcmram = .;
|
||||
*(.tcmram)
|
||||
*(.tcmram*)
|
||||
. = ALIGN(4);
|
||||
_etcmram = .;
|
||||
} > TCMRAM AT> FLASH
|
||||
}
|
||||
|
||||
/* input sections */
|
||||
GROUP(libgcc.a libc.a libm.a libnosys.a)
|
||||
|
||||
@@ -0,0 +1,191 @@
|
||||
/*!
|
||||
\file syscall.c
|
||||
\brief system calls file
|
||||
|
||||
\version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <_ansi.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/fcntl.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/times.h>
|
||||
#include <errno.h>
|
||||
#include <reent.h>
|
||||
#include <unistd.h>
|
||||
#include <sys/wait.h>
|
||||
|
||||
#undef errno
|
||||
extern int errno;
|
||||
|
||||
extern int __io_putchar(int ch) __attribute__((weak));
|
||||
extern int __io_getchar(void) __attribute__((weak));
|
||||
|
||||
caddr_t _sbrk(int incr)
|
||||
{
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if((curbrk + incr < _end) || (curbrk + incr > _heap_end)) {
|
||||
return NULL - 1;
|
||||
}
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
|
||||
/*
|
||||
* _gettimeofday primitive (Stub function)
|
||||
* */
|
||||
int _gettimeofday (struct timeval * tp, struct timezone * tzp)
|
||||
{
|
||||
/* Return fixed data for the timezone. */
|
||||
if(tzp) {
|
||||
tzp->tz_minuteswest = 0;
|
||||
tzp->tz_dsttime = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
void initialise_monitor_handles()
|
||||
{
|
||||
}
|
||||
|
||||
int _getpid(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _kill(int pid, int sig)
|
||||
{
|
||||
errno = EINVAL;
|
||||
return -1;
|
||||
}
|
||||
|
||||
void _exit (int status)
|
||||
{
|
||||
_kill(status, -1);
|
||||
while(1) {
|
||||
}
|
||||
}
|
||||
|
||||
int _write(int file, char *ptr, int len)
|
||||
{
|
||||
int DataIdx;
|
||||
|
||||
for(DataIdx = 0; DataIdx < len; DataIdx++) {
|
||||
__io_putchar(*ptr++);
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
int _close(int file)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fstat(int file, struct stat *st)
|
||||
{
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _isatty(int file)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _lseek(int file, int ptr, int dir)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _read(int file, char *ptr, int len)
|
||||
{
|
||||
int DataIdx;
|
||||
|
||||
for(DataIdx = 0; DataIdx < len; DataIdx++) {
|
||||
*ptr++ = __io_getchar();
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
int _open(char *path, int flags, ...)
|
||||
{
|
||||
/* Pretend like we always fail */
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _wait(int *status)
|
||||
{
|
||||
errno = ECHILD;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _unlink(char *name)
|
||||
{
|
||||
errno = ENOENT;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _times(struct tms *buf)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _stat(char *file, struct stat *st)
|
||||
{
|
||||
st->st_mode = S_IFCHR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _link(char *old, char *new)
|
||||
{
|
||||
errno = EMLINK;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _fork(void)
|
||||
{
|
||||
errno = EAGAIN;
|
||||
return -1;
|
||||
}
|
||||
|
||||
int _execve(char *name, char **argv, char **env)
|
||||
{
|
||||
errno = ENOMEM;
|
||||
return -1;
|
||||
}
|
||||
@@ -0,0 +1,454 @@
|
||||
;/*!
|
||||
; \file startup_gd32f405_425.S
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* necessary symbols defined in linker script to initialize data */
|
||||
.word _sidata
|
||||
.word _sdata
|
||||
.word _edata
|
||||
.word _sbss
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
/* reset Handler */
|
||||
Reset_Handler:
|
||||
movs r1, #0
|
||||
b DataInit
|
||||
|
||||
CopyData:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
DataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyData
|
||||
ldr r2, =_sbss
|
||||
b Zerobss
|
||||
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
Zerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call SystemInit function */
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/*Call the main function */
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .vectors,"a",%progbits
|
||||
.global __gVectors
|
||||
|
||||
__gVectors:
|
||||
.word _sp /* Top of Stack */
|
||||
.word Reset_Handler /* Reset Handler */
|
||||
.word NMI_Handler /* NMI Handler */
|
||||
.word HardFault_Handler /* Hard Fault Handler */
|
||||
.word MemManage_Handler /* MPU Fault Handler */
|
||||
.word BusFault_Handler /* Bus Fault Handler */
|
||||
.word UsageFault_Handler /* Usage Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* SVCall Handler */
|
||||
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* PendSV Handler */
|
||||
.word SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts handler */
|
||||
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */
|
||||
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
|
||||
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||
.word 0 /* Vector Number 64,Reserved */
|
||||
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||
.word 0 /* Vector Number 77,Reserved */
|
||||
.word 0 /* Vector Number 78,Reserved */
|
||||
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||
.word 0 /* Vector Number 95,Reserved */
|
||||
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_STAMP_IRQHandler
|
||||
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_CTC_IRQHandler
|
||||
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel0_IRQHandler
|
||||
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel1_IRQHandler
|
||||
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel2_IRQHandler
|
||||
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel3_IRQHandler
|
||||
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel4_IRQHandler
|
||||
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel5_IRQHandler
|
||||
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel6_IRQHandler
|
||||
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_TX_IRQHandler
|
||||
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX0_IRQHandler
|
||||
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX1_IRQHandler
|
||||
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_EWMC_IRQHandler
|
||||
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_9_IRQHandler
|
||||
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_IRQHandler
|
||||
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_15_IRQHandler
|
||||
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_WKUP_IRQHandler
|
||||
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_Channel_IRQHandler
|
||||
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel7_IRQHandler
|
||||
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_IRQHandler
|
||||
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_DAC_IRQHandler
|
||||
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER6_IRQHandler
|
||||
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel0_IRQHandler
|
||||
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_EWMC_IRQHandler
|
||||
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_IRQHandler
|
||||
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART5_IRQHandler
|
||||
.thumb_set USART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_Out_IRQHandler
|
||||
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_In_IRQHandler
|
||||
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_WKUP_IRQHandler
|
||||
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_IRQHandler
|
||||
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCI_IRQHandler
|
||||
.thumb_set DCI_IRQHandler,Default_Handler
|
||||
|
||||
.weak TRNG_IRQHandler
|
||||
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
@@ -0,0 +1,463 @@
|
||||
;/*!
|
||||
; \file startup_gd32f407_427.S
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* necessary symbols defined in linker script to initialize data */
|
||||
.word _sidata
|
||||
.word _sdata
|
||||
.word _edata
|
||||
.word _sbss
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
/* reset Handler */
|
||||
Reset_Handler:
|
||||
movs r1, #0
|
||||
b DataInit
|
||||
|
||||
CopyData:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
DataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyData
|
||||
ldr r2, =_sbss
|
||||
b Zerobss
|
||||
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
Zerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call SystemInit function */
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/*Call the main function */
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .vectors,"a",%progbits
|
||||
.global __gVectors
|
||||
|
||||
__gVectors:
|
||||
.word _sp /* Top of Stack */
|
||||
.word Reset_Handler /* Reset Handler */
|
||||
.word NMI_Handler /* NMI Handler */
|
||||
.word HardFault_Handler /* Hard Fault Handler */
|
||||
.word MemManage_Handler /* MPU Fault Handler */
|
||||
.word BusFault_Handler /* Bus Fault Handler */
|
||||
.word UsageFault_Handler /* Usage Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* SVCall Handler */
|
||||
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* PendSV Handler */
|
||||
.word SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts handler */
|
||||
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Channel Capture Compare */
|
||||
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Capture Compare */
|
||||
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||
.word EXMC_IRQHandler /* Vector Number 64,EXMC */
|
||||
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||
.word ENET_IRQHandler /* Vector Number 77,Ethernet */
|
||||
.word ENET_WKUP_IRQHandler /* Vector Number 78,Ethernet Wakeup through EXTI Line */
|
||||
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||
.word 0 /* Vector Number 95,Reserved */
|
||||
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_STAMP_IRQHandler
|
||||
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_CTC_IRQHandler
|
||||
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel0_IRQHandler
|
||||
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel1_IRQHandler
|
||||
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel2_IRQHandler
|
||||
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel3_IRQHandler
|
||||
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel4_IRQHandler
|
||||
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel5_IRQHandler
|
||||
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel6_IRQHandler
|
||||
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_TX_IRQHandler
|
||||
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX0_IRQHandler
|
||||
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX1_IRQHandler
|
||||
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_EWMC_IRQHandler
|
||||
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_9_IRQHandler
|
||||
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_IRQHandler
|
||||
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_15_IRQHandler
|
||||
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_WKUP_IRQHandler
|
||||
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_Channel_IRQHandler
|
||||
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel7_IRQHandler
|
||||
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXMC_IRQHandler
|
||||
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_IRQHandler
|
||||
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_DAC_IRQHandler
|
||||
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER6_IRQHandler
|
||||
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel0_IRQHandler
|
||||
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_IRQHandler
|
||||
.thumb_set ENET_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_WKUP_IRQHandler
|
||||
.thumb_set ENET_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_EWMC_IRQHandler
|
||||
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_IRQHandler
|
||||
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART5_IRQHandler
|
||||
.thumb_set USART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_Out_IRQHandler
|
||||
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_In_IRQHandler
|
||||
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_WKUP_IRQHandler
|
||||
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_IRQHandler
|
||||
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCI_IRQHandler
|
||||
.thumb_set DCI_IRQHandler,Default_Handler
|
||||
|
||||
.weak TRNG_IRQHandler
|
||||
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
@@ -0,0 +1,496 @@
|
||||
;/*!
|
||||
; \file startup_gd32f450_470.S
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2025-07-31, V3.3.2, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/*
|
||||
; * Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
; * Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
; * SPDX-License-Identifier: Apache-2.0
|
||||
; *
|
||||
; * Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
; * not use this file except in compliance with the License.
|
||||
; * You may obtain a copy of the License at
|
||||
; *
|
||||
; * www.apache.org/licenses/LICENSE-2.0
|
||||
; *
|
||||
; * Unless required by applicable law or agreed to in writing, software
|
||||
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
; * See the License for the specific language governing permissions and
|
||||
; * limitations under the License.
|
||||
; */
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global Default_Handler
|
||||
|
||||
/* necessary symbols defined in linker script to initialize data */
|
||||
.word _sidata
|
||||
.word _sdata
|
||||
.word _edata
|
||||
.word _sbss
|
||||
.word _ebss
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
/* reset Handler */
|
||||
Reset_Handler:
|
||||
movs r1, #0
|
||||
b DataInit
|
||||
|
||||
CopyData:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
DataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyData
|
||||
ldr r2, =_sbss
|
||||
b Zerobss
|
||||
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
Zerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
/* Call SystemInit function */
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/*Call the main function */
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
|
||||
.section .vectors,"a",%progbits
|
||||
.global __gVectors
|
||||
|
||||
__gVectors:
|
||||
.word _sp /* Top of Stack */
|
||||
.word Reset_Handler /* Reset Handler */
|
||||
.word NMI_Handler /* NMI Handler */
|
||||
.word HardFault_Handler /* Hard Fault Handler */
|
||||
.word MemManage_Handler /* MPU Fault Handler */
|
||||
.word BusFault_Handler /* Bus Fault Handler */
|
||||
.word UsageFault_Handler /* Usage Fault Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SVC_Handler /* SVCall Handler */
|
||||
.word DebugMon_Handler /* Debug Monitor Handler */
|
||||
.word 0 /* Reserved */
|
||||
.word PendSV_Handler /* PendSV Handler */
|
||||
.word SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts handler */
|
||||
.word WWDGT_IRQHandler /* Vector Number 16,Window Watchdog Timer */
|
||||
.word LVD_IRQHandler /* Vector Number 17,LVD through EXTI Line detect */
|
||||
.word TAMPER_STAMP_IRQHandler /* Vector Number 18,Tamper and TimeStamp through EXTI Line detect */
|
||||
.word RTC_WKUP_IRQHandler /* Vector Number 19,RTC Wakeup through EXTI Line */
|
||||
.word FMC_IRQHandler /* Vector Number 20,FMC */
|
||||
.word RCU_CTC_IRQHandler /* Vector Number 21,RCU and CTC */
|
||||
.word EXTI0_IRQHandler /* Vector Number 22,EXTI Line 0 */
|
||||
.word EXTI1_IRQHandler /* Vector Number 23,EXTI Line 1 */
|
||||
.word EXTI2_IRQHandler /* Vector Number 24,EXTI Line 2 */
|
||||
.word EXTI3_IRQHandler /* Vector Number 25,EXTI Line 3 */
|
||||
.word EXTI4_IRQHandler /* Vector Number 26,EXTI Line 4 */
|
||||
.word DMA0_Channel0_IRQHandler /* Vector Number 27,DMA0 Channel0 */
|
||||
.word DMA0_Channel1_IRQHandler /* Vector Number 28,DMA0 Channel1 */
|
||||
.word DMA0_Channel2_IRQHandler /* Vector Number 29,DMA0 Channel2 */
|
||||
.word DMA0_Channel3_IRQHandler /* Vector Number 30,DMA0 Channel3 */
|
||||
.word DMA0_Channel4_IRQHandler /* Vector Number 31,DMA0 Channel4 */
|
||||
.word DMA0_Channel5_IRQHandler /* Vector Number 32,DMA0 Channel5 */
|
||||
.word DMA0_Channel6_IRQHandler /* Vector Number 33,DMA0 Channel6 */
|
||||
.word ADC_IRQHandler /* Vector Number 34,ADC */
|
||||
.word CAN0_TX_IRQHandler /* Vector Number 35,CAN0 TX */
|
||||
.word CAN0_RX0_IRQHandler /* Vector Number 36,CAN0 RX0 */
|
||||
.word CAN0_RX1_IRQHandler /* Vector Number 37,CAN0 RX1 */
|
||||
.word CAN0_EWMC_IRQHandler /* Vector Number 38,CAN0 EWMC */
|
||||
.word EXTI5_9_IRQHandler /* Vector Number 39,EXTI5 to EXTI9 */
|
||||
.word TIMER0_BRK_TIMER8_IRQHandler /* Vector Number 40,TIMER0 Break and TIMER8 */
|
||||
.word TIMER0_UP_TIMER9_IRQHandler /* Vector Number 41,TIMER0 Update and TIMER9 */
|
||||
.word TIMER0_TRG_CMT_TIMER10_IRQHandler /* Vector Number 42,TIMER0 Trigger and Commutation and TIMER10 */
|
||||
.word TIMER0_Channel_IRQHandler /* Vector Number 43,TIMER0 Capture Compare */
|
||||
.word TIMER1_IRQHandler /* Vector Number 44,TIMER1 */
|
||||
.word TIMER2_IRQHandler /* Vector Number 45,TIMER2 */
|
||||
.word TIMER3_IRQHandler /* Vector Number 46,TIMER3 */
|
||||
.word I2C0_EV_IRQHandler /* Vector Number 47,I2C0 Event */
|
||||
.word I2C0_ER_IRQHandler /* Vector Number 48,I2C0 Error */
|
||||
.word I2C1_EV_IRQHandler /* Vector Number 49,I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* Vector Number 50,I2C1 Error */
|
||||
.word SPI0_IRQHandler /* Vector Number 51,SPI0 */
|
||||
.word SPI1_IRQHandler /* Vector Number 52,SPI1 */
|
||||
.word USART0_IRQHandler /* Vector Number 53,USART0 */
|
||||
.word USART1_IRQHandler /* Vector Number 54,USART1 */
|
||||
.word USART2_IRQHandler /* Vector Number 55,USART2 */
|
||||
.word EXTI10_15_IRQHandler /* Vector Number 56,EXTI10 to EXTI15 */
|
||||
.word RTC_Alarm_IRQHandler /* Vector Number 57,RTC Alarm */
|
||||
.word USBFS_WKUP_IRQHandler /* Vector Number 58,USBFS Wakeup */
|
||||
.word TIMER7_BRK_TIMER11_IRQHandler /* Vector Number 59,TIMER7 Break and TIMER11 */
|
||||
.word TIMER7_UP_TIMER12_IRQHandler /* Vector Number 60,TIMER7 Update and TIMER12 */
|
||||
.word TIMER7_TRG_CMT_TIMER13_IRQHandler /* Vector Number 61,TIMER7 Trigger and Commutation and TIMER13 */
|
||||
.word TIMER7_Channel_IRQHandler /* Vector Number 62,TIMER7 Channel Capture Compare */
|
||||
.word DMA0_Channel7_IRQHandler /* Vector Number 63,DMA0 Channel7 */
|
||||
.word EXMC_IRQHandler /* Vector Number 64,EXMC */
|
||||
.word SDIO_IRQHandler /* Vector Number 65,SDIO */
|
||||
.word TIMER4_IRQHandler /* Vector Number 66,TIMER4 */
|
||||
.word SPI2_IRQHandler /* Vector Number 67,SPI2 */
|
||||
.word UART3_IRQHandler /* Vector Number 68,UART3 */
|
||||
.word UART4_IRQHandler /* Vector Number 69,UART4 */
|
||||
.word TIMER5_DAC_IRQHandler /* Vector Number 70,TIMER5 and DAC0 DAC1 Underrun error */
|
||||
.word TIMER6_IRQHandler /* Vector Number 71,TIMER6 */
|
||||
.word DMA1_Channel0_IRQHandler /* Vector Number 72,DMA1 Channel0 */
|
||||
.word DMA1_Channel1_IRQHandler /* Vector Number 73,DMA1 Channel1 */
|
||||
.word DMA1_Channel2_IRQHandler /* Vector Number 74,DMA1 Channel2 */
|
||||
.word DMA1_Channel3_IRQHandler /* Vector Number 75,DMA1 Channel3 */
|
||||
.word DMA1_Channel4_IRQHandler /* Vector Number 76,DMA1 Channel4 */
|
||||
.word ENET_IRQHandler /* Vector Number 77,Ethernet */
|
||||
.word ENET_WKUP_IRQHandler /* Vector Number 78,Ethernet Wakeup through EXTI Line */
|
||||
.word CAN1_TX_IRQHandler /* Vector Number 79,CAN1 TX */
|
||||
.word CAN1_RX0_IRQHandler /* Vector Number 80,CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* Vector Number 81,CAN1 RX1 */
|
||||
.word CAN1_EWMC_IRQHandler /* Vector Number 82,CAN1 EWMC */
|
||||
.word USBFS_IRQHandler /* Vector Number 83,USBFS */
|
||||
.word DMA1_Channel5_IRQHandler /* Vector Number 84,DMA1 Channel5 */
|
||||
.word DMA1_Channel6_IRQHandler /* Vector Number 85,DMA1 Channel6 */
|
||||
.word DMA1_Channel7_IRQHandler /* Vector Number 86,DMA1 Channel7 */
|
||||
.word USART5_IRQHandler /* Vector Number 87,USART5 */
|
||||
.word I2C2_EV_IRQHandler /* Vector Number 88,I2C2 Event */
|
||||
.word I2C2_ER_IRQHandler /* Vector Number 89,I2C2 Error */
|
||||
.word USBHS_EP1_Out_IRQHandler /* Vector Number 90,USBHS Endpoint 1 Out */
|
||||
.word USBHS_EP1_In_IRQHandler /* Vector Number 91,USBHS Endpoint 1 in */
|
||||
.word USBHS_WKUP_IRQHandler /* Vector Number 92,USBHS Wakeup through EXTI Line */
|
||||
.word USBHS_IRQHandler /* Vector Number 93,USBHS */
|
||||
.word DCI_IRQHandler /* Vector Number 94,DCI */
|
||||
.word 0 /* Vector Number 95,Reserved */
|
||||
.word TRNG_IRQHandler /* Vector Number 96,TRNG */
|
||||
.word FPU_IRQHandler /* Vector Number 97,FPU */
|
||||
.word UART6_IRQHandler /* Vector Number 98,UART6 */
|
||||
.word UART7_IRQHandler /* Vector Number 99,UART7 */
|
||||
.word SPI3_IRQHandler /* Vector Number 100,SPI3 */
|
||||
.word SPI4_IRQHandler /* Vector Number 101,SPI4 */
|
||||
.word SPI5_IRQHandler /* Vector Number 102,SPI5 */
|
||||
.word 0 /* Vector Number 103,Reserved */
|
||||
.word TLI_IRQHandler /* Vector Number 104,TLI */
|
||||
.word TLI_ER_IRQHandler /* Vector Number 105,TLI Error */
|
||||
.word IPA_IRQHandler /* Vector Number 106,IPA */
|
||||
|
||||
.size __gVectors, . - __gVectors
|
||||
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDGT_IRQHandler
|
||||
.thumb_set WWDGT_IRQHandler,Default_Handler
|
||||
|
||||
.weak LVD_IRQHandler
|
||||
.thumb_set LVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_STAMP_IRQHandler
|
||||
.thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCU_CTC_IRQHandler
|
||||
.thumb_set RCU_CTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel0_IRQHandler
|
||||
.thumb_set DMA0_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel1_IRQHandler
|
||||
.thumb_set DMA0_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel2_IRQHandler
|
||||
.thumb_set DMA0_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel3_IRQHandler
|
||||
.thumb_set DMA0_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel4_IRQHandler
|
||||
.thumb_set DMA0_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel5_IRQHandler
|
||||
.thumb_set DMA0_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel6_IRQHandler
|
||||
.thumb_set DMA0_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_TX_IRQHandler
|
||||
.thumb_set CAN0_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX0_IRQHandler
|
||||
.thumb_set CAN0_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_RX1_IRQHandler
|
||||
.thumb_set CAN0_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN0_EWMC_IRQHandler
|
||||
.thumb_set CAN0_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI5_9_IRQHandler
|
||||
.thumb_set EXTI5_9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_BRK_TIMER8_IRQHandler
|
||||
.thumb_set TIMER0_BRK_TIMER8_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_UP_TIMER9_IRQHandler
|
||||
.thumb_set TIMER0_UP_TIMER9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
.thumb_set TIMER0_TRG_CMT_TIMER10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER0_Channel_IRQHandler
|
||||
.thumb_set TIMER0_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER1_IRQHandler
|
||||
.thumb_set TIMER1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER2_IRQHandler
|
||||
.thumb_set TIMER2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER3_IRQHandler
|
||||
.thumb_set TIMER3_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_EV_IRQHandler
|
||||
.thumb_set I2C0_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C0_ER_IRQHandler
|
||||
.thumb_set I2C0_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI0_IRQHandler
|
||||
.thumb_set SPI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART0_IRQHandler
|
||||
.thumb_set USART0_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI10_15_IRQHandler
|
||||
.thumb_set EXTI10_15_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_WKUP_IRQHandler
|
||||
.thumb_set USBFS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_BRK_TIMER11_IRQHandler
|
||||
.thumb_set TIMER7_BRK_TIMER11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_UP_TIMER12_IRQHandler
|
||||
.thumb_set TIMER7_UP_TIMER12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
.thumb_set TIMER7_TRG_CMT_TIMER13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER7_Channel_IRQHandler
|
||||
.thumb_set TIMER7_Channel_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA0_Channel7_IRQHandler
|
||||
.thumb_set DMA0_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXMC_IRQHandler
|
||||
.thumb_set EXMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO_IRQHandler
|
||||
.thumb_set SDIO_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER4_IRQHandler
|
||||
.thumb_set TIMER4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART3_IRQHandler
|
||||
.thumb_set UART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER5_DAC_IRQHandler
|
||||
.thumb_set TIMER5_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIMER6_IRQHandler
|
||||
.thumb_set TIMER6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel0_IRQHandler
|
||||
.thumb_set DMA1_Channel0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_IRQHandler
|
||||
.thumb_set ENET_IRQHandler,Default_Handler
|
||||
|
||||
.weak ENET_WKUP_IRQHandler
|
||||
.thumb_set ENET_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_EWMC_IRQHandler
|
||||
.thumb_set CAN1_EWMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_IRQHandler
|
||||
.thumb_set USBFS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART5_IRQHandler
|
||||
.thumb_set USART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_Out_IRQHandler
|
||||
.thumb_set USBHS_EP1_Out_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_EP1_In_IRQHandler
|
||||
.thumb_set USBHS_EP1_In_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_WKUP_IRQHandler
|
||||
.thumb_set USBHS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBHS_IRQHandler
|
||||
.thumb_set USBHS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DCI_IRQHandler
|
||||
.thumb_set DCI_IRQHandler,Default_Handler
|
||||
|
||||
.weak TRNG_IRQHandler
|
||||
.thumb_set TRNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART6_IRQHandler
|
||||
.thumb_set UART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TLI_IRQHandler
|
||||
.thumb_set TLI_IRQHandler,Default_Handler
|
||||
|
||||
.weak TLI_ER_IRQHandler
|
||||
.thumb_set TLI_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak IPA_IRQHandler
|
||||
.thumb_set IPA_IRQHandler,Default_Handler
|
||||
@@ -0,0 +1,602 @@
|
||||
;/*!
|
||||
; \file startup_gd32f405_425.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD 0 ; 64:Reserved
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD 0 ; 77:Reserved
|
||||
DCD 0 ; 78:Reserved
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_STAMP_IRQHandler
|
||||
B TAMPER_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel7_IRQHandler
|
||||
B DMA0_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_DAC_IRQHandler
|
||||
B TIMER5_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK USART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART5_IRQHandler
|
||||
B USART5_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
B USBHS_EP1_Out_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_In_IRQHandler
|
||||
B USBHS_EP1_In_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_WKUP_IRQHandler
|
||||
B USBHS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_IRQHandler
|
||||
B USBHS_IRQHandler
|
||||
|
||||
PUBWEAK DCI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCI_IRQHandler
|
||||
B DCI_IRQHandler
|
||||
|
||||
PUBWEAK TRNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TRNG_IRQHandler
|
||||
B TRNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
@@ -0,0 +1,617 @@
|
||||
;/*!
|
||||
; \file startup_gd32f407_427.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_STAMP_IRQHandler
|
||||
B TAMPER_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel7_IRQHandler
|
||||
B DMA0_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_DAC_IRQHandler
|
||||
B TIMER5_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK ENET_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_WKUP_IRQHandler
|
||||
B ENET_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK USART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART5_IRQHandler
|
||||
B USART5_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
B USBHS_EP1_Out_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_In_IRQHandler
|
||||
B USBHS_EP1_In_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_WKUP_IRQHandler
|
||||
B USBHS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_IRQHandler
|
||||
B USBHS_IRQHandler
|
||||
|
||||
PUBWEAK DCI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCI_IRQHandler
|
||||
B DCI_IRQHandler
|
||||
|
||||
PUBWEAK TRNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TRNG_IRQHandler
|
||||
B TRNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
END
|
||||
@@ -0,0 +1,666 @@
|
||||
;/*!
|
||||
; \file startup_gd32f450_470.s
|
||||
; \brief start up file
|
||||
;
|
||||
; \version 2026-02-05, V3.3.3, firmware for GD32F4xx
|
||||
;*/
|
||||
;
|
||||
;/* Copyright (c) 2012 ARM LIMITED
|
||||
; Copyright (c) 2026, GigaDevice Semiconductor Inc.
|
||||
;
|
||||
; All rights reserved.
|
||||
; Redistribution and use in source and binary forms, with or without
|
||||
; modification, are permitted provided that the following conditions are met:
|
||||
; - Redistributions of source code must retain the above copyright
|
||||
; notice, this list of conditions and the following disclaimer.
|
||||
; - Redistributions in binary form must reproduce the above copyright
|
||||
; notice, this list of conditions and the following disclaimer in the
|
||||
; documentation and/or other materials provided with the distribution.
|
||||
; - Neither the name of ARM nor the names of its contributors may be used
|
||||
; to endorse or promote products derived from this software without
|
||||
; specific prior written permission.
|
||||
; *
|
||||
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
; POSSIBILITY OF SUCH DAMAGE.
|
||||
; ---------------------------------------------------------------------------*/
|
||||
|
||||
;/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; top of stack
|
||||
DCD Reset_Handler ; Vector Number 1,Reset Handler
|
||||
|
||||
DCD NMI_Handler ; Vector Number 2,NMI Handler
|
||||
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
|
||||
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
|
||||
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; Vector Number 11,SVCall Handler
|
||||
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
|
||||
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
|
||||
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
|
||||
DCD TAMPER_STAMP_IRQHandler ; 18:Tamper and TimeStamp through EXTI Line detect
|
||||
DCD RTC_WKUP_IRQHandler ; 19:RTC Wakeup through EXTI Line
|
||||
DCD FMC_IRQHandler ; 20:FMC
|
||||
DCD RCU_CTC_IRQHandler ; 21:RCU and CTC
|
||||
DCD EXTI0_IRQHandler ; 22:EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 23:EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 24:EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 25:EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 26:EXTI Line 4
|
||||
DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel0
|
||||
DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel1
|
||||
DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel2
|
||||
DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel3
|
||||
DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel4
|
||||
DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel5
|
||||
DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel6
|
||||
DCD ADC_IRQHandler ; 34:ADC
|
||||
DCD CAN0_TX_IRQHandler ; 35:CAN0 TX
|
||||
DCD CAN0_RX0_IRQHandler ; 36:CAN0 RX0
|
||||
DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
|
||||
DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
|
||||
DCD EXTI5_9_IRQHandler ; 39:EXTI5 to EXTI9
|
||||
DCD TIMER0_BRK_TIMER8_IRQHandler ; 40:TIMER0 Break and TIMER8
|
||||
DCD TIMER0_UP_TIMER9_IRQHandler ; 41:TIMER0 Update and TIMER9
|
||||
DCD TIMER0_TRG_CMT_TIMER10_IRQHandler ; 42:TIMER0 Trigger and Commucation and TIMER10
|
||||
DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
|
||||
DCD TIMER1_IRQHandler ; 44:TIMER1
|
||||
DCD TIMER2_IRQHandler ; 45:TIMER2
|
||||
DCD TIMER3_IRQHandler ; 46:TIMER3
|
||||
DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
|
||||
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
|
||||
DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
|
||||
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
|
||||
DCD SPI0_IRQHandler ; 51:SPI0
|
||||
DCD SPI1_IRQHandler ; 52:SPI1
|
||||
DCD USART0_IRQHandler ; 53:USART0
|
||||
DCD USART1_IRQHandler ; 54:USART1
|
||||
DCD USART2_IRQHandler ; 55:USART2
|
||||
DCD EXTI10_15_IRQHandler ; 56:EXTI10 to EXTI15
|
||||
DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm
|
||||
DCD USBFS_WKUP_IRQHandler ; 58:USBFS Wakeup
|
||||
DCD TIMER7_BRK_TIMER11_IRQHandler ; 59:TIMER7 Break and TIMER11
|
||||
DCD TIMER7_UP_TIMER12_IRQHandler ; 60:TIMER7 Update and TIMER12
|
||||
DCD TIMER7_TRG_CMT_TIMER13_IRQHandler ; 61:TIMER7 Trigger and Commucation and TIMER13
|
||||
DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
|
||||
DCD DMA0_Channel7_IRQHandler ; 63:DMA0 Channel7
|
||||
DCD EXMC_IRQHandler ; 64:EXMC
|
||||
DCD SDIO_IRQHandler ; 65:SDIO
|
||||
DCD TIMER4_IRQHandler ; 66:TIMER4
|
||||
DCD SPI2_IRQHandler ; 67:SPI2
|
||||
DCD UART3_IRQHandler ; 68:UART3
|
||||
DCD UART4_IRQHandler ; 69:UART4
|
||||
DCD TIMER5_DAC_IRQHandler ; 70:TIMER5 and DAC0 DAC1 Underrun error
|
||||
DCD TIMER6_IRQHandler ; 71:TIMER6
|
||||
DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
|
||||
DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
|
||||
DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
|
||||
DCD DMA1_Channel3_IRQHandler ; 75:DMA1 Channel3
|
||||
DCD DMA1_Channel4_IRQHandler ; 76:DMA1 Channel4
|
||||
DCD ENET_IRQHandler ; 77:Ethernet
|
||||
DCD ENET_WKUP_IRQHandler ; 78:Ethernet Wakeup through EXTI Line
|
||||
DCD CAN1_TX_IRQHandler ; 79:CAN1 TX
|
||||
DCD CAN1_RX0_IRQHandler ; 80:CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; 81:CAN1 RX1
|
||||
DCD CAN1_EWMC_IRQHandler ; 82:CAN1 EWMC
|
||||
DCD USBFS_IRQHandler ; 83:USBFS
|
||||
DCD DMA1_Channel5_IRQHandler ; 84:DMA1 Channel5
|
||||
DCD DMA1_Channel6_IRQHandler ; 85:DMA1 Channel6
|
||||
DCD DMA1_Channel7_IRQHandler ; 86:DMA1 Channel7
|
||||
DCD USART5_IRQHandler ; 87:USART5
|
||||
DCD I2C2_EV_IRQHandler ; 88:I2C2 Event
|
||||
DCD I2C2_ER_IRQHandler ; 89:I2C2 Error
|
||||
DCD USBHS_EP1_Out_IRQHandler ; 90:USBHS Endpoint 1 Out
|
||||
DCD USBHS_EP1_In_IRQHandler ; 91:USBHS Endpoint 1 in
|
||||
DCD USBHS_WKUP_IRQHandler ; 92:USBHS Wakeup through EXTI Line
|
||||
DCD USBHS_IRQHandler ; 93:USBHS
|
||||
DCD DCI_IRQHandler ; 94:DCI
|
||||
DCD 0 ; 95:Reserved
|
||||
DCD TRNG_IRQHandler ; 96:TRNG
|
||||
DCD FPU_IRQHandler ; 97:FPU
|
||||
DCD UART6_IRQHandler ; 98:UART6
|
||||
DCD UART7_IRQHandler ; 99:UART7
|
||||
DCD SPI3_IRQHandler ; 100:SPI3
|
||||
DCD SPI4_IRQHandler ; 101:SPI4
|
||||
DCD SPI5_IRQHandler ; 102:SPI5
|
||||
DCD 0 ; 103:Reserved
|
||||
DCD TLI_IRQHandler ; 104:TLI
|
||||
DCD TLI_ER_IRQHandler ; 105:TLI Error
|
||||
DCD IPA_IRQHandler ; 106:IPA
|
||||
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDGT_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
WWDGT_IRQHandler
|
||||
B WWDGT_IRQHandler
|
||||
|
||||
PUBWEAK LVD_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
LVD_IRQHandler
|
||||
B LVD_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_STAMP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TAMPER_STAMP_IRQHandler
|
||||
B TAMPER_STAMP_IRQHandler
|
||||
|
||||
PUBWEAK RTC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_WKUP_IRQHandler
|
||||
B RTC_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK FMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FMC_IRQHandler
|
||||
B FMC_IRQHandler
|
||||
|
||||
PUBWEAK RCU_CTC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RCU_CTC_IRQHandler
|
||||
B RCU_CTC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI0_IRQHandler
|
||||
B EXTI0_IRQHandler
|
||||
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI1_IRQHandler
|
||||
B EXTI1_IRQHandler
|
||||
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI2_IRQHandler
|
||||
B EXTI2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI3_IRQHandler
|
||||
B EXTI3_IRQHandler
|
||||
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI4_IRQHandler
|
||||
B EXTI4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel0_IRQHandler
|
||||
B DMA0_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel1_IRQHandler
|
||||
B DMA0_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel2_IRQHandler
|
||||
B DMA0_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel3_IRQHandler
|
||||
B DMA0_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel4_IRQHandler
|
||||
B DMA0_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel5_IRQHandler
|
||||
B DMA0_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel6_IRQHandler
|
||||
B DMA0_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK ADC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ADC_IRQHandler
|
||||
B ADC_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_TX_IRQHandler
|
||||
B CAN0_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX0_IRQHandler
|
||||
B CAN0_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_RX1_IRQHandler
|
||||
B CAN0_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN0_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN0_EWMC_IRQHandler
|
||||
B CAN0_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK EXTI5_9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI5_9_IRQHandler
|
||||
B EXTI5_9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_BRK_TIMER8_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_BRK_TIMER8_IRQHandler
|
||||
B TIMER0_BRK_TIMER8_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_UP_TIMER9_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_UP_TIMER9_IRQHandler
|
||||
B TIMER0_UP_TIMER9_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
B TIMER0_TRG_CMT_TIMER10_IRQHandler
|
||||
|
||||
PUBWEAK TIMER0_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER0_Channel_IRQHandler
|
||||
B TIMER0_Channel_IRQHandler
|
||||
|
||||
PUBWEAK TIMER1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER1_IRQHandler
|
||||
B TIMER1_IRQHandler
|
||||
|
||||
PUBWEAK TIMER2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER2_IRQHandler
|
||||
B TIMER2_IRQHandler
|
||||
|
||||
PUBWEAK TIMER3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER3_IRQHandler
|
||||
B TIMER3_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_EV_IRQHandler
|
||||
B I2C0_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C0_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C0_ER_IRQHandler
|
||||
B I2C0_ER_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_EV_IRQHandler
|
||||
B I2C1_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C1_ER_IRQHandler
|
||||
B I2C1_ER_IRQHandler
|
||||
|
||||
PUBWEAK SPI0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI0_IRQHandler
|
||||
B SPI0_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK USART0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART0_IRQHandler
|
||||
B USART0_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK EXTI10_15_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXTI10_15_IRQHandler
|
||||
B EXTI10_15_IRQHandler
|
||||
|
||||
PUBWEAK RTC_Alarm_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
RTC_Alarm_IRQHandler
|
||||
B RTC_Alarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_WKUP_IRQHandler
|
||||
B USBFS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_BRK_TIMER11_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_BRK_TIMER11_IRQHandler
|
||||
B TIMER7_BRK_TIMER11_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_UP_TIMER12_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_UP_TIMER12_IRQHandler
|
||||
B TIMER7_UP_TIMER12_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
B TIMER7_TRG_CMT_TIMER13_IRQHandler
|
||||
|
||||
PUBWEAK TIMER7_Channel_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER7_Channel_IRQHandler
|
||||
B TIMER7_Channel_IRQHandler
|
||||
|
||||
PUBWEAK DMA0_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA0_Channel7_IRQHandler
|
||||
B DMA0_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK EXMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
EXMC_IRQHandler
|
||||
B EXMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SDIO_IRQHandler
|
||||
B SDIO_IRQHandler
|
||||
|
||||
PUBWEAK TIMER4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER4_IRQHandler
|
||||
B TIMER4_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI2_IRQHandler
|
||||
B SPI2_IRQHandler
|
||||
|
||||
PUBWEAK UART3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART3_IRQHandler
|
||||
B UART3_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK TIMER5_DAC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER5_DAC_IRQHandler
|
||||
B TIMER5_DAC_IRQHandler
|
||||
|
||||
PUBWEAK TIMER6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TIMER6_IRQHandler
|
||||
B TIMER6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel0_IRQHandler
|
||||
B DMA1_Channel0_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK ENET_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_IRQHandler
|
||||
B ENET_IRQHandler
|
||||
|
||||
PUBWEAK ENET_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
ENET_WKUP_IRQHandler
|
||||
B ENET_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_TX_IRQHandler
|
||||
B CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX0_IRQHandler
|
||||
B CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_EWMC_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
CAN1_EWMC_IRQHandler
|
||||
B CAN1_EWMC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBFS_IRQHandler
|
||||
B USBFS_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK USART5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USART5_IRQHandler
|
||||
B USART5_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EV_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_EV_IRQHandler
|
||||
B I2C2_EV_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
I2C2_ER_IRQHandler
|
||||
B I2C2_ER_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_Out_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_Out_IRQHandler
|
||||
B USBHS_EP1_Out_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_EP1_In_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_EP1_In_IRQHandler
|
||||
B USBHS_EP1_In_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_WKUP_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_WKUP_IRQHandler
|
||||
B USBHS_WKUP_IRQHandler
|
||||
|
||||
PUBWEAK USBHS_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
USBHS_IRQHandler
|
||||
B USBHS_IRQHandler
|
||||
|
||||
PUBWEAK DCI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
DCI_IRQHandler
|
||||
B DCI_IRQHandler
|
||||
|
||||
PUBWEAK TRNG_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TRNG_IRQHandler
|
||||
B TRNG_IRQHandler
|
||||
|
||||
PUBWEAK FPU_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
FPU_IRQHandler
|
||||
B FPU_IRQHandler
|
||||
|
||||
PUBWEAK UART6_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART6_IRQHandler
|
||||
B UART6_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI3_IRQHandler
|
||||
B SPI3_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK SPI5_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
SPI5_IRQHandler
|
||||
B SPI5_IRQHandler
|
||||
|
||||
PUBWEAK TLI_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TLI_IRQHandler
|
||||
B TLI_IRQHandler
|
||||
|
||||
PUBWEAK TLI_ER_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
TLI_ER_IRQHandler
|
||||
B TLI_ER_IRQHandler
|
||||
|
||||
PUBWEAK IPA_IRQHandler
|
||||
SECTION .text:CODE:NOROOT:REORDER(1)
|
||||
IPA_IRQHandler
|
||||
B IPA_IRQHandler
|
||||
END
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user